[NFC][PowerPC] Cleanup 64-bit and Darwin CalleeSavedRegs

[daltenty]

Summary

• Remove the no longer used Darwin CalleeSavedRegs
• Combine the SVR464 callee saved regs and AIX64 since the two are (and should be) identical into PPC64
• Update tests for 64-bit CSR change

[sfertile]

llvm/lib/Target/PowerPC/PPCCallingConv.td

328

The SVR4 is no longer appropriate, since this represent the CSRs for all the 64-bit targets, not just ELF. I think CSR_64 is fine, but open to better suggestions.

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCCallingConv.td

328

I agree with Sean. If we are going to use this for all 64BIT targets then we should name it appropriately.

You may need to change the following tests when doing so:
llvm/test/CodeGen/PowerPC/block-placement-1.mir
llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir
llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir
llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir
llvm/test/CodeGen/PowerPC/machine-backward-cp.mir
llvm/test/CodeGen/PowerPC/licm-tocReg.ll
llvm/test/CodeGen/PowerPC/setcr_bc2.mir
llvm/test/CodeGen/PowerPC/setcr_bc.mir
llvm/test/CodeGen/PowerPC/setcr_bc3.mir

[daltenty]

• Rename CSR_SRV4 to CSR_PPC64

[daltenty]

llvm/lib/Target/PowerPC/PPCCallingConv.td

328

CSR_64 is in use by X86, so to keep things clear I opted for CSR_PPC64

[sfertile]

I would rather we don't rename any of the ViaCopy lists, or CSR_SRV464_TLS_PE_SaveList since they are likely dead. We can write IR that triggers them, but Clang will only generate said IR for Darwin IIUC and from the name of the calling convention it is limited to C++.
Also please clang format the changes.

llvm/lib/Target/PowerPC/PPCCallingConv.td

328

Works for me.

[daltenty]

• Remove VIACopy changes and fix formating

[sfertile]

Thanks for the update, LGTM.

llvm/lib/Target/PowerPC/PPCCallingConv.td

def CC_PPC32_SVR4_ByVal : CallingConv<[
   CCIfByVal<CCPassByVal<4, 4>>,
   
   CCCustom<"CC_PPC32_SVR4_Custom_Dummy">
 ]>;
 
 def CSR_Altivec : CalleeSavedRegs<(add V20, V21, V22, V23, V24, V25, V26, V27,
                                        V28, V29, V30, V31)>;
 
-def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
-                                        R21, R22, R23, R24, R25, R26, R27, R28,
-                                        R29, R30, R31, F14, F15, F16, F17, F18,
-                                        F19, F20, F21, F22, F23, F24, F25, F26,
-                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
-                                   )>;
-
-def CSR_Darwin32_Altivec : CalleeSavedRegs<(add CSR_Darwin32, CSR_Altivec)>;
-
 // SPE does not use FPRs, so break out the common register set as base.
 def CSR_SVR432_COMM : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20,
                                           R21, R22, R23, R24, R25, R26, R27,
                                           R28, R29, R30, R31, CR2, CR3, CR4
                                       )>;
 def CSR_SVR432 :  CalleeSavedRegs<(add CSR_SVR432_COMM, F14, F15, F16, F17, F18,
                                         F19, F20, F21, F22, F23, F24, F25, F26,
                                         F27, F28, F29, F30, F31
                                    )>;
 def CSR_SPE : CalleeSavedRegs<(add S14, S15, S16, S17, S18, S19, S20, S21, S22,
                                    S23, S24, S25, S26, S27, S28, S29, S30, S31
                               )>;
 
 def CSR_SVR432_Altivec : CalleeSavedRegs<(add CSR_SVR432, CSR_Altivec)>;
 
 def CSR_SVR432_SPE : CalleeSavedRegs<(add CSR_SVR432_COMM, CSR_SPE)>;
 
 def CSR_AIX32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
                                      R21, R22, R23, R24, R25, R26, R27, R28,
                                      R29, R30, R31, F14, F15, F16, F17, F18,
                                      F19, F20, F21, F22, F23, F24, F25, F26,
                                      F27, F28, F29, F30, F31, CR2, CR3, CR4
                                 )>;
 
-def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
-                                        X21, X22, X23, X24, X25, X26, X27, X28,
-                                        X29, X30, X31, F14, F15, F16, F17, F18,
-                                        F19, F20, F21, F22, F23, F24, F25, F26,
-                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
-                                   )>;
-
-def CSR_Darwin64_Altivec : CalleeSavedRegs<(add CSR_Darwin64, CSR_Altivec)>;
-
-def CSR_SVR464   : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
-                                        X21, X22, X23, X24, X25, X26, X27, X28,
-                                        X29, X30, X31, F14, F15, F16, F17, F18,
-                                        F19, F20, F21, F22, F23, F24, F25, F26,
-                                        F27, F28, F29, F30, F31, CR2, CR3, CR4
-                                   )>;
-
-def CSR_AIX64 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
+// Common CalleeSavedRegs for SVR4 and AIX.
+def CSR_PPC64   : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20,
                                         X21, X22, X23, X24, X25, X26, X27, X28,
                                         X29, X30, X31, F14, F15, F16, F17, F18,
                                         F19, F20, F21, F22, F23, F24, F25, F26,
                                         F27, F28, F29, F30, F31, CR2, CR3, CR4
                                    )>;
 
 // CSRs that are handled by prologue, epilogue.
 def CSR_SRV464_TLS_PE : CalleeSavedRegs<(add)>;
 
-def CSR_SVR464_ViaCopy : CalleeSavedRegs<(add CSR_SVR464)>;
+def CSR_SVR464_ViaCopy : CalleeSavedRegs<(add CSR_PPC64)>;
 
-def CSR_SVR464_Altivec : CalleeSavedRegs<(add CSR_SVR464, CSR_Altivec)>;
+def CSR_PPC64_Altivec : CalleeSavedRegs<(add CSR_PPC64, CSR_Altivec)>;
 
-def CSR_SVR464_Altivec_ViaCopy : CalleeSavedRegs<(add CSR_SVR464_Altivec)>;
+def CSR_SVR464_Altivec_ViaCopy : CalleeSavedRegs<(add CSR_PPC64_Altivec)>;
 
-def CSR_SVR464_R2 : CalleeSavedRegs<(add CSR_SVR464, X2)>;
+def CSR_PPC64_R2 : CalleeSavedRegs<(add CSR_PPC64, X2)>;
 
-def CSR_SVR464_R2_ViaCopy : CalleeSavedRegs<(add CSR_SVR464_R2)>;
+def CSR_SVR464_R2_ViaCopy : CalleeSavedRegs<(add CSR_PPC64_R2)>;
 
-def CSR_SVR464_R2_Altivec : CalleeSavedRegs<(add CSR_SVR464_Altivec, X2)>;
+def CSR_PPC64_R2_Altivec : CalleeSavedRegs<(add CSR_PPC64_Altivec, X2)>;
 
-def CSR_SVR464_R2_Altivec_ViaCopy : CalleeSavedRegs<(add CSR_SVR464_R2_Altivec)>;
+def CSR_SVR464_R2_Altivec_ViaCopy : CalleeSavedRegs<(add CSR_PPC64_R2_Altivec)>;
 
 def CSR_NoRegs : CalleeSavedRegs<(add)>;
 
 // coldcc calling convection marks most registers as non-volatile.
 // Do not include r1 since the stack pointer is never considered a CSR.
 // Do not include r2, since it is the TOC register and is added depending
 // on whether or not the function uses the TOC and is a non-leaf.
 // Do not include r0,r11,r13 as they are optional in functional linkage

llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp

 //===-- PPCRegisterInfo.cpp - PowerPC Register Information ----------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (Subtarget.hasAltivec())
       return CSR_SVR32_ColdCC_Altivec_SaveList;
     else if (Subtarget.hasSPE())
       return CSR_SVR32_ColdCC_SPE_SaveList;
     return CSR_SVR32_ColdCC_SaveList;
   }
   // Standard calling convention CSRs.
   if (TM.isPPC64()) {
     if (Subtarget.hasAltivec())
-      return SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
-                    : CSR_SVR464_Altivec_SaveList;
-    return SaveR2 ? CSR_SVR464_R2_SaveList
-                  : CSR_SVR464_SaveList;
+      return SaveR2 ? CSR_PPC64_R2_Altivec_SaveList
+                    : CSR_PPC64_Altivec_SaveList;
+    return SaveR2 ? CSR_PPC64_R2_SaveList : CSR_PPC64_SaveList;
   }
   // 32-bit targets.
   if (Subtarget.hasAltivec())
     return CSR_SVR432_Altivec_SaveList;
   else if (Subtarget.hasSPE())
     return CSR_SVR432_SPE_SaveList;
   return CSR_SVR432_SaveList;
 }
if (Subtarget.hasVSX())
       return CSR_64_AllRegs_VSX_RegMask;
     if (Subtarget.hasAltivec())
       return CSR_64_AllRegs_Altivec_RegMask;
     return CSR_64_AllRegs_RegMask;
   }
 
   if (Subtarget.isAIXABI()) {
     assert(!Subtarget.hasAltivec() && "Altivec is not implemented on AIX yet.");
-    return TM.isPPC64() ? CSR_AIX64_RegMask : CSR_AIX32_RegMask;
+    return TM.isPPC64() ? CSR_PPC64_RegMask : CSR_AIX32_RegMask;
   }
 
   if (CC == CallingConv::Cold) {
     return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR64_ColdCC_Altivec_RegMask
                                                   : CSR_SVR64_ColdCC_RegMask)
                         : (Subtarget.hasAltivec() ? CSR_SVR32_ColdCC_Altivec_RegMask
                                                   : (Subtarget.hasSPE()
                                                   ? CSR_SVR32_ColdCC_SPE_RegMask
                                                   : CSR_SVR32_ColdCC_RegMask));
   }
 
-  return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
-                                                : CSR_SVR464_RegMask)
-                      : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask
-                                                : (Subtarget.hasSPE()
-                                                  ? CSR_SVR432_SPE_RegMask
+  return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_PPC64_Altivec_RegMask
+                                                : CSR_PPC64_RegMask)
+                      : (Subtarget.hasAltivec()
+                             ? CSR_SVR432_Altivec_RegMask
+                             : (Subtarget.hasSPE() ? CSR_SVR432_SPE_RegMask
                                                    : CSR_SVR432_RegMask));
 }
 
 const uint32_t*
 PPCRegisterInfo::getNoPreservedMask() const {
   return CSR_NoRegs_RegMask;
 }
 
 void PPCRegisterInfo::adjustStackMapLiveOutMask(uint32_t *Mask) const {

llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessNoProfileData.mir

bb.4.if.then:
     INLINEASM &"#NOTHING", 1, 12, implicit-def early-clobber $r2
     ADJCALLSTACKDOWN 32, 0, implicit-def dead $r1, implicit $r1
     %14:g8rc = COPY $x2
     STD %14, 24, $x1 :: (store 8 into stack + 24)
     %15:g8rc = EXTSW_32_64 %7
     $x3 = COPY %15
     $x12 = COPY %3
     MTCTR8 %3, implicit-def $ctr8
-    BCTRL8_LDinto_toc 24, $x1, csr_svr464_altivec, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x3, implicit $x12, implicit $x2, implicit-def $r1
+    BCTRL8_LDinto_toc 24, $x1, csr_ppc64_altivec, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x3, implicit $x12, implicit $x2, implicit-def $r1
     ADJCALLSTACKUP 32, 0, implicit-def dead $r1, implicit $r1
 
   bb.5.for.inc:
     successors: %bb.2(0x013521d0), %bb.3(0x7ecade30)
 
     %2:gprc = nuw nsw ADDI %1, 1
     %16:crrc = CMPLW %8, %2
     BCC 76, killed %16, %bb.2

llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir

bb.4.if.then:
     INLINEASM &"#NOTHING", 1, 12, implicit-def early-clobber $r2, !31
     ADJCALLSTACKDOWN 32, 0, implicit-def dead $r1, implicit $r1
     %14:g8rc = COPY $x2
     STD %14, 24, $x1 :: (store 8 into stack + 24)
     %15:g8rc = EXTSW_32_64 %7
     $x3 = COPY %15
     $x12 = COPY %3
     MTCTR8 %3, implicit-def $ctr8
-    BCTRL8_LDinto_toc 24, $x1, csr_svr464_altivec, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x3, implicit $x12, implicit $x2, implicit-def $r1
+    BCTRL8_LDinto_toc 24, $x1, csr_ppc64_altivec, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x3, implicit $x12, implicit $x2, implicit-def $r1
     ADJCALLSTACKUP 32, 0, implicit-def dead $r1, implicit $r1
 
   bb.5.for.inc:
     successors: %bb.2(0x013521d0), %bb.3(0x7ecade30)
 
     %2:gprc = nuw nsw ADDI %1, 1
     %16:crrc = CMPLW %8, %2
     BCC 76, killed %16, %bb.2

llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir

bb.0.entry:
     $x1 = STDU $x1, -144, $x1
     STD killed $x29, 120, $x1 :: (store 8 into %fixed-stack.1)
     STD killed $x30, 128, $x1 :: (store 8 into %fixed-stack.0, align 16)
     $x30 = OR8 $x4, $x4
     $x3 = LD 0, killed $x3 :: (load 8 from %ir.p1)
     $x29 = ADDI8 killed $x3, -48
     $x3 = ADDIStocHA8 $x2, @tasklist_lock
     $x3 = LDtocL @tasklist_lock, killed $x3, implicit $x2 :: (load 8 from got)
-    BL8_NOP @__raw_read_unlock, csr_svr464_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
+    BL8_NOP @__raw_read_unlock, csr_ppc64_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
     $r3 = LI 0
     STW killed $r3, 0, killed $x30 :: (volatile store 4 into %ir.p2)
     INLINEASM &"#compiler barrier", 25
     INLINEASM &"\0Alwsync \0A1:\09lwarx\09$0,0,$1\09\09# atomic_dec_return\0A\09addic\09$0,$0,-1\0A\09stwcx.\09$0,0,$1\0A\09bne-\091b\0Async \0A", 25, 131083, def early-clobber $r3, 851977, killed $x29, 12, implicit-def dead early-clobber $cr0
     ; CHECK-LABEL: @mm_update_next_owner
     ; CHECK-NOT: lwarx 29, 0, 29
     ; CHECK-NOT: stwcx. 29, 0, 29
     $cr0 = CMPLWI killed $r3, 0
     $x30 = LD 128, $x1 :: (load 8 from %fixed-stack.0, align 16)
     $x29 = LD 120, $x1 :: (load 8 from %fixed-stack.1)
     $x1 = ADDI8 $x1, 144
     $x0 = LD 16, $x1
     MTLR8 $x0, implicit-def $lr8
     BLR8 implicit $lr8, implicit $rm
 
 ...

llvm/test/CodeGen/PowerPC/aix-cc-abi.ll

 ; 32BIT: BL_NOP <mcsymbol .test_chars>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit $r2, implicit-def $r1
 ; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT: $x3 = LI8 97
 ; 64BIT: $x4 = LI8 97
 ; 64BIT: $x5 = LI8 97
 ; 64BIT: $x6 = LI8 97
-; 64BIT: BL8_NOP <mcsymbol .test_chars>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1
+; 64BIT: BL8_NOP <mcsymbol .test_chars>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1
 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 define signext i8 @test_chars(i8 signext %c1, i8 signext %c2, i8 signext %c3, i8 signext %c4) {
 entry:
   %conv = sext i8 %c1 to i32
   %conv1 = sext i8 %c2 to i32
   %add = add nsw i32 %conv, %conv1
   %conv2 = sext i8 %c3 to i32

 ; 32BIT: BL_NOP <mcsymbol .test_chars_mix>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit $r2, implicit-def $r1
 ; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT: $x3 = LI8 97
 ; 64BIT: $x4 = LI8 225
 ; 64BIT: $x5 = LI8 97
 ; 64BIT: $x6 = LI8 -31
-; 64BIT: BL8_NOP <mcsymbol .test_chars_mix>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1
+; 64BIT: BL8_NOP <mcsymbol .test_chars_mix>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1
 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 define signext i8 @test_chars_mix(i8 signext %c1, i8 zeroext %c2, i8 zeroext %c3, i8 signext %c4) {
 entry:
   %conv = sext i8 %c1 to i32
   %conv1 = zext i8 %c2 to i32
   %add = add nsw i32 %conv, %conv1
   %conv2 = zext i8 %c3 to i32

 
 ; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT: $r3 = LI 1
 ; 32BIT: BL_NOP <mcsymbol .test_i1>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit $r2, implicit-def $r1
 ; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT: $x3 = LI8 1
-; 64BIT: BL8_NOP <mcsymbol .test_i1>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1
+; 64BIT: BL8_NOP <mcsymbol .test_i1>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1
 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 define void @test_i1zext(i1 zeroext %b) {
   entry:
     %frombool = zext i1 %b to i8
     store i8 %frombool, i8 * @global_i1, align 1
     ret void
   }

 ; 64BIT: renamable $x5 = RLDICR killed renamable $x3, 31, 32
 ; 64BIT: $x3 = LI8 1
 ; 64BIT: $x4 = LI8 1
 ; 64BIT: $x6 = LIS8 32768
 ; 64BIT: $x7 = LI8 1
 ; 64BIT: $x8 = LI8 1
 ; 64BIT: $x9 = LI8 1
 ; 64BIT: $x10 = LI8 1
-; 64BIT:  BL8_NOP <mcsymbol .test_ints>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3
+; 64BIT:  BL8_NOP <mcsymbol .test_ints>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3
 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 define void @call_test_i64() {
 entry:
   call i64 @test_i64(i64 1, i64 2, i64 3, i64 4)
   ret void
 }
 

 ; 32BIT: BL_NOP <mcsymbol .test_i64>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $r2, implicit-def $r1
 ; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT: $x3 = LI8 1
 ; 64BIT: $x4 = LI8 2
 ; 64BIT: $x5 = LI8 3
 ; 64BIT: $x6 = LI8 4
-; 64BIT: BL8_NOP <mcsymbol .test_i64>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1
+; 64BIT: BL8_NOP <mcsymbol .test_i64>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1
 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 define i64 @test_i64(i64 %a, i64 %b, i64 %c, i64 %d) {
 entry:
   %add = add nsw i64 %a, %b
   %add1 = add nsw i64 %add, %c
   %add2 = add nsw i64 %add1, %d
   ret i64 %add2

 
 ; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT: renamable $r3 = ADDI %stack.0.b, 0
 ; 32BIT: BL_NOP <mcsymbol .test_int_ptr>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
 ; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT: renamable $x3 = ADDI8 %stack.0.b, 0
-; 64BIT: BL8_NOP <mcsymbol .test_int_ptr>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT: BL8_NOP <mcsymbol .test_int_ptr>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 define void @test_int_ptr(i32* %a) {
 entry:
   %a.addr = alloca i32*, align 8
   store i32* %a, i32** %a.addr, align 8
   ret void
 }

 ; 32BIT:          ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; 64BIT:        liveins:
 ; 64BIT-NEXT:   - { reg: '$x3', virtual-reg: '' }
 ; 64BIT:        body:             |
 ; 64BIT-NEXT:    bb.0.entry:
 ; 64BIT-NEXT:     liveins: $x3
 ; 64BIT:          ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT:          BL8_NOP <mcsymbol .call_test_bool>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def $x3
+; 64BIT:          BL8_NOP <mcsymbol .call_test_bool>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def $x3
 ; 64BIT:          ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 @f1 = global float 0.000000e+00, align 4
 @d1 = global double 0.000000e+00, align 8
 
 define void @call_test_floats() {
 entry:
   %0 = load float, float* @f1, align 4

 ; 32BIT-NEXT: BL_NOP <mcsymbol .test_floats>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit $r2, implicit-def $r1
 ; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; 64BIT:      renamable $x3 = LDtoc @f1, $x2 :: (load 8 from got)
 ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x3 :: (dereferenceable load 4 from @f1)
 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT: $f2 = COPY renamable $f1
 ; 64BIT-NEXT: $f3 = COPY renamable $f1
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_floats>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_floats>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 define float @test_floats(float %f1, float %f2, float %f3) {
 entry:
   %add = fadd float %f1, %f2
   %add1 = fadd float %add, %f3
   ret float %add1
 }

 ; 64BIT-DAG:  $f6 = COPY renamable $f1
 ; 64BIT-DAG:  $f7 = COPY renamable $f1
 ; 64BIT-DAG:  $f8 = COPY renamable $f1
 ; 64BIT-DAG:  $f9 = COPY renamable $f1
 ; 64BIT-DAG:  $f10 = COPY renamable $f1
 ; 64BIT-DAG:  $f11 = COPY renamable $f1
 ; 64BIT-DAG:  $f12 = COPY renamable $f1
 ; 64BIT-DAG:  $f13 = COPY renamable $f1
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_fpr_max>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_fpr_max>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT: ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:       stdu 1, -160(1)
 ; ASM64PWR4-NEXT:  ld [[REG:[0-9]+]], LC2(2)
 ; ASM64PWR4-NEXT:  lfd 1, 0([[REG]])
 ; ASM64PWR4-DAG:   stfd 1, 112(1)
 ; ASM64PWR4-DAG:   stfd 1, 120(1)
 ; ASM64PWR4-DAG:   stfd 1, 128(1)

 
 ; 64BIT:      renamable $x[[REG1:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got)
 ; 64BIT-NEXT: renamable $x[[REG2:[0-9]+]] = LDtoc @d1, $x2 :: (load 8 from got)
 ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG1]] :: (dereferenceable load 4 from @f1)
 ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG2]] :: (dereferenceable load 8 from @d1)
 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT: $x4 = LI8 1
 ; 64BIT-NEXT: $x6 = LI8 97
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_mix>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $x4, implicit $f2, implicit killed $x6, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_mix>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $x4, implicit $f2, implicit killed $x6, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 define i32 @test_mix(float %f, i32 signext %i, double %d, i8 signext %c) {
 entry:
   %conv = fpext float %f to double
   %add = fadd double %conv, %d
   %conv1 = fptrunc double %add to float
   %conv2 = zext i8 %c to i32

 ; 64BIT-NEXT: renamable $x[[REG:[0-9]+]] = LDtoc @d1, $x2 :: (load 8 from got)
 ; 64BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store 8 into %stack.[[SLOT1]])
 ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d1)
 ; 64BIT-NEXT: renamable $x4 = LD 0, %stack.[[SLOT1]] :: (load 8 from %stack.[[SLOT1]])
 ; 64BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]])
 ; 64BIT-NEXT: renamable $x5 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]])
 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT: $x3 = LI8 42
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $f2, implicit $x5, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $f2, implicit $x5, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:      stdu 1, -128(1)
 ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC1(2)
 ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
 ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC2(2)
 ; ASM64PWR4-NEXT: stfd 1, 112(1)
 ; ASM64PWR4-NEXT: lfd 2, 0([[REG]])

 ; 64BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store 8 into %stack.[[SLOT1]])
 ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d1)
 ; 64BIT-NEXT: renamable $x4 = LD 0, %stack.[[SLOT1]] :: (load 8 from %stack.[[SLOT1]])
 ; 64BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]])
 ; 64BIT-NEXT: renamable $x6 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]])
 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT: $x3 = LI8 42
 ; 64BIT-NEXT: $x5 = LI8 42
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:      stdu 1, -128(1)
 ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC1(2)
 ; ASM64PWR4-NEXT: li 5, 42
 ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
 ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC2(2)
 ; ASM64PWR4-NEXT: stfd 1, 112(1)

 ; 64BIT-NEXT: STFD renamable $f1, 0, %stack.[[SLOT1:[0-9]+]] :: (store 8 into %stack.[[SLOT1]])
 ; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d1)
 ; 64BIT-NEXT: renamable $x4 = LD 0, %stack.[[SLOT1]] :: (load 8 from %stack.[[SLOT1]])
 ; 64BIT-NEXT: STFD renamable $f2, 0, %stack.[[SLOT2:[0-9]+]] :: (store 8 into %stack.[[SLOT2]])
 ; 64BIT-NEXT: renamable $x6 = LD 0, %stack.[[SLOT2]] :: (load 8 from %stack.[[SLOT2]])
 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT: $x3 = LI8 42
 ; 64BIT-NEXT: $x5 = LI8 42
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit killed $x5, implicit $f2, implicit $x6, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:      stdu 1, -128(1)
 ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC1(2)
 ; ASM64PWR4-NEXT: li 5, 42
 ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
 ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC2(2)
 ; ASM64PWR4-NEXT: stfd 1, 112(1)

 ; ASM32PWR4-NEXT: nop
 
 ; 64BIT:      renamable $x[[REG:[0-9]+]] = LDtoc @f1, $x2 :: (load 8 from got)
 ; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x[[REG]] :: (dereferenceable load 4 from @f1)
 ; 64BIT-NEXT: STFS renamable $f1, 0, %stack.[[SLOT:[0-9]+]] :: (store 4 into %stack.[[SLOT]])
 ; 64BIT-NEXT: renamable $x4 = LWZ8 0, %stack.[[SLOT]] :: (load 4 from %stack.[[SLOT]])
 ; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT: $x3 = LI8 42
-; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_vararg>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $f1, implicit $x4, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64PWR4:      stdu 1, -128(1)
 ; ASM64PWR4-NEXT: ld [[REG:[0-9]+]], LC1(2)
 ; ASM64PWR4-NEXT: lfs 1, 0([[REG]])
 ; ASM64PWR4-NEXT: li 3, 42
 ; ASM64PWR4-NEXT: stfs 1, 124(1)
 ; ASM64PWR4-NEXT: lwz 4, 124(1)

 ; 64BIT-DAG:   STD killed renamable $x[[REGSI]], 120, $x1 :: (store 8)
 ; 64BIT-DAG:   renamable $x[[REGIADDR:[0-9]+]] = LDtoc @i, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $x[[REGI:[0-9]+]] = LWZ8 0, killed renamable $x[[REGIADDR]] :: (dereferenceable load 4 from @i)
 ; 64BIT-DAG:   STD killed renamable $x[[REGI]], 128, $x1 :: (store 8)
 ; 64BIT-DAG:   renamable $x[[REGLLIADDR:[0-9]+]] = LDtoc @lli, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $x[[REGLLI:[0-9]+]] = LD 0, killed renamable $x[[REGLLIADDR]] :: (dereferenceable load 8 from @lli)
 ; 64BIT-DAG:   STD killed renamable $x[[REGLLI]], 136, $x1 :: (store 8)
 ; 64BIT-DAG:   STD renamable $x[[REGI]], 144, $x1 :: (store 8)
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_stackarg_int>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_stackarg_int>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 152, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64PWR4-DAG:   stdu 1, -160(1)
 ; ASM64PWR4-DAG:   li 3, 1
 ; ASM64PWR4-DAG:   li 4, 2
 ; ASM64PWR4-DAG:   li 5, 3
 ; ASM64PWR4-DAG:   li 6, 4

 ; 64BIT-DAG:   $x9 = LI8 7
 ; 64BIT-DAG:   $x10 = LI8 8
 ; 64BIT-DAG:   renamable $x[[REGF:[0-9]+]] = LDtoc @f, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $f1 = LFS 0, killed renamable $x[[REGF]] :: (dereferenceable load 4 from @f)
 ; 64BIT-DAG:   renamable $x[[REGD:[0-9]+]] = LDtoc @d, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $f2 = LFD 0, killed renamable $x[[REGD]] :: (dereferenceable load 8 from @d)
 ; 64BIT-DAG:   STFS renamable $f1, 112, $x1 :: (store 4)
 ; 64BIT-DAG:   STFD renamable $f2, 120, $x1 :: (store 8)
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_stackarg_float>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $f1, implicit $f2, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_stackarg_float>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $f1, implicit $f2, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 128, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64PWR4:      stdu 1, -128(1)
 ; ASM64PWR4-DAG:  li 3, 1
 ; ASM64PWR4-DAG:  li 4, 2
 ; ASM64PWR4-DAG:  li 5, 3
 ; ASM64PWR4-DAG:  li 6, 4

 ; 64BIT-DAG:   $x5 = LI8 3
 ; 64BIT-DAG:   $x6 = LI8 4
 ; 64BIT-DAG:   $x7 = LI8 5
 ; 64BIT-DAG:   $x8 = LI8 6
 ; 64BIT-DAG:   renamable $x[[REG:[0-9]+]] = LDtoc @d, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $f1 = LFD 0, killed renamable $x[[REG]] :: (dereferenceable load 8 from @d)
 ; 64BIT-DAG:   STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0)
 ; 64BIT-DAG:   renamable $x9 = LD 0, %stack.0 :: (load 8 from %stack.0)
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_stackarg_float2>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit $f1, implicit $x9, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_stackarg_float2>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit $f1, implicit $x9, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64PWR4:     stdu 1, -128(1)
 ; ASM64PWR4-DAG: li 3, 1
 ; ASM64PWR4-DAG: li 4, 2
 ; ASM64PWR4-DAG: li 5, 3
 ; ASM64PWR4-DAG: li 6, 4

 ; 64BIT-DAG:   $x9 = LI8 7
 ; 64BIT-DAG:   renamable $x[[REGD:[0-9]+]] = LDtoc @d, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $f1 = LFD 0, killed renamable $x[[REGD]] :: (dereferenceable load 8 from @d)
 ; 64BIT-DAG:   renamable $x[[REGF:[0-9]+]] = LDtoc @f, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $f2 = LFS 0, killed renamable $x[[REGF]] :: (dereferenceable load 4 from @f)
 ; 64BIT-DAG:   STFS renamable $f2, 112, $x1 :: (store 4)
 ; 64BIT-DAG:   STFD renamable $f1, 0, %stack.0 :: (store 8 into %stack.0)
 ; 64BIT-DAG:   renamable $x10 = LD 0, %stack.0 :: (load 8 from %stack.0)
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_stackarg_float3>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $f1, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_stackarg_float3>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit $f1, implicit $x10, implicit $f2, implicit $x2, implicit-def $r1
 
 ; 64BIT-NEXT: ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64PWR4:       stdu 1, -128(1)
 ; ASM64PWR4-DAG:   li 3, 1
 ; ASM64PWR4-DAG:   li 4, 2
 ; ASM64PWR4-DAG:   li 5, 3

 ; 64BIT-DAG:   STD killed renamable $x[[REGLL2]], 152, $x1 :: (store 8)
 ; 64BIT-DAG:   renamable $x[[REGUCADDR:[0-9]+]] = LDtoc @uc1, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $x[[REGUC:[0-9]+]] = LBZ8 0, killed renamable $x[[REGUCADDR]] :: (dereferenceable load 1 from @uc1)
 ; 64BIT-DAG:   STD killed renamable $x[[REGUC]], 160, $x1 :: (store 8)
 ; 64BIT-DAG:   renamable $x[[REGIADDR:[0-9]+]] = LDtoc @i1, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $x[[REGI:[0-9]+]] = LWZ8 0, killed renamable $x[[REGIADDR]] :: (dereferenceable load 4 from @i1)
 ; 64BIT-DAG:   STD killed renamable $x[[REGI]], 168, $x1 :: (store 8)
 ; 64BIT-DAG:   ADJCALLSTACKDOWN 176, 0, implicit-def dead $r1, implicit $r1
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_ints_stack>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_ints_stack>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3
 ; 64BIT-NEXT:  ADJCALLSTACKUP 176, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:  BLR8 implicit $lr8, implicit $rm
 
 ; CHECKASM-LABEL:  .caller_ints_stack:
 
 ; ASM32PWR4:        mflr 0
 ; ASM32PWR4-DAG:    stw 0, 8(1)
 ; ASM32PWR4-DAG:    stwu 1, -96(1)

 ; 64BIT-DAG:  $x5 = LI8 3
 ; 64BIT-DAG:  $x6 = LI8 4
 ; 64BIT-DAG:  $x7 = LI8 5
 ; 64BIT-DAG:  $x8 = LI8 6
 ; 64BIT-DAG:  $x9 = LI8 7
 ; 64BIT-DAG:  $x10 = LI8 8
 ; 64BIT-DAG:  renamable $x[[REGBOOLADDR:[0-9]+]] = LI8 1
 ; 64BIT-DAG:  STD killed renamable $x[[REGBOOLADDR]], 112, $x1 :: (store 8)
-; 64BIT-DAG:  BL8_NOP <mcsymbol .test_i1_stack>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
+; 64BIT-DAG:  BL8_NOP <mcsymbol .test_i1_stack>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $x2, implicit-def $r1
 ; 64BIT-DAG:  ADJCALLSTACKUP 120, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .call_test_i1_stack:
 
 ; ASM32PWR4-DAG:   mflr 0
 ; ASM32PWR4-DAG:   li 3, 1
 ; ASM32PWR4-DAG:   li 4, 2
 ; ASM32PWR4-DAG:   li 5, 3

 ; 64BIT-DAG:   renamable $f6 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load 8 from constant-pool)
 ; 64BIT-DAG:   renamable $f7 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load 8 from constant-pool)
 ; 64BIT-DAG:   renamable $f8 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load 8 from constant-pool)
 ; 64BIT-DAG:   renamable $f9 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load 8 from constant-pool)
 ; 64BIT-DAG:   $f10 = COPY renamable $f1
 ; 64BIT-DAG:   renamable $f11 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load 8 from constant-pool)
 ; 64BIT-DAG:   renamable $f12 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load 8 from constant-pool)
 ; 64BIT-DAG:   renamable $f13 = LFD 0, killed renamable $x[[SCRATCHREG:[0-9]+]] :: (load 8 from constant-pool)
-; 64BIT-DAG:   BL8_NOP <mcsymbol .test_fpr_stack>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit killed $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $f1
+; 64BIT-DAG:   BL8_NOP <mcsymbol .test_fpr_stack>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit killed $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $f1
 ; 64BIT-NEXT:   ADJCALLSTACKUP 176, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:   BLR8 implicit $lr8, implicit $rm
 
 ; CHECKASM-LABEL:  .caller_fpr_stack:
 
 ; ASM32PWR4:       mflr 0
 ; ASM32PWR4-DAG:   stw 0, 8(1)
 ; ASM32PWR4-DAG:   stwu 1, -144(1)

 ; 64BIT-DAG:   STD killed renamable $x[[REG7:[0-9]+]], 160, $x1 :: (store 8)
 ; 64BIT-DAG:   STD killed renamable $x[[REG8:[0-9]+]], 168, $x1 :: (store 8)
 ; 64BIT-DAG:   STD killed renamable $x[[REG9:[0-9]+]], 176, $x1 :: (store 8)
 ; 64BIT-DAG:   STD killed renamable $x[[REG10:[0-9]+]], 184, $x1 :: (store 8)
 ; 64BIT-DAG:   STD killed renamable $x[[REG12:[0-9]+]], 192, $x1 :: (store 8)
 ; 64BIT-DAG:   STD killed renamable $x[[REG13:[0-9]+]], 200, $x1 :: (store 8)
 ; 64BIT-DAG:   STD killed renamable $x[[REG14:[0-9]+]], 208, $x1 :: (store 8)
 ; 64BIT-DAG:   STD killed renamable $x[[REG15:[0-9]+]], 216, $x1 :: (store 8)
-; 64BIT-DAG:   BL8_NOP <mcsymbol .mix_floats>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $x3
+; 64BIT-DAG:   BL8_NOP <mcsymbol .mix_floats>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7, implicit $x8, implicit $x9, implicit $x10, implicit $f1, implicit $f2, implicit $f3, implicit $f4, implicit $f5, implicit $f6, implicit $f7, implicit $f8, implicit $f9, implicit $f10, implicit $f11, implicit $f12, implicit $f13, implicit $x2, implicit-def $r1, implicit-def dead $x3
 ; 64BIT-NEXT:  ADJCALLSTACKUP 224, 0, implicit-def dead $r1, implicit $r1
 
 ; CHEKASM-LABEL:    .mix_floats_caller:
 
 ; ASM32PWR4:       mflr 0
 ; ASM32PWR4-DAG:   stw 0, 8(1)
 ; ASM32PWR4-DAG:   stwu 1, -176(1)
 ; ASM32PWR4-DAG:   stw [[REG:[0-9]+]], 56(1)

llvm/test/CodeGen/PowerPC/aix-cc-byval.ll

 ; ASM32-NEXT:  bl .test_byval_1Byte
 ; ASM32-NEXT:  nop
 ; ASM32-NEXT:  addi 1, 1, 64
 
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:  renamable $x[[REG:[0-9]+]] = LDtoc @gS1, $x2 :: (load 8 from got)
 ; 64BIT-NEXT:  renamable $x3 = LBZ8 0, killed renamable $x[[REG]] :: (load 1)
 ; 64BIT-NEXT:  renamable $x3 = RLDICR killed renamable $x3, 56, 7
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_1Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_1Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64:       std 0, 16(1)
 ; ASM64-NEXT:  stdu 1, -128(1)
 ; ASM64-NEXT:  ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM64-NEXT:  lbz 3, 0([[REG]])
 ; ASM64-NEXT:  sldi 3, 3, 56
 ; ASM64-NEXT:  bl .test_byval_1Byte

 ; ASM32-NEXT:  bl .test_byval_2Byte
 ; ASM32-NEXT:  nop
 ; ASM32-NEXT:  addi 1, 1, 64
 
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:  renamable $x[[REG:[0-9]+]] = LDtoc @gS2, $x2 :: (load 8 from got)
 ; 64BIT-NEXT:  renamable $x3 = LHZ8 0, killed renamable $x[[REG]] :: (load 2)
 ; 64BIT-NEXT:  renamable $x3 = RLDICR killed renamable $x3, 48, 15
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_2Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_2Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64:       std 0, 16(1)
 ; ASM64-NEXT:  stdu 1, -112(1)
 ; ASM64-NEXT:  ld [[REG:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM64-NEXT:  lhz 3, 0([[REG]])
 ; ASM64-NEXT:  sldi 3, 3, 48
 ; ASM64-NEXT:  bl .test_byval_2Byte

 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-DAG:   renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS3, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $x[[REG1:[0-9]+]] = LHZ8 0, killed renamable $x[[REGADDR]] :: (load 2)
 ; 64BIT-DAG:   renamable $x[[REG2:[0-9]+]] = LBZ8 2, renamable $x[[REGADDR]] :: (load 1)
 ; 64BIT-DAG:   renamable $x3 = RLDIC killed renamable $x[[REG2]], 40, 16
 ; 64BIT-DAG:   renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 48, 0
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_3Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_3Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM64:       stdu 1, -112(1)
 ; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM64-DAG:   lhz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lbz [[REG2:[0-9]+]], 2([[REGADDR]])
 ; ASM64-DAG:   rldic 3, [[REG2]], 40, 16

 ; ASM32-NEXT:  addi 1, 1, 80
 
 ; 64BIT:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; 64BIT-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS4, $x2 :: (load 8 from got)
 ; 64BIT-DAG:   renamable $x[[LD1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
 ; 64BIT-DAG:   renamable $x[[LD2:[0-9]+]] = LWZ8 0, %stack.1.s4a :: (load 4 from %stack.1.s4a, align 8)
 ; 64BIT-DAG:   renamable $x3 = RLDICR killed renamable $x[[LD1]], 32, 31
 ; 64BIT-DAG:   renamable $x4 = RLDICR killed renamable $x[[LD2]], 32, 31
-; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_4Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3,  implicit $x4, implicit $x2, implicit-def $r1
+; 64BIT-NEXT:  BL8_NOP <mcsymbol .test_byval_4Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3,  implicit $x4, implicit $x2, implicit-def $r1
 ; 64BIT-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM64:       stdu 1, -128(1)
 ; ASM64-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM64-DAG:   lwz [[LD1:[0-9]+]], 0([[REGADDR]])
 ; ASM64-DAG:   lwz [[LD2:[0-9]+]], 112(1)
 ; ASM64-DAG:   sldi 3, [[LD1]], 32
 ; ASM64-DAG:   sldi 4, [[LD2]], 32

llvm/test/CodeGen/PowerPC/aix-indirect-call.ll

 
 ; MIR64:      liveins: $x3
 ; MIR64:      ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; MIR64-DAG:  STD $x2, 40, $x1 :: (store 8 into stack + 40)
 ; MIR64-DAG:  renamable $x11 = LD 16, renamable $x3 :: (dereferenceable invariant load 8 from %ir.0 + 16)
 ; MIR64-DAG:  renamable $[[REG:x[0-9]+]] = LD 0, renamable $x3 :: (dereferenceable invariant load 8 from %ir.0)
 ; MIR64-DAG:  $x2 = LD 8, killed renamable $x3 :: (dereferenceable invariant load 8 from %ir.0 + 8)
 ; MIR64-DAG:  MTCTR8 killed renamable $[[REG]], implicit-def $ctr8
-; MIR64-NEXT: BCTRL8_LDinto_toc 40, $x1, csr_aix64, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x11, implicit $x2, implicit-def $r1, implicit-def $x3
+; MIR64-NEXT: BCTRL8_LDinto_toc 40, $x1, csr_ppc64, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x11, implicit $x2, implicit-def $r1, implicit-def $x3
 ; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .callThroughPtr:
 
 ; ASM32:         stwu 1, -64(1)
 ; ASM32-DAG:     lwz [[REG:[0-9]+]], 0(3)
 ; ASM32-DAG:     stw 2, 20(1)
 ; ASM32-DAG:     mtctr [[REG]]

 ; MIR64-DAG:  renamable $[[REG:x[0-9]+]] = LD 0, renamable $x3 :: (dereferenceable invariant load 8 from %ir.0)
 ; MIR64-DAG:  MTCTR8 killed renamable $[[REG]], implicit-def $ctr8
 ; MIR64-DAG:  STD $x2, 40, $x1 :: (store 8 into stack + 40)
 ; MIR64-DAG:  renamable $x11 = LD 16, renamable $x3 :: (dereferenceable invariant load 8 from %ir.0 + 16)
 ; MIR64-DAG:  $x2 = LD 8, killed renamable $x3 :: (dereferenceable invariant load 8 from %ir.0 + 8)
 ; MIR64-DAG:  $x3 = LI8 1
 ; MIR64-DAG:  $x4 = LI8 2
 ; MIR64-DAG:  $x5 = LI8 3
-; MIR64-NEXT: BCTRL8_LDinto_toc 40, $x1, csr_aix64, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x11, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1
+; MIR64-NEXT: BCTRL8_LDinto_toc 40, $x1, csr_ppc64, implicit-def dead $lr8, implicit-def dead $x2, implicit $ctr8, implicit $rm, implicit $x11, implicit $x3, implicit $x4, implicit $x5, implicit $x2, implicit-def $r1
 ; MIR64-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECKASM-LABEL: .callThroughPtrWithArgs:
 ; CHECKOBJ-LABEL: <.callThroughPtrWithArgs>:
 
 ; ASMOBJ32:      stwu 1, -64(1)
 ; ASMOBJ32-DAG:  lwz [[REG:[0-9]+]], 0(3)
 ; ASMOBJ32-DAG:  li 5, 0

llvm/test/CodeGen/PowerPC/aix-sret-param.ll

 ; MIR32-NEXT:   ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; MIR32-NEXT:   renamable $r3 = ADDI %stack.0.s, 0
 ; MIR32-NEXT:   BL_NOP <mcsymbol .foo>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
 ; MIR32-NEXT:   ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; MIR64:      bb.0.entry:
 ; MIR64-NEXT:   ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; MIR64-NEXT:   renamable $x3 = ADDI8 %stack.0.s, 0
-; MIR64-NEXT:   BL8_NOP <mcsymbol .foo>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; MIR64-NEXT:   BL8_NOP <mcsymbol .foo>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; MIR64-NEXT:   ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 
 ; ASM-LABEL: .test1:
 
 ; ASM32:       stwu 1, -64(1)
 ; ASM32-NEXT:  addi 3, 1, 56
 ; ASM32-NEXT:  bl .foo

 ; MIR32-NEXT:    ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; MIR32-NEXT:    renamable $r3 = ADDI %stack.0.t, 0
 ; MIR32-NEXT:    BL_NOP <mcsymbol .bar>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
 ; MIR32-NEXT:    ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; MIR64:      bb.0.entry:
 ; MIR64-NEXT:   ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; MIR64-NEXT:   renamable $x3 = ADDI8 %stack.0.t, 0
-; MIR64-NEXT:   BL8_NOP <mcsymbol .bar>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; MIR64-NEXT:   BL8_NOP <mcsymbol .bar>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; MIR64-NEXT:   ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 
 ; ASM-LABEL: .test2:
 
 ; ASM32:        stwu 1, -80(1)
 ; ASM32-NEXT:   addi 3, 1, 56
 ; ASM32-NEXT:   bl .bar

llvm/test/CodeGen/PowerPC/aix64-cc-byval.ll

 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; CHECK:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; CHECK-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS5, $x2 :: (load 8 from got)
 ; CHECK-DAG:   renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
 ; CHECK-DAG:   renamable $x[[REG2:[0-9]+]] = LBZ8 4, renamable $x[[REGADDR]] :: (load 1)
 ; CHECK-DAG:   renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 24, 0, 7
 ; CHECK-DAG:   renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
-; CHECK-NEXT:  BL8_NOP <mcsymbol .test_byval_5Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; CHECK-NEXT:  BL8_NOP <mcsymbol .test_byval_5Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; CHECK-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM:       stdu 1, -112(1)
 ; ASM-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM-DAG:   lbz [[REG2:[0-9]+]], 4([[REGADDR]])
 ; ASM-DAG:   rlwinm 3, [[REG2]], 24, 0, 7

 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; CHECK:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; CHECK-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS6, $x2 :: (load 8 from got)
 ; CHECK-DAG:   renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
 ; CHECK-DAG:   renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
 ; CHECK-DAG:   renamable $x3 = RLWINM8 killed renamable $x[[REG2]], 16, 0, 15
 ; CHECK-DAG:   renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
-; CHECK-NEXT:  BL8_NOP <mcsymbol .test_byval_6Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; CHECK-NEXT:  BL8_NOP <mcsymbol .test_byval_6Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; CHECK-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM:       stdu 1, -112(1)
 ; ASM-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM-DAG:   lhz [[REG2:[0-9]+]], 4([[REGADDR]])
 ; ASM-DAG:   rlwinm 3, [[REG2]], 16, 0, 15

 ; CHECK:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; CHECK-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS7, $x2 :: (load 8 from got)
 ; CHECK-DAG:   renamable $x[[REG1:[0-9]+]] = LWZ8 0, killed renamable $x[[REGADDR]] :: (load 4)
 ; CHECK-DAG:   renamable $x[[REG2:[0-9]+]] = LHZ8 4, renamable $x[[REGADDR]] :: (load 2)
 ; CHECK-DAG:   renamable $x[[REG3:[0-9]+]] = LBZ8 6, renamable $x[[REGADDR]] :: (load 1)
 ; CHECK-DAG:   renamable $x3 = RLWINM8 killed renamable $x[[REG3]], 8, 16, 23
 ; CHECK-DAG:   renamable $x3 = RLWIMI8 killed renamable $x3, killed renamable $x[[REG2]], 16, 0, 15
 ; CHECK-DAG:   renamable $x3 = RLDIMI killed renamable $x3, killed renamable $x[[REG1]], 32, 0
-; CHECK-NEXT:  BL8_NOP <mcsymbol .test_byval_7Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; CHECK-NEXT:  BL8_NOP <mcsymbol .test_byval_7Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; CHECK-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; The DAG block permits some invalid inputs for the benefit of allowing more valid orderings.
 ; ASM:       stdu 1, -112(1)
 ; ASM-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM-DAG:   lwz [[REG1:[0-9]+]], 0([[REGADDR]])
 ; ASM-DAG:   lhz [[REG2:[0-9]+]], 4([[REGADDR]])
 ; ASM-DAG:   lbz [[REG3:[0-9]+]], 6([[REGADDR]])

 
 ; CHECK-LABEL: name: call_test_byval_8Byte{{.*}}
 
 ; ASM-LABEL: .call_test_byval_8Byte:
 
 ; CHECK:       ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
 ; CHECK-NEXT:  renamable $x[[REGADDR:[0-9]+]] = LDtoc @gS8, $x2 :: (load 8 from got)
 ; CHECK-NEXT:  renamable $x3 = LD 0, killed renamable $x[[REGADDR]] :: (load 8)
-; CHECK-NEXT:  BL8_NOP <mcsymbol .test_byval_8Byte>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; CHECK-NEXT:  BL8_NOP <mcsymbol .test_byval_8Byte>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
 ; CHECK-NEXT:  ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; ASM:       stdu 1, -112(1)
 ; ASM-NEXT:  ld [[REGADDR:[0-9]+]], LC{{[0-9]+}}(2)
 ; ASM-NEXT:  ld 3, 0([[REGADDR]])
 ; ASM-NEXT:  bl .test_byval_8Byte
 ; ASM-NEXT:  nop
 

llvm/test/CodeGen/PowerPC/block-placement-1.mir

 machineFunctionInfo: {}
 body:             |
   bb.0.entry:
     $x0 = MFLR8 implicit $lr8
     STD killed $x0, 16, $x1
     $x1 = STDU $x1, -32, $x1
     CFI_INSTRUCTION def_cfa_offset 32
     CFI_INSTRUCTION offset $lr8, 16
-    BL8_NOP @__cxa_rethrow, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1
+    BL8_NOP @__cxa_rethrow, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1
 
 ...
 ---
 name:            _Z14TestSinglePredv
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
bb.0.entry:
     $x1 = STDU $x1, -64, $x1
     renamable $r29 = LI 10
   
   bb.1.for.body:
     successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
     liveins: $r29
   
     EH_LABEL <mcsymbol .Ltmp0>
-    BL8_NOP @__cxa_rethrow, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1
+    BL8_NOP @__cxa_rethrow, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1
     EH_LABEL <mcsymbol .Ltmp1>
   
   bb.2..noexc:
     successors: 
   
   
   bb.3.lpad (landing-pad):
     successors: %bb.4(0x00000001), %bb.5(0x7fffffff)
     liveins: $r29, $x3, $x4
   
     EH_LABEL <mcsymbol .Ltmp2>
     $x30 = OR8 killed $x4, $x4
     renamable $cr0 = CMPLWI renamable $r30, 3
     BCC 71, killed renamable $cr0, %bb.5
   
   bb.4.catch4:
     successors: %bb.11(0x7ffff800), %bb.6(0x00000800)
     liveins: $r29, $x3
   
-    BL8_NOP @__cxa_begin_catch, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
+    BL8_NOP @__cxa_begin_catch, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
     EH_LABEL <mcsymbol .Ltmp3>
-    BL8_NOP @__cxa_rethrow, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1
+    BL8_NOP @__cxa_rethrow, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1
     EH_LABEL <mcsymbol .Ltmp4>
     B %bb.11
   
   bb.5.catch.fallthrough:
     successors: %bb.8(0x80000000)
     liveins: $r29, $x3, $x30
   
-    BL8_NOP @__cxa_begin_catch, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
+    BL8_NOP @__cxa_begin_catch, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
     renamable $cr0 = CMPLWI killed renamable $r30, 2, implicit $x30
     B %bb.8
   
   bb.6.lpad6 (landing-pad):
     successors: %bb.7(0x7fffffff), %bb.10(0x00000001)
     liveins: $r29, $x3, $x4
   
     EH_LABEL <mcsymbol .Ltmp5>
     renamable $cr0 = CMPLWI killed renamable $r4, 4, implicit $x4
     $x30 = OR8 killed $x3, $x3
     BCC 70, killed renamable $cr0, %bb.10
   
   bb.7.catch10:
     successors: %bb.8(0x80000000)
     liveins: $r29, $x30
   
     $x3 = OR8 killed $x30, $x30
-    BL8_NOP @__cxa_begin_catch, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit-def $r1, implicit-def dead $x3
-    BL8_NOP @__cxa_end_catch, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1
+    BL8_NOP @__cxa_begin_catch, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit-def $r1, implicit-def dead $x3
+    BL8_NOP @__cxa_end_catch, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1
   
   bb.8.for.inc:
     successors: %bb.9(0x04000000), %bb.1(0x7c000000)
     liveins: $r29
   
-    BL8_NOP @__cxa_end_catch, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1
+    BL8_NOP @__cxa_end_catch, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1
     renamable $r29 = nsw ADDI killed renamable $r29, -1
     renamable $cr0 = CMPLWI renamable $r29, 0
     BCC 68, killed renamable $cr0, %bb.1
   
   bb.9.for.cond.cleanup:
     $x1 = ADDI8 $x1, 64
     $x0 = LD 16, $x1
     MTLR8 killed $x0, implicit-def $lr8
     $x30 = LD -16, $x1 :: (load 8 from %fixed-stack.0, align 16)
     $x29 = LD -24, $x1 :: (load 8 from %fixed-stack.1)
     BLR8 implicit $lr8, implicit $rm
   
   bb.10.ehcleanup:
     successors: 
     liveins: $x30
   
-    BL8_NOP @__cxa_end_catch, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1
+    BL8_NOP @__cxa_end_catch, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit-def $r1
     $x3 = OR8 killed $x30, $x30
-    BL8_NOP @_Unwind_Resume, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit-def $r1
+    BL8_NOP @_Unwind_Resume, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit-def $r1
   
   bb.11.unreachable:
 
   ; CHECK:      bb.1.for.body:
   ; CHECK:        successors: %bb.2(0x7ffff800), %bb.3(0x00000800)
   ; CHECK:        B %bb.2
 
   ; CHECK:      bb.4.catch4:
   ; CHECK:        successors: %bb.11(0x7ffff800), %bb.6(0x00000800)
   ; CHECK:        B %bb.11
 
   ; CHECK:      bb.2..noexc:
 
   ; CHECK:      bb.11.unreachable: 
 ...

llvm/test/CodeGen/PowerPC/licm-tocReg.ll

 ;    %1 = PHI %0, %bb.0.entry, %3, %bb.3.if.end
 ;    ADJCALLSTACKDOWN 32, 0, implicit-def dead %r1, implicit %r1
 ;    %20 = COPY %x2
 ;    STD %20, 24, %x1 :: (store 8 into stack + 24)
 ;    %21 = EXTSW_32_64 %1
 ;    %x3 = COPY %21
 ;    %x12 = COPY %4
 ;    MTCTR8 %4, implicit-def %ctr8
-;    BCTRL8_LDinto_toc 24, %x1, csr_svr464_altivec, implicit-def dead %lr8, implicit-def dead %x2, implicit %ctr8, implicit %rm, implicit %x3, implicit %x12, implicit %x2, implicit-def %r1, implicit-def %x3
+;    BCTRL8_LDinto_toc 24, %x1, csr_ppc64_altivec, implicit-def dead %lr8, implicit-def dead %x2, implicit %ctr8, implicit %rm, implicit %x3, implicit %x12, implicit %x2, implicit-def %r1, implicit-def %x3
 ;    ADJCALLSTACKUP 32, 0, implicit-def dead %r1, implicit %r1
 ;    %22 = COPY %x3
 ;    %x3 = COPY %22
 ;    BLR8 implicit %lr8, implicit %rm, implicit %x3
 ;
 ;  bb.3.if.end:
 ;    successors: %bb.2.if.then(0x04000000), %bb.3.if.end(0x7c000000)
 ;

llvm/test/CodeGen/PowerPC/machine-backward-cp.mir

 alignment: 4
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x2, $x3, $x20
     ; CHECK-LABEL: name: cross_call
     ; CHECK: liveins: $x2, $x3, $x20
     ; CHECK: renamable $x20 = LI8 1024
-    ; CHECK: BL8_NOP @foo, csr_svr464_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit-def $x3, implicit $x2
+    ; CHECK: BL8_NOP @foo, csr_ppc64_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit-def $x3, implicit $x2
     ; CHECK: $x3 = COPY killed renamable $x20
     ; CHECK: BLR8 implicit $lr8, implicit undef $rm, implicit $x3
     renamable $x20 = LI8 1024
-    BL8_NOP @foo, csr_svr464_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit-def $x3, implicit $x2
+    BL8_NOP @foo, csr_ppc64_altivec, implicit-def $lr8, implicit $rm, implicit $x3, implicit-def $x3, implicit $x2
     $x3 = COPY renamable killed $x20
     BLR8 implicit $lr8, implicit undef $rm, implicit $x3
 ...

llvm/test/CodeGen/PowerPC/setcr_bc.mir

bb.0.entry:
     ; CHECK-NOT: bc
     ; CHECK: .LBB0_2
 
     $x0 = MFLR8 implicit $lr8
     STD killed $x0, 16, $x1
     $x1 = STDU $x1, -48, $x1
     STD killed $x30, 32, $x1 :: (store 8 into %fixed-stack.0, align 16)
     $x30 = OR8 $x3, $x3
-    BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3
+    BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3
     renamable $cr0 = CMPLWI renamable $r3, 0
     BCC 76, killed renamable $cr0, %bb.2
   
   bb.1.if.then.i:
     successors: %bb.5(0x40000000), %bb.4(0x40000000)
     liveins: $x3
   
     renamable $x3 = EXTSW_32_64 killed renamable $r3, implicit $x3
-    BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3
+    BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3
     renamable $cr0gt = CRUNSET implicit-def $cr0
     $x30 = OR8 killed $x3, $x3
     BC killed renamable $cr0gt, %bb.5
   
   bb.4.if.then:
     successors: %bb.5(0x80000000)
     liveins: $x30
   
     $x3 = LI8 0
-    BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
+    BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
   
   bb.5.if.end:
     liveins: $x30
   
     renamable $x3 = EXTSW_32_64 killed renamable $r30, implicit $x30
     $x30 = LD 32, $x1 :: (load 8 from %fixed-stack.0, align 16)
     $x1 = ADDI8 $x1, 48
     $x0 = LD 16, $x1

llvm/test/CodeGen/PowerPC/setcr_bc2.mir

bb.0.entry:
     ; CHECK-NOT: bc
     ; CHECK: .LBB0_2
 
     $x0 = MFLR8 implicit $lr8
     STD killed $x0, 16, $x1
     $x1 = STDU $x1, -48, $x1
     STD killed $x30, 32, $x1 :: (store 8 into %fixed-stack.0, align 16)
     $x30 = OR8 $x3, $x3
-    BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3
+    BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3
     renamable $cr0 = CMPLWI renamable $r3, 0
     BCC 76, killed renamable $cr0, %bb.2
   
   bb.1.if.then.i:
     successors: %bb.5(0x40000000), %bb.4(0x40000000)
     liveins: $x3
   
     renamable $x3 = EXTSW_32_64 killed renamable $r3, implicit $x3
-    BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3
+    BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3
     renamable $cr0gt = CRSET implicit-def $cr0
     $x30 = OR8 killed $x3, $x3
     BC killed renamable $cr0gt, %bb.5
   
   bb.4.if.then:
     successors: %bb.5(0x80000000)
     liveins: $x30
   
     $x3 = LI8 0
-    BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
+    BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
   
   bb.5.if.end:
     liveins: $x30, $cr0gt
   
     renamable $x3 = EXTSW_32_64 killed renamable $r30, implicit $x30
     $x30 = LD 32, $x1 :: (load 8 from %fixed-stack.0, align 16)
     $x1 = ADDI8 $x1, 48
     $x0 = LD 16, $x1

llvm/test/CodeGen/PowerPC/setcr_bc3.mir

bb.0:
     ; CHECK: b .LBB0_3
     ; CHECK: .LBB0_2
 
     $x0 = MFLR8 implicit $lr8
     STD killed $x0, 16, $x1
     $x1 = STDU $x1, -48, $x1
     STD killed $x30, 32, $x1 :: (store 8 into %fixed-stack.0, align 16)
     $x30 = OR8 $x3, $x3
-    BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3
+    BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3
     renamable $cr0 = CMPLWI renamable $r3, 0
     BCC 76, killed renamable $cr0, %bb.2
 
   bb.1:
     successors: %bb.5(0x40000000), %bb.2(0x40000000)
     liveins: $x3
 
     renamable $x3 = EXTSW_32_64 killed renamable $r3, implicit $x3
-    BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3
+    BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def $x3
     renamable $cr2un = CRSET
     $cr2gt = CROR $cr2un, $cr2un
     $x30 = OR8 killed $x3, $x3
     BC killed renamable $cr2un, %bb.5
     B %bb.2
 
   bb.4:
     successors: %bb.5(0x80000000)
     liveins: $x30
 
     $x3 = LI8 0
-    BL8_NOP @callee, csr_svr464_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
+    BL8_NOP @callee, csr_ppc64_altivec, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1, implicit-def dead $x3
 
   bb.5:
     liveins: $x30, $cr0gt
 
     renamable $x3 = EXTSW_32_64 killed renamable $r30, implicit $x30
     $x30 = LD 32, $x1 :: (load 8 from %fixed-stack.0, align 16)
     $x1 = ADDI8 $x1, 48
     $x0 = LD 16, $x1

llvm/test/CodeGen/PowerPC/test_call_aix.ll

 
 define void @test_call() {
 entry:
 ; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT: BL_NOP <mcsymbol .foo>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r2, implicit-def $r1
 ; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: BL8_NOP <mcsymbol .foo>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x2, implicit-def $r1
+; 64BIT: BL8_NOP <mcsymbol .foo>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x2, implicit-def $r1
 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECK-LABEL: test_call
 ; CHECK: bl .foo
 ; CHECK-NEXT: nop
 
   call void bitcast (void (...)* @foo to void ()*)()
   ret void
 }
 
 define hidden void @foo_local() {
 entry:
   ret void
 }
 
 define void @test_local_call() {
 entry:
 ; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
 ; 32BIT: BL <mcsymbol .foo_local>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r2, implicit-def $r1
 ; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
 
 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: BL8 <mcsymbol .foo_local>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x2, implicit-def $r1
+; 64BIT: BL8 <mcsymbol .foo_local>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x2, implicit-def $r1
 ; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
 
 ; CHECK-LABEL: test_local_call
 ; CHECK: bl .foo_local
 ; CHECK-NOT: nop
 
   call void @foo_local()
   ret void
 }