For below case:
cat bool-math.mir
---
name: add_zext_cmp_mask_same_size_result
body: |
bb.0:
liveins: $x3
renamable $r3 = RLWINM killed renamable $r3, 0, 31, 31, implicit $x3
renamable $r3 = SUBFIC killed renamable $r3, 27, implicit-def dead $carry, implicit-def $x3
BLR8 implicit $lr8, implicit $rm, implicit killed $x3
...Use below command to build it:
llc -start-after=ppc-early-ret bool-math.mir -o bool-math.s
Before this patch, we will get:
rlwinm 3, 3, 0, 31, 31 subfic 3, 3, 27 blr
Note that rlwinm 3, 3, 0, 31, 31<--> clrlwi 3, 3, 31. But the mir case use implicit $x3 for RLWINM and PPC conserve the implicit $x3 for MCInst, so above case won't use Extended Mnemonic.
When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands.
I have seen ARM & AMDGPU have ignored the implicit operands when converting MachineInst -> MCInst.
ARM
ARMMCInstLower.cpp
72 bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
73 MCOperand &MCOp) {
74 switch (MO.getType()) {
75 default: llvm_unreachable("unknown operand type");
76 case MachineOperand::MO_Register:
77 // Ignore all implicit register operands.
78 if (MO.isImplicit())
79 return false;
80 assert(!MO.getSubReg() &AMDGPU
AMDGPUMCInstLower.cpp
126 bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
127 MCOperand &MCOp) const {
170 case MachineOperand::MO_RegisterMask:
171 // Regmasks are like implicit defs.
172 return false;
173 }
174 }After this patch, we will get
clrlwi 3, 3, 31 subfic 3, 3, 27 blr
Could you please explain more on the extra "#" here ?