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Differential D77118

[PowerPC] Ignore implicit register operands for MCInst
ClosedPublic

Authored by ZhangKang on Mar 31 2020, 12:25 AM.

Details

Reviewers
kbarton
hiraditya
nemanjai
jsji
steven.zhang
Group Reviewers
Restricted Project
Commits
rG513976df2e65: [PowerPC] Ignore implicit register operands for MCInst
Summary

For below case:
cat bool-math.mir 

---
name:            add_zext_cmp_mask_same_size_result
body:             |
  bb.0:
    liveins: $x3

    renamable $r3 = RLWINM killed renamable $r3, 0, 31, 31, implicit $x3
    renamable $r3 = SUBFIC killed renamable $r3, 27, implicit-def dead $carry, implicit-def $x3
    BLR8 implicit $lr8, implicit $rm, implicit killed $x3

...

Use below command to build it:

llc -start-after=ppc-early-ret bool-math.mir -o bool-math.s

Before this patch, we will get:

	rlwinm 3, 3, 0, 31, 31
	subfic 3, 3, 27
	blr

Note that rlwinm 3, 3, 0, 31, 31<--> clrlwi 3, 3, 31. But the mir case use implicit $x3 for RLWINM and PPC conserve the implicit $x3 for MCInst, so above case won't use Extended Mnemonic.

When doing the conversion: MachineInst -> MCInst, we should ignore the implicit operands.

I have seen ARM & AMDGPU have ignored the implicit operands when converting MachineInst -> MCInst.

ARM

ARMMCInstLower.cpp

72 bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
73                                  MCOperand &MCOp) {
74   switch (MO.getType()) {
75   default: llvm_unreachable("unknown operand type");
76   case MachineOperand::MO_Register:
77     // Ignore all implicit register operands.
78     if (MO.isImplicit())
79       return false;
80     assert(!MO.getSubReg() &

AMDGPU

AMDGPUMCInstLower.cpp

126 bool AMDGPUMCInstLower::lowerOperand(const MachineOperand &MO,
127                                      MCOperand &MCOp) const {

170   case MachineOperand::MO_RegisterMask:
171     // Regmasks are like implicit defs.
172     return false;
173   }
174 }

After this patch, we will get

	clrlwi	3, 3, 31
	subfic 3, 3, 27
	blr

Diff Detail

Event Timeline

ZhangKang created this revision.Mar 31 2020, 12:25 AM
Herald added subscribers: danielkiss, shchenz, • wuzish and 3 others. · View Herald TranscriptMar 31 2020, 12:25 AM
Harbormaster completed remote builds in B51092: Diff 253789.Mar 31 2020, 1:04 AM
steven.zhang added a comment.Mar 31 2020, 1:26 AM

I think this is a good catch. InstAlias match the MI strictly including the implicit operands. We can either try to loose that check or remove the implicit operand when lowering the MI to MCInst, as it is not needed anymore. And please test this patch completely as this patch expose much more alias opportunities that didn't test before.

llvm/test/CodeGen/PowerPC/atomics-regression.ll
1234

Could you please explain more on the extra "#" here ?

llvm/test/CodeGen/PowerPC/xray-conditional-return.ll
42–43

I don't see this change relative with alias.

ZhangKang marked 4 inline comments as done.Mar 31 2020, 2:16 AM
In D77118#1951919, @steven.zhang wrote:

I think this is a good catch. InstAlias match the MI strictly including the implicit operands. We can either try to loose that check or remove the implicit operand when lowering the MI to MCInst, as it is not needed anymore. And please test this patch completely as this patch expose much more alias opportunities that didn't test before.

Lit test and Lnt test has passed, and those modified assembly I have checked.

llvm/test/CodeGen/PowerPC/atomics-regression.ll
1234

This case is updated by update_llc_test_checks.py, last update is in Aug 30, 2019. After last update, someone modify the assembly output to add extra #.

llvm/test/CodeGen/PowerPC/xray-conditional-return.ll
42–43

In fact, the old assembly is:

cmpw 0, R1, R2
beq 0, Target

The new assembly is:

cmpw R1, R2
beq 0, Target

Because cmpw R1, R2 has omit CR0, I must specify beq use the CR0.

In fact, the beq 0, Target should also omit CR0 to beq Target, but it's not this patch should do.

jsji added inline comments.Mar 31 2020, 7:38 AM
llvm/test/CodeGen/PowerPC/atomics-regression.ll
1234

Can you please find out the patch? If the change is reasonable, then we should commit a NFC patch to update the testcases first, then rebase.

ZhangKang marked 4 inline comments as done.Mar 31 2020, 9:45 AM
ZhangKang added inline comments.
llvm/test/CodeGen/PowerPC/atomics-regression.ll
1234

This is caused by https://reviews.llvm.org/D63957 ,it will be fixed soon.

ZhangKang updated this revision to Diff 256228.Apr 9 2020, 3:21 AM
ZhangKang marked an inline comment as done.

Rebase and set the parent.

ZhangKang added a parent revision: D77357: [PowerPC][UpdateTestChecks] Remove the extra # when scrubbing loop comments.Apr 9 2020, 3:22 AM
Harbormaster completed remote builds in B52480: Diff 256228.Apr 9 2020, 4:18 AM
steven.zhang accepted this revision.EditedApr 9 2020, 6:38 PM

LGTM now. But pls wait for some days to see if Jinsong or someone else have more comments.

This revision is now accepted and ready to land.Apr 9 2020, 6:38 PM
Closed by commit rG513976df2e65: [PowerPC] Ignore implicit register operands for MCInst (authored by ZhangKang). · Explain WhyApr 16 2020, 9:29 AM
This revision was automatically updated to reflect the committed changes.

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Diff 258075

llvm/lib/Target/PowerPC/PPCMCInstLower.cpp

Show First 20 Lines • Show All 141 Lines • ▼ Show 20 Linesbool llvm::LowerPPCMachineOperandToMCOperand(const MachineOperand &MO,
switch (MO.getType()) { switch (MO.getType()) {
default: default:
llvm_unreachable("unknown operand type"); llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register: case MachineOperand::MO_Register:
assert(!MO.getSubReg() && "Subregs should be eliminated!"); assert(!MO.getSubReg() && "Subregs should be eliminated!");
assert(MO.getReg() > PPC::NoRegister && assert(MO.getReg() > PPC::NoRegister &&
MO.getReg() < PPC::NUM_TARGET_REGS && MO.getReg() < PPC::NUM_TARGET_REGS &&
"Invalid register for this target!"); "Invalid register for this target!");
// Ignore all implicit register operands.
if (MO.isImplicit())
return false;
OutMO = MCOperand::createReg(MO.getReg()); OutMO = MCOperand::createReg(MO.getReg());
return true; return true;
case MachineOperand::MO_Immediate: case MachineOperand::MO_Immediate:
OutMO = MCOperand::createImm(MO.getImm()); OutMO = MCOperand::createImm(MO.getImm());
return true; return true;
case MachineOperand::MO_MachineBasicBlock: case MachineOperand::MO_MachineBasicBlock:
OutMO = MCOperand::createExpr( OutMO = MCOperand::createExpr(
MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), AP.OutContext)); MCSymbolRefExpr::create(MO.getMBB()->getSymbol(), AP.OutContext));
Show All 22 Lines

llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir

Show First 20 Lines • Show All 88 Lines • ▼ Show 20 Linesbody: |
bb.0.entry: bb.0.entry:
liveins: $x3, $x4, $x5 liveins: $x3, $x4, $x5
renamable $cr0 = CMPW renamable $r3, renamable $r4, implicit $x4 renamable $cr0 = CMPW renamable $r3, renamable $r4, implicit $x4
renamable $cr1 = CMPW renamable $r3, renamable $r5, implicit $x5, implicit killed $x3 renamable $cr1 = CMPW renamable $r3, renamable $r5, implicit $x5, implicit killed $x3
renamable $cr5lt = CRNOR renamable $cr0lt, renamable $cr1gt, implicit killed $cr0 renamable $cr5lt = CRNOR renamable $cr0lt, renamable $cr1gt, implicit killed $cr0
renamable $cr5gt = COPY renamable $cr1gt, implicit $cr1 renamable $cr5gt = COPY renamable $cr1gt, implicit $cr1
; CHECK: crnor 4*cr5+lt, lt, 4*cr1+gt ; CHECK: crnor 4*cr5+lt, lt, 4*cr1+gt
; CHECK: cror 4*cr5+gt, 4*cr1+gt, 4*cr1+gt ; CHECK: crmove 4*cr5+gt, 4*cr1+gt
SPILL_CRBIT killed renamable $cr5lt, 0, %stack.0 :: (store 4 into %stack.0) SPILL_CRBIT killed renamable $cr5lt, 0, %stack.0 :: (store 4 into %stack.0)
renamable $cr1 = CMPW renamable $r4, renamable $r5, implicit killed $x5, implicit killed $x4 renamable $cr1 = CMPW renamable $r4, renamable $r5, implicit killed $x5, implicit killed $x4
SPILL_CRBIT killed renamable $cr5gt, 0, %stack.1 :: (store 4 into %stack.1) SPILL_CRBIT killed renamable $cr5gt, 0, %stack.1 :: (store 4 into %stack.1)
SPILL_CRBIT killed renamable $cr1gt, 0, %stack.2 :: (store 4 into %stack.2) SPILL_CRBIT killed renamable $cr1gt, 0, %stack.2 :: (store 4 into %stack.2)
INLINEASM &"# nothing", 25, 12, implicit-def dead early-clobber $cr0, 12, implicit-def dead early-clobber $cr1, 12, implicit-def dead early-clobber $cr2, 12, implicit-def dead early-clobber $cr3, 12, implicit-def dead early-clobber $cr4, 12, implicit-def dead early-clobber $cr5, 12, implicit-def dead early-clobber $cr6, 12, implicit-def dead early-clobber $cr7, !1 INLINEASM &"# nothing", 25, 12, implicit-def dead early-clobber $cr0, 12, implicit-def dead early-clobber $cr1, 12, implicit-def dead early-clobber $cr2, 12, implicit-def dead early-clobber $cr3, 12, implicit-def dead early-clobber $cr4, 12, implicit-def dead early-clobber $cr5, 12, implicit-def dead early-clobber $cr6, 12, implicit-def dead early-clobber $cr7, !1
BLR8 implicit $lr8, implicit $rm BLR8 implicit $lr8, implicit $rm
bb.1.if.end326: bb.1.if.end326:
Show All 16 Lines

llvm/test/CodeGen/PowerPC/atomics-regression.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 394 Lines • ▼ Show 20 Lines
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
fence syncscope("singlethread") seq_cst fence syncscope("singlethread") seq_cst
ret void ret void
} }
define void @test40(i8* %ptr, i8 %cmp, i8 %val) { define void @test40(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test40: ; PPC64LE-LABEL: test40:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB40_1: ; PPC64LE-NEXT: .LBB40_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB40_3 ; PPC64LE-NEXT: bne 0, .LBB40_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0 ; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: b .LBB40_1 ; PPC64LE-NEXT: b .LBB40_1
; PPC64LE-NEXT: .LBB40_3: ; PPC64LE-NEXT: .LBB40_3:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic
ret void ret void
} }
define void @test41(i8* %ptr, i8 %cmp, i8 %val) { define void @test41(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test41: ; PPC64LE-LABEL: test41:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB41_1: ; PPC64LE-NEXT: .LBB41_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB41_4 ; PPC64LE-NEXT: bne 0, .LBB41_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB41_1 ; PPC64LE-NEXT: bne 0, .LBB41_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB41_4: ; PPC64LE-NEXT: .LBB41_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic
ret void ret void
} }
define void @test42(i8* %ptr, i8 %cmp, i8 %val) { define void @test42(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test42: ; PPC64LE-LABEL: test42:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB42_1: ; PPC64LE-NEXT: .LBB42_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB42_4 ; PPC64LE-NEXT: bne 0, .LBB42_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB42_1 ; PPC64LE-NEXT: bne 0, .LBB42_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB42_4: ; PPC64LE-NEXT: .LBB42_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire
ret void ret void
} }
define void @test43(i8* %ptr, i8 %cmp, i8 %val) { define void @test43(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test43: ; PPC64LE-LABEL: test43:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB43_1: ; PPC64LE-NEXT: .LBB43_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB43_3 ; PPC64LE-NEXT: bne 0, .LBB43_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0 ; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: b .LBB43_1 ; PPC64LE-NEXT: b .LBB43_1
; PPC64LE-NEXT: .LBB43_3: ; PPC64LE-NEXT: .LBB43_3:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic
ret void ret void
} }
define void @test44(i8* %ptr, i8 %cmp, i8 %val) { define void @test44(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test44: ; PPC64LE-LABEL: test44:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB44_1: ; PPC64LE-NEXT: .LBB44_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB44_3 ; PPC64LE-NEXT: bne 0, .LBB44_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0 ; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: b .LBB44_1 ; PPC64LE-NEXT: b .LBB44_1
; PPC64LE-NEXT: .LBB44_3: ; PPC64LE-NEXT: .LBB44_3:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire
ret void ret void
} }
define void @test45(i8* %ptr, i8 %cmp, i8 %val) { define void @test45(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test45: ; PPC64LE-LABEL: test45:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB45_1: ; PPC64LE-NEXT: .LBB45_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB45_4 ; PPC64LE-NEXT: bne 0, .LBB45_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB45_1 ; PPC64LE-NEXT: bne 0, .LBB45_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB45_4: ; PPC64LE-NEXT: .LBB45_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic
ret void ret void
} }
define void @test46(i8* %ptr, i8 %cmp, i8 %val) { define void @test46(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test46: ; PPC64LE-LABEL: test46:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB46_1: ; PPC64LE-NEXT: .LBB46_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB46_4 ; PPC64LE-NEXT: bne 0, .LBB46_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB46_1 ; PPC64LE-NEXT: bne 0, .LBB46_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB46_4: ; PPC64LE-NEXT: .LBB46_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire
ret void ret void
} }
define void @test47(i8* %ptr, i8 %cmp, i8 %val) { define void @test47(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test47: ; PPC64LE-LABEL: test47:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB47_1: ; PPC64LE-NEXT: .LBB47_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB47_4 ; PPC64LE-NEXT: bne 0, .LBB47_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB47_1 ; PPC64LE-NEXT: bne 0, .LBB47_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB47_4: ; PPC64LE-NEXT: .LBB47_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic
ret void ret void
} }
define void @test48(i8* %ptr, i8 %cmp, i8 %val) { define void @test48(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test48: ; PPC64LE-LABEL: test48:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB48_1: ; PPC64LE-NEXT: .LBB48_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB48_4 ; PPC64LE-NEXT: bne 0, .LBB48_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB48_1 ; PPC64LE-NEXT: bne 0, .LBB48_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB48_4: ; PPC64LE-NEXT: .LBB48_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire
ret void ret void
} }
define void @test49(i8* %ptr, i8 %cmp, i8 %val) { define void @test49(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test49: ; PPC64LE-LABEL: test49:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB49_1: ; PPC64LE-NEXT: .LBB49_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB49_4 ; PPC64LE-NEXT: bne 0, .LBB49_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB49_1 ; PPC64LE-NEXT: bne 0, .LBB49_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB49_4: ; PPC64LE-NEXT: .LBB49_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst
ret void ret void
} }
define void @test50(i16* %ptr, i16 %cmp, i16 %val) { define void @test50(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test50: ; PPC64LE-LABEL: test50:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB50_1: ; PPC64LE-NEXT: .LBB50_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB50_3 ; PPC64LE-NEXT: bne 0, .LBB50_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0 ; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: b .LBB50_1 ; PPC64LE-NEXT: b .LBB50_1
; PPC64LE-NEXT: .LBB50_3: ; PPC64LE-NEXT: .LBB50_3:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic
ret void ret void
} }
define void @test51(i16* %ptr, i16 %cmp, i16 %val) { define void @test51(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test51: ; PPC64LE-LABEL: test51:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB51_1: ; PPC64LE-NEXT: .LBB51_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB51_4 ; PPC64LE-NEXT: bne 0, .LBB51_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB51_1 ; PPC64LE-NEXT: bne 0, .LBB51_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB51_4: ; PPC64LE-NEXT: .LBB51_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic
ret void ret void
} }
define void @test52(i16* %ptr, i16 %cmp, i16 %val) { define void @test52(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test52: ; PPC64LE-LABEL: test52:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB52_1: ; PPC64LE-NEXT: .LBB52_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB52_4 ; PPC64LE-NEXT: bne 0, .LBB52_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB52_1 ; PPC64LE-NEXT: bne 0, .LBB52_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB52_4: ; PPC64LE-NEXT: .LBB52_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire
ret void ret void
} }
define void @test53(i16* %ptr, i16 %cmp, i16 %val) { define void @test53(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test53: ; PPC64LE-LABEL: test53:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB53_1: ; PPC64LE-NEXT: .LBB53_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB53_3 ; PPC64LE-NEXT: bne 0, .LBB53_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0 ; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: b .LBB53_1 ; PPC64LE-NEXT: b .LBB53_1
; PPC64LE-NEXT: .LBB53_3: ; PPC64LE-NEXT: .LBB53_3:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic
ret void ret void
} }
define void @test54(i16* %ptr, i16 %cmp, i16 %val) { define void @test54(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test54: ; PPC64LE-LABEL: test54:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB54_1: ; PPC64LE-NEXT: .LBB54_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB54_3 ; PPC64LE-NEXT: bne 0, .LBB54_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0 ; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: b .LBB54_1 ; PPC64LE-NEXT: b .LBB54_1
; PPC64LE-NEXT: .LBB54_3: ; PPC64LE-NEXT: .LBB54_3:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire
ret void ret void
} }
define void @test55(i16* %ptr, i16 %cmp, i16 %val) { define void @test55(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test55: ; PPC64LE-LABEL: test55:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB55_1: ; PPC64LE-NEXT: .LBB55_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB55_4 ; PPC64LE-NEXT: bne 0, .LBB55_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB55_1 ; PPC64LE-NEXT: bne 0, .LBB55_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB55_4: ; PPC64LE-NEXT: .LBB55_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic
ret void ret void
} }
define void @test56(i16* %ptr, i16 %cmp, i16 %val) { define void @test56(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test56: ; PPC64LE-LABEL: test56:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB56_1: ; PPC64LE-NEXT: .LBB56_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB56_4 ; PPC64LE-NEXT: bne 0, .LBB56_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB56_1 ; PPC64LE-NEXT: bne 0, .LBB56_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB56_4: ; PPC64LE-NEXT: .LBB56_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire
ret void ret void
} }
define void @test57(i16* %ptr, i16 %cmp, i16 %val) { define void @test57(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test57: ; PPC64LE-LABEL: test57:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB57_1: ; PPC64LE-NEXT: .LBB57_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB57_4 ; PPC64LE-NEXT: bne 0, .LBB57_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB57_1 ; PPC64LE-NEXT: bne 0, .LBB57_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB57_4: ; PPC64LE-NEXT: .LBB57_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic
ret void ret void
} }
define void @test58(i16* %ptr, i16 %cmp, i16 %val) { define void @test58(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test58: ; PPC64LE-LABEL: test58:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB58_1: ; PPC64LE-NEXT: .LBB58_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB58_4 ; PPC64LE-NEXT: bne 0, .LBB58_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB58_1 ; PPC64LE-NEXT: bne 0, .LBB58_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB58_4: ; PPC64LE-NEXT: .LBB58_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire
ret void ret void
} }
define void @test59(i16* %ptr, i16 %cmp, i16 %val) { define void @test59(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test59: ; PPC64LE-LABEL: test59:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB59_1: ; PPC64LE-NEXT: .LBB59_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB59_4 ; PPC64LE-NEXT: bne 0, .LBB59_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB59_1 ; PPC64LE-NEXT: bne 0, .LBB59_1
▲ Show 20 Lines • Show All 401 Lines • ▼ Show 20 Lines; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire
ret void ret void
} }
define void @test79(i64* %ptr, i64 %cmp, i64 %val) { define void @test79(i64* %ptr, i64 %cmp, i64 %val) {
; PPC64LE-LABEL: test79: ; PPC64LE-LABEL: test79:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB79_1: ; PPC64LE-NEXT: .LBB79_1:
steven.zhangUnsubmitted
Done
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Could you please explain more on the extra "#" here ?

steven.zhang: Could you please explain more on the extra "#" here ?
ZhangKangAuthorUnsubmitted
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This case is updated by update_llc_test_checks.py, last update is in Aug 30, 2019. After last update, someone modify the assembly output to add extra #.

ZhangKang: This case is updated by update_llc_test_checks.py, last update is in Aug 30, 2019. After last…
jsjiUnsubmitted
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Can you please find out the patch? If the change is reasonable, then we should commit a NFC patch to update the testcases first, then rebase.

jsji: Can you please find out the patch? If the change is reasonable, then we should commit a NFC…
ZhangKangAuthorUnsubmitted
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This is caused by https://reviews.llvm.org/D63957 ,it will be fixed soon.

ZhangKang: This is caused by https://reviews.llvm.org/D63957 ,it will be fixed soon.
; PPC64LE-NEXT: ldarx 6, 0, 3 ; PPC64LE-NEXT: ldarx 6, 0, 3
; PPC64LE-NEXT: cmpd 4, 6 ; PPC64LE-NEXT: cmpd 4, 6
; PPC64LE-NEXT: bne 0, .LBB79_4 ; PPC64LE-NEXT: bne 0, .LBB79_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stdcx. 5, 0, 3 ; PPC64LE-NEXT: stdcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB79_1 ; PPC64LE-NEXT: bne 0, .LBB79_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB79_4: ; PPC64LE-NEXT: .LBB79_4:
; PPC64LE-NEXT: stdcx. 6, 0, 3 ; PPC64LE-NEXT: stdcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst
ret void ret void
} }
define void @test80(i8* %ptr, i8 %cmp, i8 %val) { define void @test80(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test80: ; PPC64LE-LABEL: test80:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB80_1: ; PPC64LE-NEXT: .LBB80_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB80_3 ; PPC64LE-NEXT: bne 0, .LBB80_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0 ; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: b .LBB80_1 ; PPC64LE-NEXT: b .LBB80_1
; PPC64LE-NEXT: .LBB80_3: ; PPC64LE-NEXT: .LBB80_3:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") monotonic monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") monotonic monotonic
ret void ret void
} }
define void @test81(i8* %ptr, i8 %cmp, i8 %val) { define void @test81(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test81: ; PPC64LE-LABEL: test81:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB81_1: ; PPC64LE-NEXT: .LBB81_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB81_4 ; PPC64LE-NEXT: bne 0, .LBB81_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB81_1 ; PPC64LE-NEXT: bne 0, .LBB81_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB81_4: ; PPC64LE-NEXT: .LBB81_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acquire monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acquire monotonic
ret void ret void
} }
define void @test82(i8* %ptr, i8 %cmp, i8 %val) { define void @test82(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test82: ; PPC64LE-LABEL: test82:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB82_1: ; PPC64LE-NEXT: .LBB82_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB82_4 ; PPC64LE-NEXT: bne 0, .LBB82_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB82_1 ; PPC64LE-NEXT: bne 0, .LBB82_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB82_4: ; PPC64LE-NEXT: .LBB82_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acquire acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acquire acquire
ret void ret void
} }
define void @test83(i8* %ptr, i8 %cmp, i8 %val) { define void @test83(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test83: ; PPC64LE-LABEL: test83:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB83_1: ; PPC64LE-NEXT: .LBB83_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB83_3 ; PPC64LE-NEXT: bne 0, .LBB83_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0 ; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: b .LBB83_1 ; PPC64LE-NEXT: b .LBB83_1
; PPC64LE-NEXT: .LBB83_3: ; PPC64LE-NEXT: .LBB83_3:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release monotonic
ret void ret void
} }
define void @test84(i8* %ptr, i8 %cmp, i8 %val) { define void @test84(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test84: ; PPC64LE-LABEL: test84:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB84_1: ; PPC64LE-NEXT: .LBB84_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB84_3 ; PPC64LE-NEXT: bne 0, .LBB84_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0 ; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: b .LBB84_1 ; PPC64LE-NEXT: b .LBB84_1
; PPC64LE-NEXT: .LBB84_3: ; PPC64LE-NEXT: .LBB84_3:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") release acquire
ret void ret void
} }
define void @test85(i8* %ptr, i8 %cmp, i8 %val) { define void @test85(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test85: ; PPC64LE-LABEL: test85:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB85_1: ; PPC64LE-NEXT: .LBB85_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB85_4 ; PPC64LE-NEXT: bne 0, .LBB85_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB85_1 ; PPC64LE-NEXT: bne 0, .LBB85_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB85_4: ; PPC64LE-NEXT: .LBB85_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel monotonic
ret void ret void
} }
define void @test86(i8* %ptr, i8 %cmp, i8 %val) { define void @test86(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test86: ; PPC64LE-LABEL: test86:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB86_1: ; PPC64LE-NEXT: .LBB86_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB86_4 ; PPC64LE-NEXT: bne 0, .LBB86_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB86_1 ; PPC64LE-NEXT: bne 0, .LBB86_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB86_4: ; PPC64LE-NEXT: .LBB86_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") acq_rel acquire
ret void ret void
} }
define void @test87(i8* %ptr, i8 %cmp, i8 %val) { define void @test87(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test87: ; PPC64LE-LABEL: test87:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB87_1: ; PPC64LE-NEXT: .LBB87_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB87_4 ; PPC64LE-NEXT: bne 0, .LBB87_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB87_1 ; PPC64LE-NEXT: bne 0, .LBB87_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB87_4: ; PPC64LE-NEXT: .LBB87_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst monotonic
ret void ret void
} }
define void @test88(i8* %ptr, i8 %cmp, i8 %val) { define void @test88(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test88: ; PPC64LE-LABEL: test88:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB88_1: ; PPC64LE-NEXT: .LBB88_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB88_4 ; PPC64LE-NEXT: bne 0, .LBB88_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB88_1 ; PPC64LE-NEXT: bne 0, .LBB88_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB88_4: ; PPC64LE-NEXT: .LBB88_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst acquire %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst acquire
ret void ret void
} }
define void @test89(i8* %ptr, i8 %cmp, i8 %val) { define void @test89(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test89: ; PPC64LE-LABEL: test89:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB89_1: ; PPC64LE-NEXT: .LBB89_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB89_4 ; PPC64LE-NEXT: bne 0, .LBB89_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB89_1 ; PPC64LE-NEXT: bne 0, .LBB89_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB89_4: ; PPC64LE-NEXT: .LBB89_4:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst seq_cst %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val syncscope("singlethread") seq_cst seq_cst
ret void ret void
} }
define void @test90(i16* %ptr, i16 %cmp, i16 %val) { define void @test90(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test90: ; PPC64LE-LABEL: test90:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB90_1: ; PPC64LE-NEXT: .LBB90_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB90_3 ; PPC64LE-NEXT: bne 0, .LBB90_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0 ; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: b .LBB90_1 ; PPC64LE-NEXT: b .LBB90_1
; PPC64LE-NEXT: .LBB90_3: ; PPC64LE-NEXT: .LBB90_3:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") monotonic monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") monotonic monotonic
ret void ret void
} }
define void @test91(i16* %ptr, i16 %cmp, i16 %val) { define void @test91(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test91: ; PPC64LE-LABEL: test91:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB91_1: ; PPC64LE-NEXT: .LBB91_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB91_4 ; PPC64LE-NEXT: bne 0, .LBB91_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB91_1 ; PPC64LE-NEXT: bne 0, .LBB91_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB91_4: ; PPC64LE-NEXT: .LBB91_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acquire monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acquire monotonic
ret void ret void
} }
define void @test92(i16* %ptr, i16 %cmp, i16 %val) { define void @test92(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test92: ; PPC64LE-LABEL: test92:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: .LBB92_1: ; PPC64LE-NEXT: .LBB92_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB92_4 ; PPC64LE-NEXT: bne 0, .LBB92_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB92_1 ; PPC64LE-NEXT: bne 0, .LBB92_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB92_4: ; PPC64LE-NEXT: .LBB92_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acquire acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acquire acquire
ret void ret void
} }
define void @test93(i16* %ptr, i16 %cmp, i16 %val) { define void @test93(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test93: ; PPC64LE-LABEL: test93:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB93_1: ; PPC64LE-NEXT: .LBB93_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB93_3 ; PPC64LE-NEXT: bne 0, .LBB93_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0 ; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: b .LBB93_1 ; PPC64LE-NEXT: b .LBB93_1
; PPC64LE-NEXT: .LBB93_3: ; PPC64LE-NEXT: .LBB93_3:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release monotonic
ret void ret void
} }
define void @test94(i16* %ptr, i16 %cmp, i16 %val) { define void @test94(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test94: ; PPC64LE-LABEL: test94:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB94_1: ; PPC64LE-NEXT: .LBB94_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB94_3 ; PPC64LE-NEXT: bne 0, .LBB94_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0 ; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: b .LBB94_1 ; PPC64LE-NEXT: b .LBB94_1
; PPC64LE-NEXT: .LBB94_3: ; PPC64LE-NEXT: .LBB94_3:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") release acquire
ret void ret void
} }
define void @test95(i16* %ptr, i16 %cmp, i16 %val) { define void @test95(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test95: ; PPC64LE-LABEL: test95:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB95_1: ; PPC64LE-NEXT: .LBB95_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB95_4 ; PPC64LE-NEXT: bne 0, .LBB95_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB95_1 ; PPC64LE-NEXT: bne 0, .LBB95_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB95_4: ; PPC64LE-NEXT: .LBB95_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel monotonic
ret void ret void
} }
define void @test96(i16* %ptr, i16 %cmp, i16 %val) { define void @test96(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test96: ; PPC64LE-LABEL: test96:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: .LBB96_1: ; PPC64LE-NEXT: .LBB96_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB96_4 ; PPC64LE-NEXT: bne 0, .LBB96_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB96_1 ; PPC64LE-NEXT: bne 0, .LBB96_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB96_4: ; PPC64LE-NEXT: .LBB96_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") acq_rel acquire
ret void ret void
} }
define void @test97(i16* %ptr, i16 %cmp, i16 %val) { define void @test97(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test97: ; PPC64LE-LABEL: test97:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB97_1: ; PPC64LE-NEXT: .LBB97_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB97_4 ; PPC64LE-NEXT: bne 0, .LBB97_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB97_1 ; PPC64LE-NEXT: bne 0, .LBB97_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB97_4: ; PPC64LE-NEXT: .LBB97_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst monotonic %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst monotonic
ret void ret void
} }
define void @test98(i16* %ptr, i16 %cmp, i16 %val) { define void @test98(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test98: ; PPC64LE-LABEL: test98:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB98_1: ; PPC64LE-NEXT: .LBB98_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB98_4 ; PPC64LE-NEXT: bne 0, .LBB98_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB98_1 ; PPC64LE-NEXT: bne 0, .LBB98_1
; PPC64LE-NEXT: # %bb.3: ; PPC64LE-NEXT: # %bb.3:
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
; PPC64LE-NEXT: .LBB98_4: ; PPC64LE-NEXT: .LBB98_4:
; PPC64LE-NEXT: sthcx. 6, 0, 3 ; PPC64LE-NEXT: sthcx. 6, 0, 3
; PPC64LE-NEXT: lwsync ; PPC64LE-NEXT: lwsync
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst acquire %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val syncscope("singlethread") seq_cst acquire
ret void ret void
} }
define void @test99(i16* %ptr, i16 %cmp, i16 %val) { define void @test99(i16* %ptr, i16 %cmp, i16 %val) {
; PPC64LE-LABEL: test99: ; PPC64LE-LABEL: test99:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 16, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 16
; PPC64LE-NEXT: sync ; PPC64LE-NEXT: sync
; PPC64LE-NEXT: .LBB99_1: ; PPC64LE-NEXT: .LBB99_1:
; PPC64LE-NEXT: lharx 6, 0, 3 ; PPC64LE-NEXT: lharx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB99_4 ; PPC64LE-NEXT: bne 0, .LBB99_4
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: sthcx. 5, 0, 3 ; PPC64LE-NEXT: sthcx. 5, 0, 3
; PPC64LE-NEXT: bne 0, .LBB99_1 ; PPC64LE-NEXT: bne 0, .LBB99_1
▲ Show 20 Lines • Show All 7,906 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll

; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
; RUN: --check-prefix=CHECK-P7 ; RUN: --check-prefix=CHECK-P7
; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s ; RUN: llc -verify-machineinstrs -mcpu=pwr9 -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
define signext i32 @f32toi32(float %a) { define signext i32 @f32toi32(float %a) {
entry: entry:
%0 = bitcast float %a to i32 %0 = bitcast float %a to i32
ret i32 %0 ret i32 %0
; CHECK-P7: stfs 1, ; CHECK-P7: stfs 1,
; CHECK-P7: lwa 3, ; CHECK-P7: lwa 3,
; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1 ; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3 ; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
; CHECK: mfvsrwz 3, [[SHIFTREG]] ; CHECK: mffprwz 3, [[SHIFTREG]]
} }
define i64 @f64toi64(double %a) { define i64 @f64toi64(double %a) {
entry: entry:
%0 = bitcast double %a to i64 %0 = bitcast double %a to i64
ret i64 %0 ret i64 %0
; CHECK-P7: stfd 1, ; CHECK-P7: stfd 1,
; CHECK-P7: ld 3, ; CHECK-P7: ld 3,
; CHECK: mffprd 3, 1 ; CHECK: mffprd 3, 1
} }
define float @i32tof32(i32 signext %a) { define float @i32tof32(i32 signext %a) {
entry: entry:
%0 = bitcast i32 %a to float %0 = bitcast i32 %a to float
ret float %0 ret float %0
; CHECK-P7: stw 3, ; CHECK-P7: stw 3,
; CHECK-P7: lfs 1, ; CHECK-P7: lfs 1,
; CHECK: mtvsrd [[MOVEREG:[0-9]+]], 3 ; CHECK: mtfprd [[MOVEREG:[0-9]+]], 3
; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1 ; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1
; CHECK: xscvspdpn 1, [[SHIFTREG]] ; CHECK: xscvspdpn 1, [[SHIFTREG]]
} }
define double @i64tof64(i64 %a) { define double @i64tof64(i64 %a) {
entry: entry:
%0 = bitcast i64 %a to double %0 = bitcast i64 %a to double
ret double %0 ret double %0
; CHECK-P7: std 3, ; CHECK-P7: std 3,
; CHECK-P7: lfd 1, ; CHECK-P7: lfd 1,
; CHECK: mtfprd 1, 3 ; CHECK: mtfprd 1, 3
} }
define zeroext i32 @f32toi32u(float %a) { define zeroext i32 @f32toi32u(float %a) {
entry: entry:
%0 = bitcast float %a to i32 %0 = bitcast float %a to i32
ret i32 %0 ret i32 %0
; CHECK-P7: stfs 1, ; CHECK-P7: stfs 1,
; CHECK-P7: lwz 3, ; CHECK-P7: lwz 3,
; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1 ; CHECK: xscvdpspn [[CONVREG:[0-9]+]], 1
; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3 ; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[CONVREG]], [[CONVREG]], 3
; CHECK: mfvsrwz 3, [[SHIFTREG]] ; CHECK: mffprwz 3, [[SHIFTREG]]
} }
define i64 @f64toi64u(double %a) { define i64 @f64toi64u(double %a) {
entry: entry:
%0 = bitcast double %a to i64 %0 = bitcast double %a to i64
ret i64 %0 ret i64 %0
; CHECK-P7: stfd 1, ; CHECK-P7: stfd 1,
; CHECK-P7: ld 3, ; CHECK-P7: ld 3,
; CHECK: mffprd 3, 1 ; CHECK: mffprd 3, 1
} }
define float @i32utof32(i32 zeroext %a) { define float @i32utof32(i32 zeroext %a) {
entry: entry:
%0 = bitcast i32 %a to float %0 = bitcast i32 %a to float
ret float %0 ret float %0
; CHECK-P7: stw 3, ; CHECK-P7: stw 3,
; CHECK-P7: lfs 1, ; CHECK-P7: lfs 1,
; CHECK: mtvsrd [[MOVEREG:[0-9]+]], 3 ; CHECK: mtfprd [[MOVEREG:[0-9]+]], 3
; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1 ; CHECK: xxsldwi [[SHIFTREG:[0-9]+]], [[MOVEREG]], [[MOVEREG]], 1
; CHECK: xscvspdpn 1, [[SHIFTREG]] ; CHECK: xscvspdpn 1, [[SHIFTREG]]
} }
define double @i64utof64(i64 %a) { define double @i64utof64(i64 %a) {
entry: entry:
%0 = bitcast i64 %a to double %0 = bitcast i64 %a to double
ret double %0 ret double %0
; CHECK-P7: std 3, ; CHECK-P7: std 3,
; CHECK-P7: lfd 1, ; CHECK-P7: lfd 1,
; CHECK: mtfprd 1, 3 ; CHECK: mtfprd 1, 3
} }

llvm/test/CodeGen/PowerPC/bool-math.ll

Show All 38 Lines; CHECK-NEXT: blr
%z = zext i1 %c to i8 %z = zext i1 %c to i8
%r = sub i8 47, %z %r = sub i8 47, %z
ret i8 %r ret i8 %r
} }
define i8 @add_zext_cmp_mask_same_size_result(i8 %x) { define i8 @add_zext_cmp_mask_same_size_result(i8 %x) {
; CHECK-LABEL: add_zext_cmp_mask_same_size_result: ; CHECK-LABEL: add_zext_cmp_mask_same_size_result:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 0, 31, 31 ; CHECK-NEXT: clrlwi 3, 3, 31
; CHECK-NEXT: subfic 3, 3, 27 ; CHECK-NEXT: subfic 3, 3, 27
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = and i8 %x, 1 %a = and i8 %x, 1
%c = icmp eq i8 %a, 0 %c = icmp eq i8 %a, 0
%z = zext i1 %c to i8 %z = zext i1 %c to i8
%r = add i8 %z, 26 %r = add i8 %z, 26
ret i8 %r ret i8 %r
} }
define i32 @add_zext_cmp_mask_wider_result(i8 %x) { define i32 @add_zext_cmp_mask_wider_result(i8 %x) {
; CHECK-LABEL: add_zext_cmp_mask_wider_result: ; CHECK-LABEL: add_zext_cmp_mask_wider_result:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 0, 31, 31 ; CHECK-NEXT: clrlwi 3, 3, 31
; CHECK-NEXT: subfic 3, 3, 27 ; CHECK-NEXT: subfic 3, 3, 27
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = and i8 %x, 1 %a = and i8 %x, 1
%c = icmp eq i8 %a, 0 %c = icmp eq i8 %a, 0
%z = zext i1 %c to i32 %z = zext i1 %c to i32
%r = add i32 %z, 26 %r = add i32 %z, 26
ret i32 %r ret i32 %r
} }
define i8 @add_zext_cmp_mask_narrower_result(i32 %x) { define i8 @add_zext_cmp_mask_narrower_result(i32 %x) {
; CHECK-LABEL: add_zext_cmp_mask_narrower_result: ; CHECK-LABEL: add_zext_cmp_mask_narrower_result:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 0, 31, 31 ; CHECK-NEXT: clrlwi 3, 3, 31
; CHECK-NEXT: subfic 3, 3, 43 ; CHECK-NEXT: subfic 3, 3, 43
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = and i32 %x, 1 %a = and i32 %x, 1
%c = icmp eq i32 %a, 0 %c = icmp eq i32 %a, 0
%z = zext i1 %c to i8 %z = zext i1 %c to i8
%r = add i8 %z, 42 %r = add i8 %z, 42
ret i8 %r ret i8 %r
} }
▲ Show 20 Lines • Show All 73 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/branch_coalesce.ll

; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs -enable-ppc-branch-coalesce < %s | FileCheck %s
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s
; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s ; RUN: llc -mcpu=pwr8 -mtriple=powerpc64-unknown-linux-gnu -verify-machineinstrs < %s | FileCheck --check-prefix=CHECK-NOCOALESCE %s
; Function Attrs: nounwind ; Function Attrs: nounwind
define double @testBranchCoal(double %a, double %b, double %c, i32 %x) { define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
; CHECK-LABEL: @testBranchCoal ; CHECK-LABEL: @testBranchCoal
; CHECK: cmplwi [[CMPR:[0-7]+]], 6, 0 ; CHECK: cmplwi 6, 0
; CHECK: beq [[CMPR]], .LBB[[LAB1:[0-9_]+]] ; CHECK: beq 0, .LBB[[LAB1:[0-9_]+]]
; CHECK-DAG: addis [[LD1REG:[0-9]+]], 2, .LCPI0_0@toc@ha ; CHECK-DAG: addis [[LD1REG:[0-9]+]], 2, .LCPI0_0@toc@ha
; CHECK-DAG: addis [[LD2REG:[0-9]+]], 2, .LCPI0_1@toc@ha ; CHECK-DAG: addis [[LD2REG:[0-9]+]], 2, .LCPI0_1@toc@ha
; CHECK-DAG: xxlxor 2, 2, 2 ; CHECK-DAG: xxlxor 2, 2, 2
; CHECK-NOT: beq ; CHECK-NOT: beq
; CHECK-DAG: lfd 1, .LCPI0_0@toc@l([[LD1REG]]) ; CHECK-DAG: lfd 1, .LCPI0_0@toc@l([[LD1REG]])
; CHECK-DAG: lfd 3, .LCPI0_1@toc@l([[LD2REG]]) ; CHECK-DAG: lfd 3, .LCPI0_1@toc@l([[LD2REG]])
; CHECK: .LBB[[LAB1]] ; CHECK: .LBB[[LAB1]]
; CHECK: xsadddp 0, 1, 2 ; CHECK: xsadddp 0, 1, 2
; CHECK: xsadddp 1, 0, 3 ; CHECK: xsadddp 1, 0, 3
; CHECK: blr ; CHECK: blr
; CHECK-NOCOALESCE-LABEL: testBranchCoal: ; CHECK-NOCOALESCE-LABEL: testBranchCoal:
; CHECK-NOCOALESCE: # %bb.0: # %entry ; CHECK-NOCOALESCE: # %bb.0: # %entry
; CHECK-NOCOALESCE-NEXT: cmplwi 0, 6, 0 ; CHECK-NOCOALESCE-NEXT: cmplwi 6, 0
; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_5 ; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_5
; CHECK-NOCOALESCE-NEXT: # %bb.1: # %entry ; CHECK-NOCOALESCE-NEXT: # %bb.1: # %entry
; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_6 ; CHECK-NOCOALESCE-NEXT: bne 0, .LBB0_6
; CHECK-NOCOALESCE-NEXT: .LBB0_2: # %entry ; CHECK-NOCOALESCE-NEXT: .LBB0_2: # %entry
; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_4 ; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_4
; CHECK-NOCOALESCE-NEXT: .LBB0_3: # %entry ; CHECK-NOCOALESCE-NEXT: .LBB0_3: # %entry
; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_1@toc@ha ; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
; CHECK-NOCOALESCE-NEXT: lfd 3, .LCPI0_1@toc@l(3) ; CHECK-NOCOALESCE-NEXT: lfd 3, .LCPI0_1@toc@l(3)
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llvm/test/CodeGen/PowerPC/bswap64.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \ ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \
; RUN: -mcpu=pwr9 | FileCheck %s ; RUN: -mcpu=pwr9 | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \ ; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64le-unknown-unknown \
; RUN: -mcpu=pwr9 -mattr=-altivec | FileCheck %s --check-prefix=NO-ALTIVEC ; RUN: -mcpu=pwr9 -mattr=-altivec | FileCheck %s --check-prefix=NO-ALTIVEC
declare i64 @llvm.bswap.i64(i64) declare i64 @llvm.bswap.i64(i64)
define i64 @bswap64(i64 %x) { define i64 @bswap64(i64 %x) {
; CHECK-LABEL: bswap64: ; CHECK-LABEL: bswap64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrdd 34, 3, 3 ; CHECK-NEXT: mtvsrdd 34, 3, 3
; CHECK-NEXT: xxbrd 0, 34 ; CHECK-NEXT: xxbrd 0, 34
; CHECK-NEXT: mfvsrd 3, 0 ; CHECK-NEXT: mffprd 3, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; NO-ALTIVEC-LABEL: bswap64: ; NO-ALTIVEC-LABEL: bswap64:
; NO-ALTIVEC: # %bb.0: # %entry ; NO-ALTIVEC: # %bb.0: # %entry
; NO-ALTIVEC-NEXT: rotldi 5, 3, 16 ; NO-ALTIVEC-NEXT: rotldi 5, 3, 16
; NO-ALTIVEC-NEXT: rotldi 4, 3, 8 ; NO-ALTIVEC-NEXT: rotldi 4, 3, 8
; NO-ALTIVEC-NEXT: rldimi 4, 5, 8, 48 ; NO-ALTIVEC-NEXT: rldimi 4, 5, 8, 48
; NO-ALTIVEC-NEXT: rotldi 5, 3, 24 ; NO-ALTIVEC-NEXT: rotldi 5, 3, 24
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llvm/test/CodeGen/PowerPC/build-vector-tests.ll

Show First 20 Lines • Show All 826 Lines • ▼ Show 20 Lines
; P9LE-NEXT: rldimi r5, r6, 32, 0 ; P9LE-NEXT: rldimi r5, r6, 32, 0
; P9LE-NEXT: mtvsrdd v2, r5, r3 ; P9LE-NEXT: mtvsrdd v2, r5, r3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromRegsi: ; P8BE-LABEL: fromRegsi:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: rldimi r6, r5, 32, 0 ; P8BE-NEXT: rldimi r6, r5, 32, 0
; P8BE-NEXT: rldimi r4, r3, 32, 0 ; P8BE-NEXT: rldimi r4, r3, 32, 0
; P8BE-NEXT: mtvsrd f0, r6 ; P8BE-NEXT: mtfprd f0, r6
; P8BE-NEXT: mtvsrd f1, r4 ; P8BE-NEXT: mtfprd f1, r4
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRegsi: ; P8LE-LABEL: fromRegsi:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: rldimi r3, r4, 32, 0 ; P8LE-NEXT: rldimi r3, r4, 32, 0
; P8LE-NEXT: rldimi r5, r6, 32, 0 ; P8LE-NEXT: rldimi r5, r6, 32, 0
; P8LE-NEXT: mtvsrd f0, r3 ; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: mtvsrd f1, r5 ; P8LE-NEXT: mtfprd f1, r5
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
%vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
%vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2
%vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3
ret <4 x i32> %vecinit3 ret <4 x i32> %vecinit3
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; P8BE-LABEL: fromRandMemConsi: ; P8BE-LABEL: fromRandMemConsi:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lwz r4, 8(r3) ; P8BE-NEXT: lwz r4, 8(r3)
; P8BE-NEXT: lwz r5, 352(r3) ; P8BE-NEXT: lwz r5, 352(r3)
; P8BE-NEXT: lwz r6, 16(r3) ; P8BE-NEXT: lwz r6, 16(r3)
; P8BE-NEXT: lwz r3, 72(r3) ; P8BE-NEXT: lwz r3, 72(r3)
; P8BE-NEXT: rldimi r5, r4, 32, 0 ; P8BE-NEXT: rldimi r5, r4, 32, 0
; P8BE-NEXT: rldimi r3, r6, 32, 0 ; P8BE-NEXT: rldimi r3, r6, 32, 0
; P8BE-NEXT: mtvsrd f0, r5 ; P8BE-NEXT: mtfprd f0, r5
; P8BE-NEXT: mtvsrd f1, r3 ; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRandMemConsi: ; P8LE-LABEL: fromRandMemConsi:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lwz r4, 16(r3) ; P8LE-NEXT: lwz r4, 16(r3)
; P8LE-NEXT: lwz r5, 72(r3) ; P8LE-NEXT: lwz r5, 72(r3)
; P8LE-NEXT: lwz r6, 8(r3) ; P8LE-NEXT: lwz r6, 8(r3)
; P8LE-NEXT: lwz r3, 352(r3) ; P8LE-NEXT: lwz r3, 352(r3)
; P8LE-NEXT: rldimi r4, r5, 32, 0 ; P8LE-NEXT: rldimi r4, r5, 32, 0
; P8LE-NEXT: rldimi r6, r3, 32, 0 ; P8LE-NEXT: rldimi r6, r3, 32, 0
; P8LE-NEXT: mtvsrd f0, r4 ; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtvsrd f1, r6 ; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4
%0 = load i32, i32* %arrayidx, align 4 %0 = load i32, i32* %arrayidx, align 4
%vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
%arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18
%1 = load i32, i32* %arrayidx1, align 4 %1 = load i32, i32* %arrayidx1, align 4
Show All 39 Lines
; P8BE-NEXT: sldi r4, r4, 2 ; P8BE-NEXT: sldi r4, r4, 2
; P8BE-NEXT: add r3, r3, r4 ; P8BE-NEXT: add r3, r3, r4
; P8BE-NEXT: lwz r4, 8(r3) ; P8BE-NEXT: lwz r4, 8(r3)
; P8BE-NEXT: lwz r5, 32(r3) ; P8BE-NEXT: lwz r5, 32(r3)
; P8BE-NEXT: lwz r6, 16(r3) ; P8BE-NEXT: lwz r6, 16(r3)
; P8BE-NEXT: lwz r3, 4(r3) ; P8BE-NEXT: lwz r3, 4(r3)
; P8BE-NEXT: rldimi r5, r4, 32, 0 ; P8BE-NEXT: rldimi r5, r4, 32, 0
; P8BE-NEXT: rldimi r3, r6, 32, 0 ; P8BE-NEXT: rldimi r3, r6, 32, 0
; P8BE-NEXT: mtvsrd f0, r5 ; P8BE-NEXT: mtfprd f0, r5
; P8BE-NEXT: mtvsrd f1, r3 ; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRandMemVari: ; P8LE-LABEL: fromRandMemVari:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: sldi r4, r4, 2 ; P8LE-NEXT: sldi r4, r4, 2
; P8LE-NEXT: add r3, r3, r4 ; P8LE-NEXT: add r3, r3, r4
; P8LE-NEXT: lwz r4, 16(r3) ; P8LE-NEXT: lwz r4, 16(r3)
; P8LE-NEXT: lwz r5, 4(r3) ; P8LE-NEXT: lwz r5, 4(r3)
; P8LE-NEXT: lwz r6, 8(r3) ; P8LE-NEXT: lwz r6, 8(r3)
; P8LE-NEXT: lwz r3, 32(r3) ; P8LE-NEXT: lwz r3, 32(r3)
; P8LE-NEXT: rldimi r4, r5, 32, 0 ; P8LE-NEXT: rldimi r4, r5, 32, 0
; P8LE-NEXT: rldimi r6, r3, 32, 0 ; P8LE-NEXT: rldimi r6, r3, 32, 0
; P8LE-NEXT: mtvsrd f0, r4 ; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtvsrd f1, r6 ; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%add = add nsw i32 %elem, 4 %add = add nsw i32 %elem, 4
%idxprom = sext i32 %add to i64 %idxprom = sext i32 %add to i64
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
%0 = load i32, i32* %arrayidx, align 4 %0 = load i32, i32* %arrayidx, align 4
%vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
Show All 23 Lines
; ;
; P9LE-LABEL: spltRegVali: ; P9LE-LABEL: spltRegVali:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mtvsrws v2, r3 ; P9LE-NEXT: mtvsrws v2, r3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: spltRegVali: ; P8BE-LABEL: spltRegVali:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mtvsrwz f0, r3 ; P8BE-NEXT: mtfprwz f0, r3
; P8BE-NEXT: xxspltw v2, vs0, 1 ; P8BE-NEXT: xxspltw v2, vs0, 1
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: spltRegVali: ; P8LE-LABEL: spltRegVali:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mtvsrwz f0, r3 ; P8LE-NEXT: mtfprwz f0, r3
; P8LE-NEXT: xxspltw v2, vs0, 1 ; P8LE-NEXT: xxspltw v2, vs0, 1
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %splat.splat ret <4 x i32> %splat.splat
} }
▲ Show 20 Lines • Show All 1,082 Lines • ▼ Show 20 Lines
; P9LE-NEXT: rldimi r5, r6, 32, 0 ; P9LE-NEXT: rldimi r5, r6, 32, 0
; P9LE-NEXT: mtvsrdd v2, r5, r3 ; P9LE-NEXT: mtvsrdd v2, r5, r3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromRegsui: ; P8BE-LABEL: fromRegsui:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: rldimi r6, r5, 32, 0 ; P8BE-NEXT: rldimi r6, r5, 32, 0
; P8BE-NEXT: rldimi r4, r3, 32, 0 ; P8BE-NEXT: rldimi r4, r3, 32, 0
; P8BE-NEXT: mtvsrd f0, r6 ; P8BE-NEXT: mtfprd f0, r6
; P8BE-NEXT: mtvsrd f1, r4 ; P8BE-NEXT: mtfprd f1, r4
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRegsui: ; P8LE-LABEL: fromRegsui:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: rldimi r3, r4, 32, 0 ; P8LE-NEXT: rldimi r3, r4, 32, 0
; P8LE-NEXT: rldimi r5, r6, 32, 0 ; P8LE-NEXT: rldimi r5, r6, 32, 0
; P8LE-NEXT: mtvsrd f0, r3 ; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: mtvsrd f1, r5 ; P8LE-NEXT: mtfprd f1, r5
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%vecinit = insertelement <4 x i32> undef, i32 %a, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %a, i32 0
%vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1 %vecinit1 = insertelement <4 x i32> %vecinit, i32 %b, i32 1
%vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2 %vecinit2 = insertelement <4 x i32> %vecinit1, i32 %c, i32 2
%vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3 %vecinit3 = insertelement <4 x i32> %vecinit2, i32 %d, i32 3
ret <4 x i32> %vecinit3 ret <4 x i32> %vecinit3
▲ Show 20 Lines • Show All 261 Lines • ▼ Show 20 Lines
; P8BE-LABEL: fromRandMemConsui: ; P8BE-LABEL: fromRandMemConsui:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: lwz r4, 8(r3) ; P8BE-NEXT: lwz r4, 8(r3)
; P8BE-NEXT: lwz r5, 352(r3) ; P8BE-NEXT: lwz r5, 352(r3)
; P8BE-NEXT: lwz r6, 16(r3) ; P8BE-NEXT: lwz r6, 16(r3)
; P8BE-NEXT: lwz r3, 72(r3) ; P8BE-NEXT: lwz r3, 72(r3)
; P8BE-NEXT: rldimi r5, r4, 32, 0 ; P8BE-NEXT: rldimi r5, r4, 32, 0
; P8BE-NEXT: rldimi r3, r6, 32, 0 ; P8BE-NEXT: rldimi r3, r6, 32, 0
; P8BE-NEXT: mtvsrd f0, r5 ; P8BE-NEXT: mtfprd f0, r5
; P8BE-NEXT: mtvsrd f1, r3 ; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRandMemConsui: ; P8LE-LABEL: fromRandMemConsui:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: lwz r4, 16(r3) ; P8LE-NEXT: lwz r4, 16(r3)
; P8LE-NEXT: lwz r5, 72(r3) ; P8LE-NEXT: lwz r5, 72(r3)
; P8LE-NEXT: lwz r6, 8(r3) ; P8LE-NEXT: lwz r6, 8(r3)
; P8LE-NEXT: lwz r3, 352(r3) ; P8LE-NEXT: lwz r3, 352(r3)
; P8LE-NEXT: rldimi r4, r5, 32, 0 ; P8LE-NEXT: rldimi r4, r5, 32, 0
; P8LE-NEXT: rldimi r6, r3, 32, 0 ; P8LE-NEXT: rldimi r6, r3, 32, 0
; P8LE-NEXT: mtvsrd f0, r4 ; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtvsrd f1, r6 ; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 4 %arrayidx = getelementptr inbounds i32, i32* %arr, i64 4
%0 = load i32, i32* %arrayidx, align 4 %0 = load i32, i32* %arrayidx, align 4
%vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
%arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18 %arrayidx1 = getelementptr inbounds i32, i32* %arr, i64 18
%1 = load i32, i32* %arrayidx1, align 4 %1 = load i32, i32* %arrayidx1, align 4
Show All 39 Lines
; P8BE-NEXT: sldi r4, r4, 2 ; P8BE-NEXT: sldi r4, r4, 2
; P8BE-NEXT: add r3, r3, r4 ; P8BE-NEXT: add r3, r3, r4
; P8BE-NEXT: lwz r4, 8(r3) ; P8BE-NEXT: lwz r4, 8(r3)
; P8BE-NEXT: lwz r5, 32(r3) ; P8BE-NEXT: lwz r5, 32(r3)
; P8BE-NEXT: lwz r6, 16(r3) ; P8BE-NEXT: lwz r6, 16(r3)
; P8BE-NEXT: lwz r3, 4(r3) ; P8BE-NEXT: lwz r3, 4(r3)
; P8BE-NEXT: rldimi r5, r4, 32, 0 ; P8BE-NEXT: rldimi r5, r4, 32, 0
; P8BE-NEXT: rldimi r3, r6, 32, 0 ; P8BE-NEXT: rldimi r3, r6, 32, 0
; P8BE-NEXT: mtvsrd f0, r5 ; P8BE-NEXT: mtfprd f0, r5
; P8BE-NEXT: mtvsrd f1, r3 ; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRandMemVarui: ; P8LE-LABEL: fromRandMemVarui:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: sldi r4, r4, 2 ; P8LE-NEXT: sldi r4, r4, 2
; P8LE-NEXT: add r3, r3, r4 ; P8LE-NEXT: add r3, r3, r4
; P8LE-NEXT: lwz r4, 16(r3) ; P8LE-NEXT: lwz r4, 16(r3)
; P8LE-NEXT: lwz r5, 4(r3) ; P8LE-NEXT: lwz r5, 4(r3)
; P8LE-NEXT: lwz r6, 8(r3) ; P8LE-NEXT: lwz r6, 8(r3)
; P8LE-NEXT: lwz r3, 32(r3) ; P8LE-NEXT: lwz r3, 32(r3)
; P8LE-NEXT: rldimi r4, r5, 32, 0 ; P8LE-NEXT: rldimi r4, r5, 32, 0
; P8LE-NEXT: rldimi r6, r3, 32, 0 ; P8LE-NEXT: rldimi r6, r3, 32, 0
; P8LE-NEXT: mtvsrd f0, r4 ; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtvsrd f1, r6 ; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%add = add nsw i32 %elem, 4 %add = add nsw i32 %elem, 4
%idxprom = sext i32 %add to i64 %idxprom = sext i32 %add to i64
%arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom %arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom
%0 = load i32, i32* %arrayidx, align 4 %0 = load i32, i32* %arrayidx, align 4
%vecinit = insertelement <4 x i32> undef, i32 %0, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %0, i32 0
Show All 23 Lines
; ;
; P9LE-LABEL: spltRegValui: ; P9LE-LABEL: spltRegValui:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mtvsrws v2, r3 ; P9LE-NEXT: mtvsrws v2, r3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: spltRegValui: ; P8BE-LABEL: spltRegValui:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mtvsrwz f0, r3 ; P8BE-NEXT: mtfprwz f0, r3
; P8BE-NEXT: xxspltw v2, vs0, 1 ; P8BE-NEXT: xxspltw v2, vs0, 1
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: spltRegValui: ; P8LE-LABEL: spltRegValui:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mtvsrwz f0, r3 ; P8LE-NEXT: mtfprwz f0, r3
; P8LE-NEXT: xxspltw v2, vs0, 1 ; P8LE-NEXT: xxspltw v2, vs0, 1
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0 %splat.splatinsert = insertelement <4 x i32> undef, i32 %val, i32 0
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %splat.splat ret <4 x i32> %splat.splat
} }
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; ;
; P9LE-LABEL: fromRegsll: ; P9LE-LABEL: fromRegsll:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mtvsrdd v2, r4, r3 ; P9LE-NEXT: mtvsrdd v2, r4, r3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromRegsll: ; P8BE-LABEL: fromRegsll:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mtvsrd f0, r4 ; P8BE-NEXT: mtfprd f0, r4
; P8BE-NEXT: mtvsrd f1, r3 ; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRegsll: ; P8LE-LABEL: fromRegsll:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mtvsrd f0, r3 ; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: mtvsrd f1, r4 ; P8LE-NEXT: mtfprd f1, r4
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
%vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
ret <2 x i64> %vecinit1 ret <2 x i64> %vecinit1
} }
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; P9LE-NEXT: ld r3, 144(r3) ; P9LE-NEXT: ld r3, 144(r3)
; P9LE-NEXT: mtvsrdd v2, r3, r4 ; P9LE-NEXT: mtvsrdd v2, r3, r4
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromRandMemConsll: ; P8BE-LABEL: fromRandMemConsll:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: ld r4, 144(r3) ; P8BE-NEXT: ld r4, 144(r3)
; P8BE-NEXT: ld r3, 32(r3) ; P8BE-NEXT: ld r3, 32(r3)
; P8BE-NEXT: mtvsrd f0, r4 ; P8BE-NEXT: mtfprd f0, r4
; P8BE-NEXT: mtvsrd f1, r3 ; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRandMemConsll: ; P8LE-LABEL: fromRandMemConsll:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: ld r4, 32(r3) ; P8LE-NEXT: ld r4, 32(r3)
; P8LE-NEXT: ld r3, 144(r3) ; P8LE-NEXT: ld r3, 144(r3)
; P8LE-NEXT: mtvsrd f0, r4 ; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtvsrd f1, r3 ; P8LE-NEXT: mtfprd f1, r3
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4
%0 = load i64, i64* %arrayidx, align 8 %0 = load i64, i64* %arrayidx, align 8
%vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
%arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18
%1 = load i64, i64* %arrayidx1, align 8 %1 = load i64, i64* %arrayidx1, align 8
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; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromRandMemVarll: ; P8BE-LABEL: fromRandMemVarll:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: sldi r4, r4, 3 ; P8BE-NEXT: sldi r4, r4, 3
; P8BE-NEXT: add r3, r3, r4 ; P8BE-NEXT: add r3, r3, r4
; P8BE-NEXT: ld r4, 8(r3) ; P8BE-NEXT: ld r4, 8(r3)
; P8BE-NEXT: ld r3, 32(r3) ; P8BE-NEXT: ld r3, 32(r3)
; P8BE-NEXT: mtvsrd f0, r4 ; P8BE-NEXT: mtfprd f0, r4
; P8BE-NEXT: mtvsrd f1, r3 ; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRandMemVarll: ; P8LE-LABEL: fromRandMemVarll:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: sldi r4, r4, 3 ; P8LE-NEXT: sldi r4, r4, 3
; P8LE-NEXT: add r3, r3, r4 ; P8LE-NEXT: add r3, r3, r4
; P8LE-NEXT: ld r4, 32(r3) ; P8LE-NEXT: ld r4, 32(r3)
; P8LE-NEXT: ld r3, 8(r3) ; P8LE-NEXT: ld r3, 8(r3)
; P8LE-NEXT: mtvsrd f0, r4 ; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtvsrd f1, r3 ; P8LE-NEXT: mtfprd f1, r3
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%add = add nsw i32 %elem, 4 %add = add nsw i32 %elem, 4
%idxprom = sext i32 %add to i64 %idxprom = sext i32 %add to i64
%arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom
%0 = load i64, i64* %arrayidx, align 8 %0 = load i64, i64* %arrayidx, align 8
%vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
Show All 13 Lines
; ;
; P9LE-LABEL: spltRegValll: ; P9LE-LABEL: spltRegValll:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mtvsrdd v2, r3, r3 ; P9LE-NEXT: mtvsrdd v2, r3, r3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: spltRegValll: ; P8BE-LABEL: spltRegValll:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mtvsrd f0, r3 ; P8BE-NEXT: mtfprd f0, r3
; P8BE-NEXT: xxspltd v2, vs0, 0 ; P8BE-NEXT: xxspltd v2, vs0, 0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: spltRegValll: ; P8LE-LABEL: spltRegValll:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mtvsrd f0, r3 ; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: xxspltd v2, vs0, 0 ; P8LE-NEXT: xxspltd v2, vs0, 0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0
%splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
ret <2 x i64> %splat.splat ret <2 x i64> %splat.splat
} }
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; ;
; P9LE-LABEL: fromRegsull: ; P9LE-LABEL: fromRegsull:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mtvsrdd v2, r4, r3 ; P9LE-NEXT: mtvsrdd v2, r4, r3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromRegsull: ; P8BE-LABEL: fromRegsull:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mtvsrd f0, r4 ; P8BE-NEXT: mtfprd f0, r4
; P8BE-NEXT: mtvsrd f1, r3 ; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRegsull: ; P8LE-LABEL: fromRegsull:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mtvsrd f0, r3 ; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: mtvsrd f1, r4 ; P8LE-NEXT: mtfprd f1, r4
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%vecinit = insertelement <2 x i64> undef, i64 %a, i32 0 %vecinit = insertelement <2 x i64> undef, i64 %a, i32 0
%vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1 %vecinit1 = insertelement <2 x i64> %vecinit, i64 %b, i32 1
ret <2 x i64> %vecinit1 ret <2 x i64> %vecinit1
} }
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; P9LE-NEXT: ld r3, 144(r3) ; P9LE-NEXT: ld r3, 144(r3)
; P9LE-NEXT: mtvsrdd v2, r3, r4 ; P9LE-NEXT: mtvsrdd v2, r3, r4
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromRandMemConsull: ; P8BE-LABEL: fromRandMemConsull:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: ld r4, 144(r3) ; P8BE-NEXT: ld r4, 144(r3)
; P8BE-NEXT: ld r3, 32(r3) ; P8BE-NEXT: ld r3, 32(r3)
; P8BE-NEXT: mtvsrd f0, r4 ; P8BE-NEXT: mtfprd f0, r4
; P8BE-NEXT: mtvsrd f1, r3 ; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRandMemConsull: ; P8LE-LABEL: fromRandMemConsull:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: ld r4, 32(r3) ; P8LE-NEXT: ld r4, 32(r3)
; P8LE-NEXT: ld r3, 144(r3) ; P8LE-NEXT: ld r3, 144(r3)
; P8LE-NEXT: mtvsrd f0, r4 ; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtvsrd f1, r3 ; P8LE-NEXT: mtfprd f1, r3
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%arrayidx = getelementptr inbounds i64, i64* %arr, i64 4 %arrayidx = getelementptr inbounds i64, i64* %arr, i64 4
%0 = load i64, i64* %arrayidx, align 8 %0 = load i64, i64* %arrayidx, align 8
%vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
%arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18 %arrayidx1 = getelementptr inbounds i64, i64* %arr, i64 18
%1 = load i64, i64* %arrayidx1, align 8 %1 = load i64, i64* %arrayidx1, align 8
Show All 21 Lines
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: fromRandMemVarull: ; P8BE-LABEL: fromRandMemVarull:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: sldi r4, r4, 3 ; P8BE-NEXT: sldi r4, r4, 3
; P8BE-NEXT: add r3, r3, r4 ; P8BE-NEXT: add r3, r3, r4
; P8BE-NEXT: ld r4, 8(r3) ; P8BE-NEXT: ld r4, 8(r3)
; P8BE-NEXT: ld r3, 32(r3) ; P8BE-NEXT: ld r3, 32(r3)
; P8BE-NEXT: mtvsrd f0, r4 ; P8BE-NEXT: mtfprd f0, r4
; P8BE-NEXT: mtvsrd f1, r3 ; P8BE-NEXT: mtfprd f1, r3
; P8BE-NEXT: xxmrghd v2, vs1, vs0 ; P8BE-NEXT: xxmrghd v2, vs1, vs0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: fromRandMemVarull: ; P8LE-LABEL: fromRandMemVarull:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: sldi r4, r4, 3 ; P8LE-NEXT: sldi r4, r4, 3
; P8LE-NEXT: add r3, r3, r4 ; P8LE-NEXT: add r3, r3, r4
; P8LE-NEXT: ld r4, 32(r3) ; P8LE-NEXT: ld r4, 32(r3)
; P8LE-NEXT: ld r3, 8(r3) ; P8LE-NEXT: ld r3, 8(r3)
; P8LE-NEXT: mtvsrd f0, r4 ; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: mtvsrd f1, r3 ; P8LE-NEXT: mtfprd f1, r3
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%add = add nsw i32 %elem, 4 %add = add nsw i32 %elem, 4
%idxprom = sext i32 %add to i64 %idxprom = sext i32 %add to i64
%arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom %arrayidx = getelementptr inbounds i64, i64* %arr, i64 %idxprom
%0 = load i64, i64* %arrayidx, align 8 %0 = load i64, i64* %arrayidx, align 8
%vecinit = insertelement <2 x i64> undef, i64 %0, i32 0 %vecinit = insertelement <2 x i64> undef, i64 %0, i32 0
Show All 13 Lines
; ;
; P9LE-LABEL: spltRegValull: ; P9LE-LABEL: spltRegValull:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: mtvsrdd v2, r3, r3 ; P9LE-NEXT: mtvsrdd v2, r3, r3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: spltRegValull: ; P8BE-LABEL: spltRegValull:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mtvsrd f0, r3 ; P8BE-NEXT: mtfprd f0, r3
; P8BE-NEXT: xxspltd v2, vs0, 0 ; P8BE-NEXT: xxspltd v2, vs0, 0
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: spltRegValull: ; P8LE-LABEL: spltRegValull:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: mtvsrd f0, r3 ; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: xxspltd v2, vs0, 0 ; P8LE-NEXT: xxspltd v2, vs0, 0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0 %splat.splatinsert = insertelement <2 x i64> undef, i64 %val, i32 0
%splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
ret <2 x i64> %splat.splat ret <2 x i64> %splat.splat
} }
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llvm/test/CodeGen/PowerPC/canonical-merge-shuffles.ll

Show First 20 Lines • Show All 211 Lines • ▼ Show 20 Lines
} }
define dso_local <8 x i16> @testmrglb3(<8 x i8>* nocapture readonly %a) local_unnamed_addr #0 { define dso_local <8 x i16> @testmrglb3(<8 x i8>* nocapture readonly %a) local_unnamed_addr #0 {
; CHECK-P8-LABEL: testmrglb3: ; CHECK-P8-LABEL: testmrglb3:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: ld r3, 0(r3) ; CHECK-P8-NEXT: ld r3, 0(r3)
; CHECK-P8-NEXT: addis r4, r2, .LCPI12_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI12_0@toc@ha
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI12_0@toc@l ; CHECK-P8-NEXT: addi r3, r4, .LCPI12_0@toc@l
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vperm v2, v2, v4, v3 ; CHECK-P8-NEXT: vperm v2, v2, v4, v3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: testmrglb3: ; CHECK-P9-LABEL: testmrglb3:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
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llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir

Show First 20 Lines • Show All 885 Lines • ▼ Show 20 Lines bb.0.entry:
liveins: $x3, $x4 liveins: $x3, $x4
%1 = COPY $x4 %1 = COPY $x4
%0 = COPY $x3 %0 = COPY $x3
%2 = RLDICL %1, 0, 58 %2 = RLDICL %1, 0, 58
%3 = LI -37 %3 = LI -37
%4 = RLDCL_rec %0, killed %3, 0, implicit-def $cr0 %4 = RLDCL_rec %0, killed %3, 0, implicit-def $cr0
; CHECK: RLDICL_rec %0, 27, 0, implicit-def $cr0 ; CHECK: RLDICL_rec %0, 27, 0, implicit-def $cr0
; CHECK-LATE: rldicl. 5, 3, 27, 0 ; CHECK-LATE: rotldi. 5, 3, 27
%5 = COPY killed $cr0 %5 = COPY killed $cr0
%6 = ISEL8 %2, %0, %5.sub_eq %6 = ISEL8 %2, %0, %5.sub_eq
$x3 = COPY %6 $x3 = COPY %6
BLR8 implicit $lr8, implicit $rm, implicit $x3 BLR8 implicit $lr8, implicit $rm, implicit $x3
... ...
--- ---
name: testRLDCR name: testRLDCR
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llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir

Show First 20 Lines • Show All 3,722 Lines • ▼ Show 20 Lines bb.0.entry:
liveins: $x3, $x4 liveins: $x3, $x4
%1 = COPY $x4 %1 = COPY $x4
%0 = COPY $x3 %0 = COPY $x3
%2 = RLDICL %1, 0, 58 %2 = RLDICL %1, 0, 58
%3 = LI 37 %3 = LI 37
%4 = RLDCL_rec %0, killed %3, 0, implicit-def $cr0 %4 = RLDCL_rec %0, killed %3, 0, implicit-def $cr0
; CHECK: RLDICL_rec %0, 37, 0, implicit-def $cr0 ; CHECK: RLDICL_rec %0, 37, 0, implicit-def $cr0
; CHECK-LATE: rldicl. 5, 3, 37, 0 ; CHECK-LATE: rotldi. 5, 3, 37
%5 = COPY killed $cr0 %5 = COPY killed $cr0
%6 = ISEL8 %2, %0, %5.sub_eq %6 = ISEL8 %2, %0, %5.sub_eq
$x3 = COPY %6 $x3 = COPY %6
BLR8 implicit $lr8, implicit $rm, implicit $x3 BLR8 implicit $lr8, implicit $rm, implicit $x3
... ...
--- ---
name: testRLDCR name: testRLDCR
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llvm/test/CodeGen/PowerPC/crbits.ll

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define signext i32 @exttest7(i32 signext %a) #0 { define signext i32 @exttest7(i32 signext %a) #0 {
entry: entry:
%cmp = icmp eq i32 %a, 5 %cmp = icmp eq i32 %a, 5
%cond = select i1 %cmp, i32 7, i32 8 %cond = select i1 %cmp, i32 7, i32 8
ret i32 %cond ret i32 %cond
; CHECK-LABEL: @exttest7 ; CHECK-LABEL: @exttest7
; CHECK-DAG: cmpwi {{[0-9]+}}, 3, 5 ; CHECK-DAG: cmpwi 3, 5
; CHECK-DAG: li [[REG1:[0-9]+]], 8 ; CHECK-DAG: li [[REG1:[0-9]+]], 8
; CHECK-DAG: li [[REG2:[0-9]+]], 7 ; CHECK-DAG: li [[REG2:[0-9]+]], 7
; CHECK: isel 3, [[REG2]], [[REG1]], ; CHECK: isel 3, [[REG2]], [[REG1]],
; CHECK-NOT: rldicl ; CHECK-NOT: rldicl
; CHECK: blr ; CHECK: blr
} }
define zeroext i32 @exttest8() #0 { define zeroext i32 @exttest8() #0 {
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llvm/test/CodeGen/PowerPC/dform-adjust.ll

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; CHECK-NEXT: li 8, 15 ; CHECK-NEXT: li 8, 15
; CHECK-NEXT: mfvsrld 9, 0 ; CHECK-NEXT: mfvsrld 9, 0
; CHECK-NEXT: ldx 5, 3, 5 ; CHECK-NEXT: ldx 5, 3, 5
; CHECK-NEXT: ldx 6, 3, 6 ; CHECK-NEXT: ldx 6, 3, 6
; CHECK-NEXT: ldx 7, 3, 7 ; CHECK-NEXT: ldx 7, 3, 7
; CHECK-NEXT: ldx 3, 3, 8 ; CHECK-NEXT: ldx 3, 3, 8
; CHECK-NEXT: mffprd 8, 0 ; CHECK-NEXT: mffprd 8, 0
; CHECK-NEXT: mfvsrld 10, 1 ; CHECK-NEXT: mfvsrld 10, 1
; CHECK-NEXT: mfvsrd 11, 1 ; CHECK-NEXT: mffprd 11, 1
; CHECK-NEXT: mulld 8, 9, 8 ; CHECK-NEXT: mulld 8, 9, 8
; CHECK-NEXT: mulld 5, 8, 5 ; CHECK-NEXT: mulld 5, 8, 5
; CHECK-NEXT: mulld 5, 5, 10 ; CHECK-NEXT: mulld 5, 5, 10
; CHECK-NEXT: mulld 5, 5, 11 ; CHECK-NEXT: mulld 5, 5, 11
; CHECK-NEXT: mulld 5, 5, 6 ; CHECK-NEXT: mulld 5, 5, 6
; CHECK-NEXT: mulld 5, 5, 7 ; CHECK-NEXT: mulld 5, 5, 7
; CHECK-NEXT: maddld 3, 5, 3, 4 ; CHECK-NEXT: maddld 3, 5, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
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llvm/test/CodeGen/PowerPC/expand-isel.ll

target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel
define signext i32 @testExpandISELToIfElse(i32 signext %i, i32 signext %j) { define signext i32 @testExpandISELToIfElse(i32 signext %i, i32 signext %j) {
entry: entry:
%cmp = icmp sgt i32 %i, 0 %cmp = icmp sgt i32 %i, 0
%add = add nsw i32 %i, 1 %add = add nsw i32 %i, 1
%cond = select i1 %cmp, i32 %add, i32 %j %cond = select i1 %cmp, i32 %add, i32 %j
ret i32 %cond ret i32 %cond
; CHECK-LABEL: @testExpandISELToIfElse ; CHECK-LABEL: @testExpandISELToIfElse
; CHECK: addi r5, r3, 1 ; CHECK: addi r5, r3, 1
; CHECK-NEXT: cmpwi cr0, r3, 0 ; CHECK-NEXT: cmpwi r3, 0
; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] ; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK: ori r3, r4, 0 ; CHECK: ori r3, r4, 0
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NEXT: [[TRUE]] ; CHECK-NEXT: [[TRUE]]
; CHECK-NEXT: addi r3, r5, 0 ; CHECK-NEXT: addi r3, r5, 0
; CHECK-NEXT: [[SUCCESSOR]] ; CHECK-NEXT: [[SUCCESSOR]]
; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
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entry: entry:
%cmp = icmp sgt i32 %g, 0 %cmp = icmp sgt i32 %g, 0
%a.b = select i1 %cmp, i32 %a, i32 %b %a.b = select i1 %cmp, i32 %a, i32 %b
%d.f = select i1 %cmp, i32 %d, i32 %f %d.f = select i1 %cmp, i32 %d, i32 %f
%add = add nsw i32 %a.b, %d.f %add = add nsw i32 %a.b, %d.f
ret i32 %add ret i32 %add
; CHECK-LABEL: @testExpandISELsTo2ORIs1ADDI ; CHECK-LABEL: @testExpandISELsTo2ORIs1ADDI
; CHECK: cmpwi cr0, r7, 0 ; CHECK: cmpwi r7, 0
; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] ; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK: ori r3, r4, 0 ; CHECK: ori r3, r4, 0
; CHECK-NEXT: ori r4, r6, 0 ; CHECK-NEXT: ori r4, r6, 0
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NEXT: [[TRUE]] ; CHECK-NEXT: [[TRUE]]
; CHECK-NEXT: addi r4, r5, 0 ; CHECK-NEXT: addi r4, r5, 0
; CHECK-NEXT: [[SUCCESSOR]] ; CHECK-NEXT: [[SUCCESSOR]]
; CHECK-NEXT: add r3, r3, r4 ; CHECK-NEXT: add r3, r3, r4
Show All 9 Linesentry:
%cmp = icmp sgt i32 %g, 0 %cmp = icmp sgt i32 %g, 0
%a.b = select i1 %cmp, i32 %a, i32 %b %a.b = select i1 %cmp, i32 %a, i32 %b
%d.f = select i1 %cmp, i32 %d, i32 %f %d.f = select i1 %cmp, i32 %d, i32 %f
%add1 = add nsw i32 %a.b, %d.f %add1 = add nsw i32 %a.b, %d.f
%add2 = add nsw i32 %a, %add1 %add2 = add nsw i32 %a, %add1
ret i32 %add2 ret i32 %add2
; CHECK-LABEL: @testExpandISELsTo1ORI1ADDI ; CHECK-LABEL: @testExpandISELsTo1ORI1ADDI
; CHECK: cmpwi cr0, r7, 0 ; CHECK: cmpwi r7, 0
; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] ; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK: ori r5, r6, 0 ; CHECK: ori r5, r6, 0
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NEXT: [[TRUE]] ; CHECK-NEXT: [[TRUE]]
; CHECK-NEXT: addi r4, r3, 0 ; CHECK-NEXT: addi r4, r3, 0
; CHECK-NEXT: [[SUCCESSOR]] ; CHECK-NEXT: [[SUCCESSOR]]
; CHECK-NEXT: add r4, r4, r5 ; CHECK-NEXT: add r4, r4, r5
; CHECK-NEXT: add r3, r3, r4 ; CHECK-NEXT: add r3, r3, r4
Show All 10 Linesentry:
%a.b = select i1 %cmp, i32 %a, i32 %b %a.b = select i1 %cmp, i32 %a, i32 %b
%d.f = select i1 %cmp, i32 %d, i32 %f %d.f = select i1 %cmp, i32 %d, i32 %f
%add1 = add nsw i32 %a.b, %d.f %add1 = add nsw i32 %a.b, %d.f
%add2 = add nsw i32 %a, %add1 %add2 = add nsw i32 %a, %add1
%sub1 = sub nsw i32 %add2, %d %sub1 = sub nsw i32 %add2, %d
ret i32 %sub1 ret i32 %sub1
; CHECK-LABEL: @testExpandISELsTo0ORI2ADDIs ; CHECK-LABEL: @testExpandISELsTo0ORI2ADDIs
; CHECK: cmpwi cr0, r7, 0 ; CHECK: cmpwi r7, 0
; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]] ; CHECK-NEXT: bc 12, gt, [[TRUE:.LBB[0-9]+]]
; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] ; CHECK-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NEXT: [[TRUE]] ; CHECK-NEXT: [[TRUE]]
; CHECK-NEXT: addi r4, r3, 0 ; CHECK-NEXT: addi r4, r3, 0
; CHECK-NEXT: addi r6, r5, 0 ; CHECK-NEXT: addi r6, r5, 0
; CHECK-NEXT: [[SUCCESSOR]] ; CHECK-NEXT: [[SUCCESSOR]]
; CHECK-NEXT: add r4, r4, r6 ; CHECK-NEXT: add r4, r4, r6
; CHECK-NEXT: add r3, r3, r4 ; CHECK-NEXT: add r3, r3, r4
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llvm/test/CodeGen/PowerPC/extract-and-store.ll

Show First 20 Lines • Show All 639 Lines • ▼ Show 20 Lines
define void @test_5_consecutive_stores_of_bytes(<16 x i8> %a, i8* nocapture %b) local_unnamed_addr #0 { define void @test_5_consecutive_stores_of_bytes(<16 x i8> %a, i8* nocapture %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_5_consecutive_stores_of_bytes: ; CHECK-LABEL: test_5_consecutive_stores_of_bytes:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxswapd vs0, vs34 ; CHECK-NEXT: xxswapd vs0, vs34
; CHECK-NEXT: mfvsrd r3, vs34 ; CHECK-NEXT: mfvsrd r3, vs34
; CHECK-NEXT: rldicl r6, r3, 32, 56 ; CHECK-NEXT: rldicl r6, r3, 32, 56
; CHECK-NEXT: rldicl r3, r3, 56, 56 ; CHECK-NEXT: rldicl r3, r3, 56, 56
; CHECK-NEXT: mfvsrd r4, f0 ; CHECK-NEXT: mffprd r4, f0
; CHECK-NEXT: stb r6, 1(r5) ; CHECK-NEXT: stb r6, 1(r5)
; CHECK-NEXT: stb r3, 2(r5) ; CHECK-NEXT: stb r3, 2(r5)
; CHECK-NEXT: rldicl r6, r4, 32, 56 ; CHECK-NEXT: rldicl r6, r4, 32, 56
; CHECK-NEXT: rldicl r3, r4, 8, 56 ; CHECK-NEXT: rldicl r3, r4, 8, 56
; CHECK-NEXT: rldicl r4, r4, 16, 56 ; CHECK-NEXT: rldicl r4, r4, 16, 56
; CHECK-NEXT: stb r6, 0(r5) ; CHECK-NEXT: stb r6, 0(r5)
; CHECK-NEXT: stb r3, 3(r5) ; CHECK-NEXT: stb r3, 3(r5)
; CHECK-NEXT: stb r4, 4(r5) ; CHECK-NEXT: stb r4, 4(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test_5_consecutive_stores_of_bytes: ; CHECK-BE-LABEL: test_5_consecutive_stores_of_bytes:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxswapd vs0, vs34 ; CHECK-BE-NEXT: xxswapd vs0, vs34
; CHECK-BE-NEXT: mfvsrd r3, vs34 ; CHECK-BE-NEXT: mfvsrd r3, vs34
; CHECK-BE-NEXT: rldicl r6, r3, 40, 56 ; CHECK-BE-NEXT: rldicl r6, r3, 40, 56
; CHECK-BE-NEXT: mfvsrd r4, f0 ; CHECK-BE-NEXT: mffprd r4, f0
; CHECK-BE-NEXT: stb r6, 0(r5) ; CHECK-BE-NEXT: stb r6, 0(r5)
; CHECK-BE-NEXT: rldicl r6, r4, 40, 56 ; CHECK-BE-NEXT: rldicl r6, r4, 40, 56
; CHECK-BE-NEXT: rldicl r4, r4, 16, 56 ; CHECK-BE-NEXT: rldicl r4, r4, 16, 56
; CHECK-BE-NEXT: stb r6, 1(r5) ; CHECK-BE-NEXT: stb r6, 1(r5)
; CHECK-BE-NEXT: clrldi r6, r3, 56 ; CHECK-BE-NEXT: clrldi r6, r3, 56
; CHECK-BE-NEXT: rldicl r3, r3, 56, 56 ; CHECK-BE-NEXT: rldicl r3, r3, 56, 56
; CHECK-BE-NEXT: stb r4, 2(r5) ; CHECK-BE-NEXT: stb r4, 2(r5)
; CHECK-BE-NEXT: stb r6, 3(r5) ; CHECK-BE-NEXT: stb r6, 3(r5)
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; CHECK-LABEL: test_13_consecutive_stores_of_bytes: ; CHECK-LABEL: test_13_consecutive_stores_of_bytes:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xxswapd vs0, vs34 ; CHECK-NEXT: xxswapd vs0, vs34
; CHECK-NEXT: mfvsrd r3, vs34 ; CHECK-NEXT: mfvsrd r3, vs34
; CHECK-NEXT: rldicl r4, r3, 32, 56 ; CHECK-NEXT: rldicl r4, r3, 32, 56
; CHECK-NEXT: rldicl r6, r3, 56, 56 ; CHECK-NEXT: rldicl r6, r3, 56, 56
; CHECK-NEXT: stb r4, 1(r5) ; CHECK-NEXT: stb r4, 1(r5)
; CHECK-NEXT: rldicl r4, r3, 40, 56 ; CHECK-NEXT: rldicl r4, r3, 40, 56
; CHECK-NEXT: mfvsrd r7, f0 ; CHECK-NEXT: mffprd r7, f0
; CHECK-NEXT: stb r6, 2(r5) ; CHECK-NEXT: stb r6, 2(r5)
; CHECK-NEXT: rldicl r6, r3, 24, 56 ; CHECK-NEXT: rldicl r6, r3, 24, 56
; CHECK-NEXT: stb r4, 6(r5) ; CHECK-NEXT: stb r4, 6(r5)
; CHECK-NEXT: rldicl r4, r3, 8, 56 ; CHECK-NEXT: rldicl r4, r3, 8, 56
; CHECK-NEXT: stb r6, 7(r5) ; CHECK-NEXT: stb r6, 7(r5)
; CHECK-NEXT: rldicl r3, r3, 16, 56 ; CHECK-NEXT: rldicl r3, r3, 16, 56
; CHECK-NEXT: stb r4, 9(r5) ; CHECK-NEXT: stb r4, 9(r5)
; CHECK-NEXT: rldicl r4, r7, 32, 56 ; CHECK-NEXT: rldicl r4, r7, 32, 56
Show All 16 Lines
; CHECK-BE-LABEL: test_13_consecutive_stores_of_bytes: ; CHECK-BE-LABEL: test_13_consecutive_stores_of_bytes:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mfvsrd r3, vs34 ; CHECK-BE-NEXT: mfvsrd r3, vs34
; CHECK-BE-NEXT: xxswapd vs0, vs34 ; CHECK-BE-NEXT: xxswapd vs0, vs34
; CHECK-BE-NEXT: rldicl r4, r3, 40, 56 ; CHECK-BE-NEXT: rldicl r4, r3, 40, 56
; CHECK-BE-NEXT: clrldi r6, r3, 56 ; CHECK-BE-NEXT: clrldi r6, r3, 56
; CHECK-BE-NEXT: stb r4, 0(r5) ; CHECK-BE-NEXT: stb r4, 0(r5)
; CHECK-BE-NEXT: rldicl r4, r3, 56, 56 ; CHECK-BE-NEXT: rldicl r4, r3, 56, 56
; CHECK-BE-NEXT: mfvsrd r7, f0 ; CHECK-BE-NEXT: mffprd r7, f0
; CHECK-BE-NEXT: stb r6, 3(r5) ; CHECK-BE-NEXT: stb r6, 3(r5)
; CHECK-BE-NEXT: rldicl r6, r3, 8, 56 ; CHECK-BE-NEXT: rldicl r6, r3, 8, 56
; CHECK-BE-NEXT: stb r4, 4(r5) ; CHECK-BE-NEXT: stb r4, 4(r5)
; CHECK-BE-NEXT: rldicl r4, r3, 24, 56 ; CHECK-BE-NEXT: rldicl r4, r3, 24, 56
; CHECK-BE-NEXT: stb r6, 5(r5) ; CHECK-BE-NEXT: stb r6, 5(r5)
; CHECK-BE-NEXT: rldicl r6, r3, 16, 56 ; CHECK-BE-NEXT: rldicl r6, r3, 16, 56
; CHECK-BE-NEXT: stb r4, 8(r5) ; CHECK-BE-NEXT: stb r4, 8(r5)
; CHECK-BE-NEXT: rldicl r4, r7, 40, 56 ; CHECK-BE-NEXT: rldicl r4, r7, 40, 56
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llvm/test/CodeGen/PowerPC/f128-aggregates.ll

Show First 20 Lines • Show All 337 Lines • ▼ Show 20 Lines
; CHECK-LABEL: sum_float128: ; CHECK-LABEL: sum_float128:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-DAG: std r10, 88(r1) ; CHECK-DAG: std r10, 88(r1)
; CHECK-DAG: std r9, 80(r1) ; CHECK-DAG: std r9, 80(r1)
; CHECK-DAG: std r8, 72(r1) ; CHECK-DAG: std r8, 72(r1)
; CHECK-DAG: std r7, 64(r1) ; CHECK-DAG: std r7, 64(r1)
; CHECK-DAG: std r6, 56(r1) ; CHECK-DAG: std r6, 56(r1)
; CHECK-DAG: std r4, 40(r1) ; CHECK-DAG: std r4, 40(r1)
; CHECK-DAG: cmpwi cr0, r3, 1 ; CHECK-DAG: cmpwi r3, 1
; CHECK-DAG: std r5, 48(r1) ; CHECK-DAG: std r5, 48(r1)
; CHECK-DAG: addis [[REG:r[0-9]+]], r2, .LCPI17_0@toc@ha ; CHECK-DAG: addis [[REG:r[0-9]+]], r2, .LCPI17_0@toc@ha
; CHECK-DAG: addi [[REG1:r[0-9]+]], [[REG]], .LCPI17_0@toc@l ; CHECK-DAG: addi [[REG1:r[0-9]+]], [[REG]], .LCPI17_0@toc@l
; CHECK-DAG: lxvx v2, 0, [[REG1]] ; CHECK-DAG: lxvx v2, 0, [[REG1]]
; CHECK-NEXT: bltlr cr0 ; CHECK-NEXT: bltlr cr0
; CHECK-NEXT: # %bb.1: # %if.end ; CHECK-NEXT: # %bb.1: # %if.end
; CHECK-NEXT: addi r3, r1, 40 ; CHECK-NEXT: addi r3, r1, 40
; CHECK-NEXT: lxvx v3, 0, r3 ; CHECK-NEXT: lxvx v3, 0, r3
Show All 38 Lines

llvm/test/CodeGen/PowerPC/fp-int-conversions-direct-moves.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \ ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s ; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-unknown < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \ ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -ppc-asm-full-reg-names \
; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s ; RUN: -ppc-vsr-nums-as-vr -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
; Function Attrs: nounwind ; Function Attrs: nounwind
define zeroext i8 @_Z6testcff(float %arg) { define zeroext i8 @_Z6testcff(float %arg) {
; CHECK-LABEL: _Z6testcff: ; CHECK-LABEL: _Z6testcff:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1 ; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1) ; CHECK-NEXT: stfs f1, -4(r1)
; CHECK-NEXT: mfvsrwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%arg.addr = alloca float, align 4 %arg.addr = alloca float, align 4
store float %arg, float* %arg.addr, align 4 store float %arg, float* %arg.addr, align 4
%0 = load float, float* %arg.addr, align 4 %0 = load float, float* %arg.addr, align 4
%conv = fptoui float %0 to i8 %conv = fptoui float %0 to i8
ret i8 %conv ret i8 %conv
Show All 16 Lines
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define zeroext i8 @_Z6testcdd(double %arg) { define zeroext i8 @_Z6testcdd(double %arg) {
; CHECK-LABEL: _Z6testcdd: ; CHECK-LABEL: _Z6testcdd:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1 ; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1) ; CHECK-NEXT: stfd f1, -8(r1)
; CHECK-NEXT: mfvsrwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%arg.addr = alloca double, align 8 %arg.addr = alloca double, align 8
store double %arg, double* %arg.addr, align 8 store double %arg, double* %arg.addr, align 8
%0 = load double, double* %arg.addr, align 8 %0 = load double, double* %arg.addr, align 8
%conv = fptoui double %0 to i8 %conv = fptoui double %0 to i8
ret i8 %conv ret i8 %conv
Show All 16 Lines
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define zeroext i8 @_Z7testucff(float %arg) { define zeroext i8 @_Z7testucff(float %arg) {
; CHECK-LABEL: _Z7testucff: ; CHECK-LABEL: _Z7testucff:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1 ; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1) ; CHECK-NEXT: stfs f1, -4(r1)
; CHECK-NEXT: mfvsrwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%arg.addr = alloca float, align 4 %arg.addr = alloca float, align 4
store float %arg, float* %arg.addr, align 4 store float %arg, float* %arg.addr, align 4
%0 = load float, float* %arg.addr, align 4 %0 = load float, float* %arg.addr, align 4
%conv = fptoui float %0 to i8 %conv = fptoui float %0 to i8
ret i8 %conv ret i8 %conv
Show All 16 Lines
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define zeroext i8 @_Z7testucdd(double %arg) { define zeroext i8 @_Z7testucdd(double %arg) {
; CHECK-LABEL: _Z7testucdd: ; CHECK-LABEL: _Z7testucdd:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1 ; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1) ; CHECK-NEXT: stfd f1, -8(r1)
; CHECK-NEXT: mfvsrwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%arg.addr = alloca double, align 8 %arg.addr = alloca double, align 8
store double %arg, double* %arg.addr, align 8 store double %arg, double* %arg.addr, align 8
%0 = load double, double* %arg.addr, align 8 %0 = load double, double* %arg.addr, align 8
%conv = fptoui double %0 to i8 %conv = fptoui double %0 to i8
ret i8 %conv ret i8 %conv
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} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define zeroext i16 @_Z7testusff(float %arg) { define zeroext i16 @_Z7testusff(float %arg) {
; CHECK-LABEL: _Z7testusff: ; CHECK-LABEL: _Z7testusff:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1 ; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1) ; CHECK-NEXT: stfs f1, -4(r1)
; CHECK-NEXT: mfvsrwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%arg.addr = alloca float, align 4 %arg.addr = alloca float, align 4
store float %arg, float* %arg.addr, align 4 store float %arg, float* %arg.addr, align 4
%0 = load float, float* %arg.addr, align 4 %0 = load float, float* %arg.addr, align 4
%conv = fptoui float %0 to i16 %conv = fptoui float %0 to i16
ret i16 %conv ret i16 %conv
Show All 16 Lines
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define zeroext i16 @_Z7testusdd(double %arg) { define zeroext i16 @_Z7testusdd(double %arg) {
; CHECK-LABEL: _Z7testusdd: ; CHECK-LABEL: _Z7testusdd:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpsxws f0, f1 ; CHECK-NEXT: xscvdpsxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1) ; CHECK-NEXT: stfd f1, -8(r1)
; CHECK-NEXT: mfvsrwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%arg.addr = alloca double, align 8 %arg.addr = alloca double, align 8
store double %arg, double* %arg.addr, align 8 store double %arg, double* %arg.addr, align 8
%0 = load double, double* %arg.addr, align 8 %0 = load double, double* %arg.addr, align 8
%conv = fptoui double %0 to i16 %conv = fptoui double %0 to i16
ret i16 %conv ret i16 %conv
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} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define zeroext i32 @_Z7testuiff(float %arg) { define zeroext i32 @_Z7testuiff(float %arg) {
; CHECK-LABEL: _Z7testuiff: ; CHECK-LABEL: _Z7testuiff:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpuxws f0, f1 ; CHECK-NEXT: xscvdpuxws f0, f1
; CHECK-NEXT: stfs f1, -4(r1) ; CHECK-NEXT: stfs f1, -4(r1)
; CHECK-NEXT: mfvsrwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%arg.addr = alloca float, align 4 %arg.addr = alloca float, align 4
store float %arg, float* %arg.addr, align 4 store float %arg, float* %arg.addr, align 4
%0 = load float, float* %arg.addr, align 4 %0 = load float, float* %arg.addr, align 4
%conv = fptoui float %0 to i32 %conv = fptoui float %0 to i32
ret i32 %conv ret i32 %conv
Show All 16 Lines
} }
; Function Attrs: nounwind ; Function Attrs: nounwind
define zeroext i32 @_Z7testuidd(double %arg) { define zeroext i32 @_Z7testuidd(double %arg) {
; CHECK-LABEL: _Z7testuidd: ; CHECK-LABEL: _Z7testuidd:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xscvdpuxws f0, f1 ; CHECK-NEXT: xscvdpuxws f0, f1
; CHECK-NEXT: stfd f1, -8(r1) ; CHECK-NEXT: stfd f1, -8(r1)
; CHECK-NEXT: mfvsrwz r3, f0 ; CHECK-NEXT: mffprwz r3, f0
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%arg.addr = alloca double, align 8 %arg.addr = alloca double, align 8
store double %arg, double* %arg.addr, align 8 store double %arg, double* %arg.addr, align 8
%0 = load double, double* %arg.addr, align 8 %0 = load double, double* %arg.addr, align 8
%conv = fptoui double %0 to i32 %conv = fptoui double %0 to i32
ret i32 %conv ret i32 %conv
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llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll

Show All 12 Lines
declare i64 @llvm.fshr.i64(i64, i64, i64) declare i64 @llvm.fshr.i64(i64, i64, i64)
declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
; When first 2 operands match, it's a rotate. ; When first 2 operands match, it's a rotate.
define i8 @rotl_i8_const_shift(i8 %x) { define i8 @rotl_i8_const_shift(i8 %x) {
; CHECK-LABEL: rotl_i8_const_shift: ; CHECK-LABEL: rotl_i8_const_shift:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 3, 27, 0, 31 ; CHECK-NEXT: rotlwi 4, 3, 27
; CHECK-NEXT: rlwimi 4, 3, 3, 0, 28 ; CHECK-NEXT: rlwimi 4, 3, 3, 0, 28
; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3) %f = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)
ret i8 %f ret i8 %f
} }
define i64 @rotl_i64_const_shift(i64 %x) { define i64 @rotl_i64_const_shift(i64 %x) {
; CHECK-LABEL: rotl_i64_const_shift: ; CHECK-LABEL: rotl_i64_const_shift:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rotldi 3, 3, 3 ; CHECK-NEXT: rotldi 3, 3, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 3) %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 3)
ret i64 %f ret i64 %f
} }
; When first 2 operands match, it's a rotate (by variable amount). ; When first 2 operands match, it's a rotate (by variable amount).
define i16 @rotl_i16(i16 %x, i16 %z) { define i16 @rotl_i16(i16 %x, i16 %z) {
; CHECK-LABEL: rotl_i16: ; CHECK-LABEL: rotl_i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: neg 5, 4 ; CHECK-NEXT: neg 5, 4
; CHECK-NEXT: clrlwi 6, 3, 16 ; CHECK-NEXT: clrlwi 6, 3, 16
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31 ; CHECK-NEXT: clrlwi 4, 4, 28
; CHECK-NEXT: clrlwi 5, 5, 28 ; CHECK-NEXT: clrlwi 5, 5, 28
; CHECK-NEXT: slw 3, 3, 4 ; CHECK-NEXT: slw 3, 3, 4
; CHECK-NEXT: srw 4, 6, 5 ; CHECK-NEXT: srw 4, 6, 5
; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 %z) %f = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 %z)
ret i16 %f ret i16 %f
} }
define i32 @rotl_i32(i32 %x, i32 %z) { define i32 @rotl_i32(i32 %x, i32 %z) {
; CHECK-LABEL: rotl_i32: ; CHECK-LABEL: rotl_i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwnm 3, 3, 4, 0, 31 ; CHECK-NEXT: rotlw 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z) %f = call i32 @llvm.fshl.i32(i32 %x, i32 %x, i32 %z)
ret i32 %f ret i32 %f
} }
define i64 @rotl_i64(i64 %x, i64 %z) { define i64 @rotl_i64(i64 %x, i64 %z) {
; CHECK-LABEL: rotl_i64: ; CHECK-LABEL: rotl_i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rldcl 3, 3, 4, 0 ; CHECK-NEXT: rotld 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z) %f = call i64 @llvm.fshl.i64(i64 %x, i64 %x, i64 %z)
ret i64 %f ret i64 %f
} }
; Vector rotate. ; Vector rotate.
define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) { define <4 x i32> @rotl_v4i32(<4 x i32> %x, <4 x i32> %z) {
Show All 17 Lines; CHECK-NEXT: blr
ret <4 x i32> %f ret <4 x i32> %f
} }
; Repeat everything for funnel shift right. ; Repeat everything for funnel shift right.
define i8 @rotr_i8_const_shift(i8 %x) { define i8 @rotr_i8_const_shift(i8 %x) {
; CHECK-LABEL: rotr_i8_const_shift: ; CHECK-LABEL: rotr_i8_const_shift:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 3, 29, 0, 31 ; CHECK-NEXT: rotlwi 4, 3, 29
; CHECK-NEXT: rlwimi 4, 3, 5, 0, 26 ; CHECK-NEXT: rlwimi 4, 3, 5, 0, 26
; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3) %f = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)
ret i8 %f ret i8 %f
} }
define i32 @rotr_i32_const_shift(i32 %x) { define i32 @rotr_i32_const_shift(i32 %x) {
; CHECK-LABEL: rotr_i32_const_shift: ; CHECK-LABEL: rotr_i32_const_shift:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 29, 0, 31 ; CHECK-NEXT: rotlwi 3, 3, 29
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 3) %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 3)
ret i32 %f ret i32 %f
} }
; When first 2 operands match, it's a rotate (by variable amount). ; When first 2 operands match, it's a rotate (by variable amount).
define i16 @rotr_i16(i16 %x, i16 %z) { define i16 @rotr_i16(i16 %x, i16 %z) {
; CHECK-LABEL: rotr_i16: ; CHECK-LABEL: rotr_i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: neg 5, 4 ; CHECK-NEXT: neg 5, 4
; CHECK-NEXT: clrlwi 6, 3, 16 ; CHECK-NEXT: clrlwi 6, 3, 16
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31 ; CHECK-NEXT: clrlwi 4, 4, 28
; CHECK-NEXT: clrlwi 5, 5, 28 ; CHECK-NEXT: clrlwi 5, 5, 28
; CHECK-NEXT: srw 4, 6, 4 ; CHECK-NEXT: srw 4, 6, 4
; CHECK-NEXT: slw 3, 3, 5 ; CHECK-NEXT: slw 3, 3, 5
; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %z) %f = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %z)
ret i16 %f ret i16 %f
} }
define i32 @rotr_i32(i32 %x, i32 %z) { define i32 @rotr_i32(i32 %x, i32 %z) {
; CHECK-LABEL: rotr_i32: ; CHECK-LABEL: rotr_i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: neg 4, 4 ; CHECK-NEXT: neg 4, 4
; CHECK-NEXT: rlwnm 3, 3, 4, 0, 31 ; CHECK-NEXT: rotlw 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z) %f = call i32 @llvm.fshr.i32(i32 %x, i32 %x, i32 %z)
ret i32 %f ret i32 %f
} }
define i64 @rotr_i64(i64 %x, i64 %z) { define i64 @rotr_i64(i64 %x, i64 %z) {
; CHECK-LABEL: rotr_i64: ; CHECK-LABEL: rotr_i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: neg 4, 4 ; CHECK-NEXT: neg 4, 4
; CHECK-NEXT: rldcl 3, 3, 4, 0 ; CHECK-NEXT: rotld 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %z) %f = call i64 @llvm.fshr.i64(i64 %x, i64 %x, i64 %z)
ret i64 %f ret i64 %f
} }
; Vector rotate. ; Vector rotate.
define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) { define <4 x i32> @rotr_v4i32(<4 x i32> %x, <4 x i32> %z) {
▲ Show 20 Lines • Show All 56 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/funnel-shift.ll

Show All 38 Lines
; CHECK-NEXT: ori 6, 6, 51366 ; CHECK-NEXT: ori 6, 6, 51366
; CHECK-NEXT: clrldi 4, 4, 27 ; CHECK-NEXT: clrldi 4, 4, 27
; CHECK-NEXT: sldi 6, 6, 32 ; CHECK-NEXT: sldi 6, 6, 32
; CHECK-NEXT: oris 6, 6, 3542 ; CHECK-NEXT: oris 6, 6, 3542
; CHECK-NEXT: ori 6, 6, 31883 ; CHECK-NEXT: ori 6, 6, 31883
; CHECK-NEXT: mulhdu 6, 5, 6 ; CHECK-NEXT: mulhdu 6, 5, 6
; CHECK-NEXT: rldicl 6, 6, 59, 5 ; CHECK-NEXT: rldicl 6, 6, 59, 5
; CHECK-NEXT: mulli 6, 6, 37 ; CHECK-NEXT: mulli 6, 6, 37
; CHECK-NEXT: subf. 5, 6, 5 ; CHECK-NEXT: sub. 5, 5, 6
; CHECK-NEXT: subfic 6, 5, 37 ; CHECK-NEXT: subfic 6, 5, 37
; CHECK-NEXT: sld 5, 3, 5 ; CHECK-NEXT: sld 5, 3, 5
; CHECK-NEXT: srd 4, 4, 6 ; CHECK-NEXT: srd 4, 4, 6
; CHECK-NEXT: or 4, 5, 4 ; CHECK-NEXT: or 4, 5, 4
; CHECK-NEXT: isel 3, 3, 4, 2 ; CHECK-NEXT: isel 3, 3, 4, 2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z) %f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)
ret i37 %f ret i37 %f
Show All 11 Lines; CHECK-NEXT: blr
ret i7 %f ret i7 %f
} }
; With constant shift amount, this is rotate + insert (missing extended mnemonics). ; With constant shift amount, this is rotate + insert (missing extended mnemonics).
define i32 @fshl_i32_const_shift(i32 %x, i32 %y) { define i32 @fshl_i32_const_shift(i32 %x, i32 %y) {
; CHECK-LABEL: fshl_i32_const_shift: ; CHECK-LABEL: fshl_i32_const_shift:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 9, 0, 31 ; CHECK-NEXT: rotlwi 4, 4, 9
; CHECK-NEXT: rlwimi 4, 3, 9, 0, 22 ; CHECK-NEXT: rlwimi 4, 3, 9, 0, 22
; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 9) %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 9)
ret i32 %f ret i32 %f
} }
; Check modulo math on shift amount. ; Check modulo math on shift amount.
define i32 @fshl_i32_const_overshift(i32 %x, i32 %y) { define i32 @fshl_i32_const_overshift(i32 %x, i32 %y) {
; CHECK-LABEL: fshl_i32_const_overshift: ; CHECK-LABEL: fshl_i32_const_overshift:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 9, 0, 31 ; CHECK-NEXT: rotlwi 4, 4, 9
; CHECK-NEXT: rlwimi 4, 3, 9, 0, 22 ; CHECK-NEXT: rlwimi 4, 3, 9, 0, 22
; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 41) %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 41)
ret i32 %f ret i32 %f
} }
; 64-bit should also work. ; 64-bit should also work.
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; CHECK-NEXT: clrldi 5, 5, 27 ; CHECK-NEXT: clrldi 5, 5, 27
; CHECK-NEXT: ori 6, 6, 51366 ; CHECK-NEXT: ori 6, 6, 51366
; CHECK-NEXT: sldi 6, 6, 32 ; CHECK-NEXT: sldi 6, 6, 32
; CHECK-NEXT: oris 6, 6, 3542 ; CHECK-NEXT: oris 6, 6, 3542
; CHECK-NEXT: ori 6, 6, 31883 ; CHECK-NEXT: ori 6, 6, 31883
; CHECK-NEXT: mulhdu 6, 5, 6 ; CHECK-NEXT: mulhdu 6, 5, 6
; CHECK-NEXT: rldicl 6, 6, 59, 5 ; CHECK-NEXT: rldicl 6, 6, 59, 5
; CHECK-NEXT: mulli 6, 6, 37 ; CHECK-NEXT: mulli 6, 6, 37
; CHECK-NEXT: subf. 5, 6, 5 ; CHECK-NEXT: sub. 5, 5, 6
; CHECK-NEXT: clrldi 6, 4, 27 ; CHECK-NEXT: clrldi 6, 4, 27
; CHECK-NEXT: subfic 7, 5, 37 ; CHECK-NEXT: subfic 7, 5, 37
; CHECK-NEXT: srd 5, 6, 5 ; CHECK-NEXT: srd 5, 6, 5
; CHECK-NEXT: sld 3, 3, 7 ; CHECK-NEXT: sld 3, 3, 7
; CHECK-NEXT: or 3, 3, 5 ; CHECK-NEXT: or 3, 3, 5
; CHECK-NEXT: isel 3, 4, 3, 2 ; CHECK-NEXT: isel 3, 4, 3, 2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z) %f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z)
Show All 12 Lines; CHECK-NEXT: blr
ret i7 %f ret i7 %f
} }
; With constant shift amount, this is rotate + insert (missing extended mnemonics). ; With constant shift amount, this is rotate + insert (missing extended mnemonics).
define i32 @fshr_i32_const_shift(i32 %x, i32 %y) { define i32 @fshr_i32_const_shift(i32 %x, i32 %y) {
; CHECK-LABEL: fshr_i32_const_shift: ; CHECK-LABEL: fshr_i32_const_shift:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 23, 0, 31 ; CHECK-NEXT: rotlwi 4, 4, 23
; CHECK-NEXT: rlwimi 4, 3, 23, 0, 8 ; CHECK-NEXT: rlwimi 4, 3, 23, 0, 8
; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 9) %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 9)
ret i32 %f ret i32 %f
} }
; Check modulo math on shift amount. 41-32=9. ; Check modulo math on shift amount. 41-32=9.
define i32 @fshr_i32_const_overshift(i32 %x, i32 %y) { define i32 @fshr_i32_const_overshift(i32 %x, i32 %y) {
; CHECK-LABEL: fshr_i32_const_overshift: ; CHECK-LABEL: fshr_i32_const_overshift:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 23, 0, 31 ; CHECK-NEXT: rotlwi 4, 4, 23
; CHECK-NEXT: rlwimi 4, 3, 23, 0, 8 ; CHECK-NEXT: rlwimi 4, 3, 23, 0, 8
; CHECK-NEXT: mr 3, 4 ; CHECK-NEXT: mr 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 41) %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 41)
ret i32 %f ret i32 %f
} }
; 64-bit should also work. 105-64 = 41. ; 64-bit should also work. 105-64 = 41.
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llvm/test/CodeGen/PowerPC/inlineasm-i64-reg.ll

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; CHECK-DAG: mr [[REG:[0-9]+]], 3 ; CHECK-DAG: mr [[REG:[0-9]+]], 3
; CHECK-DAG: li 0, 1076 ; CHECK-DAG: li 0, 1076
; CHECK: stw [[REG]], ; CHECK: stw [[REG]],
; CHECK: #APP ; CHECK: #APP
; CHECK: sc ; CHECK: sc
; CHECK: #NO_APP ; CHECK: #NO_APP
; CHECK: cmpwi {{[0-9]+}}, [[REG]], 1 ; CHECK: cmpwi [[REG]], 1
; CHECK: blr ; CHECK: blr
if.then: ; preds = %entry if.then: ; preds = %entry
call void @mtrace() call void @mtrace()
%.pre = load i32, i32* %argc.addr, align 4 %.pre = load i32, i32* %argc.addr, align 4
br label %if.end br label %if.end
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llvm/test/CodeGen/PowerPC/knowCRBitSpill.ll

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@b = common dso_local global %struct.anon* null, align 8 @b = common dso_local global %struct.anon* null, align 8
@a = common dso_local global i64 0, align 8 @a = common dso_local global i64 0, align 8
; Function Attrs: nounwind ; Function Attrs: nounwind
define dso_local signext i32 @spillCRSET(i32 signext %p1, i32 signext %p2) { define dso_local signext i32 @spillCRSET(i32 signext %p1, i32 signext %p2) {
; CHECK-LABEL: spillCRSET: ; CHECK-LABEL: spillCRSET:
; CHECK: # %bb.2: ; CHECK: # %bb.2:
; CHECK-DAG: crnor [[CREG:.*]]*cr5+lt, eq, eq ; CHECK-DAG: crnot [[CREG:.*]]*cr5+lt, eq
; CHECK-DAG: mfocrf [[REG2:.*]], [[CREG]] ; CHECK-DAG: mfocrf [[REG2:.*]], [[CREG]]
; CHECK-DAG: rlwinm [[REG2]], [[REG2]] ; CHECK-DAG: rlwinm [[REG2]], [[REG2]]
; CHECK: .LBB0_3: ; CHECK: .LBB0_3:
; CHECK-NOT: #UNENCODED_NOP ; CHECK-NOT: #UNENCODED_NOP
; CHECK: lis [[REG1:.*]], -32768 ; CHECK: lis [[REG1:.*]], -32768
; CHECK: .LBB0_4: ; CHECK: .LBB0_4:
; CHECK-NOT: mfocrf [[REG2:.*]], [[CREG]] ; CHECK-NOT: mfocrf [[REG2:.*]], [[CREG]]
; CHECK-NOT: rlwinm [[REG2]], [[REG2]] ; CHECK-NOT: rlwinm [[REG2]], [[REG2]]
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llvm/test/CodeGen/PowerPC/load-and-splat.ll

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; P9: # %bb.0: # %entry ; P9: # %bb.0: # %entry
; P9-NEXT: addi r3, r3, 4 ; P9-NEXT: addi r3, r3, 4
; P9-NEXT: lxvwsx v2, 0, r3 ; P9-NEXT: lxvwsx v2, 0, r3
; P9-NEXT: blr ; P9-NEXT: blr
; ;
; P8-LABEL: adjusted_lxvwsx: ; P8-LABEL: adjusted_lxvwsx:
; P8: # %bb.0: # %entry ; P8: # %bb.0: # %entry
; P8-NEXT: ld r3, 0(r3) ; P8-NEXT: ld r3, 0(r3)
; P8-NEXT: mtvsrd f0, r3 ; P8-NEXT: mtfprd f0, r3
; P8-NEXT: xxswapd v2, vs0 ; P8-NEXT: xxswapd v2, vs0
; P8-NEXT: xxspltw v2, v2, 2 ; P8-NEXT: xxspltw v2, v2, 2
; P8-NEXT: blr ; P8-NEXT: blr
entry: entry:
%0 = bitcast i64* %s to <8 x i8>* %0 = bitcast i64* %s to <8 x i8>*
%1 = load <8 x i8>, <8 x i8>* %0, align 8 %1 = load <8 x i8>, <8 x i8>* %0, align 8
%2 = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7> %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7, i32 4, i32 5, i32 6, i32 7>
ret <16 x i8> %2 ret <16 x i8> %2
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llvm/test/CodeGen/PowerPC/loop-comment.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s -check-prefix=PPC64LE ; RUN: llc -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s -check-prefix=PPC64LE
define void @test(i8* %ptr, i8 %cmp, i8 %val) { define void @test(i8* %ptr, i8 %cmp, i8 %val) {
; PPC64LE-LABEL: test: ; PPC64LE-LABEL: test:
; PPC64LE: # %bb.0: ; PPC64LE: # %bb.0:
; PPC64LE-NEXT: rlwinm 4, 4, 0, 24, 31 ; PPC64LE-NEXT: clrlwi 4, 4, 24
; PPC64LE-NEXT: .LBB0_1: ; PPC64LE-NEXT: .LBB0_1:
; PPC64LE-NEXT: lbarx 6, 0, 3 ; PPC64LE-NEXT: lbarx 6, 0, 3
; PPC64LE-NEXT: cmpw 4, 6 ; PPC64LE-NEXT: cmpw 4, 6
; PPC64LE-NEXT: bne 0, .LBB0_3 ; PPC64LE-NEXT: bne 0, .LBB0_3
; PPC64LE-NEXT: # %bb.2: ; PPC64LE-NEXT: # %bb.2:
; PPC64LE-NEXT: stbcx. 5, 0, 3 ; PPC64LE-NEXT: stbcx. 5, 0, 3
; PPC64LE-NEXT: beqlr 0 ; PPC64LE-NEXT: beqlr 0
; PPC64LE-NEXT: b .LBB0_1 ; PPC64LE-NEXT: b .LBB0_1
; PPC64LE-NEXT: .LBB0_3: ; PPC64LE-NEXT: .LBB0_3:
; PPC64LE-NEXT: stbcx. 6, 0, 3 ; PPC64LE-NEXT: stbcx. 6, 0, 3
; PPC64LE-NEXT: blr ; PPC64LE-NEXT: blr
%res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic
ret void ret void
} }

llvm/test/CodeGen/PowerPC/memcmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-gnu-linux < %s | FileCheck %s -check-prefix=CHECK ; RUN: llc -verify-machineinstrs -mcpu=pwr8 -mtriple=powerpc64le-unknown-gnu-linux < %s | FileCheck %s -check-prefix=CHECK
define signext i32 @memcmp8(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) { define signext i32 @memcmp8(i32* nocapture readonly %buffer1, i32* nocapture readonly %buffer2) {
; CHECK-LABEL: memcmp8: ; CHECK-LABEL: memcmp8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: ldbrx 3, 0, 3 ; CHECK-NEXT: ldbrx 3, 0, 3
; CHECK-NEXT: ldbrx 4, 0, 4 ; CHECK-NEXT: ldbrx 4, 0, 4
; CHECK-NEXT: subfc 5, 3, 4 ; CHECK-NEXT: subc 5, 4, 3
; CHECK-NEXT: subfe 5, 4, 4 ; CHECK-NEXT: subfe 5, 4, 4
; CHECK-NEXT: subfc 4, 4, 3 ; CHECK-NEXT: subc 4, 3, 4
; CHECK-NEXT: subfe 3, 3, 3 ; CHECK-NEXT: subfe 3, 3, 3
; CHECK-NEXT: neg 4, 5 ; CHECK-NEXT: neg 4, 5
; CHECK-NEXT: neg 3, 3 ; CHECK-NEXT: neg 3, 3
; CHECK-NEXT: subf 3, 3, 4 ; CHECK-NEXT: subf 3, 3, 4
; CHECK-NEXT: extsw 3, 3 ; CHECK-NEXT: extsw 3, 3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%t0 = bitcast i32* %buffer1 to i8* %t0 = bitcast i32* %buffer1 to i8*
%t1 = bitcast i32* %buffer2 to i8* %t1 = bitcast i32* %buffer2 to i8*
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llvm/test/CodeGen/PowerPC/optcmp.ll

Show First 20 Lines • Show All 64 Lines • ▼ Show 20 Linesentry:
%cmp = icmp sgt i32 %shl, 0 %cmp = icmp sgt i32 %shl, 0
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define i64 @fool(i64 %a, i64 %b, i64* nocapture %c) #0 { define i64 @fool(i64 %a, i64 %b, i64* nocapture %c) #0 {
; CHECK-LABEL: fool: ; CHECK-LABEL: fool:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subf. 6, 4, 3 ; CHECK-NEXT: sub. 6, 3, 4
; CHECK-NEXT: isel 3, 3, 4, 1 ; CHECK-NEXT: isel 3, 3, 4, 1
; CHECK-NEXT: std 6, 0(5) ; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-NO-ISEL-LABEL: fool: ; CHECK-NO-ISEL-LABEL: fool:
; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL: # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT: subf. 6, 4, 3 ; CHECK-NO-ISEL-NEXT: sub. 6, 3, 4
; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB2_2 ; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB2_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
; CHECK-NO-ISEL-NEXT: ori 3, 4, 0 ; CHECK-NO-ISEL-NEXT: ori 3, 4, 0
; CHECK-NO-ISEL-NEXT: b .LBB2_2 ; CHECK-NO-ISEL-NEXT: b .LBB2_2
; CHECK-NO-ISEL-NEXT: .LBB2_2: # %entry ; CHECK-NO-ISEL-NEXT: .LBB2_2: # %entry
; CHECK-NO-ISEL-NEXT: std 6, 0(5) ; CHECK-NO-ISEL-NEXT: std 6, 0(5)
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
entry: entry:
%sub = sub nsw i64 %a, %b %sub = sub nsw i64 %a, %b
store i64 %sub, i64* %c, align 8 store i64 %sub, i64* %c, align 8
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%cond = select i1 %cmp, i64 %a, i64 %b %cond = select i1 %cmp, i64 %a, i64 %b
ret i64 %cond ret i64 %cond
} }
define i64 @foolb(i64 %a, i64 %b, i64* nocapture %c) #0 { define i64 @foolb(i64 %a, i64 %b, i64* nocapture %c) #0 {
; CHECK-LABEL: foolb: ; CHECK-LABEL: foolb:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subf. 6, 4, 3 ; CHECK-NEXT: sub. 6, 3, 4
; CHECK-NEXT: isel 3, 4, 3, 1 ; CHECK-NEXT: isel 3, 4, 3, 1
; CHECK-NEXT: std 6, 0(5) ; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-NO-ISEL-LABEL: foolb: ; CHECK-NO-ISEL-LABEL: foolb:
; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL: # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT: subf. 6, 4, 3 ; CHECK-NO-ISEL-NEXT: sub. 6, 3, 4
; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB3_1 ; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB3_1
; CHECK-NO-ISEL-NEXT: b .LBB3_2 ; CHECK-NO-ISEL-NEXT: b .LBB3_2
; CHECK-NO-ISEL-NEXT: .LBB3_1: # %entry ; CHECK-NO-ISEL-NEXT: .LBB3_1: # %entry
; CHECK-NO-ISEL-NEXT: addi 3, 4, 0 ; CHECK-NO-ISEL-NEXT: addi 3, 4, 0
; CHECK-NO-ISEL-NEXT: .LBB3_2: # %entry ; CHECK-NO-ISEL-NEXT: .LBB3_2: # %entry
; CHECK-NO-ISEL-NEXT: std 6, 0(5) ; CHECK-NO-ISEL-NEXT: std 6, 0(5)
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
entry: entry:
%sub = sub nsw i64 %a, %b %sub = sub nsw i64 %a, %b
store i64 %sub, i64* %c, align 8 store i64 %sub, i64* %c, align 8
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%cond = select i1 %cmp, i64 %a, i64 %b %cond = select i1 %cmp, i64 %a, i64 %b
ret i64 %cond ret i64 %cond
} }
define i64 @foolc(i64 %a, i64 %b, i64* nocapture %c) #0 { define i64 @foolc(i64 %a, i64 %b, i64* nocapture %c) #0 {
; CHECK-LABEL: foolc: ; CHECK-LABEL: foolc:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subf. 6, 3, 4 ; CHECK-NEXT: sub. 6, 4, 3
; CHECK-NEXT: isel 3, 3, 4, 0 ; CHECK-NEXT: isel 3, 3, 4, 0
; CHECK-NEXT: std 6, 0(5) ; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-NO-ISEL-LABEL: foolc: ; CHECK-NO-ISEL-LABEL: foolc:
; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL: # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT: subf. 6, 3, 4 ; CHECK-NO-ISEL-NEXT: sub. 6, 4, 3
; CHECK-NO-ISEL-NEXT: bc 12, 0, .LBB4_2 ; CHECK-NO-ISEL-NEXT: bc 12, 0, .LBB4_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
; CHECK-NO-ISEL-NEXT: ori 3, 4, 0 ; CHECK-NO-ISEL-NEXT: ori 3, 4, 0
; CHECK-NO-ISEL-NEXT: b .LBB4_2 ; CHECK-NO-ISEL-NEXT: b .LBB4_2
; CHECK-NO-ISEL-NEXT: .LBB4_2: # %entry ; CHECK-NO-ISEL-NEXT: .LBB4_2: # %entry
; CHECK-NO-ISEL-NEXT: std 6, 0(5) ; CHECK-NO-ISEL-NEXT: std 6, 0(5)
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
entry: entry:
%sub = sub nsw i64 %b, %a %sub = sub nsw i64 %b, %a
store i64 %sub, i64* %c, align 8 store i64 %sub, i64* %c, align 8
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%cond = select i1 %cmp, i64 %a, i64 %b %cond = select i1 %cmp, i64 %a, i64 %b
ret i64 %cond ret i64 %cond
} }
define i64 @foold(i64 %a, i64 %b, i64* nocapture %c) #0 { define i64 @foold(i64 %a, i64 %b, i64* nocapture %c) #0 {
; CHECK-LABEL: foold: ; CHECK-LABEL: foold:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subf. 6, 3, 4 ; CHECK-NEXT: sub. 6, 4, 3
; CHECK-NEXT: isel 3, 3, 4, 1 ; CHECK-NEXT: isel 3, 3, 4, 1
; CHECK-NEXT: std 6, 0(5) ; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-NO-ISEL-LABEL: foold: ; CHECK-NO-ISEL-LABEL: foold:
; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL: # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT: subf. 6, 3, 4 ; CHECK-NO-ISEL-NEXT: sub. 6, 4, 3
; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB5_2 ; CHECK-NO-ISEL-NEXT: bc 12, 1, .LBB5_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
; CHECK-NO-ISEL-NEXT: ori 3, 4, 0 ; CHECK-NO-ISEL-NEXT: ori 3, 4, 0
; CHECK-NO-ISEL-NEXT: b .LBB5_2 ; CHECK-NO-ISEL-NEXT: b .LBB5_2
; CHECK-NO-ISEL-NEXT: .LBB5_2: # %entry ; CHECK-NO-ISEL-NEXT: .LBB5_2: # %entry
; CHECK-NO-ISEL-NEXT: std 6, 0(5) ; CHECK-NO-ISEL-NEXT: std 6, 0(5)
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
entry: entry:
%sub = sub nsw i64 %b, %a %sub = sub nsw i64 %b, %a
store i64 %sub, i64* %c, align 8 store i64 %sub, i64* %c, align 8
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
%cond = select i1 %cmp, i64 %a, i64 %b %cond = select i1 %cmp, i64 %a, i64 %b
ret i64 %cond ret i64 %cond
} }
define i64 @foold2(i64 %a, i64 %b, i64* nocapture %c) #0 { define i64 @foold2(i64 %a, i64 %b, i64* nocapture %c) #0 {
; CHECK-LABEL: foold2: ; CHECK-LABEL: foold2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subf. 6, 4, 3 ; CHECK-NEXT: sub. 6, 3, 4
; CHECK-NEXT: isel 3, 3, 4, 0 ; CHECK-NEXT: isel 3, 3, 4, 0
; CHECK-NEXT: std 6, 0(5) ; CHECK-NEXT: std 6, 0(5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-NO-ISEL-LABEL: foold2: ; CHECK-NO-ISEL-LABEL: foold2:
; CHECK-NO-ISEL: # %bb.0: # %entry ; CHECK-NO-ISEL: # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT: subf. 6, 4, 3 ; CHECK-NO-ISEL-NEXT: sub. 6, 3, 4
; CHECK-NO-ISEL-NEXT: bc 12, 0, .LBB6_2 ; CHECK-NO-ISEL-NEXT: bc 12, 0, .LBB6_2
; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry ; CHECK-NO-ISEL-NEXT: # %bb.1: # %entry
; CHECK-NO-ISEL-NEXT: ori 3, 4, 0 ; CHECK-NO-ISEL-NEXT: ori 3, 4, 0
; CHECK-NO-ISEL-NEXT: b .LBB6_2 ; CHECK-NO-ISEL-NEXT: b .LBB6_2
; CHECK-NO-ISEL-NEXT: .LBB6_2: # %entry ; CHECK-NO-ISEL-NEXT: .LBB6_2: # %entry
; CHECK-NO-ISEL-NEXT: std 6, 0(5) ; CHECK-NO-ISEL-NEXT: std 6, 0(5)
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
entry: entry:
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llvm/test/CodeGen/PowerPC/optimize-andiso.ll

Show All 9 Lines
; CHECK-NEXT: bclr 12, 4*cr5+lt, 0 ; CHECK-NEXT: bclr 12, 4*cr5+lt, 0
; CHECK-NEXT: # %bb.1: # %sw.epilog ; CHECK-NEXT: # %bb.1: # %sw.epilog
; CHECK-NEXT: addi r3, r3, 1 ; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: li r5, 2 ; CHECK-NEXT: li r5, 2
; CHECK-NEXT: andis. r4, r3, 1024 ; CHECK-NEXT: andis. r4, r3, 1024
; CHECK-NEXT: li r4, 3 ; CHECK-NEXT: li r4, 3
; CHECK-NEXT: isel r4, r5, r4, eq ; CHECK-NEXT: isel r4, r5, r4, eq
; CHECK-NEXT: srd r3, r3, r4 ; CHECK-NEXT: srd r3, r3, r4
; CHECK-NEXT: rlwinm r3, r3, 0, 9, 31 ; CHECK-NEXT: clrlwi r3, r3, 9
; CHECK-NEXT: mtvsrd f0, r3 ; CHECK-NEXT: mtfprd f0, r3
; CHECK-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-NEXT: xscvspdpn f1, vs0 ; CHECK-NEXT: xscvspdpn f1, vs0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
br i1 undef, label %return, label %sw.epilog br i1 undef, label %return, label %sw.epilog
sw.epilog: ; preds = %entry sw.epilog: ; preds = %entry
%or14 = or i64 0, %a %or14 = or i64 0, %a
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llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll

Show All 15 Lines
entry: entry:
%splat.splatinsert = insertelement <16 x i8> undef, i8 %a, i32 0 %splat.splatinsert = insertelement <16 x i8> undef, i8 %a, i32 0
%splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer
ret <16 x i8> %splat.splat ret <16 x i8> %splat.splat
; CHECK-LABEL: buildc ; CHECK-LABEL: buildc
; CHECK: sldi r3, r3, 56 ; CHECK: sldi r3, r3, 56
; CHECK: mtvsrd v2, r3 ; CHECK: mtvsrd v2, r3
; CHECK-LE-LABEL: buildc ; CHECK-LE-LABEL: buildc
; CHECK-LE: mtvsrd f0, r3 ; CHECK-LE: mtfprd f0, r3
; CHECK-LE: xxswapd v2, vs0 ; CHECK-LE: xxswapd v2, vs0
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define <8 x i16> @builds(i16 zeroext %a) { define <8 x i16> @builds(i16 zeroext %a) {
entry: entry:
%splat.splatinsert = insertelement <8 x i16> undef, i16 %a, i32 0 %splat.splatinsert = insertelement <8 x i16> undef, i16 %a, i32 0
%splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer
ret <8 x i16> %splat.splat ret <8 x i16> %splat.splat
; CHECK-LABEL: builds ; CHECK-LABEL: builds
; CHECK: sldi r3, r3, 48 ; CHECK: sldi r3, r3, 48
; CHECK: mtvsrd v2, r3 ; CHECK: mtvsrd v2, r3
; CHECK-LE-LABEL: builds ; CHECK-LE-LABEL: builds
; CHECK-LE: mtvsrd f0, r3 ; CHECK-LE: mtfprd f0, r3
; CHECK-LE: xxswapd v2, vs0 ; CHECK-LE: xxswapd v2, vs0
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define <4 x i32> @buildi(i32 zeroext %a) { define <4 x i32> @buildi(i32 zeroext %a) {
entry: entry:
%splat.splatinsert = insertelement <4 x i32> undef, i32 %a, i32 0 %splat.splatinsert = insertelement <4 x i32> undef, i32 %a, i32 0
%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer
ret <4 x i32> %splat.splat ret <4 x i32> %splat.splat
; CHECK-LABEL: buildi ; CHECK-LABEL: buildi
; CHECK: mtvsrwz f0, r3 ; CHECK: mtfprwz f0, r3
; CHECK: xxspltw v2, vs0, 1 ; CHECK: xxspltw v2, vs0, 1
; CHECK-LE-LABEL: buildi ; CHECK-LE-LABEL: buildi
; CHECK-LE: mtvsrwz f0, r3 ; CHECK-LE: mtfprwz f0, r3
; CHECK-LE: xxspltw v2, vs0, 1 ; CHECK-LE: xxspltw v2, vs0, 1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define <2 x i64> @buildl(i64 %a) { define <2 x i64> @buildl(i64 %a) {
entry: entry:
%splat.splatinsert = insertelement <2 x i64> undef, i64 %a, i32 0 %splat.splatinsert = insertelement <2 x i64> undef, i64 %a, i32 0
%splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer
ret <2 x i64> %splat.splat ret <2 x i64> %splat.splat
; CHECK-LABEL: buildl ; CHECK-LABEL: buildl
; CHECK: mtvsrd f0, r3 ; CHECK: mtfprd f0, r3
; CHECK-LE-LABEL: buildl ; CHECK-LE-LABEL: buildl
; CHECK-LE: mtvsrd f0, r3 ; CHECK-LE: mtfprd f0, r3
; CHECK-LE: xxspltd v2, vs0, 0 ; CHECK-LE: xxspltd v2, vs0, 0
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define <4 x float> @buildf(float %a) { define <4 x float> @buildf(float %a) {
entry: entry:
%splat.splatinsert = insertelement <4 x float> undef, float %a, i32 0 %splat.splatinsert = insertelement <4 x float> undef, float %a, i32 0
%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer
Show All 28 Lines
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 0 %vecext = extractelement <16 x i8> %vsc, i32 0
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc0 ; CHECK-LABEL: @getsc0
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 8, 56 ; CHECK: rldicl r3, r3, 8, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc0 ; CHECK-LE-LABEL: @getsc0
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: clrldi r3, r3, 56 ; CHECK-LE: clrldi r3, r3, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc1(<16 x i8> %vsc) { define signext i8 @getsc1(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 1 %vecext = extractelement <16 x i8> %vsc, i32 1
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc1 ; CHECK-LABEL: @getsc1
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 16, 56 ; CHECK: rldicl r3, r3, 16, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc1 ; CHECK-LE-LABEL: @getsc1
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 56, 56 ; CHECK-LE: rldicl r3, r3, 56, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc2(<16 x i8> %vsc) { define signext i8 @getsc2(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 2 %vecext = extractelement <16 x i8> %vsc, i32 2
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc2 ; CHECK-LABEL: @getsc2
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 24, 56 ; CHECK: rldicl r3, r3, 24, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc2 ; CHECK-LE-LABEL: @getsc2
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 48, 56 ; CHECK-LE: rldicl r3, r3, 48, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc3(<16 x i8> %vsc) { define signext i8 @getsc3(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 3 %vecext = extractelement <16 x i8> %vsc, i32 3
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc3 ; CHECK-LABEL: @getsc3
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 32, 56 ; CHECK: rldicl r3, r3, 32, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc3 ; CHECK-LE-LABEL: @getsc3
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 40, 56 ; CHECK-LE: rldicl r3, r3, 40, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc4(<16 x i8> %vsc) { define signext i8 @getsc4(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 4 %vecext = extractelement <16 x i8> %vsc, i32 4
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc4 ; CHECK-LABEL: @getsc4
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 40, 56 ; CHECK: rldicl r3, r3, 40, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc4 ; CHECK-LE-LABEL: @getsc4
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 32, 56 ; CHECK-LE: rldicl r3, r3, 32, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc5(<16 x i8> %vsc) { define signext i8 @getsc5(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 5 %vecext = extractelement <16 x i8> %vsc, i32 5
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc5 ; CHECK-LABEL: @getsc5
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 48, 56 ; CHECK: rldicl r3, r3, 48, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc5 ; CHECK-LE-LABEL: @getsc5
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 24, 56 ; CHECK-LE: rldicl r3, r3, 24, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc6(<16 x i8> %vsc) { define signext i8 @getsc6(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 6 %vecext = extractelement <16 x i8> %vsc, i32 6
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc6 ; CHECK-LABEL: @getsc6
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 56, 56 ; CHECK: rldicl r3, r3, 56, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc6 ; CHECK-LE-LABEL: @getsc6
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 16, 56 ; CHECK-LE: rldicl r3, r3, 16, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc7(<16 x i8> %vsc) { define signext i8 @getsc7(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 7 %vecext = extractelement <16 x i8> %vsc, i32 7
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc7 ; CHECK-LABEL: @getsc7
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: clrldi r3, r3, 56 ; CHECK: clrldi r3, r3, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc7 ; CHECK-LE-LABEL: @getsc7
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 8, 56 ; CHECK-LE: rldicl r3, r3, 8, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc8(<16 x i8> %vsc) { define signext i8 @getsc8(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 8 %vecext = extractelement <16 x i8> %vsc, i32 8
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc8 ; CHECK-LABEL: @getsc8
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 8, 56 ; CHECK: rldicl r3, r3, 8, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc8 ; CHECK-LE-LABEL: @getsc8
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: clrldi r3, r3, 56 ; CHECK-LE: clrldi r3, r3, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc9(<16 x i8> %vsc) { define signext i8 @getsc9(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 9 %vecext = extractelement <16 x i8> %vsc, i32 9
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc9 ; CHECK-LABEL: @getsc9
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 16, 56 ; CHECK: rldicl r3, r3, 16, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc9 ; CHECK-LE-LABEL: @getsc9
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 56, 56 ; CHECK-LE: rldicl r3, r3, 56, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc10(<16 x i8> %vsc) { define signext i8 @getsc10(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 10 %vecext = extractelement <16 x i8> %vsc, i32 10
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc10 ; CHECK-LABEL: @getsc10
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 24, 56 ; CHECK: rldicl r3, r3, 24, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc10 ; CHECK-LE-LABEL: @getsc10
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 48, 56 ; CHECK-LE: rldicl r3, r3, 48, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc11(<16 x i8> %vsc) { define signext i8 @getsc11(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 11 %vecext = extractelement <16 x i8> %vsc, i32 11
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc11 ; CHECK-LABEL: @getsc11
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 32, 56 ; CHECK: rldicl r3, r3, 32, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc11 ; CHECK-LE-LABEL: @getsc11
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 40, 56 ; CHECK-LE: rldicl r3, r3, 40, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc12(<16 x i8> %vsc) { define signext i8 @getsc12(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 12 %vecext = extractelement <16 x i8> %vsc, i32 12
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc12 ; CHECK-LABEL: @getsc12
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 40, 56 ; CHECK: rldicl r3, r3, 40, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc12 ; CHECK-LE-LABEL: @getsc12
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 32, 56 ; CHECK-LE: rldicl r3, r3, 32, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc13(<16 x i8> %vsc) { define signext i8 @getsc13(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 13 %vecext = extractelement <16 x i8> %vsc, i32 13
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc13 ; CHECK-LABEL: @getsc13
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 48, 56 ; CHECK: rldicl r3, r3, 48, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc13 ; CHECK-LE-LABEL: @getsc13
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 24, 56 ; CHECK-LE: rldicl r3, r3, 24, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc14(<16 x i8> %vsc) { define signext i8 @getsc14(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 14 %vecext = extractelement <16 x i8> %vsc, i32 14
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc14 ; CHECK-LABEL: @getsc14
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 56, 56 ; CHECK: rldicl r3, r3, 56, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc14 ; CHECK-LE-LABEL: @getsc14
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 16, 56 ; CHECK-LE: rldicl r3, r3, 16, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getsc15(<16 x i8> %vsc) { define signext i8 @getsc15(<16 x i8> %vsc) {
entry: entry:
%vecext = extractelement <16 x i8> %vsc, i32 15 %vecext = extractelement <16 x i8> %vsc, i32 15
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getsc15 ; CHECK-LABEL: @getsc15
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: clrldi r3, r3, 56 ; CHECK: clrldi r3, r3, 56
; CHECK: extsb r3, r3 ; CHECK: extsb r3, r3
; CHECK-LE-LABEL: @getsc15 ; CHECK-LE-LABEL: @getsc15
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 8, 56 ; CHECK-LE: rldicl r3, r3, 8, 56
; CHECK-LE: extsb r3, r3 ; CHECK-LE: extsb r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc0(<16 x i8> %vuc) { define zeroext i8 @getuc0(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 0 %vecext = extractelement <16 x i8> %vuc, i32 0
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc0 ; CHECK-LABEL: @getuc0
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 8, 56 ; CHECK: rldicl r3, r3, 8, 56
; CHECK-LE-LABEL: @getuc0 ; CHECK-LE-LABEL: @getuc0
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: clrldi r3, r3, 56 ; CHECK-LE: clrldi r3, r3, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc1(<16 x i8> %vuc) { define zeroext i8 @getuc1(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 1 %vecext = extractelement <16 x i8> %vuc, i32 1
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc1 ; CHECK-LABEL: @getuc1
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 16, 56 ; CHECK: rldicl r3, r3, 16, 56
; CHECK-LE-LABEL: @getuc1 ; CHECK-LE-LABEL: @getuc1
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 56, 56 ; CHECK-LE: rldicl r3, r3, 56, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc2(<16 x i8> %vuc) { define zeroext i8 @getuc2(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 2 %vecext = extractelement <16 x i8> %vuc, i32 2
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc2 ; CHECK-LABEL: @getuc2
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 24, 56 ; CHECK: rldicl r3, r3, 24, 56
; CHECK-LE-LABEL: @getuc2 ; CHECK-LE-LABEL: @getuc2
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 48, 56 ; CHECK-LE: rldicl r3, r3, 48, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc3(<16 x i8> %vuc) { define zeroext i8 @getuc3(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 3 %vecext = extractelement <16 x i8> %vuc, i32 3
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc3 ; CHECK-LABEL: @getuc3
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 32, 56 ; CHECK: rldicl r3, r3, 32, 56
; CHECK-LE-LABEL: @getuc3 ; CHECK-LE-LABEL: @getuc3
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 40, 56 ; CHECK-LE: rldicl r3, r3, 40, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc4(<16 x i8> %vuc) { define zeroext i8 @getuc4(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 4 %vecext = extractelement <16 x i8> %vuc, i32 4
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc4 ; CHECK-LABEL: @getuc4
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 40, 56 ; CHECK: rldicl r3, r3, 40, 56
; CHECK-LE-LABEL: @getuc4 ; CHECK-LE-LABEL: @getuc4
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 32, 56 ; CHECK-LE: rldicl r3, r3, 32, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc5(<16 x i8> %vuc) { define zeroext i8 @getuc5(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 5 %vecext = extractelement <16 x i8> %vuc, i32 5
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc5 ; CHECK-LABEL: @getuc5
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 48, 56 ; CHECK: rldicl r3, r3, 48, 56
; CHECK-LE-LABEL: @getuc5 ; CHECK-LE-LABEL: @getuc5
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 24, 56 ; CHECK-LE: rldicl r3, r3, 24, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc6(<16 x i8> %vuc) { define zeroext i8 @getuc6(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 6 %vecext = extractelement <16 x i8> %vuc, i32 6
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc6 ; CHECK-LABEL: @getuc6
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 56, 56 ; CHECK: rldicl r3, r3, 56, 56
; CHECK-LE-LABEL: @getuc6 ; CHECK-LE-LABEL: @getuc6
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 16, 56 ; CHECK-LE: rldicl r3, r3, 16, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc7(<16 x i8> %vuc) { define zeroext i8 @getuc7(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 7 %vecext = extractelement <16 x i8> %vuc, i32 7
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc7 ; CHECK-LABEL: @getuc7
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: clrldi r3, r3, 56 ; CHECK: clrldi r3, r3, 56
; CHECK-LE-LABEL: @getuc7 ; CHECK-LE-LABEL: @getuc7
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 8, 56 ; CHECK-LE: rldicl r3, r3, 8, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc8(<16 x i8> %vuc) { define zeroext i8 @getuc8(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 8 %vecext = extractelement <16 x i8> %vuc, i32 8
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc8 ; CHECK-LABEL: @getuc8
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 8, 56 ; CHECK: rldicl r3, r3, 8, 56
; CHECK-LE-LABEL: @getuc8 ; CHECK-LE-LABEL: @getuc8
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: clrldi r3, r3, 56 ; CHECK-LE: clrldi r3, r3, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc9(<16 x i8> %vuc) { define zeroext i8 @getuc9(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 9 %vecext = extractelement <16 x i8> %vuc, i32 9
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc9 ; CHECK-LABEL: @getuc9
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 16, 56 ; CHECK: rldicl r3, r3, 16, 56
; CHECK-LE-LABEL: @getuc9 ; CHECK-LE-LABEL: @getuc9
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 56, 56 ; CHECK-LE: rldicl r3, r3, 56, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc10(<16 x i8> %vuc) { define zeroext i8 @getuc10(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 10 %vecext = extractelement <16 x i8> %vuc, i32 10
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc10 ; CHECK-LABEL: @getuc10
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 24, 56 ; CHECK: rldicl r3, r3, 24, 56
; CHECK-LE-LABEL: @getuc10 ; CHECK-LE-LABEL: @getuc10
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 48, 56 ; CHECK-LE: rldicl r3, r3, 48, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc11(<16 x i8> %vuc) { define zeroext i8 @getuc11(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 11 %vecext = extractelement <16 x i8> %vuc, i32 11
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc11 ; CHECK-LABEL: @getuc11
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 32, 56 ; CHECK: rldicl r3, r3, 32, 56
; CHECK-LE-LABEL: @getuc11 ; CHECK-LE-LABEL: @getuc11
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 40, 56 ; CHECK-LE: rldicl r3, r3, 40, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc12(<16 x i8> %vuc) { define zeroext i8 @getuc12(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 12 %vecext = extractelement <16 x i8> %vuc, i32 12
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc12 ; CHECK-LABEL: @getuc12
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 40, 56 ; CHECK: rldicl r3, r3, 40, 56
; CHECK-LE-LABEL: @getuc12 ; CHECK-LE-LABEL: @getuc12
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 32, 56 ; CHECK-LE: rldicl r3, r3, 32, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc13(<16 x i8> %vuc) { define zeroext i8 @getuc13(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 13 %vecext = extractelement <16 x i8> %vuc, i32 13
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc13 ; CHECK-LABEL: @getuc13
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 48, 56 ; CHECK: rldicl r3, r3, 48, 56
; CHECK-LE-LABEL: @getuc13 ; CHECK-LE-LABEL: @getuc13
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 24, 56 ; CHECK-LE: rldicl r3, r3, 24, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc14(<16 x i8> %vuc) { define zeroext i8 @getuc14(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 14 %vecext = extractelement <16 x i8> %vuc, i32 14
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc14 ; CHECK-LABEL: @getuc14
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 56, 56 ; CHECK: rldicl r3, r3, 56, 56
; CHECK-LE-LABEL: @getuc14 ; CHECK-LE-LABEL: @getuc14
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 16, 56 ; CHECK-LE: rldicl r3, r3, 16, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i8 @getuc15(<16 x i8> %vuc) { define zeroext i8 @getuc15(<16 x i8> %vuc) {
entry: entry:
%vecext = extractelement <16 x i8> %vuc, i32 15 %vecext = extractelement <16 x i8> %vuc, i32 15
ret i8 %vecext ret i8 %vecext
; CHECK-LABEL: @getuc15 ; CHECK-LABEL: @getuc15
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: clrldi r3, r3, 56 ; CHECK: clrldi r3, r3, 56
; CHECK-LE-LABEL: @getuc15 ; CHECK-LE-LABEL: @getuc15
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 8, 56 ; CHECK-LE: rldicl r3, r3, 8, 56
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i8 @getvelsc(<16 x i8> %vsc, i32 signext %i) { define signext i8 @getvelsc(<16 x i8> %vsc, i32 signext %i) {
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
entry: entry:
%vecext = extractelement <8 x i16> %vss, i32 0 %vecext = extractelement <8 x i16> %vss, i32 0
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getss0 ; CHECK-LABEL: @getss0
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 16, 48 ; CHECK: rldicl r3, r3, 16, 48
; CHECK: extsh r3, r3 ; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss0 ; CHECK-LE-LABEL: @getss0
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: clrldi r3, r3, 48 ; CHECK-LE: clrldi r3, r3, 48
; CHECK-LE: extsh r3, r3 ; CHECK-LE: extsh r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getss1(<8 x i16> %vss) { define signext i16 @getss1(<8 x i16> %vss) {
entry: entry:
%vecext = extractelement <8 x i16> %vss, i32 1 %vecext = extractelement <8 x i16> %vss, i32 1
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getss1 ; CHECK-LABEL: @getss1
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 32, 48 ; CHECK: rldicl r3, r3, 32, 48
; CHECK: extsh r3, r3 ; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss1 ; CHECK-LE-LABEL: @getss1
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 48, 48 ; CHECK-LE: rldicl r3, r3, 48, 48
; CHECK-LE: extsh r3, r3 ; CHECK-LE: extsh r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getss2(<8 x i16> %vss) { define signext i16 @getss2(<8 x i16> %vss) {
entry: entry:
%vecext = extractelement <8 x i16> %vss, i32 2 %vecext = extractelement <8 x i16> %vss, i32 2
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getss2 ; CHECK-LABEL: @getss2
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 48, 48 ; CHECK: rldicl r3, r3, 48, 48
; CHECK: extsh r3, r3 ; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss2 ; CHECK-LE-LABEL: @getss2
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 32, 48 ; CHECK-LE: rldicl r3, r3, 32, 48
; CHECK-LE: extsh r3, r3 ; CHECK-LE: extsh r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getss3(<8 x i16> %vss) { define signext i16 @getss3(<8 x i16> %vss) {
entry: entry:
%vecext = extractelement <8 x i16> %vss, i32 3 %vecext = extractelement <8 x i16> %vss, i32 3
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getss3 ; CHECK-LABEL: @getss3
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: clrldi r3, r3, 48 ; CHECK: clrldi r3, r3, 48
; CHECK: extsh r3, r3 ; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss3 ; CHECK-LE-LABEL: @getss3
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 16, 48 ; CHECK-LE: rldicl r3, r3, 16, 48
; CHECK-LE: extsh r3, r3 ; CHECK-LE: extsh r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getss4(<8 x i16> %vss) { define signext i16 @getss4(<8 x i16> %vss) {
entry: entry:
%vecext = extractelement <8 x i16> %vss, i32 4 %vecext = extractelement <8 x i16> %vss, i32 4
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getss4 ; CHECK-LABEL: @getss4
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 16, 48 ; CHECK: rldicl r3, r3, 16, 48
; CHECK: extsh r3, r3 ; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss4 ; CHECK-LE-LABEL: @getss4
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: clrldi r3, r3, 48 ; CHECK-LE: clrldi r3, r3, 48
; CHECK-LE: extsh r3, r3 ; CHECK-LE: extsh r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getss5(<8 x i16> %vss) { define signext i16 @getss5(<8 x i16> %vss) {
entry: entry:
%vecext = extractelement <8 x i16> %vss, i32 5 %vecext = extractelement <8 x i16> %vss, i32 5
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getss5 ; CHECK-LABEL: @getss5
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 32, 48 ; CHECK: rldicl r3, r3, 32, 48
; CHECK: extsh r3, r3 ; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss5 ; CHECK-LE-LABEL: @getss5
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 48, 48 ; CHECK-LE: rldicl r3, r3, 48, 48
; CHECK-LE: extsh r3, r3 ; CHECK-LE: extsh r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getss6(<8 x i16> %vss) { define signext i16 @getss6(<8 x i16> %vss) {
entry: entry:
%vecext = extractelement <8 x i16> %vss, i32 6 %vecext = extractelement <8 x i16> %vss, i32 6
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getss6 ; CHECK-LABEL: @getss6
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 48, 48 ; CHECK: rldicl r3, r3, 48, 48
; CHECK: extsh r3, r3 ; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss6 ; CHECK-LE-LABEL: @getss6
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 32, 48 ; CHECK-LE: rldicl r3, r3, 32, 48
; CHECK-LE: extsh r3, r3 ; CHECK-LE: extsh r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getss7(<8 x i16> %vss) { define signext i16 @getss7(<8 x i16> %vss) {
entry: entry:
%vecext = extractelement <8 x i16> %vss, i32 7 %vecext = extractelement <8 x i16> %vss, i32 7
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getss7 ; CHECK-LABEL: @getss7
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: clrldi r3, r3, 48 ; CHECK: clrldi r3, r3, 48
; CHECK: extsh r3, r3 ; CHECK: extsh r3, r3
; CHECK-LE-LABEL: @getss7 ; CHECK-LE-LABEL: @getss7
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 16, 48 ; CHECK-LE: rldicl r3, r3, 16, 48
; CHECK-LE: extsh r3, r3 ; CHECK-LE: extsh r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus0(<8 x i16> %vus) { define zeroext i16 @getus0(<8 x i16> %vus) {
entry: entry:
%vecext = extractelement <8 x i16> %vus, i32 0 %vecext = extractelement <8 x i16> %vus, i32 0
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getus0 ; CHECK-LABEL: @getus0
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 16, 48 ; CHECK: rldicl r3, r3, 16, 48
; CHECK-LE-LABEL: @getus0 ; CHECK-LE-LABEL: @getus0
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: clrldi r3, r3, 48 ; CHECK-LE: clrldi r3, r3, 48
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus1(<8 x i16> %vus) { define zeroext i16 @getus1(<8 x i16> %vus) {
entry: entry:
%vecext = extractelement <8 x i16> %vus, i32 1 %vecext = extractelement <8 x i16> %vus, i32 1
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getus1 ; CHECK-LABEL: @getus1
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 32, 48 ; CHECK: rldicl r3, r3, 32, 48
; CHECK-LE-LABEL: @getus1 ; CHECK-LE-LABEL: @getus1
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 48, 48 ; CHECK-LE: rldicl r3, r3, 48, 48
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus2(<8 x i16> %vus) { define zeroext i16 @getus2(<8 x i16> %vus) {
entry: entry:
%vecext = extractelement <8 x i16> %vus, i32 2 %vecext = extractelement <8 x i16> %vus, i32 2
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getus2 ; CHECK-LABEL: @getus2
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: rldicl r3, r3, 48, 48 ; CHECK: rldicl r3, r3, 48, 48
; CHECK-LE-LABEL: @getus2 ; CHECK-LE-LABEL: @getus2
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 32, 48 ; CHECK-LE: rldicl r3, r3, 32, 48
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus3(<8 x i16> %vus) { define zeroext i16 @getus3(<8 x i16> %vus) {
entry: entry:
%vecext = extractelement <8 x i16> %vus, i32 3 %vecext = extractelement <8 x i16> %vus, i32 3
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getus3 ; CHECK-LABEL: @getus3
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK: clrldi r3, r3, 48 ; CHECK: clrldi r3, r3, 48
; CHECK-LE-LABEL: @getus3 ; CHECK-LE-LABEL: @getus3
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
; CHECK-LE: rldicl r3, r3, 16, 48 ; CHECK-LE: rldicl r3, r3, 16, 48
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus4(<8 x i16> %vus) { define zeroext i16 @getus4(<8 x i16> %vus) {
entry: entry:
%vecext = extractelement <8 x i16> %vus, i32 4 %vecext = extractelement <8 x i16> %vus, i32 4
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getus4 ; CHECK-LABEL: @getus4
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 16, 48 ; CHECK: rldicl r3, r3, 16, 48
; CHECK-LE-LABEL: @getus4 ; CHECK-LE-LABEL: @getus4
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: clrldi r3, r3, 48 ; CHECK-LE: clrldi r3, r3, 48
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus5(<8 x i16> %vus) { define zeroext i16 @getus5(<8 x i16> %vus) {
entry: entry:
%vecext = extractelement <8 x i16> %vus, i32 5 %vecext = extractelement <8 x i16> %vus, i32 5
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getus5 ; CHECK-LABEL: @getus5
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 32, 48 ; CHECK: rldicl r3, r3, 32, 48
; CHECK-LE-LABEL: @getus5 ; CHECK-LE-LABEL: @getus5
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 48, 48 ; CHECK-LE: rldicl r3, r3, 48, 48
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus6(<8 x i16> %vus) { define zeroext i16 @getus6(<8 x i16> %vus) {
entry: entry:
%vecext = extractelement <8 x i16> %vus, i32 6 %vecext = extractelement <8 x i16> %vus, i32 6
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getus6 ; CHECK-LABEL: @getus6
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: rldicl r3, r3, 48, 48 ; CHECK: rldicl r3, r3, 48, 48
; CHECK-LE-LABEL: @getus6 ; CHECK-LE-LABEL: @getus6
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 32, 48 ; CHECK-LE: rldicl r3, r3, 32, 48
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i16 @getus7(<8 x i16> %vus) { define zeroext i16 @getus7(<8 x i16> %vus) {
entry: entry:
%vecext = extractelement <8 x i16> %vus, i32 7 %vecext = extractelement <8 x i16> %vus, i32 7
ret i16 %vecext ret i16 %vecext
; CHECK-LABEL: @getus7 ; CHECK-LABEL: @getus7
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK: clrldi r3, r3, 48 ; CHECK: clrldi r3, r3, 48
; CHECK-LE-LABEL: @getus7 ; CHECK-LE-LABEL: @getus7
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
; CHECK-LE: rldicl r3, r3, 16, 48 ; CHECK-LE: rldicl r3, r3, 16, 48
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i16 @getvelss(<8 x i16> %vss, i32 signext %i) { define signext i16 @getvelss(<8 x i16> %vss, i32 signext %i) {
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @getsi0(<4 x i32> %vsi) { define signext i32 @getsi0(<4 x i32> %vsi) {
entry: entry:
%vecext = extractelement <4 x i32> %vsi, i32 0 %vecext = extractelement <4 x i32> %vsi, i32 0
ret i32 %vecext ret i32 %vecext
; CHECK-LABEL: @getsi0 ; CHECK-LABEL: @getsi0
; CHECK: xxsldwi vs0, v2, v2, 3 ; CHECK: xxsldwi vs0, v2, v2, 3
; CHECK: mfvsrwz r3, f0 ; CHECK: mffprwz r3, f0
; CHECK: extsw r3, r3 ; CHECK: extsw r3, r3
; CHECK-LE-LABEL: @getsi0 ; CHECK-LE-LABEL: @getsi0
; CHECK-LE: xxswapd vs0, v2 ; CHECK-LE: xxswapd vs0, v2
; CHECK-LE: mfvsrwz r3, f0 ; CHECK-LE: mffprwz r3, f0
; CHECK-LE: extsw r3, r3 ; CHECK-LE: extsw r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @getsi1(<4 x i32> %vsi) { define signext i32 @getsi1(<4 x i32> %vsi) {
entry: entry:
%vecext = extractelement <4 x i32> %vsi, i32 1 %vecext = extractelement <4 x i32> %vsi, i32 1
ret i32 %vecext ret i32 %vecext
; CHECK-LABEL: @getsi1 ; CHECK-LABEL: @getsi1
; CHECK: mfvsrwz r3, v2 ; CHECK: mfvsrwz r3, v2
; CHECK: extsw r3, r3 ; CHECK: extsw r3, r3
; CHECK-LE-LABEL: @getsi1 ; CHECK-LE-LABEL: @getsi1
; CHECK-LE: xxsldwi vs0, v2, v2, 1 ; CHECK-LE: xxsldwi vs0, v2, v2, 1
; CHECK-LE: mfvsrwz r3, f0 ; CHECK-LE: mffprwz r3, f0
; CHECK-LE: extsw r3, r3 ; CHECK-LE: extsw r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @getsi2(<4 x i32> %vsi) { define signext i32 @getsi2(<4 x i32> %vsi) {
entry: entry:
%vecext = extractelement <4 x i32> %vsi, i32 2 %vecext = extractelement <4 x i32> %vsi, i32 2
ret i32 %vecext ret i32 %vecext
; CHECK-LABEL: @getsi2 ; CHECK-LABEL: @getsi2
; CHECK: xxsldwi vs0, v2, v2, 1 ; CHECK: xxsldwi vs0, v2, v2, 1
; CHECK: mfvsrwz r3, f0 ; CHECK: mffprwz r3, f0
; CHECK: extsw r3, r3 ; CHECK: extsw r3, r3
; CHECK-LE-LABEL: @getsi2 ; CHECK-LE-LABEL: @getsi2
; CHECK-LE: mfvsrwz r3, v2 ; CHECK-LE: mfvsrwz r3, v2
; CHECK-LE: extsw r3, r3 ; CHECK-LE: extsw r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @getsi3(<4 x i32> %vsi) { define signext i32 @getsi3(<4 x i32> %vsi) {
entry: entry:
%vecext = extractelement <4 x i32> %vsi, i32 3 %vecext = extractelement <4 x i32> %vsi, i32 3
ret i32 %vecext ret i32 %vecext
; CHECK-LABEL: @getsi3 ; CHECK-LABEL: @getsi3
; CHECK: xxswapd vs0, v2 ; CHECK: xxswapd vs0, v2
; CHECK: mfvsrwz r3, f0 ; CHECK: mffprwz r3, f0
; CHECK: extsw r3, r3 ; CHECK: extsw r3, r3
; CHECK-LE-LABEL: @getsi3 ; CHECK-LE-LABEL: @getsi3
; CHECK-LE: xxsldwi vs0, v2, v2, 3 ; CHECK-LE: xxsldwi vs0, v2, v2, 3
; CHECK-LE: mfvsrwz r3, f0 ; CHECK-LE: mffprwz r3, f0
; CHECK-LE: extsw r3, r3 ; CHECK-LE: extsw r3, r3
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @getui0(<4 x i32> %vui) { define zeroext i32 @getui0(<4 x i32> %vui) {
entry: entry:
%vecext = extractelement <4 x i32> %vui, i32 0 %vecext = extractelement <4 x i32> %vui, i32 0
ret i32 %vecext ret i32 %vecext
; CHECK-LABEL: @getui0 ; CHECK-LABEL: @getui0
; CHECK: xxsldwi vs0, v2, v2, 3 ; CHECK: xxsldwi vs0, v2, v2, 3
; CHECK: mfvsrwz r3, f0 ; CHECK: mffprwz r3, f0
; CHECK-LE-LABEL: @getui0 ; CHECK-LE-LABEL: @getui0
; CHECK-LE: xxswapd vs0, v2 ; CHECK-LE: xxswapd vs0, v2
; CHECK-LE: mfvsrwz r3, f0 ; CHECK-LE: mffprwz r3, f0
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @getui1(<4 x i32> %vui) { define zeroext i32 @getui1(<4 x i32> %vui) {
entry: entry:
%vecext = extractelement <4 x i32> %vui, i32 1 %vecext = extractelement <4 x i32> %vui, i32 1
ret i32 %vecext ret i32 %vecext
; CHECK-LABEL: @getui1 ; CHECK-LABEL: @getui1
; CHECK: mfvsrwz r3, v2 ; CHECK: mfvsrwz r3, v2
; CHECK-LE-LABEL: @getui1 ; CHECK-LE-LABEL: @getui1
; CHECK-LE: xxsldwi vs0, v2, v2, 1 ; CHECK-LE: xxsldwi vs0, v2, v2, 1
; CHECK-LE: mfvsrwz r3, f0 ; CHECK-LE: mffprwz r3, f0
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @getui2(<4 x i32> %vui) { define zeroext i32 @getui2(<4 x i32> %vui) {
entry: entry:
%vecext = extractelement <4 x i32> %vui, i32 2 %vecext = extractelement <4 x i32> %vui, i32 2
ret i32 %vecext ret i32 %vecext
; CHECK-LABEL: @getui2 ; CHECK-LABEL: @getui2
; CHECK: xxsldwi vs0, v2, v2, 1 ; CHECK: xxsldwi vs0, v2, v2, 1
; CHECK: mfvsrwz r3, f0 ; CHECK: mffprwz r3, f0
; CHECK-LE-LABEL: @getui2 ; CHECK-LE-LABEL: @getui2
; CHECK-LE: mfvsrwz r3, v2 ; CHECK-LE: mfvsrwz r3, v2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define zeroext i32 @getui3(<4 x i32> %vui) { define zeroext i32 @getui3(<4 x i32> %vui) {
entry: entry:
%vecext = extractelement <4 x i32> %vui, i32 3 %vecext = extractelement <4 x i32> %vui, i32 3
ret i32 %vecext ret i32 %vecext
; CHECK-LABEL: @getui3 ; CHECK-LABEL: @getui3
; CHECK: xxswapd vs0, v2 ; CHECK: xxswapd vs0, v2
; CHECK: mfvsrwz r3, f0 ; CHECK: mffprwz r3, f0
; CHECK-LE-LABEL: @getui3 ; CHECK-LE-LABEL: @getui3
; CHECK-LE: xxsldwi vs0, v2, v2, 3 ; CHECK-LE: xxsldwi vs0, v2, v2, 3
; CHECK-LE: mfvsrwz r3, f0 ; CHECK-LE: mffprwz r3, f0
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @getvelsi(<4 x i32> %vsi, i32 signext %i) { define signext i32 @getvelsi(<4 x i32> %vsi, i32 signext %i) {
entry: entry:
%vecext = extractelement <4 x i32> %vsi, i32 %i %vecext = extractelement <4 x i32> %vsi, i32 %i
ret i32 %vecext ret i32 %vecext
; CHECK-LABEL: @getvelsi ; CHECK-LABEL: @getvelsi
Show All 15 Lines
define i64 @getsl0(<2 x i64> %vsl) { define i64 @getsl0(<2 x i64> %vsl) {
entry: entry:
%vecext = extractelement <2 x i64> %vsl, i32 0 %vecext = extractelement <2 x i64> %vsl, i32 0
ret i64 %vecext ret i64 %vecext
; CHECK-LABEL: @getsl0 ; CHECK-LABEL: @getsl0
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK-LE-LABEL: @getsl0 ; CHECK-LE-LABEL: @getsl0
; CHECK-LE: xxswapd vs0, v2 ; CHECK-LE: xxswapd vs0, v2
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @getsl1(<2 x i64> %vsl) { define i64 @getsl1(<2 x i64> %vsl) {
entry: entry:
%vecext = extractelement <2 x i64> %vsl, i32 1 %vecext = extractelement <2 x i64> %vsl, i32 1
ret i64 %vecext ret i64 %vecext
; CHECK-LABEL: @getsl1 ; CHECK-LABEL: @getsl1
; CHECK: xxswapd vs0, v2 ; CHECK: xxswapd vs0, v2
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK-LE-LABEL: @getsl1 ; CHECK-LE-LABEL: @getsl1
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @getul0(<2 x i64> %vul) { define i64 @getul0(<2 x i64> %vul) {
entry: entry:
%vecext = extractelement <2 x i64> %vul, i32 0 %vecext = extractelement <2 x i64> %vul, i32 0
ret i64 %vecext ret i64 %vecext
; CHECK-LABEL: @getul0 ; CHECK-LABEL: @getul0
; CHECK: mfvsrd r3, v2 ; CHECK: mfvsrd r3, v2
; CHECK-LE-LABEL: @getul0 ; CHECK-LE-LABEL: @getul0
; CHECK-LE: xxswapd vs0, v2 ; CHECK-LE: xxswapd vs0, v2
; CHECK-LE: mfvsrd r3, f0 ; CHECK-LE: mffprd r3, f0
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @getul1(<2 x i64> %vul) { define i64 @getul1(<2 x i64> %vul) {
entry: entry:
%vecext = extractelement <2 x i64> %vul, i32 1 %vecext = extractelement <2 x i64> %vul, i32 1
ret i64 %vecext ret i64 %vecext
; CHECK-LABEL: @getul1 ; CHECK-LABEL: @getul1
; CHECK: xxswapd vs0, v2 ; CHECK: xxswapd vs0, v2
; CHECK: mfvsrd r3, f0 ; CHECK: mffprd r3, f0
; CHECK-LE-LABEL: @getul1 ; CHECK-LE-LABEL: @getul1
; CHECK-LE: mfvsrd r3, v2 ; CHECK-LE: mfvsrd r3, v2
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @getvelsl(<2 x i64> %vsl, i32 signext %i) { define i64 @getvelsl(<2 x i64> %vsl, i32 signext %i) {
entry: entry:
%vecext = extractelement <2 x i64> %vsl, i32 %i %vecext = extractelement <2 x i64> %vsl, i32 %i
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llvm/test/CodeGen/PowerPC/p9-xxinsertw-xxextractuw.ll

Show First 20 Lines • Show All 555 Lines • ▼ Show 20 Lines
; CHECK-BE: xxinsertw 34, 0, 12 ; CHECK-BE: xxinsertw 34, 0, 12
%vecins = insertelement <4 x float> %a, float %b, i32 3 %vecins = insertelement <4 x float> %a, float %b, i32 3
ret <4 x float> %vecins ret <4 x float> %vecins
} }
define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) { define <4 x i32> @_Z10testInsEltILj0EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
entry: entry:
; CHECK-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_ ; CHECK-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_
; CHECK: mtvsrwz 0, 5 ; CHECK: mtfprwz 0, 5
; CHECK: xxinsertw 34, 0, 12 ; CHECK: xxinsertw 34, 0, 12
; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_ ; CHECK-BE-LABEL: _Z10testInsEltILj0EDv4_jjET0_S1_T1_
; CHECK-BE: mtvsrwz 0, 5 ; CHECK-BE: mtfprwz 0, 5
; CHECK-BE: xxinsertw 34, 0, 0 ; CHECK-BE: xxinsertw 34, 0, 0
%vecins = insertelement <4 x i32> %a, i32 %b, i32 0 %vecins = insertelement <4 x i32> %a, i32 %b, i32 0
ret <4 x i32> %vecins ret <4 x i32> %vecins
} }
define <4 x i32> @_Z10testInsEltILj1EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) { define <4 x i32> @_Z10testInsEltILj1EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
entry: entry:
; CHECK-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_ ; CHECK-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_
; CHECK: mtvsrwz 0, 5 ; CHECK: mtfprwz 0, 5
; CHECK: xxinsertw 34, 0, 8 ; CHECK: xxinsertw 34, 0, 8
; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_ ; CHECK-BE-LABEL: _Z10testInsEltILj1EDv4_jjET0_S1_T1_
; CHECK-BE: mtvsrwz 0, 5 ; CHECK-BE: mtfprwz 0, 5
; CHECK-BE: xxinsertw 34, 0, 4 ; CHECK-BE: xxinsertw 34, 0, 4
%vecins = insertelement <4 x i32> %a, i32 %b, i32 1 %vecins = insertelement <4 x i32> %a, i32 %b, i32 1
ret <4 x i32> %vecins ret <4 x i32> %vecins
} }
define <4 x i32> @_Z10testInsEltILj2EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) { define <4 x i32> @_Z10testInsEltILj2EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
entry: entry:
; CHECK-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_ ; CHECK-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_
; CHECK: mtvsrwz 0, 5 ; CHECK: mtfprwz 0, 5
; CHECK: xxinsertw 34, 0, 4 ; CHECK: xxinsertw 34, 0, 4
; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_ ; CHECK-BE-LABEL: _Z10testInsEltILj2EDv4_jjET0_S1_T1_
; CHECK-BE: mtvsrwz 0, 5 ; CHECK-BE: mtfprwz 0, 5
; CHECK-BE: xxinsertw 34, 0, 8 ; CHECK-BE: xxinsertw 34, 0, 8
%vecins = insertelement <4 x i32> %a, i32 %b, i32 2 %vecins = insertelement <4 x i32> %a, i32 %b, i32 2
ret <4 x i32> %vecins ret <4 x i32> %vecins
} }
define <4 x i32> @_Z10testInsEltILj3EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) { define <4 x i32> @_Z10testInsEltILj3EDv4_jjET0_S1_T1_(<4 x i32> %a, i32 zeroext %b) {
entry: entry:
; CHECK-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_ ; CHECK-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_
; CHECK: mtvsrwz 0, 5 ; CHECK: mtfprwz 0, 5
; CHECK: xxinsertw 34, 0, 0 ; CHECK: xxinsertw 34, 0, 0
; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_ ; CHECK-BE-LABEL: _Z10testInsEltILj3EDv4_jjET0_S1_T1_
; CHECK-BE: mtvsrwz 0, 5 ; CHECK-BE: mtfprwz 0, 5
; CHECK-BE: xxinsertw 34, 0, 12 ; CHECK-BE: xxinsertw 34, 0, 12
%vecins = insertelement <4 x i32> %a, i32 %b, i32 3 %vecins = insertelement <4 x i32> %a, i32 %b, i32 3
ret <4 x i32> %vecins ret <4 x i32> %vecins
} }
define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) { define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_r(<4 x float> %a, <4 x float> %b) {
entry: entry:
; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_ ; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
▲ Show 20 Lines • Show All 462 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/popcnt-zext.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mattr=+popcntd < %s | FileCheck %s --check-prefixes=ANY,FAST ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mattr=+popcntd < %s | FileCheck %s --check-prefixes=ANY,FAST
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mattr=+slow-popcntd < %s | FileCheck %s --check-prefixes=ANY,SLOW ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-- -mattr=+slow-popcntd < %s | FileCheck %s --check-prefixes=ANY,SLOW
define i16 @zpop_i8_i16(i8 %x) { define i16 @zpop_i8_i16(i8 %x) {
; FAST-LABEL: zpop_i8_i16: ; FAST-LABEL: zpop_i8_i16:
; FAST: # %bb.0: ; FAST: # %bb.0:
; FAST-NEXT: clrldi 3, 3, 56 ; FAST-NEXT: clrldi 3, 3, 56
; FAST-NEXT: popcntd 3, 3 ; FAST-NEXT: popcntd 3, 3
; FAST-NEXT: blr ; FAST-NEXT: blr
; ;
; SLOW-LABEL: zpop_i8_i16: ; SLOW-LABEL: zpop_i8_i16:
; SLOW: # %bb.0: ; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 24 ; SLOW-NEXT: clrlwi 5, 3, 24
; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31 ; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 85 ; SLOW-NEXT: andi. 3, 3, 85
; SLOW-NEXT: lis 4, 13107 ; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5 ; SLOW-NEXT: subf 3, 3, 5
; SLOW-NEXT: ori 4, 4, 13107 ; SLOW-NEXT: ori 4, 4, 13107
; SLOW-NEXT: rotlwi 5, 3, 30 ; SLOW-NEXT: rotlwi 5, 3, 30
; SLOW-NEXT: and 3, 3, 4 ; SLOW-NEXT: and 3, 3, 4
; SLOW-NEXT: andis. 4, 5, 13107 ; SLOW-NEXT: andis. 4, 5, 13107
; SLOW-NEXT: andi. 5, 5, 13107 ; SLOW-NEXT: andi. 5, 5, 13107
Show All 19 Lines
; FAST: # %bb.0: ; FAST: # %bb.0:
; FAST-NEXT: clrldi 3, 3, 56 ; FAST-NEXT: clrldi 3, 3, 56
; FAST-NEXT: popcntd 3, 3 ; FAST-NEXT: popcntd 3, 3
; FAST-NEXT: blr ; FAST-NEXT: blr
; ;
; SLOW-LABEL: popz_i8_i16: ; SLOW-LABEL: popz_i8_i16:
; SLOW: # %bb.0: ; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 24 ; SLOW-NEXT: clrlwi 5, 3, 24
; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31 ; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 85 ; SLOW-NEXT: andi. 3, 3, 85
; SLOW-NEXT: lis 4, 13107 ; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5 ; SLOW-NEXT: subf 3, 3, 5
; SLOW-NEXT: ori 4, 4, 13107 ; SLOW-NEXT: ori 4, 4, 13107
; SLOW-NEXT: rotlwi 5, 3, 30 ; SLOW-NEXT: rotlwi 5, 3, 30
; SLOW-NEXT: and 3, 3, 4 ; SLOW-NEXT: and 3, 3, 4
; SLOW-NEXT: andis. 4, 5, 13107 ; SLOW-NEXT: andis. 4, 5, 13107
; SLOW-NEXT: andi. 5, 5, 13107 ; SLOW-NEXT: andi. 5, 5, 13107
Show All 12 Lines; SLOW-NEXT: blr
%pop = tail call i8 @llvm.ctpop.i8(i8 %x) %pop = tail call i8 @llvm.ctpop.i8(i8 %x)
%z = zext i8 %pop to i16 %z = zext i8 %pop to i16
ret i16 %z ret i16 %z
} }
define i32 @zpop_i8_i32(i8 %x) { define i32 @zpop_i8_i32(i8 %x) {
; FAST-LABEL: zpop_i8_i32: ; FAST-LABEL: zpop_i8_i32:
; FAST: # %bb.0: ; FAST: # %bb.0:
; FAST-NEXT: rlwinm 3, 3, 0, 24, 31 ; FAST-NEXT: clrlwi 3, 3, 24
; FAST-NEXT: popcntw 3, 3 ; FAST-NEXT: popcntw 3, 3
; FAST-NEXT: blr ; FAST-NEXT: blr
; ;
; SLOW-LABEL: zpop_i8_i32: ; SLOW-LABEL: zpop_i8_i32:
; SLOW: # %bb.0: ; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 24 ; SLOW-NEXT: clrlwi 5, 3, 24
; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31 ; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 85 ; SLOW-NEXT: andi. 3, 3, 85
; SLOW-NEXT: lis 4, 13107 ; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5 ; SLOW-NEXT: subf 3, 3, 5
; SLOW-NEXT: ori 4, 4, 13107 ; SLOW-NEXT: ori 4, 4, 13107
; SLOW-NEXT: rotlwi 5, 3, 30 ; SLOW-NEXT: rotlwi 5, 3, 30
; SLOW-NEXT: and 3, 3, 4 ; SLOW-NEXT: and 3, 3, 4
; SLOW-NEXT: andis. 4, 5, 13107 ; SLOW-NEXT: andis. 4, 5, 13107
; SLOW-NEXT: andi. 5, 5, 13107 ; SLOW-NEXT: andi. 5, 5, 13107
Show All 19 Lines
; FAST: # %bb.0: ; FAST: # %bb.0:
; FAST-NEXT: clrldi 3, 3, 56 ; FAST-NEXT: clrldi 3, 3, 56
; FAST-NEXT: popcntd 3, 3 ; FAST-NEXT: popcntd 3, 3
; FAST-NEXT: blr ; FAST-NEXT: blr
; ;
; SLOW-LABEL: popz_i8_32: ; SLOW-LABEL: popz_i8_32:
; SLOW: # %bb.0: ; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 24 ; SLOW-NEXT: clrlwi 5, 3, 24
; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31 ; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 85 ; SLOW-NEXT: andi. 3, 3, 85
; SLOW-NEXT: lis 4, 13107 ; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5 ; SLOW-NEXT: subf 3, 3, 5
; SLOW-NEXT: ori 4, 4, 13107 ; SLOW-NEXT: ori 4, 4, 13107
; SLOW-NEXT: rotlwi 5, 3, 30 ; SLOW-NEXT: rotlwi 5, 3, 30
; SLOW-NEXT: and 3, 3, 4 ; SLOW-NEXT: and 3, 3, 4
; SLOW-NEXT: andis. 4, 5, 13107 ; SLOW-NEXT: andis. 4, 5, 13107
; SLOW-NEXT: andi. 5, 5, 13107 ; SLOW-NEXT: andi. 5, 5, 13107
Show All 12 Lines; SLOW-NEXT: blr
%pop = tail call i8 @llvm.ctpop.i8(i8 %x) %pop = tail call i8 @llvm.ctpop.i8(i8 %x)
%z = zext i8 %pop to i32 %z = zext i8 %pop to i32
ret i32 %z ret i32 %z
} }
define i32 @zpop_i16_i32(i16 %x) { define i32 @zpop_i16_i32(i16 %x) {
; FAST-LABEL: zpop_i16_i32: ; FAST-LABEL: zpop_i16_i32:
; FAST: # %bb.0: ; FAST: # %bb.0:
; FAST-NEXT: rlwinm 3, 3, 0, 16, 31 ; FAST-NEXT: clrlwi 3, 3, 16
; FAST-NEXT: popcntw 3, 3 ; FAST-NEXT: popcntw 3, 3
; FAST-NEXT: blr ; FAST-NEXT: blr
; ;
; SLOW-LABEL: zpop_i16_i32: ; SLOW-LABEL: zpop_i16_i32:
; SLOW: # %bb.0: ; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 16 ; SLOW-NEXT: clrlwi 5, 3, 16
; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31 ; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 21845 ; SLOW-NEXT: andi. 3, 3, 21845
; SLOW-NEXT: lis 4, 13107 ; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5 ; SLOW-NEXT: subf 3, 3, 5
; SLOW-NEXT: ori 4, 4, 13107 ; SLOW-NEXT: ori 4, 4, 13107
; SLOW-NEXT: rotlwi 5, 3, 30 ; SLOW-NEXT: rotlwi 5, 3, 30
; SLOW-NEXT: and 3, 3, 4 ; SLOW-NEXT: and 3, 3, 4
; SLOW-NEXT: andis. 4, 5, 13107 ; SLOW-NEXT: andis. 4, 5, 13107
; SLOW-NEXT: andi. 5, 5, 13107 ; SLOW-NEXT: andi. 5, 5, 13107
Show All 19 Lines
; FAST: # %bb.0: ; FAST: # %bb.0:
; FAST-NEXT: clrldi 3, 3, 48 ; FAST-NEXT: clrldi 3, 3, 48
; FAST-NEXT: popcntd 3, 3 ; FAST-NEXT: popcntd 3, 3
; FAST-NEXT: blr ; FAST-NEXT: blr
; ;
; SLOW-LABEL: popz_i16_32: ; SLOW-LABEL: popz_i16_32:
; SLOW: # %bb.0: ; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 16 ; SLOW-NEXT: clrlwi 5, 3, 16
; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31 ; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 21845 ; SLOW-NEXT: andi. 3, 3, 21845
; SLOW-NEXT: lis 4, 13107 ; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5 ; SLOW-NEXT: subf 3, 3, 5
; SLOW-NEXT: ori 4, 4, 13107 ; SLOW-NEXT: ori 4, 4, 13107
; SLOW-NEXT: rotlwi 5, 3, 30 ; SLOW-NEXT: rotlwi 5, 3, 30
; SLOW-NEXT: and 3, 3, 4 ; SLOW-NEXT: and 3, 3, 4
; SLOW-NEXT: andis. 4, 5, 13107 ; SLOW-NEXT: andis. 4, 5, 13107
; SLOW-NEXT: andi. 5, 5, 13107 ; SLOW-NEXT: andi. 5, 5, 13107
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines
; FAST-NEXT: clrldi 3, 3, 48 ; FAST-NEXT: clrldi 3, 3, 48
; FAST-NEXT: popcntd 3, 3 ; FAST-NEXT: popcntd 3, 3
; FAST-NEXT: rlwinm 3, 3, 0, 27, 27 ; FAST-NEXT: rlwinm 3, 3, 0, 27, 27
; FAST-NEXT: blr ; FAST-NEXT: blr
; ;
; SLOW-LABEL: popa_i16_i64: ; SLOW-LABEL: popa_i16_i64:
; SLOW: # %bb.0: ; SLOW: # %bb.0:
; SLOW-NEXT: clrlwi 5, 3, 16 ; SLOW-NEXT: clrlwi 5, 3, 16
; SLOW-NEXT: rlwinm 3, 3, 31, 0, 31 ; SLOW-NEXT: rotlwi 3, 3, 31
; SLOW-NEXT: andi. 3, 3, 21845 ; SLOW-NEXT: andi. 3, 3, 21845
; SLOW-NEXT: lis 4, 13107 ; SLOW-NEXT: lis 4, 13107
; SLOW-NEXT: subf 3, 3, 5 ; SLOW-NEXT: subf 3, 3, 5
; SLOW-NEXT: ori 4, 4, 13107 ; SLOW-NEXT: ori 4, 4, 13107
; SLOW-NEXT: rotlwi 5, 3, 30 ; SLOW-NEXT: rotlwi 5, 3, 30
; SLOW-NEXT: and 3, 3, 4 ; SLOW-NEXT: and 3, 3, 4
; SLOW-NEXT: andis. 4, 5, 13107 ; SLOW-NEXT: andis. 4, 5, 13107
; SLOW-NEXT: andi. 5, 5, 13107 ; SLOW-NEXT: andi. 5, 5, 13107
Show All 23 Lines

llvm/test/CodeGen/PowerPC/ppc-crbits-onoff.ll

; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 < %s | FileCheck %s
; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s ; RUN: llc -ppc-gpr-icmps=all -verify-machineinstrs -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck --check-prefix=CHECK-NO-ISEL %s
target datalayout = "E-m:e-i64:64-n32:64" target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu" target triple = "powerpc64-unknown-linux-gnu"
; Function Attrs: nounwind readnone ; Function Attrs: nounwind readnone
define signext i32 @crbitsoff(i32 signext %v1, i32 signext %v2) #0 { define signext i32 @crbitsoff(i32 signext %v1, i32 signext %v2) #0 {
entry: entry:
%tobool = icmp ne i32 %v1, 0 %tobool = icmp ne i32 %v1, 0
%lnot = icmp eq i32 %v2, 0 %lnot = icmp eq i32 %v2, 0
%and3 = and i1 %tobool, %lnot %and3 = and i1 %tobool, %lnot
%and = zext i1 %and3 to i32 %and = zext i1 %and3 to i32
ret i32 %and ret i32 %and
; CHECK-LABEL: @crbitsoff ; CHECK-LABEL: @crbitsoff
; CHECK-NO-ISEL-LABEL: @crbitsoff ; CHECK-NO-ISEL-LABEL: @crbitsoff
; CHECK-DAG: cmplwi {{[0-9]+}}, 3, 0 ; CHECK-DAG: cmplwi 3, 0
; CHECK-DAG: li [[REG2:[0-9]+]], 1 ; CHECK-DAG: li [[REG2:[0-9]+]], 1
; CHECK-DAG: cntlzw [[REG3:[0-9]+]], ; CHECK-DAG: cntlzw [[REG3:[0-9]+]],
; CHECK: isel [[REG4:[0-9]+]], 0, [[REG2]] ; CHECK: isel [[REG4:[0-9]+]], 0, [[REG2]]
; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]] ; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
; CHECK-NO-ISEL: ori 4, 5, 0 ; CHECK-NO-ISEL: ori 4, 5, 0
; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]] ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NO-ISEL: [[TRUE]] ; CHECK-NO-ISEL: [[TRUE]]
; CHECK-NO-ISEL-NEXT: addi 4, 0, 0 ; CHECK-NO-ISEL-NEXT: addi 4, 0, 0
Show All 27 Lines

llvm/test/CodeGen/PowerPC/ppc-shrink-wrapping.ll

; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 %s -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 %s -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu %s -o - -enable-shrink-wrap=false -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE ; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu %s -o - -enable-shrink-wrap=false -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
; ;
; Note: Lots of tests use inline asm instead of regular calls. ; Note: Lots of tests use inline asm instead of regular calls.
; This allows to have a better control on what the allocation will do. ; This allows to have a better control on what the allocation will do.
; Otherwise, we may have spill right in the entry block, defeating ; Otherwise, we may have spill right in the entry block, defeating
; shrink-wrapping. Moreover, some of the inline asm statement (nop) ; shrink-wrapping. Moreover, some of the inline asm statement (nop)
; are here to ensure that the related paths do not end up as critical ; are here to ensure that the related paths do not end up as critical
; edges. ; edges.
; Initial motivating example: Simple diamond with a call just on one side. ; Initial motivating example: Simple diamond with a call just on one side.
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; ;
; Compare the arguments and return ; Compare the arguments and return
; No prologue needed. ; No prologue needed.
; ENABLE: cmpw 0, 3, 4 ; ENABLE: cmpw 3, 4
; ENABLE-NEXT: bgelr 0 ; ENABLE-NEXT: bgelr 0
; ;
; Prologue code. ; Prologue code.
; At a minimum, we save/restore the link register. Other registers may be saved ; At a minimum, we save/restore the link register. Other registers may be saved
; as well. ; as well.
; CHECK: mflr ; CHECK: mflr
; ;
; Compare the arguments and jump to exit. ; Compare the arguments and jump to exit.
; After the prologue is set. ; After the prologue is set.
; DISABLE: cmpw 0, 3, 4 ; DISABLE: cmpw 3, 4
; DISABLE-NEXT: bge 0, .[[EXIT_LABEL:LBB[0-9_]+]] ; DISABLE-NEXT: bge 0, .[[EXIT_LABEL:LBB[0-9_]+]]
; ;
; Store %a on the stack ; Store %a on the stack
; CHECK: stw 3, {{[0-9]+([0-9]+)}} ; CHECK: stw 3, {{[0-9]+([0-9]+)}}
; Set the alloca address in the second argument. ; Set the alloca address in the second argument.
; CHECK-NEXT: addi 4, 1, {{[0-9]+}} ; CHECK-NEXT: addi 4, 1, {{[0-9]+}}
; Set the first argument to zero. ; Set the first argument to zero.
; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: li 3, 0
Show All 34 Lines
; Check that we do not perform the restore inside the loop whereas the save ; Check that we do not perform the restore inside the loop whereas the save
; is outside. ; is outside.
; CHECK-LABEL: freqSaveAndRestoreOutsideLoop: ; CHECK-LABEL: freqSaveAndRestoreOutsideLoop:
; ;
; Shrink-wrapping allows to skip the prologue in the else case. ; Shrink-wrapping allows to skip the prologue in the else case.
; ENABLE: cmplwi 0, 3, 0 ; ENABLE: cmplwi 3, 0
; ENABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] ; ENABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
; ;
; Prologue code. ; Prologue code.
; Make sure we save the link register ; Make sure we save the link register
; CHECK: mflr {{[0-9]+}} ; CHECK: mflr {{[0-9]+}}
; ;
; DISABLE: cmplwi 0, 3, 0 ; DISABLE: cmplwi 3, 0
; DISABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] ; DISABLE: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
; ;
; Loop preheader ; Loop preheader
; CHECK-DAG: li [[SUM:[0-9]+]], 0 ; CHECK-DAG: li [[SUM:[0-9]+]], 0
; CHECK-DAG: li [[IV:[0-9]+]], 10 ; CHECK-DAG: li [[IV:[0-9]+]], 10
; ;
; Loop body ; Loop body
; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body ; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body
▲ Show 20 Lines • Show All 103 Lines • ▼ Show 20 Linesfor.end: ; preds = %for.body
ret i32 %add ret i32 %add
} }
; Check with a more complex case that we do not have save within the loop and ; Check with a more complex case that we do not have save within the loop and
; restore outside. ; restore outside.
; CHECK-LABEL: loopInfoSaveOutsideLoop: ; CHECK-LABEL: loopInfoSaveOutsideLoop:
; ;
; ENABLE: cmplwi 0, 3, 0 ; ENABLE: cmplwi 3, 0
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] ; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
; ;
; Prologue code. ; Prologue code.
; Make sure we save the link register ; Make sure we save the link register
; CHECK: mflr {{[0-9]+}} ; CHECK: mflr {{[0-9]+}}
; ;
; DISABLE: std ; DISABLE: std
; DISABLE-NEXT: std ; DISABLE-NEXT: std
; DISABLE: cmplwi 0, 3, 0 ; DISABLE: cmplwi 3, 0
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] ; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
; ;
; Loop preheader ; Loop preheader
; CHECK-DAG: li [[SUM:[0-9]+]], 0 ; CHECK-DAG: li [[SUM:[0-9]+]], 0
; CHECK-DAG: li [[IV:[0-9]+]], 10 ; CHECK-DAG: li [[IV:[0-9]+]], 10
; ;
; Loop body ; Loop body
; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body ; CHECK: .[[LOOP:LBB[0-9_]+]]: # %for.body
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
} }
declare void @somethingElse(...) declare void @somethingElse(...)
; Check with a more complex case that we do not have restore within the loop and ; Check with a more complex case that we do not have restore within the loop and
; save outside. ; save outside.
; CHECK-LABEL: loopInfoRestoreOutsideLoop: ; CHECK-LABEL: loopInfoRestoreOutsideLoop:
; ;
; ENABLE: cmplwi 0, 3, 0 ; ENABLE: cmplwi 3, 0
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] ; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
; ;
; Prologue code. ; Prologue code.
; Make sure we save the link register ; Make sure we save the link register
; CHECK: mflr {{[0-9]+}} ; CHECK: mflr {{[0-9]+}}
; ;
; DISABLE: std ; DISABLE: std
; DISABLE-NEXT: std ; DISABLE-NEXT: std
; DISABLE: cmplwi 0, 3, 0 ; DISABLE: cmplwi 3, 0
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] ; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
; ;
; CHECK: bl somethingElse ; CHECK: bl somethingElse
; ;
; Loop preheader ; Loop preheader
; CHECK-DAG: li [[SUM:[0-9]+]], 0 ; CHECK-DAG: li [[SUM:[0-9]+]], 0
; CHECK-DAG: li [[IV:[0-9]+]], 10 ; CHECK-DAG: li [[IV:[0-9]+]], 10
; ;
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
entry: entry:
ret i32 0 ret i32 0
} }
; Check that we handle inline asm correctly. ; Check that we handle inline asm correctly.
; CHECK-LABEL: inlineAsm: ; CHECK-LABEL: inlineAsm:
; ;
; ENABLE: cmplwi 0, 3, 0 ; ENABLE: cmplwi 3, 0
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] ; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
; ;
; Prologue code. ; Prologue code.
; Make sure we save the CSR used in the inline asm: r14 ; Make sure we save the CSR used in the inline asm: r14
; ENABLE-DAG: li [[IV:[0-9]+]], 10 ; ENABLE-DAG: li [[IV:[0-9]+]], 10
; ENABLE-DAG: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill ; ENABLE-DAG: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
; ;
; DISABLE: cmplwi 0, 3, 0 ; DISABLE: cmplwi 3, 0
; DISABLE-NEXT: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill ; DISABLE-NEXT: std 14, -[[STACK_OFFSET:[0-9]+]](1) # 8-byte Folded Spill
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] ; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
; DISABLE: li [[IV:[0-9]+]], 10 ; DISABLE: li [[IV:[0-9]+]], 10
; ;
; CHECK: nop ; CHECK: nop
; CHECK: mtctr [[IV]] ; CHECK: mtctr [[IV]]
; ;
; CHECK: .[[LOOP_LABEL:LBB[0-9_]+]]: # %for.body ; CHECK: .[[LOOP_LABEL:LBB[0-9_]+]]: # %for.body
Show All 40 Linesif.end: ; preds = %for.body, %if.else
%sum.0 = phi i32 [ %mul, %if.else ], [ 0, %for.exit ] %sum.0 = phi i32 [ %mul, %if.else ], [ 0, %for.exit ]
ret i32 %sum.0 ret i32 %sum.0
} }
; Check that we handle calls to variadic functions correctly. ; Check that we handle calls to variadic functions correctly.
; CHECK-LABEL: callVariadicFunc: ; CHECK-LABEL: callVariadicFunc:
; ;
; ENABLE: cmplwi 0, 3, 0 ; ENABLE: cmplwi 3, 0
; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] ; ENABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
; ;
; Prologue code. ; Prologue code.
; CHECK: mflr {{[0-9]+}} ; CHECK: mflr {{[0-9]+}}
; ;
; DISABLE: cmplwi 0, 3, 0 ; DISABLE: cmplwi 3, 0
; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]] ; DISABLE-NEXT: beq 0, .[[ELSE_LABEL:LBB[0-9_]+]]
; ;
; Setup of the varags. ; Setup of the varags.
; CHECK: mr 4, 3 ; CHECK: mr 4, 3
; CHECK-NEXT: mr 5, 3 ; CHECK-NEXT: mr 5, 3
; CHECK-NEXT: mr 6, 3 ; CHECK-NEXT: mr 6, 3
; CHECK-NEXT: mr 7, 3 ; CHECK-NEXT: mr 7, 3
; CHECK-NEXT: mr 8, 3 ; CHECK-NEXT: mr 8, 3
Show All 36 Lines
; Make sure we do not insert unreachable code after noreturn function. ; Make sure we do not insert unreachable code after noreturn function.
; Although this is not incorrect to insert such code, it is useless ; Although this is not incorrect to insert such code, it is useless
; and it hurts the binary size. ; and it hurts the binary size.
; ;
; CHECK-LABEL: noreturn: ; CHECK-LABEL: noreturn:
; DISABLE: mflr {{[0-9]+}} ; DISABLE: mflr {{[0-9]+}}
; ;
; CHECK: cmplwi 0, 3, 0 ; CHECK: cmplwi 3, 0
; CHECK-NEXT: bne{{[-]?}} 0, .[[ABORT:LBB[0-9_]+]] ; CHECK-NEXT: bne{{[-]?}} 0, .[[ABORT:LBB[0-9_]+]]
; ;
; CHECK: li 3, 42 ; CHECK: li 3, 42
; ;
; DISABLE: mtlr {{[0-9]+}} ; DISABLE: mtlr {{[0-9]+}}
; ;
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
▲ Show 20 Lines • Show All 283 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/ppc64-P9-setb.ll

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Linesdefine i64 @setb5(i64 %a, i64 %b) {
%t4 = select i1 %t1, i64 -1, i64 %t3 %t4 = select i1 %t1, i64 -1, i64 %t3
ret i64 %t4 ret i64 %t4
; CHECK-LABEL: setb5: ; CHECK-LABEL: setb5:
; CHECK-NOT: sradi ; CHECK-NOT: sradi
; CHECK-NOT: rldicl ; CHECK-NOT: rldicl
; CHECK-NOT: li ; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb5 ; CHECK-PWR8-LABEL: setb5
; CHECK-PWR8-DAG: sradi ; CHECK-PWR8-DAG: sradi
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li ; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori ; CHECK-PWR8-DAG: xori
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setgt)), setgt
define i64 @setb6(i64 %a, i64 %b) { define i64 @setb6(i64 %a, i64 %b) {
%t1 = icmp sgt i64 %b, %a %t1 = icmp sgt i64 %b, %a
%t2 = icmp sgt i64 %a, %b %t2 = icmp sgt i64 %a, %b
%t3 = zext i1 %t2 to i64 %t3 = zext i1 %t2 to i64
%t4 = select i1 %t1, i64 -1, i64 %t3 %t4 = select i1 %t1, i64 -1, i64 %t3
ret i64 %t4 ret i64 %t4
; CHECK-LABEL: setb6: ; CHECK-LABEL: setb6:
; CHECK-NOT: sradi ; CHECK-NOT: sradi
; CHECK-NOT: rldicl ; CHECK-NOT: rldicl
; CHECK-NOT: li ; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb6 ; CHECK-PWR8-LABEL: setb6
; CHECK-PWR8-DAG: sradi ; CHECK-PWR8-DAG: sradi
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li ; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori ; CHECK-PWR8-DAG: xori
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt ; select_cc lhs, rhs, -1, (zext (setcc rhs, lhs, setlt)), setlt
define i64 @setb7(i64 %a, i64 %b) { define i64 @setb7(i64 %a, i64 %b) {
%t1 = icmp slt i64 %a, %b %t1 = icmp slt i64 %a, %b
%t2 = icmp slt i64 %b, %a %t2 = icmp slt i64 %b, %a
%t3 = zext i1 %t2 to i64 %t3 = zext i1 %t2 to i64
%t4 = select i1 %t1, i64 -1, i64 %t3 %t4 = select i1 %t1, i64 -1, i64 %t3
ret i64 %t4 ret i64 %t4
; CHECK-LABEL: setb7: ; CHECK-LABEL: setb7:
; CHECK-NOT: sradi ; CHECK-NOT: sradi
; CHECK-NOT: rldicl ; CHECK-NOT: rldicl
; CHECK-NOT: li ; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb7 ; CHECK-PWR8-LABEL: setb7
; CHECK-PWR8-DAG: sradi ; CHECK-PWR8-DAG: sradi
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li ; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori ; CHECK-PWR8-DAG: xori
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt ; select_cc lhs, rhs, -1, (zext (setcc lhs, rhs, setlt)), setgt
define i64 @setb8(i64 %a, i64 %b) { define i64 @setb8(i64 %a, i64 %b) {
%t1 = icmp sgt i64 %b, %a %t1 = icmp sgt i64 %b, %a
%t2 = icmp slt i64 %b, %a %t2 = icmp slt i64 %b, %a
%t3 = zext i1 %t2 to i64 %t3 = zext i1 %t2 to i64
%t4 = select i1 %t1, i64 -1, i64 %t3 %t4 = select i1 %t1, i64 -1, i64 %t3
ret i64 %t4 ret i64 %t4
; CHECK-LABEL: setb8: ; CHECK-LABEL: setb8:
; CHECK-NOT: sradi ; CHECK-NOT: sradi
; CHECK-NOT: rldicl ; CHECK-NOT: rldicl
; CHECK-NOT: li ; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb8 ; CHECK-PWR8-LABEL: setb8
; CHECK-PWR8-DAG: sradi ; CHECK-PWR8-DAG: sradi
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li ; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori ; CHECK-PWR8-DAG: xori
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setgt ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setgt
define i64 @setb9(i64 %a, i64 %b) { define i64 @setb9(i64 %a, i64 %b) {
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Linesdefine i64 @setb13(i64 %a, i64 %b) {
%t4 = select i1 %t1, i64 1, i64 %t3 %t4 = select i1 %t1, i64 1, i64 %t3
ret i64 %t4 ret i64 %t4
; CHECK-LABEL: setb13: ; CHECK-LABEL: setb13:
; CHECK-NOT: sradi ; CHECK-NOT: sradi
; CHECK-NOT: rldicl ; CHECK-NOT: rldicl
; CHECK-NOT: li ; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: neg ; CHECK-NOT: neg
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb13 ; CHECK-PWR8-LABEL: setb13
; CHECK-PWR8-DAG: sradi ; CHECK-PWR8-DAG: sradi
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li ; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori ; CHECK-PWR8-DAG: xori
; CHECK-PWR8-DAG: neg ; CHECK-PWR8-DAG: neg
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setlt)), setlt ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setlt)), setlt
define i64 @setb14(i64 %a, i64 %b) { define i64 @setb14(i64 %a, i64 %b) {
%t1 = icmp slt i64 %b, %a %t1 = icmp slt i64 %b, %a
%t2 = icmp slt i64 %a, %b %t2 = icmp slt i64 %a, %b
%t3 = sext i1 %t2 to i64 %t3 = sext i1 %t2 to i64
%t4 = select i1 %t1, i64 1, i64 %t3 %t4 = select i1 %t1, i64 1, i64 %t3
ret i64 %t4 ret i64 %t4
; CHECK-LABEL: setb14: ; CHECK-LABEL: setb14:
; CHECK-NOT: sradi ; CHECK-NOT: sradi
; CHECK-NOT: rldicl ; CHECK-NOT: rldicl
; CHECK-NOT: li ; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: neg ; CHECK-NOT: neg
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb14 ; CHECK-PWR8-LABEL: setb14
; CHECK-PWR8-DAG: sradi ; CHECK-PWR8-DAG: sradi
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li ; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori ; CHECK-PWR8-DAG: xori
; CHECK-PWR8-DAG: neg ; CHECK-PWR8-DAG: neg
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setgt)), setgt ; select_cc lhs, rhs, 1, (sext (setcc rhs, lhs, setgt)), setgt
define i64 @setb15(i64 %a, i64 %b) { define i64 @setb15(i64 %a, i64 %b) {
%t1 = icmp sgt i64 %a, %b %t1 = icmp sgt i64 %a, %b
%t2 = icmp sgt i64 %b, %a %t2 = icmp sgt i64 %b, %a
%t3 = sext i1 %t2 to i64 %t3 = sext i1 %t2 to i64
%t4 = select i1 %t1, i64 1, i64 %t3 %t4 = select i1 %t1, i64 1, i64 %t3
ret i64 %t4 ret i64 %t4
; CHECK-LABEL: setb15: ; CHECK-LABEL: setb15:
; CHECK-NOT: sradi ; CHECK-NOT: sradi
; CHECK-NOT: rldicl ; CHECK-NOT: rldicl
; CHECK-NOT: li ; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: neg ; CHECK-NOT: neg
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb15 ; CHECK-PWR8-LABEL: setb15
; CHECK-PWR8-DAG: sradi ; CHECK-PWR8-DAG: sradi
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li ; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori ; CHECK-PWR8-DAG: xori
; CHECK-PWR8-DAG: neg ; CHECK-PWR8-DAG: neg
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setlt ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setgt)), setlt
define i64 @setb16(i64 %a, i64 %b) { define i64 @setb16(i64 %a, i64 %b) {
%t1 = icmp slt i64 %b, %a %t1 = icmp slt i64 %b, %a
%t2 = icmp sgt i64 %b, %a %t2 = icmp sgt i64 %b, %a
%t3 = sext i1 %t2 to i64 %t3 = sext i1 %t2 to i64
%t4 = select i1 %t1, i64 1, i64 %t3 %t4 = select i1 %t1, i64 1, i64 %t3
ret i64 %t4 ret i64 %t4
; CHECK-LABEL: setb16: ; CHECK-LABEL: setb16:
; CHECK-NOT: sradi ; CHECK-NOT: sradi
; CHECK-NOT: rldicl ; CHECK-NOT: rldicl
; CHECK-NOT: li ; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: neg ; CHECK-NOT: neg
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb16 ; CHECK-PWR8-LABEL: setb16
; CHECK-PWR8-DAG: sradi ; CHECK-PWR8-DAG: sradi
; CHECK-PWR8-DAG: rldicl ; CHECK-PWR8-DAG: rldicl
; CHECK-PWR8-DAG: li ; CHECK-PWR8-DAG: li
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8-DAG: xori ; CHECK-PWR8-DAG: xori
; CHECK-PWR8-DAG: neg ; CHECK-PWR8-DAG: neg
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
; select_cc lhs, rhs, 0, (select_cc lhs, rhs, 1, -1, setgt), seteq ; select_cc lhs, rhs, 0, (select_cc lhs, rhs, 1, -1, setgt), seteq
▲ Show 20 Lines • Show All 298 Lines • ▼ Show 20 Linesdefine i64 @setb29(i64 %a, i64 %b) {
%t5 = zext i8 %t4 to i64 %t5 = zext i8 %t4 to i64
ret i64 %t5 ret i64 %t5
; CHECK-LABEL: setb29: ; CHECK-LABEL: setb29:
; CHECK-NOT: sradi ; CHECK-NOT: sradi
; CHECK-NOT: rldicl ; CHECK-NOT: rldicl
; CHECK-NOT: li ; CHECK-NOT: li
; CHECK: cmpd {{c?r?(0, )?}}r3, r4 ; CHECK: cmpd {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc ; CHECK-NOT: subc
; CHECK-NOT: adde ; CHECK-NOT: adde
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setb29 ; CHECK-PWR8-LABEL: setb29
; CHECK-PWR8-DAG: cmpd ; CHECK-PWR8-DAG: cmpd
; CHECK-PWR8-DAG: subfc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: adde ; CHECK-PWR8-DAG: adde
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
; Testings to cover different comparison opcodes ; Testings to cover different comparison opcodes
; Test with integer type i32/i16/i8 for input parameter ; Test with integer type i32/i16/i8 for input parameter
▲ Show 20 Lines • Show All 220 Lines • ▼ Show 20 Linesdefine i64 @setbud1(i64 %a, i64 %b) {
%t2 = icmp ult i64 %b, %a %t2 = icmp ult i64 %b, %a
%t3 = zext i1 %t2 to i64 %t3 = zext i1 %t2 to i64
%t4 = select i1 %t1, i64 -1, i64 %t3 %t4 = select i1 %t1, i64 -1, i64 %t3
ret i64 %t4 ret i64 %t4
; CHECK-LABEL: setbud1: ; CHECK-LABEL: setbud1:
; CHECK-NOT: li ; CHECK-NOT: li
; CHECK: cmpld {{c?r?(0, )?}}r3, r4 ; CHECK: cmpld {{c?r?(0, )?}}r3, r4
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: subfc ; CHECK-NOT: subc
; CHECK-NOT: subfe ; CHECK-NOT: subfe
; CHECK-NOT: neg ; CHECK-NOT: neg
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setbud1 ; CHECK-PWR8-LABEL: setbud1
; CHECK-PWR8-DAG: subfc ; CHECK-PWR8-DAG: subc
; CHECK-PWR8-DAG: subfe ; CHECK-PWR8-DAG: subfe
; CHECK-PWR8-DAG: cmpld ; CHECK-PWR8-DAG: cmpld
; CHECK-PWR8-DAG: neg ; CHECK-PWR8-DAG: neg
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setugt ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setugt
▲ Show 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setult ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setne)), setult
define i64 @setbuh(i16 %a, i16 %b) { define i64 @setbuh(i16 %a, i16 %b) {
%t1 = icmp ult i16 %b, %a %t1 = icmp ult i16 %b, %a
%t2 = icmp ne i16 %b, %a %t2 = icmp ne i16 %b, %a
%t3 = sext i1 %t2 to i64 %t3 = sext i1 %t2 to i64
%t4 = select i1 %t1, i64 1, i64 %t3 %t4 = select i1 %t1, i64 1, i64 %t3
ret i64 %t4 ret i64 %t4
; CHECK-LABEL: setbuh: ; CHECK-LABEL: setbuh:
; CHECK-DAG: rlwinm [[RA:r[0-9]+]], r3, 0, 16, 31 ; CHECK-DAG: clrlwi [[RA:r[0-9]+]], r3, 16
; CHECK-DAG: rlwinm [[RB:r[0-9]+]], r4, 0, 16, 31 ; CHECK-DAG: clrlwi [[RB:r[0-9]+]], r4, 16
; CHECK-NOT: li ; CHECK-NOT: li
; CHECK-NOT: xor ; CHECK-NOT: xor
; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]] ; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]]
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: cntlzw ; CHECK-NOT: cntlzw
; CHECK-NOT: srwi ; CHECK-NOT: srwi
; CHECK-NOT: xori ; CHECK-NOT: xori
; CHECK-NOT: neg ; CHECK-NOT: neg
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setbuh ; CHECK-PWR8-LABEL: setbuh
; CHECK-PWR8: rlwinm ; CHECK-PWR8: clrlwi
; CHECK-PWR8: rlwinm ; CHECK-PWR8: clrlwi
; CHECK-PWR8-DAG: cmplw ; CHECK-PWR8-DAG: cmplw
; CHECK-PWR8-DAG: cntlzw ; CHECK-PWR8-DAG: cntlzw
; CHECK-PWR8: srwi ; CHECK-PWR8: srwi
; CHECK-PWR8: xori ; CHECK-PWR8: xori
; CHECK-PWR8: neg ; CHECK-PWR8: neg
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setult)), setugt ; select_cc lhs, rhs, 1, (sext (setcc lhs, rhs, setult)), setugt
define i64 @setbuc(i8 %a, i8 %b) { define i64 @setbuc(i8 %a, i8 %b) {
%t1 = icmp ugt i8 %a, %b %t1 = icmp ugt i8 %a, %b
%t2 = icmp ult i8 %a, %b %t2 = icmp ult i8 %a, %b
%t3 = sext i1 %t2 to i64 %t3 = sext i1 %t2 to i64
%t4 = select i1 %t1, i64 1, i64 %t3 %t4 = select i1 %t1, i64 1, i64 %t3
ret i64 %t4 ret i64 %t4
; CHECK-LABEL: setbuc: ; CHECK-LABEL: setbuc:
; CHECK-DAG: rlwinm [[RA:r[0-9]+]], r3, 0, 24, 31 ; CHECK-DAG: clrlwi [[RA:r[0-9]+]], r3, 24
; CHECK-DAG: rlwinm [[RB:r[0-9]+]], r4, 0, 24, 31 ; CHECK-DAG: clrlwi [[RB:r[0-9]+]], r4, 24
; CHECK-NOT: li ; CHECK-NOT: li
; CHECK-NOT: clrldi ; CHECK-NOT: clrldi
; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]] ; CHECK: cmplw {{c?r?(0, )?}}[[RA]], [[RB]]
; CHECK-NEXT: setb r3, cr0 ; CHECK-NEXT: setb r3, cr0
; CHECK-NOT: sub ; CHECK-NOT: sub
; CHECK-NOT: sradi ; CHECK-NOT: sradi
; CHECK-NOT: isel ; CHECK-NOT: isel
; CHECK: blr ; CHECK: blr
; CHECK-PWR8-LABEL: setbuc ; CHECK-PWR8-LABEL: setbuc
; CHECK-PWR8: rlwinm ; CHECK-PWR8: clrlwi
; CHECK-PWR8: rlwinm ; CHECK-PWR8: clrlwi
; CHECK-PWR8-DAG: clrldi ; CHECK-PWR8-DAG: clrldi
; CHECK-PWR8-DAG: clrldi ; CHECK-PWR8-DAG: clrldi
; CHECK-PWR8-DAG: cmplw ; CHECK-PWR8-DAG: cmplw
; CHECK-PWR8: sradi ; CHECK-PWR8: sradi
; CHECK-PWR8: isel ; CHECK-PWR8: isel
; CHECK-PWR8: blr ; CHECK-PWR8: blr
} }
▲ Show 20 Lines • Show All 137 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/pr25080.ll

Show All 12 Lines
; LE-NEXT: xxland 35, 35, 36 ; LE-NEXT: xxland 35, 35, 36
; LE-NEXT: vcmpequw 2, 2, 5 ; LE-NEXT: vcmpequw 2, 2, 5
; LE-NEXT: vcmpequw 3, 3, 5 ; LE-NEXT: vcmpequw 3, 3, 5
; LE-NEXT: xxswapd 0, 34 ; LE-NEXT: xxswapd 0, 34
; LE-NEXT: mfvsrwz 3, 34 ; LE-NEXT: mfvsrwz 3, 34
; LE-NEXT: xxsldwi 1, 34, 34, 1 ; LE-NEXT: xxsldwi 1, 34, 34, 1
; LE-NEXT: mfvsrwz 4, 35 ; LE-NEXT: mfvsrwz 4, 35
; LE-NEXT: xxsldwi 4, 34, 34, 3 ; LE-NEXT: xxsldwi 4, 34, 34, 3
; LE-NEXT: mtvsrd 2, 3 ; LE-NEXT: mtfprd 2, 3
; LE-NEXT: mfvsrwz 3, 0 ; LE-NEXT: mffprwz 3, 0
; LE-NEXT: xxswapd 0, 35 ; LE-NEXT: xxswapd 0, 35
; LE-NEXT: mtvsrd 3, 4 ; LE-NEXT: mtfprd 3, 4
; LE-NEXT: xxsldwi 5, 35, 35, 1 ; LE-NEXT: xxsldwi 5, 35, 35, 1
; LE-NEXT: mfvsrwz 4, 1 ; LE-NEXT: mffprwz 4, 1
; LE-NEXT: xxsldwi 7, 35, 35, 3 ; LE-NEXT: xxsldwi 7, 35, 35, 3
; LE-NEXT: mtvsrd 1, 3 ; LE-NEXT: mtfprd 1, 3
; LE-NEXT: xxswapd 33, 3 ; LE-NEXT: xxswapd 33, 3
; LE-NEXT: mfvsrwz 3, 4 ; LE-NEXT: mffprwz 3, 4
; LE-NEXT: mtvsrd 4, 4 ; LE-NEXT: mtfprd 4, 4
; LE-NEXT: xxswapd 34, 1 ; LE-NEXT: xxswapd 34, 1
; LE-NEXT: mfvsrwz 4, 0 ; LE-NEXT: mffprwz 4, 0
; LE-NEXT: mtvsrd 0, 3 ; LE-NEXT: mtfprd 0, 3
; LE-NEXT: xxswapd 35, 4 ; LE-NEXT: xxswapd 35, 4
; LE-NEXT: mfvsrwz 3, 5 ; LE-NEXT: mffprwz 3, 5
; LE-NEXT: mtvsrd 6, 4 ; LE-NEXT: mtfprd 6, 4
; LE-NEXT: xxswapd 36, 0 ; LE-NEXT: xxswapd 36, 0
; LE-NEXT: mtvsrd 1, 3 ; LE-NEXT: mtfprd 1, 3
; LE-NEXT: mfvsrwz 3, 7 ; LE-NEXT: mffprwz 3, 7
; LE-NEXT: xxswapd 37, 6 ; LE-NEXT: xxswapd 37, 6
; LE-NEXT: vmrglh 2, 3, 2 ; LE-NEXT: vmrglh 2, 3, 2
; LE-NEXT: xxswapd 35, 2 ; LE-NEXT: xxswapd 35, 2
; LE-NEXT: mtvsrd 2, 3 ; LE-NEXT: mtfprd 2, 3
; LE-NEXT: xxswapd 32, 1 ; LE-NEXT: xxswapd 32, 1
; LE-NEXT: addis 3, 2, .LCPI0_1@toc@ha ; LE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
; LE-NEXT: addi 3, 3, .LCPI0_1@toc@l ; LE-NEXT: addi 3, 3, .LCPI0_1@toc@l
; LE-NEXT: xxswapd 38, 2 ; LE-NEXT: xxswapd 38, 2
; LE-NEXT: vmrglh 3, 4, 3 ; LE-NEXT: vmrglh 3, 4, 3
; LE-NEXT: vmrglh 4, 0, 5 ; LE-NEXT: vmrglh 4, 0, 5
; LE-NEXT: vmrglh 5, 6, 1 ; LE-NEXT: vmrglh 5, 6, 1
; LE-NEXT: vmrglw 2, 3, 2 ; LE-NEXT: vmrglw 2, 3, 2
Show All 15 Lines
; BE-NEXT: xxland 35, 35, 0 ; BE-NEXT: xxland 35, 35, 0
; BE-NEXT: xxland 34, 34, 0 ; BE-NEXT: xxland 34, 34, 0
; BE-NEXT: vcmpequw 3, 3, 4 ; BE-NEXT: vcmpequw 3, 3, 4
; BE-NEXT: vcmpequw 2, 2, 4 ; BE-NEXT: vcmpequw 2, 2, 4
; BE-NEXT: xxswapd 0, 35 ; BE-NEXT: xxswapd 0, 35
; BE-NEXT: mfvsrwz 3, 35 ; BE-NEXT: mfvsrwz 3, 35
; BE-NEXT: xxsldwi 1, 35, 35, 1 ; BE-NEXT: xxsldwi 1, 35, 35, 1
; BE-NEXT: sldi 3, 3, 48 ; BE-NEXT: sldi 3, 3, 48
; BE-NEXT: mfvsrwz 4, 0 ; BE-NEXT: mffprwz 4, 0
; BE-NEXT: xxsldwi 0, 35, 35, 3 ; BE-NEXT: xxsldwi 0, 35, 35, 3
; BE-NEXT: mtvsrd 36, 3 ; BE-NEXT: mtvsrd 36, 3
; BE-NEXT: mfvsrwz 3, 1 ; BE-NEXT: mffprwz 3, 1
; BE-NEXT: sldi 4, 4, 48 ; BE-NEXT: sldi 4, 4, 48
; BE-NEXT: xxswapd 1, 34 ; BE-NEXT: xxswapd 1, 34
; BE-NEXT: mtvsrd 35, 4 ; BE-NEXT: mtvsrd 35, 4
; BE-NEXT: mfvsrwz 4, 34 ; BE-NEXT: mfvsrwz 4, 34
; BE-NEXT: sldi 3, 3, 48 ; BE-NEXT: sldi 3, 3, 48
; BE-NEXT: mtvsrd 37, 3 ; BE-NEXT: mtvsrd 37, 3
; BE-NEXT: mfvsrwz 3, 0 ; BE-NEXT: mffprwz 3, 0
; BE-NEXT: sldi 4, 4, 48 ; BE-NEXT: sldi 4, 4, 48
; BE-NEXT: xxsldwi 0, 34, 34, 1 ; BE-NEXT: xxsldwi 0, 34, 34, 1
; BE-NEXT: vmrghh 3, 5, 3 ; BE-NEXT: vmrghh 3, 5, 3
; BE-NEXT: mtvsrd 37, 4 ; BE-NEXT: mtvsrd 37, 4
; BE-NEXT: sldi 3, 3, 48 ; BE-NEXT: sldi 3, 3, 48
; BE-NEXT: mfvsrwz 4, 1 ; BE-NEXT: mffprwz 4, 1
; BE-NEXT: xxsldwi 1, 34, 34, 3 ; BE-NEXT: xxsldwi 1, 34, 34, 3
; BE-NEXT: mtvsrd 34, 3 ; BE-NEXT: mtvsrd 34, 3
; BE-NEXT: mfvsrwz 3, 0 ; BE-NEXT: mffprwz 3, 0
; BE-NEXT: sldi 4, 4, 48 ; BE-NEXT: sldi 4, 4, 48
; BE-NEXT: mtvsrd 32, 4 ; BE-NEXT: mtvsrd 32, 4
; BE-NEXT: mfvsrwz 4, 1 ; BE-NEXT: mffprwz 4, 1
; BE-NEXT: sldi 3, 3, 48 ; BE-NEXT: sldi 3, 3, 48
; BE-NEXT: mtvsrd 33, 3 ; BE-NEXT: mtvsrd 33, 3
; BE-NEXT: sldi 3, 4, 48 ; BE-NEXT: sldi 3, 4, 48
; BE-NEXT: vmrghh 2, 2, 4 ; BE-NEXT: vmrghh 2, 2, 4
; BE-NEXT: mtvsrd 36, 3 ; BE-NEXT: mtvsrd 36, 3
; BE-NEXT: addis 3, 2, .LCPI0_1@toc@ha ; BE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
; BE-NEXT: vmrghh 0, 1, 0 ; BE-NEXT: vmrghh 0, 1, 0
; BE-NEXT: addi 3, 3, .LCPI0_1@toc@l ; BE-NEXT: addi 3, 3, .LCPI0_1@toc@l
Show All 17 Lines

llvm/test/CodeGen/PowerPC/pr33093.ll

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Lines
; CHECK-NEXT: sldi 6, 3, 4 ; CHECK-NEXT: sldi 6, 3, 4
; CHECK-NEXT: ori 5, 5, 61680 ; CHECK-NEXT: ori 5, 5, 61680
; CHECK-NEXT: ori 4, 4, 3855 ; CHECK-NEXT: ori 4, 4, 3855
; CHECK-NEXT: rldicl 3, 3, 60, 4 ; CHECK-NEXT: rldicl 3, 3, 60, 4
; CHECK-NEXT: and 5, 6, 5 ; CHECK-NEXT: and 5, 6, 5
; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: or 3, 3, 5 ; CHECK-NEXT: or 3, 3, 5
; CHECK-NEXT: rldicl 4, 3, 32, 32 ; CHECK-NEXT: rldicl 4, 3, 32, 32
; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31 ; CHECK-NEXT: rotlwi 5, 3, 24
; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31 ; CHECK-NEXT: rotlwi 6, 4, 24
; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15 ; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31 ; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15 ; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31 ; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31
; CHECK-NEXT: sldi 3, 5, 32 ; CHECK-NEXT: sldi 3, 5, 32
; CHECK-NEXT: or 3, 3, 6 ; CHECK-NEXT: or 3, 3, 6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
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llvm/test/CodeGen/PowerPC/pr35688.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -enable-mssa-loop-dependency=false -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | \ ; RUN: llc -enable-mssa-loop-dependency=false -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | \
; RUN: FileCheck %s ; RUN: FileCheck %s
; RUN: llc -enable-mssa-loop-dependency=true -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | \ ; RUN: llc -enable-mssa-loop-dependency=true -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | \
; RUN: FileCheck %s --check-prefix=MSSA ; RUN: FileCheck %s --check-prefix=MSSA
; Function Attrs: nounwind ; Function Attrs: nounwind
define void @ec_GFp_nistp256_points_mul() { define void @ec_GFp_nistp256_points_mul() {
; CHECK-LABEL: ec_GFp_nistp256_points_mul: ; CHECK-LABEL: ec_GFp_nistp256_points_mul:
; CHECK: ld 5, 0(3) ; CHECK: ld 5, 0(3)
; CHECK: li 3, 127 ; CHECK: li 3, 127
; CHECK: li 4, 0 ; CHECK: li 4, 0
; CHECK: subfic 6, 5, 0 ; CHECK: subfic 6, 5, 0
; CHECK: subfze 6, 4 ; CHECK: subfze 6, 4
; CHECK: sradi 7, 6, 63 ; CHECK: sradi 7, 6, 63
; CHECK: srad 6, 6, 3 ; CHECK: srad 6, 6, 3
; CHECK: subfc 5, 5, 7 ; CHECK: subc 5, 7, 5
; CHECK: subfe 5, 4, 6 ; CHECK: subfe 5, 4, 6
; CHECK: sradi 5, 5, 63 ; CHECK: sradi 5, 5, 63
; With MemorySSA, everything is taken out of the loop by licm. ; With MemorySSA, everything is taken out of the loop by licm.
; Loads and stores to undef are treated as non-aliasing. ; Loads and stores to undef are treated as non-aliasing.
; MSSA-LABEL: ec_GFp_nistp256_points_mul ; MSSA-LABEL: ec_GFp_nistp256_points_mul
; MSSA: ld 3, 0(3) ; MSSA: ld 3, 0(3)
; MSSA: li 4, 0 ; MSSA: li 4, 0
; MSSA: subfic 5, 3, 0 ; MSSA: subfic 5, 3, 0
; MSSA: subfze 5, 4 ; MSSA: subfze 5, 4
; MSSA: sradi 5, 5, 63 ; MSSA: sradi 5, 5, 63
; MSSA: subfc 3, 3, 5 ; MSSA: subc 3, 5, 3
; MSSA: subfe 3, 4, 5 ; MSSA: subfe 3, 4, 5
; MSSA: sradi 3, 3, 63 ; MSSA: sradi 3, 3, 63
; MSSA: std 3, 0(3) ; MSSA: std 3, 0(3)
entry: entry:
br label %fe_cmovznz.exit.i534.i.15 br label %fe_cmovznz.exit.i534.i.15
fe_cmovznz.exit.i534.i.15: ; preds = %fe_cmovznz.exit.i534.i.15, %entry fe_cmovznz.exit.i534.i.15: ; preds = %fe_cmovznz.exit.i534.i.15, %entry
%0 = load i64, i64* undef, align 8 %0 = load i64, i64* undef, align 8
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llvm/test/CodeGen/PowerPC/pr45448.ll

Show All 20 Lines
; CHECK-NEXT: .LBB0_7: # %L670 ; CHECK-NEXT: .LBB0_7: # %L670
; CHECK-NEXT: lis r5, 4095 ; CHECK-NEXT: lis r5, 4095
; CHECK-NEXT: ori r5, r5, 65533 ; CHECK-NEXT: ori r5, r5, 65533
; CHECK-NEXT: sldi r5, r5, 4 ; CHECK-NEXT: sldi r5, r5, 4
; CHECK-NEXT: cmpdi r3, 0 ; CHECK-NEXT: cmpdi r3, 0
; CHECK-NEXT: sradi r4, r3, 63 ; CHECK-NEXT: sradi r4, r3, 63
; CHECK-NEXT: mulhdu r3, r3, r5 ; CHECK-NEXT: mulhdu r3, r3, r5
; CHECK-NEXT: maddld r6, r4, r5, r3 ; CHECK-NEXT: maddld r6, r4, r5, r3
; CHECK-NEXT: crnor 4*cr5+gt, eq, eq ; CHECK-NEXT: crnot 4*cr5+gt, eq
; CHECK-NEXT: cmpld r6, r3 ; CHECK-NEXT: cmpld r6, r3
; CHECK-NEXT: mulld r3, r4, r5 ; CHECK-NEXT: mulld r3, r4, r5
; CHECK-NEXT: cmpldi cr1, r3, 0 ; CHECK-NEXT: cmpldi cr1, r3, 0
; CHECK-NEXT: crandc 4*cr5+lt, lt, 4*cr1+eq ; CHECK-NEXT: crandc 4*cr5+lt, lt, 4*cr1+eq
; CHECK-NEXT: mulhdu. r3, r4, r5 ; CHECK-NEXT: mulhdu. r3, r4, r5
; CHECK-NEXT: bc 4, 4*cr5+gt, .LBB0_10 ; CHECK-NEXT: bc 4, 4*cr5+gt, .LBB0_10
; CHECK-NEXT: # %bb.8: # %L670 ; CHECK-NEXT: # %bb.8: # %L670
; CHECK-NEXT: crorc 4*cr5+lt, 4*cr5+lt, eq ; CHECK-NEXT: crorc 4*cr5+lt, 4*cr5+lt, eq
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llvm/test/CodeGen/PowerPC/pre-inc-disable.ll

Show First 20 Lines • Show All 355 Lines • ▼ Show 20 Lines
; CHECK-LABEL: test16: ; CHECK-LABEL: test16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sldi r4, r4, 1 ; CHECK-NEXT: sldi r4, r4, 1
; CHECK-NEXT: add r6, r3, r4 ; CHECK-NEXT: add r6, r3, r4
; CHECK-NEXT: li r7, 16 ; CHECK-NEXT: li r7, 16
; CHECK-NEXT: lxsihzx v2, r6, r7 ; CHECK-NEXT: lxsihzx v2, r6, r7
; CHECK-NEXT: lxsihzx v4, r3, r4 ; CHECK-NEXT: lxsihzx v4, r3, r4
; CHECK-NEXT: li r6, 0 ; CHECK-NEXT: li r6, 0
; CHECK-NEXT: mtvsrd f0, r6 ; CHECK-NEXT: mtfprd f0, r6
; CHECK-NEXT: vsplth v4, v4, 3 ; CHECK-NEXT: vsplth v4, v4, 3
; CHECK-NEXT: xxswapd v3, vs0 ; CHECK-NEXT: xxswapd v3, vs0
; CHECK-NEXT: vsplth v2, v2, 3 ; CHECK-NEXT: vsplth v2, v2, 3
; CHECK-NEXT: addis r3, r2, .LCPI3_0@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI3_0@toc@ha
; CHECK-NEXT: addi r3, r3, .LCPI3_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI3_0@toc@l
; CHECK-NEXT: vmrglh v2, v3, v2 ; CHECK-NEXT: vmrglh v2, v3, v2
; CHECK-NEXT: vmrglh v3, v3, v4 ; CHECK-NEXT: vmrglh v3, v3, v4
; CHECK-NEXT: xxlxor v4, v4, v4 ; CHECK-NEXT: xxlxor v4, v4, v4
; CHECK-NEXT: vmrglw v3, v3, v4 ; CHECK-NEXT: vmrglw v3, v3, v4
; CHECK-NEXT: lxvx v4, 0, r3 ; CHECK-NEXT: lxvx v4, 0, r3
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: vperm v2, v2, v3, v4 ; CHECK-NEXT: vperm v2, v2, v3, v4
; CHECK-NEXT: xxspltw v3, v2, 2 ; CHECK-NEXT: xxspltw v3, v2, 2
; CHECK-NEXT: vadduwm v2, v2, v3 ; CHECK-NEXT: vadduwm v2, v2, v3
; CHECK-NEXT: vextuwrx r3, r3, v2 ; CHECK-NEXT: vextuwrx r3, r3, v2
; CHECK-NEXT: cmpw cr0, r3, r5 ; CHECK-NEXT: cmpw r3, r5
; CHECK-NEXT: bgelr+ cr0 ; CHECK-NEXT: bgelr+ cr0
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; ;
; P9BE-LABEL: test16: ; P9BE-LABEL: test16:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: sldi r4, r4, 1 ; P9BE-NEXT: sldi r4, r4, 1
; P9BE-NEXT: add r6, r3, r4 ; P9BE-NEXT: add r6, r3, r4
; P9BE-NEXT: li r7, 16 ; P9BE-NEXT: li r7, 16
Show All 11 Lines
; P9BE-NEXT: vsplth v3, v3, 0 ; P9BE-NEXT: vsplth v3, v3, 0
; P9BE-NEXT: vmrghw v3, v3, v4 ; P9BE-NEXT: vmrghw v3, v3, v4
; P9BE-NEXT: lxvx v4, 0, r3 ; P9BE-NEXT: lxvx v4, 0, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vperm v2, v3, v2, v4 ; P9BE-NEXT: vperm v2, v3, v2, v4
; P9BE-NEXT: xxspltw v3, v2, 1 ; P9BE-NEXT: xxspltw v3, v2, 1
; P9BE-NEXT: vadduwm v2, v2, v3 ; P9BE-NEXT: vadduwm v2, v2, v3
; P9BE-NEXT: vextuwlx r3, r3, v2 ; P9BE-NEXT: vextuwlx r3, r3, v2
; P9BE-NEXT: cmpw cr0, r3, r5 ; P9BE-NEXT: cmpw r3, r5
; P9BE-NEXT: bgelr+ cr0 ; P9BE-NEXT: bgelr+ cr0
; P9BE-NEXT: # %bb.1: # %if.then ; P9BE-NEXT: # %bb.1: # %if.then
entry: entry:
%idxprom = sext i32 %delta to i64 %idxprom = sext i32 %delta to i64
%add14 = add nsw i32 %delta, 8 %add14 = add nsw i32 %delta, 8
%idxprom15 = sext i32 %add14 to i64 %idxprom15 = sext i32 %add14 to i64
br label %for.body br label %for.body
Show All 24 Lines
} }
define void @test8(i8* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) { define void @test8(i8* nocapture readonly %sums, i32 signext %delta, i32 signext %thresh) {
; CHECK-LABEL: test8: ; CHECK-LABEL: test8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: add r6, r3, r4 ; CHECK-NEXT: add r6, r3, r4
; CHECK-NEXT: lxsibzx v2, r3, r4 ; CHECK-NEXT: lxsibzx v2, r3, r4
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: mtvsrd f0, r3 ; CHECK-NEXT: mtfprd f0, r3
; CHECK-NEXT: li r3, 8 ; CHECK-NEXT: li r3, 8
; CHECK-NEXT: lxsibzx v5, r6, r3 ; CHECK-NEXT: lxsibzx v5, r6, r3
; CHECK-NEXT: xxswapd v3, vs0 ; CHECK-NEXT: xxswapd v3, vs0
; CHECK-NEXT: vspltb v4, v3, 15 ; CHECK-NEXT: vspltb v4, v3, 15
; CHECK-NEXT: vspltb v2, v2, 7 ; CHECK-NEXT: vspltb v2, v2, 7
; CHECK-NEXT: vmrglb v2, v3, v2 ; CHECK-NEXT: vmrglb v2, v3, v2
; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha ; CHECK-NEXT: addis r3, r2, .LCPI4_0@toc@ha
; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l ; CHECK-NEXT: addi r3, r3, .LCPI4_0@toc@l
; CHECK-NEXT: vspltb v5, v5, 7 ; CHECK-NEXT: vspltb v5, v5, 7
; CHECK-NEXT: vmrglh v2, v2, v4 ; CHECK-NEXT: vmrglh v2, v2, v4
; CHECK-NEXT: vmrglb v3, v3, v5 ; CHECK-NEXT: vmrglb v3, v3, v5
; CHECK-NEXT: vmrglw v2, v2, v4 ; CHECK-NEXT: vmrglw v2, v2, v4
; CHECK-NEXT: vmrglh v3, v3, v4 ; CHECK-NEXT: vmrglh v3, v3, v4
; CHECK-NEXT: vmrglw v3, v4, v3 ; CHECK-NEXT: vmrglw v3, v4, v3
; CHECK-NEXT: lxvx v4, 0, r3 ; CHECK-NEXT: lxvx v4, 0, r3
; CHECK-NEXT: li r3, 0 ; CHECK-NEXT: li r3, 0
; CHECK-NEXT: vperm v2, v3, v2, v4 ; CHECK-NEXT: vperm v2, v3, v2, v4
; CHECK-NEXT: xxspltw v3, v2, 2 ; CHECK-NEXT: xxspltw v3, v2, 2
; CHECK-NEXT: vadduwm v2, v2, v3 ; CHECK-NEXT: vadduwm v2, v2, v3
; CHECK-NEXT: vextuwrx r3, r3, v2 ; CHECK-NEXT: vextuwrx r3, r3, v2
; CHECK-NEXT: cmpw cr0, r3, r5 ; CHECK-NEXT: cmpw r3, r5
; CHECK-NEXT: bgelr+ cr0 ; CHECK-NEXT: bgelr+ cr0
; CHECK-NEXT: # %bb.1: # %if.then ; CHECK-NEXT: # %bb.1: # %if.then
; ;
; P9BE-LABEL: test8: ; P9BE-LABEL: test8:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: add r6, r3, r4 ; P9BE-NEXT: add r6, r3, r4
; P9BE-NEXT: li r7, 8 ; P9BE-NEXT: li r7, 8
; P9BE-NEXT: lxsibzx v2, r6, r7 ; P9BE-NEXT: lxsibzx v2, r6, r7
Show All 12 Lines
; P9BE-NEXT: xxspltw v3, v3, 0 ; P9BE-NEXT: xxspltw v3, v3, 0
; P9BE-NEXT: vmrghw v2, v4, v2 ; P9BE-NEXT: vmrghw v2, v4, v2
; P9BE-NEXT: lxvx v4, 0, r3 ; P9BE-NEXT: lxvx v4, 0, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vperm v2, v3, v2, v4 ; P9BE-NEXT: vperm v2, v3, v2, v4
; P9BE-NEXT: xxspltw v3, v2, 1 ; P9BE-NEXT: xxspltw v3, v2, 1
; P9BE-NEXT: vadduwm v2, v2, v3 ; P9BE-NEXT: vadduwm v2, v2, v3
; P9BE-NEXT: vextuwlx r3, r3, v2 ; P9BE-NEXT: vextuwlx r3, r3, v2
; P9BE-NEXT: cmpw cr0, r3, r5 ; P9BE-NEXT: cmpw r3, r5
; P9BE-NEXT: bgelr+ cr0 ; P9BE-NEXT: bgelr+ cr0
; P9BE-NEXT: # %bb.1: # %if.then ; P9BE-NEXT: # %bb.1: # %if.then
entry: entry:
%idxprom = sext i32 %delta to i64 %idxprom = sext i32 %delta to i64
%add14 = add nsw i32 %delta, 8 %add14 = add nsw i32 %delta, 8
%idxprom15 = sext i32 %add14 to i64 %idxprom15 = sext i32 %add14 to i64
br label %for.body br label %for.body
Show All 25 Lines

llvm/test/CodeGen/PowerPC/qpx-s-sel.ll

Show First 20 Lines • Show All 50 Lines • ▼ Show 20 Lines
; CHECK-LABEL: @test4 ; CHECK-LABEL: @test4
; CHECK-DAG: lbz ; CHECK-DAG: lbz
; CHECK-DAG: qvlfdx [[REG1:[0-9]+]], ; CHECK-DAG: qvlfdx [[REG1:[0-9]+]],
; CHECK-DAG: stw ; CHECK-DAG: stw
; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]], ; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]] ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]] ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]]
; CHECK: qvflogical 1, 1, [[REG4]], 1 ; CHECK: qvfand 1, 1, [[REG4]]
; CHECK: blr ; CHECK: blr
} }
define void @test5(<4 x i1> %a) nounwind { define void @test5(<4 x i1> %a) nounwind {
entry: entry:
store <4 x i1> %a, <4 x i1>* @R store <4 x i1> %a, <4 x i1>* @R
ret void ret void
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llvm/test/CodeGen/PowerPC/qpx-sel.ll

Show First 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; CHECK-LABEL: @test4 ; CHECK-LABEL: @test4
; CHECK-DAG: lbz ; CHECK-DAG: lbz
; CHECK-DAG: qvlfdx [[REG1:[0-9]+]], ; CHECK-DAG: qvlfdx [[REG1:[0-9]+]],
; CHECK-DAG: stw ; CHECK-DAG: stw
; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]], ; CHECK-DAG: qvlfiwzx [[REG2:[0-9]+]],
; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]] ; CHECK-DAG: qvfcfidu [[REG3:[0-9]+]], [[REG2]]
; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]] ; CHECK: qvfcmpeq [[REG4:[0-9]+]], [[REG3]], [[REG1]]
; CHECK: qvflogical 1, 1, [[REG4]], 1 ; CHECK: qvfand 1, 1, [[REG4]]
; CHECK: blr ; CHECK: blr
} }
define void @test5(<4 x i1> %a) nounwind { define void @test5(<4 x i1> %a) nounwind {
entry: entry:
store <4 x i1> %a, <4 x i1>* @R store <4 x i1> %a, <4 x i1>* @R
ret void ret void
▲ Show 20 Lines • Show All 80 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/redundant-copy-after-tail-dup.ll

Show All 23 Lines
; CHECK-P9-NEXT: .LBB0_2: # %for.inc ; CHECK-P9-NEXT: .LBB0_2: # %for.inc
; CHECK-P9-NEXT: lhz r3, 5308(r3) ; CHECK-P9-NEXT: lhz r3, 5308(r3)
; CHECK-P9-NEXT: cmplwi r3, 2 ; CHECK-P9-NEXT: cmplwi r3, 2
; CHECK-P9-NEXT: bge- cr0, .LBB0_6 ; CHECK-P9-NEXT: bge- cr0, .LBB0_6
; CHECK-P9-NEXT: # %bb.3: # %land.lhs.true.1 ; CHECK-P9-NEXT: # %bb.3: # %land.lhs.true.1
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; CHECK-P9-NEXT: .LBB0_4: # %lor.lhs.false ; CHECK-P9-NEXT: .LBB0_4: # %lor.lhs.false
; CHECK-P9-NEXT: cmplwi cr0, r4, 0 ; CHECK-P9-NEXT: cmplwi r4, 0
; CHECK-P9-NEXT: bne cr0, .LBB0_2 ; CHECK-P9-NEXT: bne cr0, .LBB0_2
; CHECK-P9-NEXT: .LBB0_5: # %cleanup16 ; CHECK-P9-NEXT: .LBB0_5: # %cleanup16
; CHECK-P9-NEXT: mr r3, r5 ; CHECK-P9-NEXT: mr r3, r5
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; CHECK-P9-NEXT: .LBB0_6: # %lor.lhs.false.1 ; CHECK-P9-NEXT: .LBB0_6: # %lor.lhs.false.1
entry: entry:
br i1 undef, label %land.lhs.true, label %lor.lhs.false br i1 undef, label %land.lhs.true, label %lor.lhs.false
Show All 32 Lines

llvm/test/CodeGen/PowerPC/sat-add.ll

Show All 18 Lines; CHECK-NEXT: blr
%s = select i1 %c, i8 %x, i8 -43 %s = select i1 %c, i8 %x, i8 -43
%r = add i8 %s, 42 %r = add i8 %s, 42
ret i8 %r ret i8 %r
} }
define i8 @unsigned_sat_constant_i8_using_cmp_sum(i8 %x) { define i8 @unsigned_sat_constant_i8_using_cmp_sum(i8 %x) {
; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_sum: ; CHECK-LABEL: unsigned_sat_constant_i8_using_cmp_sum:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 0, 24, 31 ; CHECK-NEXT: clrlwi 3, 3, 24
; CHECK-NEXT: addi 3, 3, 42 ; CHECK-NEXT: addi 3, 3, 42
; CHECK-NEXT: andi. 4, 3, 256 ; CHECK-NEXT: andi. 4, 3, 256
; CHECK-NEXT: li 4, -1 ; CHECK-NEXT: li 4, -1
; CHECK-NEXT: isel 3, 3, 4, 2 ; CHECK-NEXT: isel 3, 3, 4, 2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = add i8 %x, 42 %a = add i8 %x, 42
%c = icmp ugt i8 %x, %a %c = icmp ugt i8 %x, %a
%r = select i1 %c, i8 -1, i8 %a %r = select i1 %c, i8 -1, i8 %a
Show All 28 Lines; CHECK-NEXT: blr
%s = select i1 %c, i16 %x, i16 -43 %s = select i1 %c, i16 %x, i16 -43
%r = add i16 %s, 42 %r = add i16 %s, 42
ret i16 %r ret i16 %r
} }
define i16 @unsigned_sat_constant_i16_using_cmp_sum(i16 %x) { define i16 @unsigned_sat_constant_i16_using_cmp_sum(i16 %x) {
; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_sum: ; CHECK-LABEL: unsigned_sat_constant_i16_using_cmp_sum:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 0, 16, 31 ; CHECK-NEXT: clrlwi 3, 3, 16
; CHECK-NEXT: addi 3, 3, 42 ; CHECK-NEXT: addi 3, 3, 42
; CHECK-NEXT: andis. 4, 3, 1 ; CHECK-NEXT: andis. 4, 3, 1
; CHECK-NEXT: li 4, -1 ; CHECK-NEXT: li 4, -1
; CHECK-NEXT: isel 3, 3, 4, 2 ; CHECK-NEXT: isel 3, 3, 4, 2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = add i16 %x, 42 %a = add i16 %x, 42
%c = icmp ugt i16 %x, %a %c = icmp ugt i16 %x, %a
%r = select i1 %c, i16 -1, i16 %a %r = select i1 %c, i16 -1, i16 %a
Show All 29 Lines; CHECK-NEXT: blr
ret i32 %r ret i32 %r
} }
define i32 @unsigned_sat_constant_i32_using_cmp_sum(i32 %x) { define i32 @unsigned_sat_constant_i32_using_cmp_sum(i32 %x) {
; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_sum: ; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_sum:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: addi 5, 3, 42 ; CHECK-NEXT: addi 5, 3, 42
; CHECK-NEXT: li 4, -1 ; CHECK-NEXT: li 4, -1
; CHECK-NEXT: cmplw 0, 5, 3 ; CHECK-NEXT: cmplw 5, 3
; CHECK-NEXT: isel 3, 4, 5, 0 ; CHECK-NEXT: isel 3, 4, 5, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = add i32 %x, 42 %a = add i32 %x, 42
%c = icmp ugt i32 %x, %a %c = icmp ugt i32 %x, %a
%r = select i1 %c, i32 -1, i32 %a %r = select i1 %c, i32 -1, i32 %a
ret i32 %r ret i32 %r
} }
define i32 @unsigned_sat_constant_i32_using_cmp_notval(i32 %x) { define i32 @unsigned_sat_constant_i32_using_cmp_notval(i32 %x) {
; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_notval: ; CHECK-LABEL: unsigned_sat_constant_i32_using_cmp_notval:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li 4, -43 ; CHECK-NEXT: li 4, -43
; CHECK-NEXT: addi 5, 3, 42 ; CHECK-NEXT: addi 5, 3, 42
; CHECK-NEXT: cmplw 0, 3, 4 ; CHECK-NEXT: cmplw 3, 4
; CHECK-NEXT: li 3, -1 ; CHECK-NEXT: li 3, -1
; CHECK-NEXT: isel 3, 3, 5, 1 ; CHECK-NEXT: isel 3, 3, 5, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = add i32 %x, 42 %a = add i32 %x, 42
%c = icmp ugt i32 %x, -43 %c = icmp ugt i32 %x, -43
%r = select i1 %c, i32 -1, i32 %a %r = select i1 %c, i32 -1, i32 %a
ret i32 %r ret i32 %r
} }
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines; CHECK-NEXT: blr
%s = select i1 %c, i8 %x, i8 %noty %s = select i1 %c, i8 %x, i8 %noty
%r = add i8 %s, %y %r = add i8 %s, %y
ret i8 %r ret i8 %r
} }
define i8 @unsigned_sat_variable_i8_using_cmp_sum(i8 %x, i8 %y) { define i8 @unsigned_sat_variable_i8_using_cmp_sum(i8 %x, i8 %y) {
; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_sum: ; CHECK-LABEL: unsigned_sat_variable_i8_using_cmp_sum:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 24, 31 ; CHECK-NEXT: clrlwi 4, 4, 24
; CHECK-NEXT: rlwinm 3, 3, 0, 24, 31 ; CHECK-NEXT: clrlwi 3, 3, 24
; CHECK-NEXT: add 3, 3, 4 ; CHECK-NEXT: add 3, 3, 4
; CHECK-NEXT: andi. 4, 3, 256 ; CHECK-NEXT: andi. 4, 3, 256
; CHECK-NEXT: li 4, -1 ; CHECK-NEXT: li 4, -1
; CHECK-NEXT: isel 3, 3, 4, 2 ; CHECK-NEXT: isel 3, 3, 4, 2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = add i8 %x, %y %a = add i8 %x, %y
%c = icmp ugt i8 %x, %a %c = icmp ugt i8 %x, %a
%r = select i1 %c, i8 -1, i8 %a %r = select i1 %c, i8 -1, i8 %a
Show All 33 Lines; CHECK-NEXT: blr
%s = select i1 %c, i16 %x, i16 %noty %s = select i1 %c, i16 %x, i16 %noty
%r = add i16 %s, %y %r = add i16 %s, %y
ret i16 %r ret i16 %r
} }
define i16 @unsigned_sat_variable_i16_using_cmp_sum(i16 %x, i16 %y) { define i16 @unsigned_sat_variable_i16_using_cmp_sum(i16 %x, i16 %y) {
; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_sum: ; CHECK-LABEL: unsigned_sat_variable_i16_using_cmp_sum:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 16, 31 ; CHECK-NEXT: clrlwi 4, 4, 16
; CHECK-NEXT: rlwinm 3, 3, 0, 16, 31 ; CHECK-NEXT: clrlwi 3, 3, 16
; CHECK-NEXT: add 3, 3, 4 ; CHECK-NEXT: add 3, 3, 4
; CHECK-NEXT: andis. 4, 3, 1 ; CHECK-NEXT: andis. 4, 3, 1
; CHECK-NEXT: li 4, -1 ; CHECK-NEXT: li 4, -1
; CHECK-NEXT: isel 3, 3, 4, 2 ; CHECK-NEXT: isel 3, 3, 4, 2
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = add i16 %x, %y %a = add i16 %x, %y
%c = icmp ugt i16 %x, %a %c = icmp ugt i16 %x, %a
%r = select i1 %c, i16 -1, i16 %a %r = select i1 %c, i16 -1, i16 %a
Show All 33 Lines; CHECK-NEXT: blr
ret i32 %r ret i32 %r
} }
define i32 @unsigned_sat_variable_i32_using_cmp_sum(i32 %x, i32 %y) { define i32 @unsigned_sat_variable_i32_using_cmp_sum(i32 %x, i32 %y) {
; CHECK-LABEL: unsigned_sat_variable_i32_using_cmp_sum: ; CHECK-LABEL: unsigned_sat_variable_i32_using_cmp_sum:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: add 4, 3, 4 ; CHECK-NEXT: add 4, 3, 4
; CHECK-NEXT: li 5, -1 ; CHECK-NEXT: li 5, -1
; CHECK-NEXT: cmplw 0, 4, 3 ; CHECK-NEXT: cmplw 4, 3
; CHECK-NEXT: isel 3, 5, 4, 0 ; CHECK-NEXT: isel 3, 5, 4, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%a = add i32 %x, %y %a = add i32 %x, %y
%c = icmp ugt i32 %x, %a %c = icmp ugt i32 %x, %a
%r = select i1 %c, i32 -1, i32 %a %r = select i1 %c, i32 -1, i32 %a
ret i32 %r ret i32 %r
} }
▲ Show 20 Lines • Show All 462 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/select-i1-vs-i1.ll

Show All 12 Linesentry:
%cmp1 = icmp eq i32 %c3, %c4 %cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2 %cmp3tmp = icmp eq i32 %c1, %c2
%cmp3 = icmp slt i1 %cmp3tmp, %cmp1 %cmp3 = icmp slt i1 %cmp3tmp, %cmp1
%cond = select i1 %cmp3, i32 %a1, i32 %a2 %cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond ret i32 %cond
; CHECK-LABEL: @testi32slt ; CHECK-LABEL: @testi32slt
; CHECK-NO-ISEL-LABEL: @testi32slt ; CHECK-NO-ISEL-LABEL: @testi32slt
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 ; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]] ; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
; CHECK-NO-ISEL: ori 3, 8, 0 ; CHECK-NO-ISEL: ori 3, 8, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL: [[TRUE]] ; CHECK-NO-ISEL: [[TRUE]]
; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK: blr ; CHECK: blr
} }
define signext i32 @testi32ult(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { define signext i32 @testi32ult(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
entry: entry:
%cmp1 = icmp eq i32 %c3, %c4 %cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2 %cmp3tmp = icmp eq i32 %c1, %c2
%cmp3 = icmp ult i1 %cmp3tmp, %cmp1 %cmp3 = icmp ult i1 %cmp3tmp, %cmp1
%cond = select i1 %cmp3, i32 %a1, i32 %a2 %cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond ret i32 %cond
; CHECK-NO-ISEL-LABEL: @testi32ult ; CHECK-NO-ISEL-LABEL: @testi32ult
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 ; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]] ; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
; CHECK-NO-ISEL: ori 3, 8, 0 ; CHECK-NO-ISEL: ori 3, 8, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL: [[TRUE]] ; CHECK-NO-ISEL: [[TRUE]]
; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK: blr ; CHECK: blr
} }
define signext i32 @testi32sle(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { define signext i32 @testi32sle(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
entry: entry:
%cmp1 = icmp eq i32 %c3, %c4 %cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2 %cmp3tmp = icmp eq i32 %c1, %c2
%cmp3 = icmp sle i1 %cmp3tmp, %cmp1 %cmp3 = icmp sle i1 %cmp3tmp, %cmp1
%cond = select i1 %cmp3, i32 %a1, i32 %a2 %cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond ret i32 %cond
; CHECK-LABEL: @testi32sle ; CHECK-LABEL: @testi32sle
; CHECK-NO-ISEL-LABEL: @testi32sle ; CHECK-NO-ISEL-LABEL: @testi32sle
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 ; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]] ; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
; CHECK-NO-ISEL: ori 3, 8, 0 ; CHECK-NO-ISEL: ori 3, 8, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL: [[TRUE]] ; CHECK-NO-ISEL: [[TRUE]]
; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK: blr ; CHECK: blr
} }
define signext i32 @testi32ule(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { define signext i32 @testi32ule(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
entry: entry:
%cmp1 = icmp eq i32 %c3, %c4 %cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2 %cmp3tmp = icmp eq i32 %c1, %c2
%cmp3 = icmp ule i1 %cmp3tmp, %cmp1 %cmp3 = icmp ule i1 %cmp3tmp, %cmp1
%cond = select i1 %cmp3, i32 %a1, i32 %a2 %cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond ret i32 %cond
; CHECK-LABEL: @testi32ule ; CHECK-LABEL: @testi32ule
; CHECK-NO-ISEL-LABEL: @testi32ule ; CHECK-NO-ISEL-LABEL: @testi32ule
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 ; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]] ; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
; CHECK-NO-ISEL: ori 3, 8, 0 ; CHECK-NO-ISEL: ori 3, 8, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL: [[TRUE]] ; CHECK-NO-ISEL: [[TRUE]]
; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK: blr ; CHECK: blr
} }
define signext i32 @testi32eq(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { define signext i32 @testi32eq(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
entry: entry:
%cmp1 = icmp eq i32 %c3, %c4 %cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2 %cmp3tmp = icmp eq i32 %c1, %c2
%cmp3 = icmp eq i1 %cmp3tmp, %cmp1 %cmp3 = icmp eq i1 %cmp3tmp, %cmp1
%cond = select i1 %cmp3, i32 %a1, i32 %a2 %cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond ret i32 %cond
; CHECK-LABEL: @testi32eq ; CHECK-LABEL: @testi32eq
; CHECK-NO-ISEL-LABEL: @testi32eq ; CHECK-NO-ISEL-LABEL: @testi32eq
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 ; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: creqv [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]] ; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
; CHECK-NO-ISEL: ori 3, 8, 0 ; CHECK-NO-ISEL: ori 3, 8, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL: [[TRUE]] ; CHECK-NO-ISEL: [[TRUE]]
; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK: blr ; CHECK: blr
} }
define signext i32 @testi32sge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { define signext i32 @testi32sge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
entry: entry:
%cmp1 = icmp eq i32 %c3, %c4 %cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2 %cmp3tmp = icmp eq i32 %c1, %c2
%cmp3 = icmp sge i1 %cmp3tmp, %cmp1 %cmp3 = icmp sge i1 %cmp3tmp, %cmp1
%cond = select i1 %cmp3, i32 %a1, i32 %a2 %cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond ret i32 %cond
; CHECK-LABEL: @testi32sge ; CHECK-LABEL: @testi32sge
; CHECK-NO-ISEL-LABEL: @testi32sge ; CHECK-NO-ISEL-LABEL: @testi32sge
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 ; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]] ; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
; CHECK-NO-ISEL: ori 3, 8, 0 ; CHECK-NO-ISEL: ori 3, 8, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL: [[TRUE]] ; CHECK-NO-ISEL: [[TRUE]]
; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK: blr ; CHECK: blr
} }
define signext i32 @testi32uge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { define signext i32 @testi32uge(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
entry: entry:
%cmp1 = icmp eq i32 %c3, %c4 %cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2 %cmp3tmp = icmp eq i32 %c1, %c2
%cmp3 = icmp uge i1 %cmp3tmp, %cmp1 %cmp3 = icmp uge i1 %cmp3tmp, %cmp1
%cond = select i1 %cmp3, i32 %a1, i32 %a2 %cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond ret i32 %cond
; CHECK-LABEL: @testi32uge ; CHECK-LABEL: @testi32uge
; CHECK-NO-ISEL-LABEL: @testi32uge ; CHECK-NO-ISEL-LABEL: @testi32uge
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 ; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: crorc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]] ; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
; CHECK-NO-ISEL: ori 3, 8, 0 ; CHECK-NO-ISEL: ori 3, 8, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL: [[TRUE]] ; CHECK-NO-ISEL: [[TRUE]]
; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK: blr ; CHECK: blr
} }
define signext i32 @testi32sgt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { define signext i32 @testi32sgt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
entry: entry:
%cmp1 = icmp eq i32 %c3, %c4 %cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2 %cmp3tmp = icmp eq i32 %c1, %c2
%cmp3 = icmp sgt i1 %cmp3tmp, %cmp1 %cmp3 = icmp sgt i1 %cmp3tmp, %cmp1
%cond = select i1 %cmp3, i32 %a1, i32 %a2 %cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond ret i32 %cond
; CHECK-LABEL: @testi32sgt ; CHECK-LABEL: @testi32sgt
; CHECK-NO-ISEL-LABEL: @testi32sgt ; CHECK-NO-ISEL-LABEL: @testi32sgt
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 ; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]] ; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
; CHECK-NO-ISEL: ori 3, 8, 0 ; CHECK-NO-ISEL: ori 3, 8, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL: [[TRUE]] ; CHECK-NO-ISEL: [[TRUE]]
; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK: blr ; CHECK: blr
} }
define signext i32 @testi32ugt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { define signext i32 @testi32ugt(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
entry: entry:
%cmp1 = icmp eq i32 %c3, %c4 %cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2 %cmp3tmp = icmp eq i32 %c1, %c2
%cmp3 = icmp ugt i1 %cmp3tmp, %cmp1 %cmp3 = icmp ugt i1 %cmp3tmp, %cmp1
%cond = select i1 %cmp3, i32 %a1, i32 %a2 %cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond ret i32 %cond
; CHECK-LABEL: @testi32ugt ; CHECK-LABEL: @testi32ugt
; CHECK-NO-ISEL-LABEL: @testi32ugt ; CHECK-NO-ISEL-LABEL: @testi32ugt
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 ; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: crandc [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]] ; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
; CHECK-NO-ISEL: ori 3, 8, 0 ; CHECK-NO-ISEL: ori 3, 8, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL: [[TRUE]] ; CHECK-NO-ISEL: [[TRUE]]
; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK: blr ; CHECK: blr
} }
define signext i32 @testi32ne(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 { define signext i32 @testi32ne(i32 signext %c1, i32 signext %c2, i32 signext %c3, i32 signext %c4, i32 signext %a1, i32 signext %a2) #0 {
entry: entry:
%cmp1 = icmp eq i32 %c3, %c4 %cmp1 = icmp eq i32 %c3, %c4
%cmp3tmp = icmp eq i32 %c1, %c2 %cmp3tmp = icmp eq i32 %c1, %c2
%cmp3 = icmp ne i1 %cmp3tmp, %cmp1 %cmp3 = icmp ne i1 %cmp3tmp, %cmp1
%cond = select i1 %cmp3, i32 %a1, i32 %a2 %cond = select i1 %cmp3, i32 %a1, i32 %a2
ret i32 %cond ret i32 %cond
; CHECK-LABEL: @testi32ne ; CHECK-LABEL: @testi32ne
; CHECK-NO-ISEL-LABEL: @testi32ne ; CHECK-NO-ISEL-LABEL: @testi32ne
; CHECK-DAG: cmpw {{[0-9]+}}, 5, 6 ; CHECK-DAG: cmpw 5, 6
; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4 ; CHECK-DAG: cmpw {{[0-9]+}}, 3, 4
; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}} ; CHECK: crxor [[REG1:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}
; CHECK: isel 3, 7, 8, [[REG1]] ; CHECK: isel 3, 7, 8, [[REG1]]
; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]] ; CHECK-NO-ISEL: bc 12, 20, [[TRUE:.LBB[0-9]+]]
; CHECK-NO-ISEL: ori 3, 8, 0 ; CHECK-NO-ISEL: ori 3, 8, 0
; CHECK-NO-ISEL-NEXT: blr ; CHECK-NO-ISEL-NEXT: blr
; CHECK-NO-ISEL: [[TRUE]] ; CHECK-NO-ISEL: [[TRUE]]
; CHECK-NO-ISEL-NEXT: addi 3, 7, 0 ; CHECK-NO-ISEL-NEXT: addi 3, 7, 0
▲ Show 20 Lines • Show All 1,565 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/select_const.ll

Show First 20 Lines • Show All 608 Lines • ▼ Show 20 Lines; NO_ISEL-NEXT: blr
%sel = select i1 %cond, i8 -4, i8 23 %sel = select i1 %cond, i8 -4, i8 23
%bo = shl i8 %sel, 5 %bo = shl i8 %sel, 5
ret i8 %bo ret i8 %bo
} }
define i8 @shl_constant_sel_constants(i1 %cond) { define i8 @shl_constant_sel_constants(i1 %cond) {
; ALL-LABEL: shl_constant_sel_constants: ; ALL-LABEL: shl_constant_sel_constants:
; ALL: # %bb.0: ; ALL: # %bb.0:
; ALL-NEXT: rlwinm 3, 3, 0, 31, 31 ; ALL-NEXT: clrlwi 3, 3, 31
; ALL-NEXT: li 4, 1 ; ALL-NEXT: li 4, 1
; ALL-NEXT: subfic 3, 3, 3 ; ALL-NEXT: subfic 3, 3, 3
; ALL-NEXT: slw 3, 4, 3 ; ALL-NEXT: slw 3, 4, 3
; ALL-NEXT: blr ; ALL-NEXT: blr
%sel = select i1 %cond, i8 2, i8 3 %sel = select i1 %cond, i8 2, i8 3
%bo = shl i8 1, %sel %bo = shl i8 1, %sel
ret i8 %bo ret i8 %bo
} }
Show All 20 Lines; NO_ISEL-NEXT: blr
%sel = select i1 %cond, i8 -4, i8 23 %sel = select i1 %cond, i8 -4, i8 23
%bo = lshr i8 %sel, 5 %bo = lshr i8 %sel, 5
ret i8 %bo ret i8 %bo
} }
define i8 @lshr_constant_sel_constants(i1 %cond) { define i8 @lshr_constant_sel_constants(i1 %cond) {
; ALL-LABEL: lshr_constant_sel_constants: ; ALL-LABEL: lshr_constant_sel_constants:
; ALL: # %bb.0: ; ALL: # %bb.0:
; ALL-NEXT: rlwinm 3, 3, 0, 31, 31 ; ALL-NEXT: clrlwi 3, 3, 31
; ALL-NEXT: li 4, 64 ; ALL-NEXT: li 4, 64
; ALL-NEXT: subfic 3, 3, 3 ; ALL-NEXT: subfic 3, 3, 3
; ALL-NEXT: srw 3, 4, 3 ; ALL-NEXT: srw 3, 4, 3
; ALL-NEXT: blr ; ALL-NEXT: blr
%sel = select i1 %cond, i8 2, i8 3 %sel = select i1 %cond, i8 2, i8 3
%bo = lshr i8 64, %sel %bo = lshr i8 64, %sel
ret i8 %bo ret i8 %bo
} }
define i8 @sel_constants_ashr_constant(i1 %cond) { define i8 @sel_constants_ashr_constant(i1 %cond) {
; ALL-LABEL: sel_constants_ashr_constant: ; ALL-LABEL: sel_constants_ashr_constant:
; ALL: # %bb.0: ; ALL: # %bb.0:
; ALL-NEXT: clrldi 3, 3, 63 ; ALL-NEXT: clrldi 3, 3, 63
; ALL-NEXT: neg 3, 3 ; ALL-NEXT: neg 3, 3
; ALL-NEXT: blr ; ALL-NEXT: blr
%sel = select i1 %cond, i8 -4, i8 23 %sel = select i1 %cond, i8 -4, i8 23
%bo = ashr i8 %sel, 5 %bo = ashr i8 %sel, 5
ret i8 %bo ret i8 %bo
} }
define i8 @ashr_constant_sel_constants(i1 %cond) { define i8 @ashr_constant_sel_constants(i1 %cond) {
; ALL-LABEL: ashr_constant_sel_constants: ; ALL-LABEL: ashr_constant_sel_constants:
; ALL: # %bb.0: ; ALL: # %bb.0:
; ALL-NEXT: rlwinm 3, 3, 0, 31, 31 ; ALL-NEXT: clrlwi 3, 3, 31
; ALL-NEXT: li 4, -128 ; ALL-NEXT: li 4, -128
; ALL-NEXT: subfic 3, 3, 3 ; ALL-NEXT: subfic 3, 3, 3
; ALL-NEXT: sraw 3, 4, 3 ; ALL-NEXT: sraw 3, 4, 3
; ALL-NEXT: blr ; ALL-NEXT: blr
%sel = select i1 %cond, i8 2, i8 3 %sel = select i1 %cond, i8 2, i8 3
%bo = ashr i8 128, %sel %bo = ashr i8 128, %sel
ret i8 %bo ret i8 %bo
} }
▲ Show 20 Lines • Show All 235 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/setcc-logic.ll

Show First 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
return: return:
ret i32 192 ret i32 192
} }
define i32 @all_sign_bits_clear_branch(i32 %P, i32 %Q) { define i32 @all_sign_bits_clear_branch(i32 %P, i32 %Q) {
; CHECK-LABEL: all_sign_bits_clear_branch: ; CHECK-LABEL: all_sign_bits_clear_branch:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: cmpwi 0, 3, 0 ; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: blt 0, .LBB9_2 ; CHECK-NEXT: blt 0, .LBB9_2
; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: li 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-NEXT: .LBB9_2: # %return ; CHECK-NEXT: .LBB9_2: # %return
; CHECK-NEXT: li 3, 192 ; CHECK-NEXT: li 3, 192
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%a = icmp sgt i32 %P, -1 %a = icmp sgt i32 %P, -1
%b = icmp sgt i32 %Q, -1 %b = icmp sgt i32 %Q, -1
%c = and i1 %a, %b %c = and i1 %a, %b
br i1 %c, label %bb1, label %return br i1 %c, label %bb1, label %return
bb1: bb1:
ret i32 4 ret i32 4
return: return:
ret i32 192 ret i32 192
} }
define i32 @all_bits_set_branch(i32 %P, i32 %Q) { define i32 @all_bits_set_branch(i32 %P, i32 %Q) {
; CHECK-LABEL: all_bits_set_branch: ; CHECK-LABEL: all_bits_set_branch:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: cmpwi 0, 3, -1 ; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: bne 0, .LBB10_2 ; CHECK-NEXT: bne 0, .LBB10_2
; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: li 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-NEXT: .LBB10_2: # %return ; CHECK-NEXT: .LBB10_2: # %return
; CHECK-NEXT: li 3, 192 ; CHECK-NEXT: li 3, 192
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%a = icmp eq i32 %P, -1 %a = icmp eq i32 %P, -1
%b = icmp eq i32 %Q, -1 %b = icmp eq i32 %Q, -1
%c = and i1 %a, %b %c = and i1 %a, %b
br i1 %c, label %bb1, label %return br i1 %c, label %bb1, label %return
bb1: bb1:
ret i32 4 ret i32 4
return: return:
ret i32 192 ret i32 192
} }
define i32 @all_sign_bits_set_branch(i32 %P, i32 %Q) { define i32 @all_sign_bits_set_branch(i32 %P, i32 %Q) {
; CHECK-LABEL: all_sign_bits_set_branch: ; CHECK-LABEL: all_sign_bits_set_branch:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: cmpwi 0, 3, -1 ; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: bgt 0, .LBB11_2 ; CHECK-NEXT: bgt 0, .LBB11_2
; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: li 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-NEXT: .LBB11_2: # %return ; CHECK-NEXT: .LBB11_2: # %return
; CHECK-NEXT: li 3, 192 ; CHECK-NEXT: li 3, 192
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
Show All 33 Lines
return: return:
ret i32 192 ret i32 192
} }
define i32 @any_sign_bits_set_branch(i32 %P, i32 %Q) { define i32 @any_sign_bits_set_branch(i32 %P, i32 %Q) {
; CHECK-LABEL: any_sign_bits_set_branch: ; CHECK-LABEL: any_sign_bits_set_branch:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: or 3, 3, 4 ; CHECK-NEXT: or 3, 3, 4
; CHECK-NEXT: cmpwi 0, 3, -1 ; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: bgt 0, .LBB13_2 ; CHECK-NEXT: bgt 0, .LBB13_2
; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: li 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-NEXT: .LBB13_2: # %return ; CHECK-NEXT: .LBB13_2: # %return
; CHECK-NEXT: li 3, 192 ; CHECK-NEXT: li 3, 192
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%a = icmp slt i32 %P, 0 %a = icmp slt i32 %P, 0
%b = icmp slt i32 %Q, 0 %b = icmp slt i32 %Q, 0
%c = or i1 %a, %b %c = or i1 %a, %b
br i1 %c, label %bb1, label %return br i1 %c, label %bb1, label %return
bb1: bb1:
ret i32 4 ret i32 4
return: return:
ret i32 192 ret i32 192
} }
define i32 @any_bits_clear_branch(i32 %P, i32 %Q) { define i32 @any_bits_clear_branch(i32 %P, i32 %Q) {
; CHECK-LABEL: any_bits_clear_branch: ; CHECK-LABEL: any_bits_clear_branch:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: cmpwi 0, 3, -1 ; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: beq 0, .LBB14_2 ; CHECK-NEXT: beq 0, .LBB14_2
; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: li 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-NEXT: .LBB14_2: # %return ; CHECK-NEXT: .LBB14_2: # %return
; CHECK-NEXT: li 3, 192 ; CHECK-NEXT: li 3, 192
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%a = icmp ne i32 %P, -1 %a = icmp ne i32 %P, -1
%b = icmp ne i32 %Q, -1 %b = icmp ne i32 %Q, -1
%c = or i1 %a, %b %c = or i1 %a, %b
br i1 %c, label %bb1, label %return br i1 %c, label %bb1, label %return
bb1: bb1:
ret i32 4 ret i32 4
return: return:
ret i32 192 ret i32 192
} }
define i32 @any_sign_bits_clear_branch(i32 %P, i32 %Q) { define i32 @any_sign_bits_clear_branch(i32 %P, i32 %Q) {
; CHECK-LABEL: any_sign_bits_clear_branch: ; CHECK-LABEL: any_sign_bits_clear_branch:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: cmpwi 0, 3, 0 ; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: blt 0, .LBB15_2 ; CHECK-NEXT: blt 0, .LBB15_2
; CHECK-NEXT: # %bb.1: # %bb1 ; CHECK-NEXT: # %bb.1: # %bb1
; CHECK-NEXT: li 3, 4 ; CHECK-NEXT: li 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-NEXT: .LBB15_2: # %return ; CHECK-NEXT: .LBB15_2: # %return
; CHECK-NEXT: li 3, 192 ; CHECK-NEXT: li 3, 192
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
▲ Show 20 Lines • Show All 211 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/shift_mask.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
target triple = "powerpc64le-linux-gnu" target triple = "powerpc64le-linux-gnu"
define i8 @test000(i8 %a, i8 %b) { define i8 @test000(i8 %a, i8 %b) {
; CHECK-LABEL: test000: ; CHECK-LABEL: test000:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31 ; CHECK-NEXT: clrlwi 4, 4, 29
; CHECK-NEXT: slw 3, 3, 4 ; CHECK-NEXT: slw 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%rem = and i8 %b, 7 %rem = and i8 %b, 7
%shl = shl i8 %a, %rem %shl = shl i8 %a, %rem
ret i8 %shl ret i8 %shl
} }
define i16 @test001(i16 %a, i16 %b) { define i16 @test001(i16 %a, i16 %b) {
; CHECK-LABEL: test001: ; CHECK-LABEL: test001:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31 ; CHECK-NEXT: clrlwi 4, 4, 28
; CHECK-NEXT: slw 3, 3, 4 ; CHECK-NEXT: slw 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%rem = and i16 %b, 15 %rem = and i16 %b, 15
%shl = shl i16 %a, %rem %shl = shl i16 %a, %rem
ret i16 %shl ret i16 %shl
} }
define i32 @test002(i32 %a, i32 %b) { define i32 @test002(i32 %a, i32 %b) {
; CHECK-LABEL: test002: ; CHECK-LABEL: test002:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31 ; CHECK-NEXT: clrlwi 4, 4, 27
; CHECK-NEXT: slw 3, 3, 4 ; CHECK-NEXT: slw 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%rem = and i32 %b, 31 %rem = and i32 %b, 31
%shl = shl i32 %a, %rem %shl = shl i32 %a, %rem
ret i32 %shl ret i32 %shl
} }
define i64 @test003(i64 %a, i64 %b) { define i64 @test003(i64 %a, i64 %b) {
; CHECK-LABEL: test003: ; CHECK-LABEL: test003:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31 ; CHECK-NEXT: clrlwi 4, 4, 26
; CHECK-NEXT: sld 3, 3, 4 ; CHECK-NEXT: sld 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%rem = and i64 %b, 63 %rem = and i64 %b, 63
%shl = shl i64 %a, %rem %shl = shl i64 %a, %rem
ret i64 %shl ret i64 %shl
} }
define <16 x i8> @test010(<16 x i8> %a, <16 x i8> %b) { define <16 x i8> @test010(<16 x i8> %a, <16 x i8> %b) {
Show All 34 Lines; CHECK-NEXT: blr
%rem = and <2 x i64> %b, <i64 63, i64 63> %rem = and <2 x i64> %b, <i64 63, i64 63>
%shl = shl <2 x i64> %a, %rem %shl = shl <2 x i64> %a, %rem
ret <2 x i64> %shl ret <2 x i64> %shl
} }
define i8 @test100(i8 %a, i8 %b) { define i8 @test100(i8 %a, i8 %b) {
; CHECK-LABEL: test100: ; CHECK-LABEL: test100:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 0, 24, 31 ; CHECK-NEXT: clrlwi 3, 3, 24
; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31 ; CHECK-NEXT: clrlwi 4, 4, 29
; CHECK-NEXT: srw 3, 3, 4 ; CHECK-NEXT: srw 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%rem = and i8 %b, 7 %rem = and i8 %b, 7
%lshr = lshr i8 %a, %rem %lshr = lshr i8 %a, %rem
ret i8 %lshr ret i8 %lshr
} }
define i16 @test101(i16 %a, i16 %b) { define i16 @test101(i16 %a, i16 %b) {
; CHECK-LABEL: test101: ; CHECK-LABEL: test101:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 3, 3, 0, 16, 31 ; CHECK-NEXT: clrlwi 3, 3, 16
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31 ; CHECK-NEXT: clrlwi 4, 4, 28
; CHECK-NEXT: srw 3, 3, 4 ; CHECK-NEXT: srw 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%rem = and i16 %b, 15 %rem = and i16 %b, 15
%lshr = lshr i16 %a, %rem %lshr = lshr i16 %a, %rem
ret i16 %lshr ret i16 %lshr
} }
define i32 @test102(i32 %a, i32 %b) { define i32 @test102(i32 %a, i32 %b) {
; CHECK-LABEL: test102: ; CHECK-LABEL: test102:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31 ; CHECK-NEXT: clrlwi 4, 4, 27
; CHECK-NEXT: srw 3, 3, 4 ; CHECK-NEXT: srw 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%rem = and i32 %b, 31 %rem = and i32 %b, 31
%lshr = lshr i32 %a, %rem %lshr = lshr i32 %a, %rem
ret i32 %lshr ret i32 %lshr
} }
define i64 @test103(i64 %a, i64 %b) { define i64 @test103(i64 %a, i64 %b) {
; CHECK-LABEL: test103: ; CHECK-LABEL: test103:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31 ; CHECK-NEXT: clrlwi 4, 4, 26
; CHECK-NEXT: srd 3, 3, 4 ; CHECK-NEXT: srd 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%rem = and i64 %b, 63 %rem = and i64 %b, 63
%lshr = lshr i64 %a, %rem %lshr = lshr i64 %a, %rem
ret i64 %lshr ret i64 %lshr
} }
define <16 x i8> @test110(<16 x i8> %a, <16 x i8> %b) { define <16 x i8> @test110(<16 x i8> %a, <16 x i8> %b) {
Show All 35 Lines; CHECK-NEXT: blr
%lshr = lshr <2 x i64> %a, %rem %lshr = lshr <2 x i64> %a, %rem
ret <2 x i64> %lshr ret <2 x i64> %lshr
} }
define i8 @test200(i8 %a, i8 %b) { define i8 @test200(i8 %a, i8 %b) {
; CHECK-LABEL: test200: ; CHECK-LABEL: test200:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: extsb 3, 3 ; CHECK-NEXT: extsb 3, 3
; CHECK-NEXT: rlwinm 4, 4, 0, 29, 31 ; CHECK-NEXT: clrlwi 4, 4, 29
; CHECK-NEXT: sraw 3, 3, 4 ; CHECK-NEXT: sraw 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%rem = and i8 %b, 7 %rem = and i8 %b, 7
%ashr = ashr i8 %a, %rem %ashr = ashr i8 %a, %rem
ret i8 %ashr ret i8 %ashr
} }
define i16 @test201(i16 %a, i16 %b) { define i16 @test201(i16 %a, i16 %b) {
; CHECK-LABEL: test201: ; CHECK-LABEL: test201:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: extsh 3, 3 ; CHECK-NEXT: extsh 3, 3
; CHECK-NEXT: rlwinm 4, 4, 0, 28, 31 ; CHECK-NEXT: clrlwi 4, 4, 28
; CHECK-NEXT: sraw 3, 3, 4 ; CHECK-NEXT: sraw 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%rem = and i16 %b, 15 %rem = and i16 %b, 15
%ashr = ashr i16 %a, %rem %ashr = ashr i16 %a, %rem
ret i16 %ashr ret i16 %ashr
} }
define i32 @test202(i32 %a, i32 %b) { define i32 @test202(i32 %a, i32 %b) {
; CHECK-LABEL: test202: ; CHECK-LABEL: test202:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 27, 31 ; CHECK-NEXT: clrlwi 4, 4, 27
; CHECK-NEXT: sraw 3, 3, 4 ; CHECK-NEXT: sraw 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%rem = and i32 %b, 31 %rem = and i32 %b, 31
%ashr = ashr i32 %a, %rem %ashr = ashr i32 %a, %rem
ret i32 %ashr ret i32 %ashr
} }
define i64 @test203(i64 %a, i64 %b) { define i64 @test203(i64 %a, i64 %b) {
; CHECK-LABEL: test203: ; CHECK-LABEL: test203:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: rlwinm 4, 4, 0, 26, 31 ; CHECK-NEXT: clrlwi 4, 4, 26
; CHECK-NEXT: srad 3, 3, 4 ; CHECK-NEXT: srad 3, 3, 4
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%rem = and i64 %b, 63 %rem = and i64 %b, 63
%ashr = ashr i64 %a, %rem %ashr = ashr i64 %a, %rem
ret i64 %ashr ret i64 %ashr
} }
define <16 x i8> @test210(<16 x i8> %a, <16 x i8> %b) { define <16 x i8> @test210(<16 x i8> %a, <16 x i8> %b) {
Show All 38 Lines

llvm/test/CodeGen/PowerPC/signbit-shift.ll

Show All 40 Lines; CHECK-NEXT: blr
%r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41> %r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>
ret <4 x i32> %r ret <4 x i32> %r
} }
define i32 @sel_ifpos_tval_bigger(i32 %x) { define i32 @sel_ifpos_tval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifpos_tval_bigger: ; CHECK-LABEL: sel_ifpos_tval_bigger:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 41 ; CHECK-NEXT: li 4, 41
; CHECK-NEXT: cmpwi 0, 3, -1 ; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: li 3, 42 ; CHECK-NEXT: li 3, 42
; CHECK-NEXT: isel 3, 3, 4, 1 ; CHECK-NEXT: isel 3, 3, 4, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%c = icmp sgt i32 %x, -1 %c = icmp sgt i32 %x, -1
%r = select i1 %c, i32 42, i32 41 %r = select i1 %c, i32 42, i32 41
ret i32 %r ret i32 %r
} }
Show All 35 Lines; CHECK-NEXT: blr
%r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42> %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>
ret <4 x i32> %r ret <4 x i32> %r
} }
define i32 @sel_ifpos_fval_bigger(i32 %x) { define i32 @sel_ifpos_fval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifpos_fval_bigger: ; CHECK-LABEL: sel_ifpos_fval_bigger:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 42 ; CHECK-NEXT: li 4, 42
; CHECK-NEXT: cmpwi 0, 3, -1 ; CHECK-NEXT: cmpwi 3, -1
; CHECK-NEXT: li 3, 41 ; CHECK-NEXT: li 3, 41
; CHECK-NEXT: isel 3, 3, 4, 1 ; CHECK-NEXT: isel 3, 3, 4, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%c = icmp sgt i32 %x, -1 %c = icmp sgt i32 %x, -1
%r = select i1 %c, i32 41, i32 42 %r = select i1 %c, i32 41, i32 42
ret i32 %r ret i32 %r
} }
Show All 20 Lines; CHECK-NEXT: blr
%r = add i32 %e, 41 %r = add i32 %e, 41
ret i32 %r ret i32 %r
} }
define i32 @sel_ifneg_tval_bigger(i32 %x) { define i32 @sel_ifneg_tval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifneg_tval_bigger: ; CHECK-LABEL: sel_ifneg_tval_bigger:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 41 ; CHECK-NEXT: li 4, 41
; CHECK-NEXT: cmpwi 0, 3, 0 ; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: li 3, 42 ; CHECK-NEXT: li 3, 42
; CHECK-NEXT: isel 3, 3, 4, 0 ; CHECK-NEXT: isel 3, 3, 4, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%c = icmp slt i32 %x, 0 %c = icmp slt i32 %x, 0
%r = select i1 %c, i32 42, i32 41 %r = select i1 %c, i32 42, i32 41
ret i32 %r ret i32 %r
} }
Show All 18 Lines; CHECK-NEXT: blr
%r = add i32 %e, 42 %r = add i32 %e, 42
ret i32 %r ret i32 %r
} }
define i32 @sel_ifneg_fval_bigger(i32 %x) { define i32 @sel_ifneg_fval_bigger(i32 %x) {
; CHECK-LABEL: sel_ifneg_fval_bigger: ; CHECK-LABEL: sel_ifneg_fval_bigger:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li 4, 42 ; CHECK-NEXT: li 4, 42
; CHECK-NEXT: cmpwi 0, 3, 0 ; CHECK-NEXT: cmpwi 3, 0
; CHECK-NEXT: li 3, 41 ; CHECK-NEXT: li 3, 41
; CHECK-NEXT: isel 3, 3, 4, 0 ; CHECK-NEXT: isel 3, 3, 4, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%c = icmp slt i32 %x, 0 %c = icmp slt i32 %x, 0
%r = select i1 %c, i32 41, i32 42 %r = select i1 %c, i32 41, i32 42
ret i32 %r ret i32 %r
} }
▲ Show 20 Lines • Show All 113 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/simplifyConstCmpToISEL.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 \ ; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 \
; RUN: -ppc-convert-rr-to-ri -verify-machineinstrs | FileCheck %s ; RUN: -ppc-convert-rr-to-ri -verify-machineinstrs | FileCheck %s
define void @test(i32 zeroext %parts) { define void @test(i32 zeroext %parts) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmplwi 0, 3, 1 ; CHECK-NEXT: cmplwi 3, 1
; CHECK-NEXT: bnelr+ 0 ; CHECK-NEXT: bnelr+ 0
; CHECK-NEXT: # %bb.1: # %test2.exit.us.unr-lcssa ; CHECK-NEXT: # %bb.1: # %test2.exit.us.unr-lcssa
; CHECK-NEXT: ld 3, 0(3) ; CHECK-NEXT: ld 3, 0(3)
; CHECK-NEXT: std 3, 0(3) ; CHECK-NEXT: std 3, 0(3)
entry: entry:
br label %cond.end.i br label %cond.end.i
cond.end.i: ; preds = %entry cond.end.i: ; preds = %entry
Show All 36 Lines

llvm/test/CodeGen/PowerPC/sms-cpy-1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s ; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
@.str.28 = external unnamed_addr constant [69 x i8], align 1 @.str.28 = external unnamed_addr constant [69 x i8], align 1
define void @print_res() nounwind { define void @print_res() nounwind {
; CHECK-LABEL: print_res: ; CHECK-LABEL: print_res:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: std 0, 16(1) ; CHECK-NEXT: std 0, 16(1)
; CHECK-NEXT: stdu 1, -128(1) ; CHECK-NEXT: stdu 1, -128(1)
; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: lwz 3, 0(3)
; CHECK-NEXT: addi 3, 3, -1 ; CHECK-NEXT: addi 3, 3, -1
; CHECK-NEXT: clrldi 4, 3, 32 ; CHECK-NEXT: clrldi 4, 3, 32
; CHECK-NEXT: cmplwi 0, 3, 1 ; CHECK-NEXT: cmplwi 3, 1
; CHECK-NEXT: li 3, 1 ; CHECK-NEXT: li 3, 1
; CHECK-NEXT: isel 3, 4, 3, 1 ; CHECK-NEXT: isel 3, 4, 3, 1
; CHECK-NEXT: li 4, 2 ; CHECK-NEXT: li 4, 2
; CHECK-NEXT: addi 3, 3, -1 ; CHECK-NEXT: addi 3, 3, -1
; CHECK-NEXT: cmpldi 3, 2 ; CHECK-NEXT: cmpldi 3, 2
; CHECK-NEXT: isel 3, 3, 4, 0 ; CHECK-NEXT: isel 3, 3, 4, 0
; CHECK-NEXT: li 4, 0 ; CHECK-NEXT: li 4, 0
; CHECK-NEXT: addi 3, 3, 1 ; CHECK-NEXT: addi 3, 3, 1
▲ Show 20 Lines • Show All 89 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/spill_p9_setb.ll

Show All 11 Lines
; RUN: | FileCheck %s --check-prefix=CHECK-P8 ; RUN: | FileCheck %s --check-prefix=CHECK-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr8 < %s \ ; RUN: -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr -mcpu=pwr8 < %s \
; RUN: | FileCheck %s --check-prefix=CHECK-P8 ; RUN: | FileCheck %s --check-prefix=CHECK-P8
define void @p9_setb_spill() { define void @p9_setb_spill() {
; CHECK-P9-LABEL: p9_setb_spill: ; CHECK-P9-LABEL: p9_setb_spill:
; CHECK-P9: # %bb.1: # %if.then ; CHECK-P9: # %bb.1: # %if.then
; CHECK-P9-DAG: crnor 4*cr[[CREG:.*]]+lt, eq, eq ; CHECK-P9-DAG: crnot 4*cr[[CREG:.*]]+lt, eq
; CHECK-P9-DAG: setb [[REG1:.*]], cr[[CREG]] ; CHECK-P9-DAG: setb [[REG1:.*]], cr[[CREG]]
; CHECK-P9-DAG: stw [[REG1]] ; CHECK-P9-DAG: stw [[REG1]]
; CHECK-P9: blr ; CHECK-P9: blr
; CHECK-P9: .LBB0_4: # %if.then1 ; CHECK-P9: .LBB0_4: # %if.then1
; ;
; CHECK-P8-LABEL: p9_setb_spill: ; CHECK-P8-LABEL: p9_setb_spill:
; CHECK-P8: # %bb.1: # %if.then ; CHECK-P8: # %bb.1: # %if.then
; CHECK-P8-DAG: crnor 4*cr[[CREG2:.*]]+lt, eq, eq ; CHECK-P8-DAG: crnot 4*cr[[CREG2:.*]]+lt, eq
; CHECK-P8-DAG: mfocrf [[REG2:.*]], ; CHECK-P8-DAG: mfocrf [[REG2:.*]],
; CHECK-P8-DAG: rlwinm [[REG2]], [[REG2]] ; CHECK-P8-DAG: rlwinm [[REG2]], [[REG2]]
; CHECK-P8-DAG: stw [[REG2]] ; CHECK-P8-DAG: stw [[REG2]]
; CHECK-P8: blr ; CHECK-P8: blr
; CHECK-P8: .LBB0_4: # %if.then1 ; CHECK-P8: .LBB0_4: # %if.then1
entry: entry:
br i1 undef, label %if.end, label %if.then br i1 undef, label %if.end, label %if.then
Show All 20 Lines

llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll

Show All 20 Lines
; P9LE-NEXT: rldicl r5, r5, 32, 32 ; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: add r4, r5, r4 ; P9LE-NEXT: add r4, r5, r4
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 6 ; P9LE-NEXT: srawi r4, r4, 6
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: lis r5, 31710 ; P9LE-NEXT: lis r5, 31710
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3 ; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: extsw r4, r4 ; P9LE-NEXT: extsw r4, r4
; P9LE-NEXT: ori r5, r5, 63421 ; P9LE-NEXT: ori r5, r5, 63421
; P9LE-NEXT: mulld r5, r4, r5 ; P9LE-NEXT: mulld r5, r4, r5
; P9LE-NEXT: rldicl r5, r5, 32, 32 ; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: subf r4, r4, r5 ; P9LE-NEXT: subf r4, r4, r5
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 6 ; P9LE-NEXT: srawi r4, r4, 6
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: lis r5, 21399 ; P9LE-NEXT: lis r5, 21399
; P9LE-NEXT: mulli r4, r4, -124 ; P9LE-NEXT: mulli r4, r4, -124
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0 ; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3 ; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: extsw r4, r4 ; P9LE-NEXT: extsw r4, r4
; P9LE-NEXT: ori r5, r5, 33437 ; P9LE-NEXT: ori r5, r5, 33437
; P9LE-NEXT: mulld r4, r4, r5 ; P9LE-NEXT: mulld r4, r4, r5
; P9LE-NEXT: rldicl r5, r4, 1, 63 ; P9LE-NEXT: rldicl r5, r4, 1, 63
; P9LE-NEXT: rldicl r4, r4, 32, 32 ; P9LE-NEXT: rldicl r4, r4, 32, 32
; P9LE-NEXT: srawi r4, r4, 5 ; P9LE-NEXT: srawi r4, r4, 5
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: lis r5, -16728 ; P9LE-NEXT: lis r5, -16728
; P9LE-NEXT: mulli r4, r4, 98 ; P9LE-NEXT: mulli r4, r4, 98
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3 ; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: extsw r4, r4 ; P9LE-NEXT: extsw r4, r4
; P9LE-NEXT: ori r5, r5, 63249 ; P9LE-NEXT: ori r5, r5, 63249
; P9LE-NEXT: mulld r4, r4, r5 ; P9LE-NEXT: mulld r4, r4, r5
; P9LE-NEXT: rldicl r5, r4, 1, 63 ; P9LE-NEXT: rldicl r5, r4, 1, 63
; P9LE-NEXT: rldicl r4, r4, 32, 32 ; P9LE-NEXT: rldicl r4, r4, 32, 32
; P9LE-NEXT: srawi r4, r4, 8 ; P9LE-NEXT: srawi r4, r4, 8
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, -1003 ; P9LE-NEXT: mulli r4, r4, -1003
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: vmrglh v3, v4, v3 ; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0 ; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v2, v4 ; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: fold_srem_vec_1: ; P9BE-LABEL: fold_srem_vec_1:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
▲ Show 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r4, 21399 ; P8LE-NEXT: lis r4, 21399
; P8LE-NEXT: lis r9, -16728 ; P8LE-NEXT: lis r9, -16728
; P8LE-NEXT: lis r11, -21386 ; P8LE-NEXT: lis r11, -21386
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r4, r4, 33437 ; P8LE-NEXT: ori r4, r4, 33437
; P8LE-NEXT: ori r9, r9, 63249 ; P8LE-NEXT: ori r9, r9, 63249
; P8LE-NEXT: ori r11, r11, 37253 ; P8LE-NEXT: ori r11, r11, 37253
; P8LE-NEXT: mfvsrd r5, f0 ; P8LE-NEXT: mffprd r5, f0
; P8LE-NEXT: rldicl r3, r5, 32, 48 ; P8LE-NEXT: rldicl r3, r5, 32, 48
; P8LE-NEXT: rldicl r6, r5, 16, 48 ; P8LE-NEXT: rldicl r6, r5, 16, 48
; P8LE-NEXT: clrldi r7, r5, 48 ; P8LE-NEXT: clrldi r7, r5, 48
; P8LE-NEXT: extsh r8, r3 ; P8LE-NEXT: extsh r8, r3
; P8LE-NEXT: extsh r10, r6 ; P8LE-NEXT: extsh r10, r6
; P8LE-NEXT: rldicl r5, r5, 48, 48 ; P8LE-NEXT: rldicl r5, r5, 48, 48
; P8LE-NEXT: extsw r8, r8 ; P8LE-NEXT: extsw r8, r8
; P8LE-NEXT: extsh r12, r7 ; P8LE-NEXT: extsh r12, r7
Show All 27 Lines
; P8LE-NEXT: srawi r8, r8, 6 ; P8LE-NEXT: srawi r8, r8, 6
; P8LE-NEXT: mulli r4, r4, 98 ; P8LE-NEXT: mulli r4, r4, 98
; P8LE-NEXT: mulli r9, r9, -1003 ; P8LE-NEXT: mulli r9, r9, -1003
; P8LE-NEXT: add r8, r8, r11 ; P8LE-NEXT: add r8, r8, r11
; P8LE-NEXT: mulli r10, r10, 95 ; P8LE-NEXT: mulli r10, r10, 95
; P8LE-NEXT: mulli r8, r8, -124 ; P8LE-NEXT: mulli r8, r8, -124
; P8LE-NEXT: subf r3, r4, r3 ; P8LE-NEXT: subf r3, r4, r3
; P8LE-NEXT: subf r4, r9, r6 ; P8LE-NEXT: subf r4, r9, r6
; P8LE-NEXT: mtvsrd f0, r3 ; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r3, r10, r7 ; P8LE-NEXT: subf r3, r10, r7
; P8LE-NEXT: mtvsrd f1, r4 ; P8LE-NEXT: mtfprd f1, r4
; P8LE-NEXT: subf r4, r8, r5 ; P8LE-NEXT: subf r4, r8, r5
; P8LE-NEXT: mtvsrd f2, r3 ; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: mtvsrd f3, r4 ; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v3, vs1 ; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2 ; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: xxswapd v5, vs3 ; P8LE-NEXT: xxswapd v5, vs3
; P8LE-NEXT: vmrglh v2, v3, v2 ; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: vmrglh v3, v5, v4 ; P8LE-NEXT: vmrglh v3, v5, v4
; P8LE-NEXT: vmrglw v2, v2, v3 ; P8LE-NEXT: vmrglw v2, v2, v3
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
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; P9LE-NEXT: mulld r6, r4, r5 ; P9LE-NEXT: mulld r6, r4, r5
; P9LE-NEXT: rldicl r6, r6, 32, 32 ; P9LE-NEXT: rldicl r6, r6, 32, 32
; P9LE-NEXT: add r4, r6, r4 ; P9LE-NEXT: add r4, r6, r4
; P9LE-NEXT: srwi r6, r4, 31 ; P9LE-NEXT: srwi r6, r4, 31
; P9LE-NEXT: srawi r4, r4, 6 ; P9LE-NEXT: srawi r4, r4, 6
; P9LE-NEXT: add r4, r4, r6 ; P9LE-NEXT: add r4, r4, r6
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3 ; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: extsw r4, r4 ; P9LE-NEXT: extsw r4, r4
; P9LE-NEXT: mulld r6, r4, r5 ; P9LE-NEXT: mulld r6, r4, r5
; P9LE-NEXT: rldicl r6, r6, 32, 32 ; P9LE-NEXT: rldicl r6, r6, 32, 32
; P9LE-NEXT: add r4, r6, r4 ; P9LE-NEXT: add r4, r6, r4
; P9LE-NEXT: srwi r6, r4, 31 ; P9LE-NEXT: srwi r6, r4, 31
; P9LE-NEXT: srawi r4, r4, 6 ; P9LE-NEXT: srawi r4, r4, 6
; P9LE-NEXT: add r4, r4, r6 ; P9LE-NEXT: add r4, r4, r6
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0 ; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3 ; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: extsw r4, r4 ; P9LE-NEXT: extsw r4, r4
; P9LE-NEXT: mulld r6, r4, r5 ; P9LE-NEXT: mulld r6, r4, r5
; P9LE-NEXT: rldicl r6, r6, 32, 32 ; P9LE-NEXT: rldicl r6, r6, 32, 32
; P9LE-NEXT: add r4, r6, r4 ; P9LE-NEXT: add r4, r6, r4
; P9LE-NEXT: srwi r6, r4, 31 ; P9LE-NEXT: srwi r6, r4, 31
; P9LE-NEXT: srawi r4, r4, 6 ; P9LE-NEXT: srawi r4, r4, 6
; P9LE-NEXT: add r4, r4, r6 ; P9LE-NEXT: add r4, r4, r6
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3 ; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: extsw r4, r4 ; P9LE-NEXT: extsw r4, r4
; P9LE-NEXT: mulld r5, r4, r5 ; P9LE-NEXT: mulld r5, r4, r5
; P9LE-NEXT: rldicl r5, r5, 32, 32 ; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: add r4, r5, r4 ; P9LE-NEXT: add r4, r5, r4
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 6 ; P9LE-NEXT: srawi r4, r4, 6
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: vmrglh v3, v4, v3 ; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0 ; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v2, v4 ; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: fold_srem_vec_2: ; P9BE-LABEL: fold_srem_vec_2:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
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; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: fold_srem_vec_2: ; P8LE-LABEL: fold_srem_vec_2:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r4, -21386 ; P8LE-NEXT: lis r4, -21386
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r4, r4, 37253 ; P8LE-NEXT: ori r4, r4, 37253
; P8LE-NEXT: mfvsrd r5, f0 ; P8LE-NEXT: mffprd r5, f0
; P8LE-NEXT: clrldi r3, r5, 48 ; P8LE-NEXT: clrldi r3, r5, 48
; P8LE-NEXT: rldicl r7, r5, 32, 48 ; P8LE-NEXT: rldicl r7, r5, 32, 48
; P8LE-NEXT: extsh r8, r3 ; P8LE-NEXT: extsh r8, r3
; P8LE-NEXT: rldicl r6, r5, 48, 48 ; P8LE-NEXT: rldicl r6, r5, 48, 48
; P8LE-NEXT: extsh r10, r7 ; P8LE-NEXT: extsh r10, r7
; P8LE-NEXT: rldicl r5, r5, 16, 48 ; P8LE-NEXT: rldicl r5, r5, 16, 48
; P8LE-NEXT: extsw r8, r8 ; P8LE-NEXT: extsw r8, r8
; P8LE-NEXT: extsh r9, r6 ; P8LE-NEXT: extsh r9, r6
Show All 27 Lines
; P8LE-NEXT: add r9, r9, r12 ; P8LE-NEXT: add r9, r9, r12
; P8LE-NEXT: mulli r8, r8, 95 ; P8LE-NEXT: mulli r8, r8, 95
; P8LE-NEXT: add r4, r4, r11 ; P8LE-NEXT: add r4, r4, r11
; P8LE-NEXT: mulli r9, r9, 95 ; P8LE-NEXT: mulli r9, r9, 95
; P8LE-NEXT: mulli r10, r10, 95 ; P8LE-NEXT: mulli r10, r10, 95
; P8LE-NEXT: mulli r4, r4, 95 ; P8LE-NEXT: mulli r4, r4, 95
; P8LE-NEXT: subf r3, r8, r3 ; P8LE-NEXT: subf r3, r8, r3
; P8LE-NEXT: subf r6, r9, r6 ; P8LE-NEXT: subf r6, r9, r6
; P8LE-NEXT: mtvsrd f0, r3 ; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r3, r10, r7 ; P8LE-NEXT: subf r3, r10, r7
; P8LE-NEXT: subf r4, r4, r5 ; P8LE-NEXT: subf r4, r4, r5
; P8LE-NEXT: mtvsrd f1, r6 ; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: mtvsrd f2, r3 ; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: mtvsrd f3, r4 ; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v3, vs1 ; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2 ; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: xxswapd v5, vs3 ; P8LE-NEXT: xxswapd v5, vs3
; P8LE-NEXT: vmrglh v2, v3, v2 ; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: vmrglh v3, v5, v4 ; P8LE-NEXT: vmrglh v3, v5, v4
; P8LE-NEXT: vmrglw v2, v3, v2 ; P8LE-NEXT: vmrglw v2, v3, v2
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
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; P9LE-NEXT: mulld r6, r4, r5 ; P9LE-NEXT: mulld r6, r4, r5
; P9LE-NEXT: rldicl r6, r6, 32, 32 ; P9LE-NEXT: rldicl r6, r6, 32, 32
; P9LE-NEXT: add r4, r6, r4 ; P9LE-NEXT: add r4, r6, r4
; P9LE-NEXT: srwi r6, r4, 31 ; P9LE-NEXT: srwi r6, r4, 31
; P9LE-NEXT: srawi r4, r4, 6 ; P9LE-NEXT: srawi r4, r4, 6
; P9LE-NEXT: add r4, r4, r6 ; P9LE-NEXT: add r4, r4, r6
; P9LE-NEXT: mulli r6, r4, 95 ; P9LE-NEXT: mulli r6, r4, 95
; P9LE-NEXT: subf r3, r6, r3 ; P9LE-NEXT: subf r3, r6, r3
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r6, r3 ; P9LE-NEXT: extsh r6, r3
; P9LE-NEXT: extsw r6, r6 ; P9LE-NEXT: extsw r6, r6
; P9LE-NEXT: mulld r7, r6, r5 ; P9LE-NEXT: mulld r7, r6, r5
; P9LE-NEXT: rldicl r7, r7, 32, 32 ; P9LE-NEXT: rldicl r7, r7, 32, 32
; P9LE-NEXT: add r6, r7, r6 ; P9LE-NEXT: add r6, r7, r6
; P9LE-NEXT: srwi r7, r6, 31 ; P9LE-NEXT: srwi r7, r6, 31
; P9LE-NEXT: srawi r6, r6, 6 ; P9LE-NEXT: srawi r6, r6, 6
; P9LE-NEXT: add r6, r6, r7 ; P9LE-NEXT: add r6, r6, r7
; P9LE-NEXT: mulli r7, r6, 95 ; P9LE-NEXT: mulli r7, r6, 95
; P9LE-NEXT: subf r3, r7, r3 ; P9LE-NEXT: subf r3, r7, r3
; P9LE-NEXT: xxswapd v3, vs0 ; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r7, r3 ; P9LE-NEXT: extsh r7, r3
; P9LE-NEXT: extsw r7, r7 ; P9LE-NEXT: extsw r7, r7
; P9LE-NEXT: mulld r8, r7, r5 ; P9LE-NEXT: mulld r8, r7, r5
; P9LE-NEXT: rldicl r8, r8, 32, 32 ; P9LE-NEXT: rldicl r8, r8, 32, 32
; P9LE-NEXT: add r7, r8, r7 ; P9LE-NEXT: add r7, r8, r7
; P9LE-NEXT: srwi r8, r7, 31 ; P9LE-NEXT: srwi r8, r7, 31
; P9LE-NEXT: srawi r7, r7, 6 ; P9LE-NEXT: srawi r7, r7, 6
; P9LE-NEXT: add r7, r7, r8 ; P9LE-NEXT: add r7, r7, r8
; P9LE-NEXT: mulli r8, r7, 95 ; P9LE-NEXT: mulli r8, r7, 95
; P9LE-NEXT: subf r3, r8, r3 ; P9LE-NEXT: subf r3, r8, r3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r8, r3 ; P9LE-NEXT: extsh r8, r3
; P9LE-NEXT: extsw r8, r8 ; P9LE-NEXT: extsw r8, r8
; P9LE-NEXT: mulld r5, r8, r5 ; P9LE-NEXT: mulld r5, r8, r5
; P9LE-NEXT: rldicl r5, r5, 32, 32 ; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: add r5, r5, r8 ; P9LE-NEXT: add r5, r5, r8
; P9LE-NEXT: srwi r8, r5, 31 ; P9LE-NEXT: srwi r8, r5, 31
; P9LE-NEXT: srawi r5, r5, 6 ; P9LE-NEXT: srawi r5, r5, 6
; P9LE-NEXT: add r5, r5, r8 ; P9LE-NEXT: add r5, r5, r8
; P9LE-NEXT: mulli r8, r5, 95 ; P9LE-NEXT: mulli r8, r5, 95
; P9LE-NEXT: subf r3, r8, r3 ; P9LE-NEXT: subf r3, r8, r3
; P9LE-NEXT: vmrglh v3, v4, v3 ; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0 ; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: mtvsrd f0, r4 ; P9LE-NEXT: mtfprd f0, r4
; P9LE-NEXT: vmrglh v2, v2, v4 ; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: xxswapd v3, vs0 ; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r6 ; P9LE-NEXT: mtfprd f0, r6
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r7 ; P9LE-NEXT: mtfprd f0, r7
; P9LE-NEXT: vmrglh v3, v4, v3 ; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r5 ; P9LE-NEXT: mtfprd f0, r5
; P9LE-NEXT: xxswapd v5, vs0 ; P9LE-NEXT: xxswapd v5, vs0
; P9LE-NEXT: vmrglh v4, v5, v4 ; P9LE-NEXT: vmrglh v4, v5, v4
; P9LE-NEXT: vmrglw v3, v4, v3 ; P9LE-NEXT: vmrglw v3, v4, v3
; P9LE-NEXT: vadduhm v2, v2, v3 ; P9LE-NEXT: vadduhm v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: combine_srem_sdiv: ; P9BE-LABEL: combine_srem_sdiv:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
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; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: combine_srem_sdiv: ; P8LE-LABEL: combine_srem_sdiv:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r5, -21386 ; P8LE-NEXT: lis r5, -21386
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r5, r5, 37253 ; P8LE-NEXT: ori r5, r5, 37253
; P8LE-NEXT: mfvsrd r6, f0 ; P8LE-NEXT: mffprd r6, f0
; P8LE-NEXT: clrldi r3, r6, 48 ; P8LE-NEXT: clrldi r3, r6, 48
; P8LE-NEXT: rldicl r4, r6, 48, 48 ; P8LE-NEXT: rldicl r4, r6, 48, 48
; P8LE-NEXT: rldicl r7, r6, 32, 48 ; P8LE-NEXT: rldicl r7, r6, 32, 48
; P8LE-NEXT: extsh r8, r3 ; P8LE-NEXT: extsh r8, r3
; P8LE-NEXT: extsh r9, r4 ; P8LE-NEXT: extsh r9, r4
; P8LE-NEXT: rldicl r6, r6, 16, 48 ; P8LE-NEXT: rldicl r6, r6, 16, 48
; P8LE-NEXT: extsh r10, r7 ; P8LE-NEXT: extsh r10, r7
; P8LE-NEXT: extsw r8, r8 ; P8LE-NEXT: extsw r8, r8
Show All 19 Lines
; P8LE-NEXT: srwi r9, r9, 31 ; P8LE-NEXT: srwi r9, r9, 31
; P8LE-NEXT: add r5, r5, r11 ; P8LE-NEXT: add r5, r5, r11
; P8LE-NEXT: add r8, r8, r12 ; P8LE-NEXT: add r8, r8, r12
; P8LE-NEXT: srawi r12, r10, 6 ; P8LE-NEXT: srawi r12, r10, 6
; P8LE-NEXT: srwi r10, r10, 31 ; P8LE-NEXT: srwi r10, r10, 31
; P8LE-NEXT: add r9, r0, r9 ; P8LE-NEXT: add r9, r0, r9
; P8LE-NEXT: mulli r0, r8, 95 ; P8LE-NEXT: mulli r0, r8, 95
; P8LE-NEXT: add r10, r12, r10 ; P8LE-NEXT: add r10, r12, r10
; P8LE-NEXT: mtvsrd f0, r8 ; P8LE-NEXT: mtfprd f0, r8
; P8LE-NEXT: srwi r8, r5, 31 ; P8LE-NEXT: srwi r8, r5, 31
; P8LE-NEXT: srawi r5, r5, 6 ; P8LE-NEXT: srawi r5, r5, 6
; P8LE-NEXT: mulli r11, r9, 95 ; P8LE-NEXT: mulli r11, r9, 95
; P8LE-NEXT: mtvsrd f1, r9 ; P8LE-NEXT: mtfprd f1, r9
; P8LE-NEXT: mulli r9, r10, 95 ; P8LE-NEXT: mulli r9, r10, 95
; P8LE-NEXT: add r5, r5, r8 ; P8LE-NEXT: add r5, r5, r8
; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: mtvsrd f2, r10 ; P8LE-NEXT: mtfprd f2, r10
; P8LE-NEXT: mtvsrd f3, r5 ; P8LE-NEXT: mtfprd f3, r5
; P8LE-NEXT: mulli r5, r5, 95 ; P8LE-NEXT: mulli r5, r5, 95
; P8LE-NEXT: xxswapd v3, vs1 ; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: subf r3, r0, r3 ; P8LE-NEXT: subf r3, r0, r3
; P8LE-NEXT: xxswapd v1, vs2 ; P8LE-NEXT: xxswapd v1, vs2
; P8LE-NEXT: mtvsrd f0, r3 ; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r4, r11, r4 ; P8LE-NEXT: subf r4, r11, r4
; P8LE-NEXT: xxswapd v6, vs3 ; P8LE-NEXT: xxswapd v6, vs3
; P8LE-NEXT: subf r3, r9, r7 ; P8LE-NEXT: subf r3, r9, r7
; P8LE-NEXT: mtvsrd f1, r4 ; P8LE-NEXT: mtfprd f1, r4
; P8LE-NEXT: mtvsrd f4, r3 ; P8LE-NEXT: mtfprd f4, r3
; P8LE-NEXT: subf r3, r5, r6 ; P8LE-NEXT: subf r3, r5, r6
; P8LE-NEXT: mtvsrd f5, r3 ; P8LE-NEXT: mtfprd f5, r3
; P8LE-NEXT: xxswapd v4, vs1 ; P8LE-NEXT: xxswapd v4, vs1
; P8LE-NEXT: vmrglh v2, v3, v2 ; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: xxswapd v3, vs0 ; P8LE-NEXT: xxswapd v3, vs0
; P8LE-NEXT: xxswapd v5, vs4 ; P8LE-NEXT: xxswapd v5, vs4
; P8LE-NEXT: xxswapd v0, vs5 ; P8LE-NEXT: xxswapd v0, vs5
; P8LE-NEXT: vmrglh v3, v4, v3 ; P8LE-NEXT: vmrglh v3, v4, v3
; P8LE-NEXT: vmrglh v4, v0, v5 ; P8LE-NEXT: vmrglh v4, v0, v5
; P8LE-NEXT: vmrglh v5, v6, v1 ; P8LE-NEXT: vmrglh v5, v6, v1
▲ Show 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3 ; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: srawi r4, r4, 6 ; P9LE-NEXT: srawi r4, r4, 6
; P9LE-NEXT: addze r4, r4 ; P9LE-NEXT: addze r4, r4
; P9LE-NEXT: slwi r4, r4, 6 ; P9LE-NEXT: slwi r4, r4, 6
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3 ; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: srawi r4, r4, 5 ; P9LE-NEXT: srawi r4, r4, 5
; P9LE-NEXT: addze r4, r4 ; P9LE-NEXT: addze r4, r4
; P9LE-NEXT: slwi r4, r4, 5 ; P9LE-NEXT: slwi r4, r4, 5
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0 ; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3 ; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: lis r5, -21386 ; P9LE-NEXT: lis r5, -21386
; P9LE-NEXT: ori r5, r5, 37253 ; P9LE-NEXT: ori r5, r5, 37253
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: vmrglh v3, v4, v3 ; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: extsw r4, r4 ; P9LE-NEXT: extsw r4, r4
; P9LE-NEXT: mulld r5, r4, r5 ; P9LE-NEXT: mulld r5, r4, r5
; P9LE-NEXT: rldicl r5, r5, 32, 32 ; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: add r4, r5, r4 ; P9LE-NEXT: add r4, r5, r4
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 6 ; P9LE-NEXT: srawi r4, r4, 6
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3 ; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: srawi r4, r4, 3 ; P9LE-NEXT: srawi r4, r4, 3
; P9LE-NEXT: addze r4, r4 ; P9LE-NEXT: addze r4, r4
; P9LE-NEXT: slwi r4, r4, 3 ; P9LE-NEXT: slwi r4, r4, 3
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0 ; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v4, v2 ; P9LE-NEXT: vmrglh v2, v4, v2
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: dont_fold_srem_power_of_two: ; P9BE-LABEL: dont_fold_srem_power_of_two:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; P9BE-NEXT: vmrghw v2, v3, v2 ; P9BE-NEXT: vmrghw v2, v3, v2
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: dont_fold_srem_power_of_two: ; P8LE-LABEL: dont_fold_srem_power_of_two:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r3, -21386 ; P8LE-NEXT: lis r3, -21386
; P8LE-NEXT: ori r3, r3, 37253 ; P8LE-NEXT: ori r3, r3, 37253
; P8LE-NEXT: mfvsrd r4, f0 ; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r5, r4, 16, 48 ; P8LE-NEXT: rldicl r5, r4, 16, 48
; P8LE-NEXT: clrldi r7, r4, 48 ; P8LE-NEXT: clrldi r7, r4, 48
; P8LE-NEXT: extsh r6, r5 ; P8LE-NEXT: extsh r6, r5
; P8LE-NEXT: extsh r8, r7 ; P8LE-NEXT: extsh r8, r7
; P8LE-NEXT: extsw r6, r6 ; P8LE-NEXT: extsw r6, r6
; P8LE-NEXT: rldicl r9, r4, 48, 48 ; P8LE-NEXT: rldicl r9, r4, 48, 48
; P8LE-NEXT: mulld r3, r6, r3 ; P8LE-NEXT: mulld r3, r6, r3
; P8LE-NEXT: srawi r8, r8, 6 ; P8LE-NEXT: srawi r8, r8, 6
; P8LE-NEXT: extsh r10, r9 ; P8LE-NEXT: extsh r10, r9
; P8LE-NEXT: addze r8, r8 ; P8LE-NEXT: addze r8, r8
; P8LE-NEXT: rldicl r4, r4, 32, 48 ; P8LE-NEXT: rldicl r4, r4, 32, 48
; P8LE-NEXT: srawi r10, r10, 5 ; P8LE-NEXT: srawi r10, r10, 5
; P8LE-NEXT: slwi r8, r8, 6 ; P8LE-NEXT: slwi r8, r8, 6
; P8LE-NEXT: subf r7, r8, r7 ; P8LE-NEXT: subf r7, r8, r7
; P8LE-NEXT: rldicl r3, r3, 32, 32 ; P8LE-NEXT: rldicl r3, r3, 32, 32
; P8LE-NEXT: mtvsrd f0, r7 ; P8LE-NEXT: mtfprd f0, r7
; P8LE-NEXT: add r3, r3, r6 ; P8LE-NEXT: add r3, r3, r6
; P8LE-NEXT: addze r6, r10 ; P8LE-NEXT: addze r6, r10
; P8LE-NEXT: srwi r10, r3, 31 ; P8LE-NEXT: srwi r10, r3, 31
; P8LE-NEXT: srawi r3, r3, 6 ; P8LE-NEXT: srawi r3, r3, 6
; P8LE-NEXT: slwi r6, r6, 5 ; P8LE-NEXT: slwi r6, r6, 5
; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: add r3, r3, r10 ; P8LE-NEXT: add r3, r3, r10
; P8LE-NEXT: extsh r10, r4 ; P8LE-NEXT: extsh r10, r4
; P8LE-NEXT: subf r6, r6, r9 ; P8LE-NEXT: subf r6, r6, r9
; P8LE-NEXT: mulli r3, r3, 95 ; P8LE-NEXT: mulli r3, r3, 95
; P8LE-NEXT: srawi r8, r10, 3 ; P8LE-NEXT: srawi r8, r10, 3
; P8LE-NEXT: mtvsrd f1, r6 ; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: addze r7, r8 ; P8LE-NEXT: addze r7, r8
; P8LE-NEXT: xxswapd v3, vs1 ; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: subf r3, r3, r5 ; P8LE-NEXT: subf r3, r3, r5
; P8LE-NEXT: slwi r5, r7, 3 ; P8LE-NEXT: slwi r5, r7, 3
; P8LE-NEXT: subf r4, r5, r4 ; P8LE-NEXT: subf r4, r5, r4
; P8LE-NEXT: mtvsrd f2, r3 ; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: mtvsrd f3, r4 ; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v4, vs2 ; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: vmrglh v2, v3, v2 ; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: xxswapd v5, vs3 ; P8LE-NEXT: xxswapd v5, vs3
; P8LE-NEXT: vmrglh v3, v4, v5 ; P8LE-NEXT: vmrglh v3, v4, v5
; P8LE-NEXT: vmrglw v2, v3, v2 ; P8LE-NEXT: vmrglw v2, v3, v2
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: dont_fold_srem_power_of_two: ; P8BE-LABEL: dont_fold_srem_power_of_two:
▲ Show 20 Lines • Show All 61 Lines • ▼ Show 20 Lines
; P9LE-NEXT: xxlxor v4, v4, v4 ; P9LE-NEXT: xxlxor v4, v4, v4
; P9LE-NEXT: add r4, r5, r4 ; P9LE-NEXT: add r4, r5, r4
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 9 ; P9LE-NEXT: srawi r4, r4, 9
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: lis r5, -19946 ; P9LE-NEXT: lis r5, -19946
; P9LE-NEXT: mulli r4, r4, 654 ; P9LE-NEXT: mulli r4, r4, 654
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3 ; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: extsw r4, r4 ; P9LE-NEXT: extsw r4, r4
; P9LE-NEXT: ori r5, r5, 17097 ; P9LE-NEXT: ori r5, r5, 17097
; P9LE-NEXT: mulld r5, r4, r5 ; P9LE-NEXT: mulld r5, r4, r5
; P9LE-NEXT: rldicl r5, r5, 32, 32 ; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: add r4, r5, r4 ; P9LE-NEXT: add r4, r5, r4
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 4 ; P9LE-NEXT: srawi r4, r4, 4
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: lis r5, 24749 ; P9LE-NEXT: lis r5, 24749
; P9LE-NEXT: mulli r4, r4, 23 ; P9LE-NEXT: mulli r4, r4, 23
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0 ; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3 ; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: extsw r4, r4 ; P9LE-NEXT: extsw r4, r4
; P9LE-NEXT: ori r5, r5, 47143 ; P9LE-NEXT: ori r5, r5, 47143
; P9LE-NEXT: mulld r4, r4, r5 ; P9LE-NEXT: mulld r4, r4, r5
; P9LE-NEXT: rldicl r5, r4, 1, 63 ; P9LE-NEXT: rldicl r5, r4, 1, 63
; P9LE-NEXT: rldicl r4, r4, 32, 32 ; P9LE-NEXT: rldicl r4, r4, 32, 32
; P9LE-NEXT: srawi r4, r4, 11 ; P9LE-NEXT: srawi r4, r4, 11
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 5423 ; P9LE-NEXT: mulli r4, r4, 5423
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: vmrglh v3, v3, v4 ; P9LE-NEXT: vmrglh v3, v3, v4
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0 ; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v2, v4 ; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: dont_fold_srem_one: ; P9BE-LABEL: dont_fold_srem_one:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: li r3, 4
▲ Show 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r3, 24749 ; P8LE-NEXT: lis r3, 24749
; P8LE-NEXT: lis r8, -19946 ; P8LE-NEXT: lis r8, -19946
; P8LE-NEXT: lis r10, -14230 ; P8LE-NEXT: lis r10, -14230
; P8LE-NEXT: xxlxor v5, v5, v5 ; P8LE-NEXT: xxlxor v5, v5, v5
; P8LE-NEXT: ori r3, r3, 47143 ; P8LE-NEXT: ori r3, r3, 47143
; P8LE-NEXT: ori r8, r8, 17097 ; P8LE-NEXT: ori r8, r8, 17097
; P8LE-NEXT: mfvsrd r4, f0 ; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r5, r4, 16, 48 ; P8LE-NEXT: rldicl r5, r4, 16, 48
; P8LE-NEXT: rldicl r6, r4, 32, 48 ; P8LE-NEXT: rldicl r6, r4, 32, 48
; P8LE-NEXT: rldicl r4, r4, 48, 48 ; P8LE-NEXT: rldicl r4, r4, 48, 48
; P8LE-NEXT: extsh r7, r5 ; P8LE-NEXT: extsh r7, r5
; P8LE-NEXT: extsh r9, r6 ; P8LE-NEXT: extsh r9, r6
; P8LE-NEXT: extsw r7, r7 ; P8LE-NEXT: extsw r7, r7
; P8LE-NEXT: extsh r11, r4 ; P8LE-NEXT: extsh r11, r4
; P8LE-NEXT: extsw r9, r9 ; P8LE-NEXT: extsw r9, r9
Show All 15 Lines
; P8LE-NEXT: add r8, r8, r9 ; P8LE-NEXT: add r8, r8, r9
; P8LE-NEXT: srwi r9, r7, 31 ; P8LE-NEXT: srwi r9, r7, 31
; P8LE-NEXT: srawi r7, r7, 9 ; P8LE-NEXT: srawi r7, r7, 9
; P8LE-NEXT: mulli r3, r3, 5423 ; P8LE-NEXT: mulli r3, r3, 5423
; P8LE-NEXT: add r7, r7, r9 ; P8LE-NEXT: add r7, r7, r9
; P8LE-NEXT: mulli r8, r8, 23 ; P8LE-NEXT: mulli r8, r8, 23
; P8LE-NEXT: mulli r7, r7, 654 ; P8LE-NEXT: mulli r7, r7, 654
; P8LE-NEXT: subf r3, r3, r5 ; P8LE-NEXT: subf r3, r3, r5
; P8LE-NEXT: mtvsrd f0, r3 ; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r3, r8, r6 ; P8LE-NEXT: subf r3, r8, r6
; P8LE-NEXT: subf r4, r7, r4 ; P8LE-NEXT: subf r4, r7, r4
; P8LE-NEXT: mtvsrd f1, r3 ; P8LE-NEXT: mtfprd f1, r3
; P8LE-NEXT: mtvsrd f2, r4 ; P8LE-NEXT: mtfprd f2, r4
; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v3, vs1 ; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2 ; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: vmrglh v2, v2, v3 ; P8LE-NEXT: vmrglh v2, v2, v3
; P8LE-NEXT: vmrglh v3, v4, v5 ; P8LE-NEXT: vmrglh v3, v4, v5
; P8LE-NEXT: vmrglw v2, v2, v3 ; P8LE-NEXT: vmrglw v2, v2, v3
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Lines
; P9LE-NEXT: rldicl r5, r5, 32, 32 ; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: add r4, r5, r4 ; P9LE-NEXT: add r4, r5, r4
; P9LE-NEXT: srwi r5, r4, 31 ; P9LE-NEXT: srwi r5, r4, 31
; P9LE-NEXT: srawi r4, r4, 4 ; P9LE-NEXT: srawi r4, r4, 4
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: lis r5, 24749 ; P9LE-NEXT: lis r5, 24749
; P9LE-NEXT: mulli r4, r4, 23 ; P9LE-NEXT: mulli r4, r4, 23
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3 ; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: extsw r4, r4 ; P9LE-NEXT: extsw r4, r4
; P9LE-NEXT: ori r5, r5, 47143 ; P9LE-NEXT: ori r5, r5, 47143
; P9LE-NEXT: mulld r4, r4, r5 ; P9LE-NEXT: mulld r4, r4, r5
; P9LE-NEXT: rldicl r5, r4, 1, 63 ; P9LE-NEXT: rldicl r5, r4, 1, 63
; P9LE-NEXT: rldicl r4, r4, 32, 32 ; P9LE-NEXT: rldicl r4, r4, 32, 32
; P9LE-NEXT: srawi r4, r4, 11 ; P9LE-NEXT: srawi r4, r4, 11
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: mulli r4, r4, 5423 ; P9LE-NEXT: mulli r4, r4, 5423
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0 ; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: extsh r4, r3 ; P9LE-NEXT: extsh r4, r3
; P9LE-NEXT: srawi r4, r4, 15 ; P9LE-NEXT: srawi r4, r4, 15
; P9LE-NEXT: addze r4, r4 ; P9LE-NEXT: addze r4, r4
; P9LE-NEXT: slwi r4, r4, 15 ; P9LE-NEXT: slwi r4, r4, 15
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0 ; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v3, v4, v3 ; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxlxor v4, v4, v4 ; P9LE-NEXT: xxlxor v4, v4, v4
; P9LE-NEXT: vmrglh v2, v2, v4 ; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v3, v2 ; P9LE-NEXT: vmrglw v2, v3, v2
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: dont_fold_urem_i16_smax: ; P9BE-LABEL: dont_fold_urem_i16_smax:
▲ Show 20 Lines • Show All 49 Lines • ▼ Show 20 Lines
; P8LE-LABEL: dont_fold_urem_i16_smax: ; P8LE-LABEL: dont_fold_urem_i16_smax:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r6, 24749 ; P8LE-NEXT: lis r6, 24749
; P8LE-NEXT: lis r7, -19946 ; P8LE-NEXT: lis r7, -19946
; P8LE-NEXT: xxlxor v5, v5, v5 ; P8LE-NEXT: xxlxor v5, v5, v5
; P8LE-NEXT: ori r6, r6, 47143 ; P8LE-NEXT: ori r6, r6, 47143
; P8LE-NEXT: ori r7, r7, 17097 ; P8LE-NEXT: ori r7, r7, 17097
; P8LE-NEXT: mfvsrd r3, f0 ; P8LE-NEXT: mffprd r3, f0
; P8LE-NEXT: rldicl r4, r3, 16, 48 ; P8LE-NEXT: rldicl r4, r3, 16, 48
; P8LE-NEXT: rldicl r5, r3, 32, 48 ; P8LE-NEXT: rldicl r5, r3, 32, 48
; P8LE-NEXT: extsh r8, r4 ; P8LE-NEXT: extsh r8, r4
; P8LE-NEXT: extsh r9, r5 ; P8LE-NEXT: extsh r9, r5
; P8LE-NEXT: extsw r8, r8 ; P8LE-NEXT: extsw r8, r8
; P8LE-NEXT: extsw r9, r9 ; P8LE-NEXT: extsw r9, r9
; P8LE-NEXT: mulld r6, r8, r6 ; P8LE-NEXT: mulld r6, r8, r6
; P8LE-NEXT: mulld r7, r9, r7 ; P8LE-NEXT: mulld r7, r9, r7
; P8LE-NEXT: rldicl r3, r3, 48, 48 ; P8LE-NEXT: rldicl r3, r3, 48, 48
; P8LE-NEXT: rldicl r8, r6, 32, 32 ; P8LE-NEXT: rldicl r8, r6, 32, 32
; P8LE-NEXT: rldicl r7, r7, 32, 32 ; P8LE-NEXT: rldicl r7, r7, 32, 32
; P8LE-NEXT: rldicl r6, r6, 1, 63 ; P8LE-NEXT: rldicl r6, r6, 1, 63
; P8LE-NEXT: srawi r8, r8, 11 ; P8LE-NEXT: srawi r8, r8, 11
; P8LE-NEXT: add r7, r7, r9 ; P8LE-NEXT: add r7, r7, r9
; P8LE-NEXT: add r6, r8, r6 ; P8LE-NEXT: add r6, r8, r6
; P8LE-NEXT: srwi r8, r7, 31 ; P8LE-NEXT: srwi r8, r7, 31
; P8LE-NEXT: srawi r7, r7, 4 ; P8LE-NEXT: srawi r7, r7, 4
; P8LE-NEXT: mulli r6, r6, 5423 ; P8LE-NEXT: mulli r6, r6, 5423
; P8LE-NEXT: add r7, r7, r8 ; P8LE-NEXT: add r7, r7, r8
; P8LE-NEXT: extsh r8, r3 ; P8LE-NEXT: extsh r8, r3
; P8LE-NEXT: mulli r7, r7, 23 ; P8LE-NEXT: mulli r7, r7, 23
; P8LE-NEXT: srawi r8, r8, 15 ; P8LE-NEXT: srawi r8, r8, 15
; P8LE-NEXT: subf r4, r6, r4 ; P8LE-NEXT: subf r4, r6, r4
; P8LE-NEXT: addze r6, r8 ; P8LE-NEXT: addze r6, r8
; P8LE-NEXT: mtvsrd f0, r4 ; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: slwi r4, r6, 15 ; P8LE-NEXT: slwi r4, r6, 15
; P8LE-NEXT: subf r5, r7, r5 ; P8LE-NEXT: subf r5, r7, r5
; P8LE-NEXT: subf r3, r4, r3 ; P8LE-NEXT: subf r3, r4, r3
; P8LE-NEXT: mtvsrd f1, r5 ; P8LE-NEXT: mtfprd f1, r5
; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: mtvsrd f2, r3 ; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v3, vs1 ; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2 ; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: vmrglh v2, v2, v3 ; P8LE-NEXT: vmrglh v2, v2, v3
; P8LE-NEXT: vmrglh v3, v4, v5 ; P8LE-NEXT: vmrglh v3, v4, v5
; P8LE-NEXT: vmrglw v2, v2, v3 ; P8LE-NEXT: vmrglw v2, v2, v3
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: dont_fold_urem_i16_smax: ; P8BE-LABEL: dont_fold_urem_i16_smax:
▲ Show 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
; P8LE-NEXT: ori r4, r4, 17096 ; P8LE-NEXT: ori r4, r4, 17096
; P8LE-NEXT: ori r5, r5, 15432 ; P8LE-NEXT: ori r5, r5, 15432
; P8LE-NEXT: mfvsrd r7, v2 ; P8LE-NEXT: mfvsrd r7, v2
; P8LE-NEXT: sldi r3, r3, 32 ; P8LE-NEXT: sldi r3, r3, 32
; P8LE-NEXT: sldi r4, r4, 32 ; P8LE-NEXT: sldi r4, r4, 32
; P8LE-NEXT: sldi r5, r5, 32 ; P8LE-NEXT: sldi r5, r5, 32
; P8LE-NEXT: oris r3, r3, 58853 ; P8LE-NEXT: oris r3, r3, 58853
; P8LE-NEXT: oris r4, r4, 22795 ; P8LE-NEXT: oris r4, r4, 22795
; P8LE-NEXT: mfvsrd r8, f0 ; P8LE-NEXT: mffprd r8, f0
; P8LE-NEXT: oris r5, r5, 1603 ; P8LE-NEXT: oris r5, r5, 1603
; P8LE-NEXT: ori r3, r3, 6055 ; P8LE-NEXT: ori r3, r3, 6055
; P8LE-NEXT: ori r4, r4, 8549 ; P8LE-NEXT: ori r4, r4, 8549
; P8LE-NEXT: ori r5, r5, 21445 ; P8LE-NEXT: ori r5, r5, 21445
; P8LE-NEXT: mulhd r3, r6, r3 ; P8LE-NEXT: mulhd r3, r6, r3
; P8LE-NEXT: mulhd r5, r7, r5 ; P8LE-NEXT: mulhd r5, r7, r5
; P8LE-NEXT: mulhd r4, r8, r4 ; P8LE-NEXT: mulhd r4, r8, r4
; P8LE-NEXT: rldicl r9, r3, 1, 63 ; P8LE-NEXT: rldicl r9, r3, 1, 63
; P8LE-NEXT: sradi r3, r3, 11 ; P8LE-NEXT: sradi r3, r3, 11
; P8LE-NEXT: add r3, r3, r9 ; P8LE-NEXT: add r3, r3, r9
; P8LE-NEXT: rldicl r9, r5, 1, 63 ; P8LE-NEXT: rldicl r9, r5, 1, 63
; P8LE-NEXT: add r4, r4, r8 ; P8LE-NEXT: add r4, r4, r8
; P8LE-NEXT: sradi r5, r5, 8 ; P8LE-NEXT: sradi r5, r5, 8
; P8LE-NEXT: mulli r3, r3, 5423 ; P8LE-NEXT: mulli r3, r3, 5423
; P8LE-NEXT: add r5, r5, r9 ; P8LE-NEXT: add r5, r5, r9
; P8LE-NEXT: rldicl r9, r4, 1, 63 ; P8LE-NEXT: rldicl r9, r4, 1, 63
; P8LE-NEXT: sradi r4, r4, 4 ; P8LE-NEXT: sradi r4, r4, 4
; P8LE-NEXT: mulli r5, r5, 654 ; P8LE-NEXT: mulli r5, r5, 654
; P8LE-NEXT: add r4, r4, r9 ; P8LE-NEXT: add r4, r4, r9
; P8LE-NEXT: mulli r4, r4, 23 ; P8LE-NEXT: mulli r4, r4, 23
; P8LE-NEXT: sub r3, r6, r3 ; P8LE-NEXT: sub r3, r6, r3
; P8LE-NEXT: mtvsrd f0, r3 ; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: sub r5, r7, r5 ; P8LE-NEXT: sub r5, r7, r5
; P8LE-NEXT: mtvsrd f1, r5 ; P8LE-NEXT: mtfprd f1, r5
; P8LE-NEXT: sub r3, r8, r4 ; P8LE-NEXT: sub r3, r8, r4
; P8LE-NEXT: li r4, 0 ; P8LE-NEXT: li r4, 0
; P8LE-NEXT: mtvsrd f2, r3 ; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: mtvsrd f3, r4 ; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxmrghd v3, vs0, vs2 ; P8LE-NEXT: xxmrghd v3, vs0, vs2
; P8LE-NEXT: xxmrghd v2, vs1, vs3 ; P8LE-NEXT: xxmrghd v2, vs1, vs3
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: dont_fold_srem_i64: ; P8BE-LABEL: dont_fold_srem_i64:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: lis r4, -19946 ; P8BE-NEXT: lis r4, -19946
; P8BE-NEXT: lis r3, 24749 ; P8BE-NEXT: lis r3, 24749
; P8BE-NEXT: xxswapd vs0, v3 ; P8BE-NEXT: xxswapd vs0, v3
; P8BE-NEXT: lis r5, 25653 ; P8BE-NEXT: lis r5, 25653
; P8BE-NEXT: xxswapd vs1, v2 ; P8BE-NEXT: xxswapd vs1, v2
; P8BE-NEXT: ori r4, r4, 17096 ; P8BE-NEXT: ori r4, r4, 17096
; P8BE-NEXT: ori r3, r3, 47142 ; P8BE-NEXT: ori r3, r3, 47142
; P8BE-NEXT: ori r5, r5, 15432 ; P8BE-NEXT: ori r5, r5, 15432
; P8BE-NEXT: mfvsrd r6, v3 ; P8BE-NEXT: mfvsrd r6, v3
; P8BE-NEXT: sldi r4, r4, 32 ; P8BE-NEXT: sldi r4, r4, 32
; P8BE-NEXT: sldi r3, r3, 32 ; P8BE-NEXT: sldi r3, r3, 32
; P8BE-NEXT: oris r4, r4, 22795 ; P8BE-NEXT: oris r4, r4, 22795
; P8BE-NEXT: sldi r5, r5, 32 ; P8BE-NEXT: sldi r5, r5, 32
; P8BE-NEXT: oris r3, r3, 58853 ; P8BE-NEXT: oris r3, r3, 58853
; P8BE-NEXT: mfvsrd r7, f0 ; P8BE-NEXT: mffprd r7, f0
; P8BE-NEXT: ori r4, r4, 8549 ; P8BE-NEXT: ori r4, r4, 8549
; P8BE-NEXT: ori r3, r3, 6055 ; P8BE-NEXT: ori r3, r3, 6055
; P8BE-NEXT: oris r5, r5, 1603 ; P8BE-NEXT: oris r5, r5, 1603
; P8BE-NEXT: mfvsrd r8, f1 ; P8BE-NEXT: mffprd r8, f1
; P8BE-NEXT: mulhd r4, r6, r4 ; P8BE-NEXT: mulhd r4, r6, r4
; P8BE-NEXT: mulhd r3, r7, r3 ; P8BE-NEXT: mulhd r3, r7, r3
; P8BE-NEXT: ori r5, r5, 21445 ; P8BE-NEXT: ori r5, r5, 21445
; P8BE-NEXT: mulhd r5, r8, r5 ; P8BE-NEXT: mulhd r5, r8, r5
; P8BE-NEXT: add r4, r4, r6 ; P8BE-NEXT: add r4, r4, r6
; P8BE-NEXT: rldicl r9, r3, 1, 63 ; P8BE-NEXT: rldicl r9, r3, 1, 63
; P8BE-NEXT: sradi r3, r3, 11 ; P8BE-NEXT: sradi r3, r3, 11
; P8BE-NEXT: rldicl r10, r4, 1, 63 ; P8BE-NEXT: rldicl r10, r4, 1, 63
; P8BE-NEXT: sradi r4, r4, 4 ; P8BE-NEXT: sradi r4, r4, 4
; P8BE-NEXT: add r3, r3, r9 ; P8BE-NEXT: add r3, r3, r9
; P8BE-NEXT: rldicl r9, r5, 1, 63 ; P8BE-NEXT: rldicl r9, r5, 1, 63
; P8BE-NEXT: add r4, r4, r10 ; P8BE-NEXT: add r4, r4, r10
; P8BE-NEXT: sradi r5, r5, 8 ; P8BE-NEXT: sradi r5, r5, 8
; P8BE-NEXT: mulli r3, r3, 5423 ; P8BE-NEXT: mulli r3, r3, 5423
; P8BE-NEXT: add r5, r5, r9 ; P8BE-NEXT: add r5, r5, r9
; P8BE-NEXT: mulli r4, r4, 23 ; P8BE-NEXT: mulli r4, r4, 23
; P8BE-NEXT: mulli r5, r5, 654 ; P8BE-NEXT: mulli r5, r5, 654
; P8BE-NEXT: sub r3, r7, r3 ; P8BE-NEXT: sub r3, r7, r3
; P8BE-NEXT: sub r4, r6, r4 ; P8BE-NEXT: sub r4, r6, r4
; P8BE-NEXT: mtvsrd f0, r3 ; P8BE-NEXT: mtfprd f0, r3
; P8BE-NEXT: sub r3, r8, r5 ; P8BE-NEXT: sub r3, r8, r5
; P8BE-NEXT: mtvsrd f1, r4 ; P8BE-NEXT: mtfprd f1, r4
; P8BE-NEXT: li r4, 0 ; P8BE-NEXT: li r4, 0
; P8BE-NEXT: mtvsrd f2, r3 ; P8BE-NEXT: mtfprd f2, r3
; P8BE-NEXT: mtvsrd f3, r4 ; P8BE-NEXT: mtfprd f3, r4
; P8BE-NEXT: xxmrghd v3, vs1, vs0 ; P8BE-NEXT: xxmrghd v3, vs1, vs0
; P8BE-NEXT: xxmrghd v2, vs3, vs2 ; P8BE-NEXT: xxmrghd v2, vs3, vs2
; P8BE-NEXT: blr ; P8BE-NEXT: blr
%1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423> %1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1 ret <4 x i64> %1
} }

llvm/test/CodeGen/PowerPC/stack-realign.ll

Show First 20 Lines • Show All 123 Lines • ▼ Show 20 Lines
; CHECK-DAG: lis [[REG1:[0-9]+]], -13 ; CHECK-DAG: lis [[REG1:[0-9]+]], -13
; CHECK-DAG: clrldi [[REG3:[0-9]+]], 1, 59 ; CHECK-DAG: clrldi [[REG3:[0-9]+]], 1, 59
; CHECK-DAG: mflr {{[0-9]+}} ; CHECK-DAG: mflr {{[0-9]+}}
; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51808 ; CHECK-DAG: ori [[REG2:[0-9]+]], [[REG1]], 51808
; CHECK-DAG: std 30, -16(1) ; CHECK-DAG: std 30, -16(1)
; CHECK-DAG: mr 30, 1 ; CHECK-DAG: mr 30, 1
; CHECK-DAG: std 0, 16(1) ; CHECK-DAG: std 0, 16(1)
; CHECK-DAG: subfc 0, [[REG3]], [[REG2]] ; CHECK-DAG: subc 0, [[REG2]], [[REG3]]
; CHECK: stdux 1, 1, 0 ; CHECK: stdux 1, 1, 0
; CHECK: .cfi_def_cfa_register r30 ; CHECK: .cfi_def_cfa_register r30
; CHECK: blr ; CHECK: blr
; CHECK-32-LABEL: @hoo ; CHECK-32-LABEL: @hoo
▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testBitReverse.ll

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
; CHECK-NEXT: sldi 6, 3, 4 ; CHECK-NEXT: sldi 6, 3, 4
; CHECK-NEXT: ori 5, 5, 61680 ; CHECK-NEXT: ori 5, 5, 61680
; CHECK-NEXT: ori 4, 4, 3855 ; CHECK-NEXT: ori 4, 4, 3855
; CHECK-NEXT: rldicl 3, 3, 60, 4 ; CHECK-NEXT: rldicl 3, 3, 60, 4
; CHECK-NEXT: and 5, 6, 5 ; CHECK-NEXT: and 5, 6, 5
; CHECK-NEXT: and 3, 3, 4 ; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: or 3, 3, 5 ; CHECK-NEXT: or 3, 3, 5
; CHECK-NEXT: rldicl 4, 3, 32, 32 ; CHECK-NEXT: rldicl 4, 3, 32, 32
; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31 ; CHECK-NEXT: rotlwi 5, 3, 24
; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31 ; CHECK-NEXT: rotlwi 6, 4, 24
; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15 ; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31 ; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15 ; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31 ; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31
; CHECK-NEXT: sldi 3, 5, 32 ; CHECK-NEXT: sldi 3, 5, 32
; CHECK-NEXT: or 3, 3, 6 ; CHECK-NEXT: or 3, 3, 6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%res = call i64 @llvm.bitreverse.i64(i64 %arg) %res = call i64 @llvm.bitreverse.i64(i64 %arg)
ret i64 %res ret i64 %res
} }

llvm/test/CodeGen/PowerPC/testComparesi32gtu.ll

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Linesentry:
%call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 signext %conv) #2 %call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 signext %conv) #2
ret i32 undef ret i32 undef
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) { define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: testCompare2: ; CHECK-LABEL: testCompare2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31 ; CHECK-NEXT: clrlwi r3, r3, 31
; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31 ; CHECK-NEXT: clrlwi r4, r4, 31
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32 ; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%and = and i32 %a, 1 %and = and i32 %a, 1
%and1 = and i32 %b, 1 %and1 = and i32 %b, 1
%cmp = icmp ugt i32 %and, %and1 %cmp = icmp ugt i32 %and, %and1
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }

llvm/test/CodeGen/PowerPC/testComparesi32leu.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
define signext i32 @test(i8 zeroext %a, i8 zeroext %b) { define signext i32 @test(i8 zeroext %a, i8 zeroext %b) {
; CHECK-LABEL: test: ; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31 ; CHECK-NEXT: clrlwi r3, r3, 31
; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31 ; CHECK-NEXT: clrlwi r4, r4, 31
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32 ; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub r3, r4, r3 ; CHECK-NEXT: sub r3, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%0 = and i8 %a, 1 %0 = and i8 %a, 1
%1 = and i8 %b, 1 %1 = and i8 %b, 1
%cmp = icmp ule i8 %0, %1 %cmp = icmp ule i8 %0, %1
%conv3 = zext i1 %cmp to i32 %conv3 = zext i1 %cmp to i32
ret i32 %conv3 ret i32 %conv3
} }

llvm/test/CodeGen/PowerPC/testComparesi32ltu.ll

Show First 20 Lines • Show All 66 Lines • ▼ Show 20 Linesentry:
%call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 signext %conv) #2 %call = tail call signext i32 bitcast (i32 (...)* @fn2 to i32 (i32)*)(i32 signext %conv) #2
ret i32 undef ret i32 undef
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) { define signext i32 @testCompare2(i32 zeroext %a, i32 zeroext %b) {
; CHECK-LABEL: testCompare2: ; CHECK-LABEL: testCompare2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: rlwinm r3, r3, 0, 31, 31 ; CHECK-NEXT: clrlwi r3, r3, 31
; CHECK-NEXT: rlwinm r4, r4, 0, 31, 31 ; CHECK-NEXT: clrlwi r4, r4, 31
; CHECK-NEXT: clrldi r3, r3, 32 ; CHECK-NEXT: clrldi r3, r3, 32
; CHECK-NEXT: clrldi r4, r4, 32 ; CHECK-NEXT: clrldi r4, r4, 32
; CHECK-NEXT: sub r3, r3, r4 ; CHECK-NEXT: sub r3, r3, r4
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%and = and i32 %a, 1 %and = and i32 %a, 1
%and1 = and i32 %b, 1 %and1 = and i32 %b, 1
%cmp = icmp ult i32 %and, %and1 %cmp = icmp ult i32 %and, %and1
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }

llvm/test/CodeGen/PowerPC/testComparesigesll.ll

Show All 13 Lines
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll: ; CHECK-BE-LABEL: test_igesll:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63 ; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63 ; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
; CHECK-BE-NEXT: subfc r3, r4, r3 ; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6 ; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesll: ; CHECK-LE-LABEL: test_igesll:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63 ; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63 ; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
; CHECK-LE-NEXT: subfc r3, r4, r3 ; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6 ; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_igesll_sext(i64 %a, i64 %b) { define signext i32 @test_igesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_igesll_sext: ; CHECK-LABEL: test_igesll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_sext: ; CHECK-BE-LABEL: test_igesll_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63 ; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63 ; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
; CHECK-BE-NEXT: subfc r3, r4, r3 ; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6 ; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3 ; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesll_sext: ; CHECK-LE-LABEL: test_igesll_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63 ; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63 ; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
; CHECK-LE-NEXT: subfc r3, r4, r3 ; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6 ; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3 ; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_store: ; CHECK-BE-LABEL: test_igesll_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r3, 63 ; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfc r3, r4, r3 ; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63 ; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3 ; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5) ; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesll_store: ; CHECK-LE-LABEL: test_igesll_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63 ; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r3, r4, r3 ; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63 ; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3 ; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
Show All 10 Lines
; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_igesll_sext_store: ; CHECK-BE-LABEL: test_igesll_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r3, 63 ; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfc r3, r4, r3 ; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63 ; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3 ; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: neg r3, r3 ; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_igesll_sext_store: ; CHECK-LE-LABEL: test_igesll_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63 ; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r3, r4, r3 ; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63 ; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3 ; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3 ; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesigeull.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,BE ; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,LE ; RUN: --check-prefixes=CHECK,LE
@glob = local_unnamed_addr global i64 0, align 8 @glob = local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeull(i64 %a, i64 %b) { define signext i32 @test_igeull(i64 %a, i64 %b) {
; CHECK-LABEL: test_igeull: ; CHECK-LABEL: test_igeull:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: subfe r3, r4, r4 ; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: addi r3, r3, 1 ; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp uge i64 %a, %b %cmp = icmp uge i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igeull_sext(i64 %a, i64 %b) { define signext i32 @test_igeull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_igeull_sext: ; CHECK-LABEL: test_igeull_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: subfe r3, r4, r4 ; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp uge i64 %a, %b %cmp = icmp uge i64 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
Show All 22 Linesentry:
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igeull_store(i64 %a, i64 %b) { define void @test_igeull_store(i64 %a, i64 %b) {
; BE-LABEL: test_igeull_store: ; BE-LABEL: test_igeull_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r3, r4, r3 ; BE-NEXT: subc r3, r3, r4
; BE-NEXT: ld r3, .LC0@toc@l(r5) ; BE-NEXT: ld r3, .LC0@toc@l(r5)
; BE-NEXT: subfe r4, r4, r4 ; BE-NEXT: subfe r4, r4, r4
; BE-NEXT: addi r4, r4, 1 ; BE-NEXT: addi r4, r4, 1
; BE-NEXT: std r4, 0(r3) ; BE-NEXT: std r4, 0(r3)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_igeull_store: ; LE-LABEL: test_igeull_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: subfc r3, r4, r3 ; LE-NEXT: subc r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r4, r4 ; LE-NEXT: subfe r3, r4, r4
; LE-NEXT: addi r3, r3, 1 ; LE-NEXT: addi r3, r3, 1
; LE-NEXT: std r3, glob@toc@l(r5) ; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp uge i64 %a, %b %cmp = icmp uge i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob store i64 %conv1, i64* @glob
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igeull_sext_store(i64 %a, i64 %b) { define void @test_igeull_sext_store(i64 %a, i64 %b) {
; BE-LABEL: test_igeull_sext_store: ; BE-LABEL: test_igeull_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r3, r4, r3 ; BE-NEXT: subc r3, r3, r4
; BE-NEXT: ld r3, .LC0@toc@l(r5) ; BE-NEXT: ld r3, .LC0@toc@l(r5)
; BE-NEXT: subfe r4, r4, r4 ; BE-NEXT: subfe r4, r4, r4
; BE-NEXT: not r4, r4 ; BE-NEXT: not r4, r4
; BE-NEXT: std r4, 0(r3) ; BE-NEXT: std r4, 0(r3)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_igeull_sext_store: ; LE-LABEL: test_igeull_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: subfc r3, r4, r3 ; LE-NEXT: subc r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r4, r4 ; LE-NEXT: subfe r3, r4, r4
; LE-NEXT: not r3, r3 ; LE-NEXT: not r3, r3
; LE-NEXT: std r3, glob@toc@l(r5) ; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp uge i64 %a, %b %cmp = icmp uge i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesigtsll.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i64 0, align 8 @glob = local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsll(i64 %a, i64 %b) { define signext i32 @test_igtsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll: ; CHECK-LABEL: test_igtsll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: subc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r5 ; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_igtsll_sext(i64 %a, i64 %b) { define signext i32 @test_igtsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll_sext: ; CHECK-LABEL: test_igtsll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: subc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r5 ; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
Show All 29 Lines
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igtsll_store(i64 %a, i64 %b) { define void @test_igtsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll_store: ; CHECK-LABEL: test_igtsll_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63 ; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r3, r6 ; CHECK-NEXT: adde r3, r3, r6
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
entry: entry:
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_igtsll_sext_store(i64 %a, i64 %b) { define void @test_igtsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_igtsll_sext_store: ; CHECK-LABEL: test_igtsll_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63 ; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: adde r3, r3, r6 ; CHECK-NEXT: adde r3, r3, r6
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
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llvm/test/CodeGen/PowerPC/testComparesilesll.ll

Show All 13 Lines
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll: ; CHECK-BE-LABEL: test_ilesll:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63 ; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63 ; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
; CHECK-BE-NEXT: subfc r3, r3, r4 ; CHECK-BE-NEXT: subc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6 ; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesll: ; CHECK-LE-LABEL: test_ilesll:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63 ; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63 ; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
; CHECK-LE-NEXT: subfc r3, r3, r4 ; CHECK-LE-NEXT: subc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6 ; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
define signext i32 @test_ilesll_sext(i64 %a, i64 %b) { define signext i32 @test_ilesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_ilesll_sext: ; CHECK-LABEL: test_ilesll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_sext: ; CHECK-BE-LABEL: test_ilesll_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63 ; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63 ; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
; CHECK-BE-NEXT: subfc r3, r3, r4 ; CHECK-BE-NEXT: subc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6 ; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3 ; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesll_sext: ; CHECK-LE-LABEL: test_ilesll_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63 ; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63 ; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
; CHECK-LE-NEXT: subfc r3, r3, r4 ; CHECK-LE-NEXT: subc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6 ; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3 ; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
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; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_store: ; CHECK-BE-LABEL: test_ilesll_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r4, 63 ; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfc r4, r3, r4 ; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3 ; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5) ; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesll_store: ; CHECK-LE-LABEL: test_ilesll_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63 ; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r4, r3, r4 ; CHECK-LE-NEXT: subc r4, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3 ; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
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; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_ilesll_sext_store: ; CHECK-BE-LABEL: test_ilesll_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r4, 63 ; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfc r4, r3, r4 ; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3 ; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: neg r3, r3 ; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_ilesll_sext_store: ; CHECK-LE-LABEL: test_ilesll_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63 ; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r4, r3, r4 ; CHECK-LE-NEXT: subc r4, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3 ; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3 ; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesileull.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,BE ; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,LE ; RUN: --check-prefixes=CHECK,LE
@glob = local_unnamed_addr global i64 0, align 8 @glob = local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileull(i64 %a, i64 %b) { define signext i32 @test_ileull(i64 %a, i64 %b) {
; CHECK-LABEL: test_ileull: ; CHECK-LABEL: test_ileull:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: addi r3, r3, 1 ; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i64 %a, %b %cmp = icmp ule i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_ileull_sext(i64 %a, i64 %b) { define signext i32 @test_ileull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_ileull_sext: ; CHECK-LABEL: test_ileull_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i64 %a, %b %cmp = icmp ule i64 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
} }
Show All 24 Linesentry:
ret i32 %sub ret i32 %sub
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ileull_store(i64 %a, i64 %b) { define void @test_ileull_store(i64 %a, i64 %b) {
; BE-LABEL: test_ileull_store: ; BE-LABEL: test_ileull_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r4, r3, r4 ; BE-NEXT: subc r4, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: subfe r3, r3, r3 ; BE-NEXT: subfe r3, r3, r3
; BE-NEXT: addi r3, r3, 1 ; BE-NEXT: addi r3, r3, 1
; BE-NEXT: std r3, 0(r4) ; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_ileull_store: ; LE-LABEL: test_ileull_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: subfc r4, r3, r4 ; LE-NEXT: subc r4, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r3, r3 ; LE-NEXT: subfe r3, r3, r3
; LE-NEXT: addi r3, r3, 1 ; LE-NEXT: addi r3, r3, 1
; LE-NEXT: std r3, glob@toc@l(r5) ; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i64 %a, %b %cmp = icmp ule i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob store i64 %conv1, i64* @glob
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_ileull_sext_store(i64 %a, i64 %b) { define void @test_ileull_sext_store(i64 %a, i64 %b) {
; BE-LABEL: test_ileull_sext_store: ; BE-LABEL: test_ileull_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r4, r3, r4 ; BE-NEXT: subc r4, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: subfe r3, r3, r3 ; BE-NEXT: subfe r3, r3, r3
; BE-NEXT: not r3, r3 ; BE-NEXT: not r3, r3
; BE-NEXT: std r3, 0(r4) ; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_ileull_sext_store: ; LE-LABEL: test_ileull_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: subfc r4, r3, r4 ; LE-NEXT: subc r4, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r3, r3 ; LE-NEXT: subfe r3, r3, r3
; LE-NEXT: not r3, r3 ; LE-NEXT: not r3, r3
; LE-NEXT: std r3, glob@toc@l(r5) ; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i64 %a, %b %cmp = icmp ule i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesiltsll.ll

Show All 10 Lines
@glob = local_unnamed_addr global i64 0, align 8 @glob = local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsll(i64 %a, i64 %b) { define signext i32 @test_iltsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_iltsll: ; CHECK-LABEL: test_iltsll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: adde r3, r6, r5 ; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
%conv = zext i1 %cmp to i32 %conv = zext i1 %cmp to i32
ret i32 %conv ret i32 %conv
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define signext i32 @test_iltsll_sext(i64 %a, i64 %b) { define signext i32 @test_iltsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_iltsll_sext: ; CHECK-LABEL: test_iltsll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: adde r3, r6, r5 ; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
ret i32 %sub ret i32 %sub
Show All 12 Lines
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iltsll_store(i64 %a, i64 %b) { define void @test_iltsll_store(i64 %a, i64 %b) {
; BE-LABEL: test_iltsll_store: ; BE-LABEL: test_iltsll_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63 ; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r3, r4, r3 ; BE-NEXT: subc r3, r3, r4
; BE-NEXT: rldicl r3, r4, 1, 63 ; BE-NEXT: rldicl r3, r4, 1, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6 ; BE-NEXT: adde r3, r3, r6
; BE-NEXT: xori r3, r3, 1 ; BE-NEXT: xori r3, r3, 1
; BE-NEXT: std r3, 0(r4) ; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_iltsll_store: ; LE-LABEL: test_iltsll_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63 ; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfc r3, r4, r3 ; LE-NEXT: subc r3, r3, r4
; LE-NEXT: rldicl r3, r4, 1, 63 ; LE-NEXT: rldicl r3, r4, 1, 63
; LE-NEXT: adde r3, r3, r6 ; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1 ; LE-NEXT: xori r3, r3, 1
; LE-NEXT: std r3, glob@toc@l(r5) ; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
entry: entry:
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_iltsll_sext_store(i64 %a, i64 %b) { define void @test_iltsll_sext_store(i64 %a, i64 %b) {
; BE-LABEL: test_iltsll_sext_store: ; BE-LABEL: test_iltsll_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63 ; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r3, r4, r3 ; BE-NEXT: subc r3, r3, r4
; BE-NEXT: rldicl r3, r4, 1, 63 ; BE-NEXT: rldicl r3, r4, 1, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6 ; BE-NEXT: adde r3, r3, r6
; BE-NEXT: xori r3, r3, 1 ; BE-NEXT: xori r3, r3, 1
; BE-NEXT: neg r3, r3 ; BE-NEXT: neg r3, r3
; BE-NEXT: std r3, 0(r4) ; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_iltsll_sext_store: ; LE-LABEL: test_iltsll_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63 ; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfc r3, r4, r3 ; LE-NEXT: subc r3, r3, r4
; LE-NEXT: rldicl r3, r4, 1, 63 ; LE-NEXT: rldicl r3, r4, 1, 63
; LE-NEXT: adde r3, r3, r6 ; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1 ; LE-NEXT: xori r3, r3, 1
; LE-NEXT: neg r3, r3 ; LE-NEXT: neg r3, r3
; LE-NEXT: std r3, glob@toc@l(r5) ; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
entry: entry:
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llvm/test/CodeGen/PowerPC/testComparesllgesll.ll

Show All 13 Lines
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll: ; CHECK-BE-LABEL: test_llgesll:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63 ; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63 ; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
; CHECK-BE-NEXT: subfc r3, r4, r3 ; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6 ; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesll: ; CHECK-LE-LABEL: test_llgesll:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63 ; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63 ; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
; CHECK-LE-NEXT: subfc r3, r4, r3 ; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6 ; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
define i64 @test_llgesll_sext(i64 %a, i64 %b) { define i64 @test_llgesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgesll_sext: ; CHECK-LABEL: test_llgesll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subfc r3, r4, r3
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll_sext: ; CHECK-BE-LABEL: test_llgesll_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r3, 63 ; CHECK-BE-NEXT: sradi r5, r3, 63
; CHECK-BE-NEXT: rldicl r6, r4, 1, 63 ; CHECK-BE-NEXT: rldicl r6, r4, 1, 63
; CHECK-BE-NEXT: subfc r3, r4, r3 ; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: adde r3, r5, r6 ; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3 ; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesll_sext: ; CHECK-LE-LABEL: test_llgesll_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r3, 63 ; CHECK-LE-NEXT: sradi r5, r3, 63
; CHECK-LE-NEXT: rldicl r6, r4, 1, 63 ; CHECK-LE-NEXT: rldicl r6, r4, 1, 63
; CHECK-LE-NEXT: subfc r3, r4, r3 ; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: adde r3, r5, r6 ; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3 ; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll_store: ; CHECK-BE-LABEL: test_llgesll_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r3, 63 ; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfc r3, r4, r3 ; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63 ; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3 ; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5) ; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesll_store: ; CHECK-LE-LABEL: test_llgesll_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63 ; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r3, r4, r3 ; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63 ; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3 ; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
Show All 10 Lines
; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_llgesll_sext_store: ; CHECK-BE-LABEL: test_llgesll_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r3, 63 ; CHECK-BE-NEXT: sradi r6, r3, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfc r3, r4, r3 ; CHECK-BE-NEXT: subc r3, r3, r4
; CHECK-BE-NEXT: rldicl r3, r4, 1, 63 ; CHECK-BE-NEXT: rldicl r3, r4, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3 ; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: neg r3, r3 ; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_llgesll_sext_store: ; CHECK-LE-LABEL: test_llgesll_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r3, 63 ; CHECK-LE-NEXT: sradi r6, r3, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r3, r4, r3 ; CHECK-LE-NEXT: subc r3, r3, r4
; CHECK-LE-NEXT: rldicl r3, r4, 1, 63 ; CHECK-LE-NEXT: rldicl r3, r4, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3 ; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3 ; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sge i64 %a, %b %cmp = icmp sge i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
▲ Show 20 Lines • Show All 65 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesllgeull.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,BE ; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,LE ; RUN: --check-prefixes=CHECK,LE
@glob = local_unnamed_addr global i64 0, align 8 @glob = local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeull(i64 %a, i64 %b) { define i64 @test_llgeull(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgeull: ; CHECK-LABEL: test_llgeull:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: subfe r3, r4, r4 ; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: addi r3, r3, 1 ; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp uge i64 %a, %b %cmp = icmp uge i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgeull_sext(i64 %a, i64 %b) { define i64 @test_llgeull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgeull_sext: ; CHECK-LABEL: test_llgeull_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: subfe r3, r4, r4 ; CHECK-NEXT: subfe r3, r4, r4
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp uge i64 %a, %b %cmp = icmp uge i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
Show All 22 Linesentry:
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llgeull_store(i64 %a, i64 %b) { define void @test_llgeull_store(i64 %a, i64 %b) {
; BE-LABEL: test_llgeull_store: ; BE-LABEL: test_llgeull_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r3, r4, r3 ; BE-NEXT: subc r3, r3, r4
; BE-NEXT: ld r3, .LC0@toc@l(r5) ; BE-NEXT: ld r3, .LC0@toc@l(r5)
; BE-NEXT: subfe r4, r4, r4 ; BE-NEXT: subfe r4, r4, r4
; BE-NEXT: addi r4, r4, 1 ; BE-NEXT: addi r4, r4, 1
; BE-NEXT: std r4, 0(r3) ; BE-NEXT: std r4, 0(r3)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llgeull_store: ; LE-LABEL: test_llgeull_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: subfc r3, r4, r3 ; LE-NEXT: subc r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r4, r4 ; LE-NEXT: subfe r3, r4, r4
; LE-NEXT: addi r3, r3, 1 ; LE-NEXT: addi r3, r3, 1
; LE-NEXT: std r3, glob@toc@l(r5) ; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp uge i64 %a, %b %cmp = icmp uge i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob store i64 %conv1, i64* @glob
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llgeull_sext_store(i64 %a, i64 %b) { define void @test_llgeull_sext_store(i64 %a, i64 %b) {
; BE-LABEL: test_llgeull_sext_store: ; BE-LABEL: test_llgeull_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r3, r4, r3 ; BE-NEXT: subc r3, r3, r4
; BE-NEXT: ld r3, .LC0@toc@l(r5) ; BE-NEXT: ld r3, .LC0@toc@l(r5)
; BE-NEXT: subfe r4, r4, r4 ; BE-NEXT: subfe r4, r4, r4
; BE-NEXT: not r4, r4 ; BE-NEXT: not r4, r4
; BE-NEXT: std r4, 0(r3) ; BE-NEXT: std r4, 0(r3)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llgeull_sext_store: ; LE-LABEL: test_llgeull_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: subfc r3, r4, r3 ; LE-NEXT: subc r3, r3, r4
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r4, r4 ; LE-NEXT: subfe r3, r4, r4
; LE-NEXT: not r3, r3 ; LE-NEXT: not r3, r3
; LE-NEXT: std r3, glob@toc@l(r5) ; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp uge i64 %a, %b %cmp = icmp uge i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesllgtsll.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -relocation-model=pic -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
@glob = local_unnamed_addr global i64 0, align 8 @glob = local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsll(i64 %a, i64 %b) { define i64 @test_llgtsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll: ; CHECK-LABEL: test_llgtsll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: subc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r5 ; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llgtsll_sext(i64 %a, i64 %b) { define i64 @test_llgtsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll_sext: ; CHECK-LABEL: test_llgtsll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: subc r3, r4, r3
; CHECK-NEXT: adde r3, r6, r5 ; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
Show All 29 Lines
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llgtsll_store(i64 %a, i64 %b) { define void @test_llgtsll_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll_store: ; CHECK-LABEL: test_llgtsll_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63 ; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: adde r3, r3, r6 ; CHECK-NEXT: adde r3, r3, r6
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
entry: entry:
%cmp = icmp sgt i64 %a, %b %cmp = icmp sgt i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llgtsll_sext_store(i64 %a, i64 %b) { define void @test_llgtsll_sext_store(i64 %a, i64 %b) {
; CHECK-LABEL: test_llgtsll_sext_store: ; CHECK-LABEL: test_llgtsll_sext_store:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r6, r4, 63 ; CHECK-NEXT: sradi r6, r4, 63
; CHECK-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: rldicl r3, r3, 1, 63 ; CHECK-NEXT: rldicl r3, r3, 1, 63
; CHECK-NEXT: adde r3, r3, r6 ; CHECK-NEXT: adde r3, r3, r6
; CHECK-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, 0(r4) ; CHECK-NEXT: std r3, 0(r4)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r3, r4
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llvm/test/CodeGen/PowerPC/testCompareslllesll.ll

Show All 14 Lines
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll: ; CHECK-BE-LABEL: test_lllesll:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63 ; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63 ; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
; CHECK-BE-NEXT: subfc r3, r3, r4 ; CHECK-BE-NEXT: subc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6 ; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesll: ; CHECK-LE-LABEL: test_lllesll:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63 ; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63 ; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
; CHECK-LE-NEXT: subfc r3, r3, r4 ; CHECK-LE-NEXT: subc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6 ; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_lllesll_sext(i64 %a, i64 %b) { define i64 @test_lllesll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_lllesll_sext: ; CHECK-LABEL: test_lllesll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r4, 63 ; CHECK-NEXT: sradi r5, r4, 63
; CHECK-NEXT: rldicl r6, r3, 1, 63 ; CHECK-NEXT: rldicl r6, r3, 1, 63
; CHECK-NEXT: subfc r3, r3, r4 ; CHECK-NEXT: subfc r3, r3, r4
; CHECK-NEXT: adde r3, r5, r6 ; CHECK-NEXT: adde r3, r5, r6
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll_sext: ; CHECK-BE-LABEL: test_lllesll_sext:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r5, r4, 63 ; CHECK-BE-NEXT: sradi r5, r4, 63
; CHECK-BE-NEXT: rldicl r6, r3, 1, 63 ; CHECK-BE-NEXT: rldicl r6, r3, 1, 63
; CHECK-BE-NEXT: subfc r3, r3, r4 ; CHECK-BE-NEXT: subc r3, r4, r3
; CHECK-BE-NEXT: adde r3, r5, r6 ; CHECK-BE-NEXT: adde r3, r5, r6
; CHECK-BE-NEXT: neg r3, r3 ; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesll_sext: ; CHECK-LE-LABEL: test_lllesll_sext:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r5, r4, 63 ; CHECK-LE-NEXT: sradi r5, r4, 63
; CHECK-LE-NEXT: rldicl r6, r3, 1, 63 ; CHECK-LE-NEXT: rldicl r6, r3, 1, 63
; CHECK-LE-NEXT: subfc r3, r3, r4 ; CHECK-LE-NEXT: subc r3, r4, r3
; CHECK-LE-NEXT: adde r3, r5, r6 ; CHECK-LE-NEXT: adde r3, r5, r6
; CHECK-LE-NEXT: neg r3, r3 ; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll_store: ; CHECK-BE-LABEL: test_lllesll_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: sradi r6, r4, 63 ; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r5, .LC0@toc@l(r5)
; CHECK-BE-NEXT: subfc r4, r3, r4 ; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: adde r3, r6, r3 ; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: std r3, 0(r5) ; CHECK-BE-NEXT: std r3, 0(r5)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesll_store: ; CHECK-LE-LABEL: test_lllesll_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63 ; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r4, r3, r4 ; CHECK-LE-NEXT: subc r4, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3 ; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
Show All 11 Lines
; CHECK-NEXT: adde r3, r6, r3 ; CHECK-NEXT: adde r3, r6, r3
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: std r3, glob@toc@l(r5) ; CHECK-NEXT: std r3, glob@toc@l(r5)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-BE-LABEL: test_lllesll_sext_store: ; CHECK-BE-LABEL: test_lllesll_sext_store:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: sradi r6, r4, 63 ; CHECK-BE-NEXT: sradi r6, r4, 63
; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha ; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
; CHECK-BE-NEXT: subfc r4, r3, r4 ; CHECK-BE-NEXT: subc r4, r4, r3
; CHECK-BE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5) ; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
; CHECK-BE-NEXT: adde r3, r6, r3 ; CHECK-BE-NEXT: adde r3, r6, r3
; CHECK-BE-NEXT: neg r3, r3 ; CHECK-BE-NEXT: neg r3, r3
; CHECK-BE-NEXT: std r3, 0(r4) ; CHECK-BE-NEXT: std r3, 0(r4)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
; ;
; CHECK-LE-LABEL: test_lllesll_sext_store: ; CHECK-LE-LABEL: test_lllesll_sext_store:
; CHECK-LE: # %bb.0: # %entry ; CHECK-LE: # %bb.0: # %entry
; CHECK-LE-NEXT: sradi r6, r4, 63 ; CHECK-LE-NEXT: sradi r6, r4, 63
; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha ; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
; CHECK-LE-NEXT: subfc r4, r3, r4 ; CHECK-LE-NEXT: subc r4, r4, r3
; CHECK-LE-NEXT: rldicl r3, r3, 1, 63 ; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
; CHECK-LE-NEXT: adde r3, r6, r3 ; CHECK-LE-NEXT: adde r3, r6, r3
; CHECK-LE-NEXT: neg r3, r3 ; CHECK-LE-NEXT: neg r3, r3
; CHECK-LE-NEXT: std r3, glob@toc@l(r5) ; CHECK-LE-NEXT: std r3, glob@toc@l(r5)
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
entry: entry:
%cmp = icmp sle i64 %a, %b %cmp = icmp sle i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
▲ Show 20 Lines • Show All 73 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesllleull.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,BE ; RUN: --check-prefixes=CHECK,BE
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \ ; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s \
; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \ ; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl \
; RUN: --check-prefixes=CHECK,LE ; RUN: --check-prefixes=CHECK,LE
@glob = local_unnamed_addr global i64 0, align 8 @glob = local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llleull(i64 %a, i64 %b) { define i64 @test_llleull(i64 %a, i64 %b) {
; CHECK-LABEL: test_llleull: ; CHECK-LABEL: test_llleull:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: addi r3, r3, 1 ; CHECK-NEXT: addi r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i64 %a, %b %cmp = icmp ule i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llleull_sext(i64 %a, i64 %b) { define i64 @test_llleull_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llleull_sext: ; CHECK-LABEL: test_llleull_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subfc r4, r3, r4 ; CHECK-NEXT: subc r4, r4, r3
; CHECK-NEXT: subfe r3, r3, r3 ; CHECK-NEXT: subfe r3, r3, r3
; CHECK-NEXT: not r3, r3 ; CHECK-NEXT: not r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp ule i64 %a, %b %cmp = icmp ule i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
Show All 24 Linesentry:
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llleull_store(i64 %a, i64 %b) { define void @test_llleull_store(i64 %a, i64 %b) {
; BE-LABEL: test_llleull_store: ; BE-LABEL: test_llleull_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r4, r3, r4 ; BE-NEXT: subc r4, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: subfe r3, r3, r3 ; BE-NEXT: subfe r3, r3, r3
; BE-NEXT: addi r3, r3, 1 ; BE-NEXT: addi r3, r3, 1
; BE-NEXT: std r3, 0(r4) ; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llleull_store: ; LE-LABEL: test_llleull_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: subfc r4, r3, r4 ; LE-NEXT: subc r4, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r3, r3 ; LE-NEXT: subfe r3, r3, r3
; LE-NEXT: addi r3, r3, 1 ; LE-NEXT: addi r3, r3, 1
; LE-NEXT: std r3, glob@toc@l(r5) ; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i64 %a, %b %cmp = icmp ule i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob store i64 %conv1, i64* @glob
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llleull_sext_store(i64 %a, i64 %b) { define void @test_llleull_sext_store(i64 %a, i64 %b) {
; BE-LABEL: test_llleull_sext_store: ; BE-LABEL: test_llleull_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r4, r3, r4 ; BE-NEXT: subc r4, r4, r3
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: subfe r3, r3, r3 ; BE-NEXT: subfe r3, r3, r3
; BE-NEXT: not r3, r3 ; BE-NEXT: not r3, r3
; BE-NEXT: std r3, 0(r4) ; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llleull_sext_store: ; LE-LABEL: test_llleull_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: subfc r4, r3, r4 ; LE-NEXT: subc r4, r4, r3
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfe r3, r3, r3 ; LE-NEXT: subfe r3, r3, r3
; LE-NEXT: not r3, r3 ; LE-NEXT: not r3, r3
; LE-NEXT: std r3, glob@toc@l(r5) ; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
entry: entry:
%cmp = icmp ule i64 %a, %b %cmp = icmp ule i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/testComparesllltsll.ll

Show All 10 Lines
@glob = local_unnamed_addr global i64 0, align 8 @glob = local_unnamed_addr global i64 0, align 8
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llltsll(i64 %a, i64 %b) { define i64 @test_llltsll(i64 %a, i64 %b) {
; CHECK-LABEL: test_llltsll: ; CHECK-LABEL: test_llltsll:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: adde r3, r6, r5 ; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
} }
; Function Attrs: norecurse nounwind readnone ; Function Attrs: norecurse nounwind readnone
define i64 @test_llltsll_sext(i64 %a, i64 %b) { define i64 @test_llltsll_sext(i64 %a, i64 %b) {
; CHECK-LABEL: test_llltsll_sext: ; CHECK-LABEL: test_llltsll_sext:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: sradi r5, r3, 63 ; CHECK-NEXT: sradi r5, r3, 63
; CHECK-NEXT: rldicl r6, r4, 1, 63 ; CHECK-NEXT: rldicl r6, r4, 1, 63
; CHECK-NEXT: subfc r3, r4, r3 ; CHECK-NEXT: subc r3, r3, r4
; CHECK-NEXT: adde r3, r6, r5 ; CHECK-NEXT: adde r3, r6, r5
; CHECK-NEXT: xori r3, r3, 1 ; CHECK-NEXT: xori r3, r3, 1
; CHECK-NEXT: neg r3, r3 ; CHECK-NEXT: neg r3, r3
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
%conv1 = sext i1 %cmp to i64 %conv1 = sext i1 %cmp to i64
ret i64 %conv1 ret i64 %conv1
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} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llltsll_store(i64 %a, i64 %b) { define void @test_llltsll_store(i64 %a, i64 %b) {
; BE-LABEL: test_llltsll_store: ; BE-LABEL: test_llltsll_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63 ; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r3, r4, r3 ; BE-NEXT: subc r3, r3, r4
; BE-NEXT: rldicl r3, r4, 1, 63 ; BE-NEXT: rldicl r3, r4, 1, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6 ; BE-NEXT: adde r3, r3, r6
; BE-NEXT: xori r3, r3, 1 ; BE-NEXT: xori r3, r3, 1
; BE-NEXT: std r3, 0(r4) ; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llltsll_store: ; LE-LABEL: test_llltsll_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63 ; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfc r3, r4, r3 ; LE-NEXT: subc r3, r3, r4
; LE-NEXT: rldicl r3, r4, 1, 63 ; LE-NEXT: rldicl r3, r4, 1, 63
; LE-NEXT: adde r3, r3, r6 ; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1 ; LE-NEXT: xori r3, r3, 1
; LE-NEXT: std r3, glob@toc@l(r5) ; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
entry: entry:
%cmp = icmp slt i64 %a, %b %cmp = icmp slt i64 %a, %b
%conv1 = zext i1 %cmp to i64 %conv1 = zext i1 %cmp to i64
store i64 %conv1, i64* @glob, align 8 store i64 %conv1, i64* @glob, align 8
ret void ret void
} }
; Function Attrs: norecurse nounwind ; Function Attrs: norecurse nounwind
define void @test_llltsll_sext_store(i64 %a, i64 %b) { define void @test_llltsll_sext_store(i64 %a, i64 %b) {
; BE-LABEL: test_llltsll_sext_store: ; BE-LABEL: test_llltsll_sext_store:
; BE: # %bb.0: # %entry ; BE: # %bb.0: # %entry
; BE-NEXT: sradi r6, r3, 63 ; BE-NEXT: sradi r6, r3, 63
; BE-NEXT: addis r5, r2, .LC0@toc@ha ; BE-NEXT: addis r5, r2, .LC0@toc@ha
; BE-NEXT: subfc r3, r4, r3 ; BE-NEXT: subc r3, r3, r4
; BE-NEXT: rldicl r3, r4, 1, 63 ; BE-NEXT: rldicl r3, r4, 1, 63
; BE-NEXT: ld r4, .LC0@toc@l(r5) ; BE-NEXT: ld r4, .LC0@toc@l(r5)
; BE-NEXT: adde r3, r3, r6 ; BE-NEXT: adde r3, r3, r6
; BE-NEXT: xori r3, r3, 1 ; BE-NEXT: xori r3, r3, 1
; BE-NEXT: neg r3, r3 ; BE-NEXT: neg r3, r3
; BE-NEXT: std r3, 0(r4) ; BE-NEXT: std r3, 0(r4)
; BE-NEXT: blr ; BE-NEXT: blr
; ;
; LE-LABEL: test_llltsll_sext_store: ; LE-LABEL: test_llltsll_sext_store:
; LE: # %bb.0: # %entry ; LE: # %bb.0: # %entry
; LE-NEXT: sradi r6, r3, 63 ; LE-NEXT: sradi r6, r3, 63
; LE-NEXT: addis r5, r2, glob@toc@ha ; LE-NEXT: addis r5, r2, glob@toc@ha
; LE-NEXT: subfc r3, r4, r3 ; LE-NEXT: subc r3, r3, r4
; LE-NEXT: rldicl r3, r4, 1, 63 ; LE-NEXT: rldicl r3, r4, 1, 63
; LE-NEXT: adde r3, r3, r6 ; LE-NEXT: adde r3, r3, r6
; LE-NEXT: xori r3, r3, 1 ; LE-NEXT: xori r3, r3, 1
; LE-NEXT: neg r3, r3 ; LE-NEXT: neg r3, r3
; LE-NEXT: std r3, glob@toc@l(r5) ; LE-NEXT: std r3, glob@toc@l(r5)
; LE-NEXT: blr ; LE-NEXT: blr
; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3 ; CHECK-DIAG: subfc [[REG3:r[0-9]+]], r4, r3
entry: entry:
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llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll

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; CHECK-NEXT: stdu r1, -64(r1) ; CHECK-NEXT: stdu r1, -64(r1)
; CHECK-NEXT: mr r29, r5 ; CHECK-NEXT: mr r29, r5
; CHECK-NEXT: mr r30, r3 ; CHECK-NEXT: mr r30, r3
; CHECK-NEXT: extsw r28, r4 ; CHECK-NEXT: extsw r28, r4
; CHECK-NEXT: std r2, 24(r1) ; CHECK-NEXT: std r2, 24(r1)
; CHECK-NEXT: cmpwi r29, 1 ; CHECK-NEXT: cmpwi r29, 1
; CHECK-NEXT: bc 12, lt, .LBB0_3 ; CHECK-NEXT: bc 12, lt, .LBB0_3
; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: cmpwi cr0, r4, 11 ; CHECK-NEXT: cmpwi r4, 11
; CHECK-NEXT: bc 12, lt, .LBB0_3 ; CHECK-NEXT: bc 12, lt, .LBB0_3
; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_2: # %for.body.us ; CHECK-NEXT: .LBB0_2: # %for.body.us
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: mtctr r30 ; CHECK-NEXT: mtctr r30
; CHECK-NEXT: mr r3, r28 ; CHECK-NEXT: mr r3, r28
; CHECK-NEXT: mr r12, r30 ; CHECK-NEXT: mr r12, r30
; CHECK-NEXT: bctrl ; CHECK-NEXT: bctrl
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llvm/test/CodeGen/PowerPC/trunc-srl-load.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64-unknown-unknown %s -o - | FileCheck %s ; RUN: llc -mtriple=powerpc64-unknown-unknown %s -o - | FileCheck %s
define dso_local fastcc void @trunc_srl_load(i32 zeroext %AttrArgNo) { define dso_local fastcc void @trunc_srl_load(i32 zeroext %AttrArgNo) {
; CHECK-LABEL: trunc_srl_load: ; CHECK-LABEL: trunc_srl_load:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lhz 4, 2(0) ; CHECK-NEXT: lhz 4, 2(0)
; CHECK-NEXT: cmplw 0, 4, 3 ; CHECK-NEXT: cmplw 4, 3
; CHECK-NEXT: ble 0, .LBB0_2 ; CHECK-NEXT: ble 0, .LBB0_2
; CHECK-NEXT: # %bb.1: # %exit ; CHECK-NEXT: # %bb.1: # %exit
; CHECK-NEXT: .LBB0_2: # %cond.false ; CHECK-NEXT: .LBB0_2: # %cond.false
entry: entry:
%bf.load.i = load i64, i64* null, align 8 %bf.load.i = load i64, i64* null, align 8
%bf.lshr.i = lshr i64 %bf.load.i, 32 %bf.lshr.i = lshr i64 %bf.load.i, 32
%0 = trunc i64 %bf.lshr.i to i32 %0 = trunc i64 %bf.lshr.i to i32
%bf.cast.i = and i32 %0, 65535 %bf.cast.i = and i32 %0, 65535
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llvm/test/CodeGen/PowerPC/uint-to-fp-v4i32.ll

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; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \ ; RUN: llc -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \ ; RUN: -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s \
; RUN: -check-prefix=P8LE ; RUN: -check-prefix=P8LE
define dso_local <2 x double> @test1(<8 x i16> %a) { define dso_local <2 x double> @test1(<8 x i16> %a) {
; P9BE-LABEL: test1: ; P9BE-LABEL: test1:
; P9BE: # %bb.0: # %entry ; P9BE: # %bb.0: # %entry
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mtfprwz f0, r3 ; P9BE-NEXT: mtfprwz f0, r3
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: mtfprwz f1, r3 ; P9BE-NEXT: mtfprwz f1, r3
; P9BE-NEXT: xscvuxddp f0, f0 ; P9BE-NEXT: xscvuxddp f0, f0
; P9BE-NEXT: xscvuxddp f1, f1 ; P9BE-NEXT: xscvuxddp f1, f1
; P9BE-NEXT: xxmrghd v2, vs0, vs1 ; P9BE-NEXT: xxmrghd v2, vs0, vs1
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P9LE-LABEL: test1: ; P9LE-LABEL: test1:
; P9LE: # %bb.0: # %entry ; P9LE: # %bb.0: # %entry
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mtfprwz f0, r3 ; P9LE-NEXT: mtfprwz f0, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P9LE-NEXT: clrlwi r3, r3, 16
; P9LE-NEXT: mtfprwz f1, r3 ; P9LE-NEXT: mtfprwz f1, r3
; P9LE-NEXT: xscvuxddp f0, f0 ; P9LE-NEXT: xscvuxddp f0, f0
; P9LE-NEXT: xscvuxddp f1, f1 ; P9LE-NEXT: xscvuxddp f1, f1
; P9LE-NEXT: xxmrghd v2, vs1, vs0 ; P9LE-NEXT: xxmrghd v2, vs1, vs0
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: test1: ; P8BE-LABEL: test1:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: mfvsrd r3, v2 ; P8BE-NEXT: mfvsrd r3, v2
; P8BE-NEXT: rldicl r4, r3, 16, 48 ; P8BE-NEXT: rldicl r4, r3, 16, 48
; P8BE-NEXT: rldicl r3, r3, 32, 48 ; P8BE-NEXT: rldicl r3, r3, 32, 48
; P8BE-NEXT: rlwinm r4, r4, 0, 16, 31 ; P8BE-NEXT: clrlwi r4, r4, 16
; P8BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P8BE-NEXT: clrlwi r3, r3, 16
; P8BE-NEXT: mtfprwz f0, r4 ; P8BE-NEXT: mtfprwz f0, r4
; P8BE-NEXT: mtfprwz f1, r3 ; P8BE-NEXT: mtfprwz f1, r3
; P8BE-NEXT: xscvuxddp f0, f0 ; P8BE-NEXT: xscvuxddp f0, f0
; P8BE-NEXT: xscvuxddp f1, f1 ; P8BE-NEXT: xscvuxddp f1, f1
; P8BE-NEXT: xxmrghd v2, vs0, vs1 ; P8BE-NEXT: xxmrghd v2, vs0, vs1
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: test1: ; P8LE-LABEL: test1:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: mfvsrd r3, f0 ; P8LE-NEXT: mffprd r3, f0
; P8LE-NEXT: clrldi r4, r3, 48 ; P8LE-NEXT: clrldi r4, r3, 48
; P8LE-NEXT: rldicl r3, r3, 48, 48 ; P8LE-NEXT: rldicl r3, r3, 48, 48
; P8LE-NEXT: rlwinm r4, r4, 0, 16, 31 ; P8LE-NEXT: clrlwi r4, r4, 16
; P8LE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P8LE-NEXT: clrlwi r3, r3, 16
; P8LE-NEXT: mtfprwz f0, r4 ; P8LE-NEXT: mtfprwz f0, r4
; P8LE-NEXT: mtfprwz f1, r3 ; P8LE-NEXT: mtfprwz f1, r3
; P8LE-NEXT: xscvuxddp f0, f0 ; P8LE-NEXT: xscvuxddp f0, f0
; P8LE-NEXT: xscvuxddp f1, f1 ; P8LE-NEXT: xscvuxddp f1, f1
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%vecext = extractelement <8 x i16> %a, i32 0 %vecext = extractelement <8 x i16> %a, i32 0
Show All 24 Lines
; P9LE-NEXT: xxmrghd v2, vs1, vs0 ; P9LE-NEXT: xxmrghd v2, vs1, vs0
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P8BE-LABEL: test2: ; P8BE-LABEL: test2:
; P8BE: # %bb.0: # %entry ; P8BE: # %bb.0: # %entry
; P8BE-NEXT: xxsldwi vs0, v2, v2, 3 ; P8BE-NEXT: xxsldwi vs0, v2, v2, 3
; P8BE-NEXT: mfvsrwz r4, v3 ; P8BE-NEXT: mfvsrwz r4, v3
; P8BE-NEXT: mtfprwz f1, r4 ; P8BE-NEXT: mtfprwz f1, r4
; P8BE-NEXT: mfvsrwz r3, f0 ; P8BE-NEXT: mffprwz r3, f0
; P8BE-NEXT: xscvuxddp f1, f1 ; P8BE-NEXT: xscvuxddp f1, f1
; P8BE-NEXT: mtfprwz f0, r3 ; P8BE-NEXT: mtfprwz f0, r3
; P8BE-NEXT: xscvuxddp f0, f0 ; P8BE-NEXT: xscvuxddp f0, f0
; P8BE-NEXT: xxmrghd v2, vs0, vs1 ; P8BE-NEXT: xxmrghd v2, vs0, vs1
; P8BE-NEXT: blr ; P8BE-NEXT: blr
; ;
; P8LE-LABEL: test2: ; P8LE-LABEL: test2:
; P8LE: # %bb.0: # %entry ; P8LE: # %bb.0: # %entry
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: xxsldwi vs1, v3, v3, 1 ; P8LE-NEXT: xxsldwi vs1, v3, v3, 1
; P8LE-NEXT: mfvsrwz r3, f0 ; P8LE-NEXT: mffprwz r3, f0
; P8LE-NEXT: mfvsrwz r4, f1 ; P8LE-NEXT: mffprwz r4, f1
; P8LE-NEXT: mtfprwz f0, r3 ; P8LE-NEXT: mtfprwz f0, r3
; P8LE-NEXT: mtfprwz f1, r4 ; P8LE-NEXT: mtfprwz f1, r4
; P8LE-NEXT: xscvuxddp f0, f0 ; P8LE-NEXT: xscvuxddp f0, f0
; P8LE-NEXT: xscvuxddp f1, f1 ; P8LE-NEXT: xscvuxddp f1, f1
; P8LE-NEXT: xxmrghd v2, vs1, vs0 ; P8LE-NEXT: xxmrghd v2, vs1, vs0
; P8LE-NEXT: blr ; P8LE-NEXT: blr
entry: entry:
%vecext = extractelement <4 x i32> %a, i32 0 %vecext = extractelement <4 x i32> %a, i32 0
%conv = uitofp i32 %vecext to double %conv = uitofp i32 %vecext to double
%vecinit = insertelement <2 x double> undef, double %conv, i32 0 %vecinit = insertelement <2 x double> undef, double %conv, i32 0
%vecext1 = extractelement <4 x i32> %b, i32 1 %vecext1 = extractelement <4 x i32> %b, i32 1
%conv2 = uitofp i32 %vecext1 to double %conv2 = uitofp i32 %vecext1 to double
%vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1 %vecinit3 = insertelement <2 x double> %vecinit, double %conv2, i32 1
ret <2 x double> %vecinit3 ret <2 x double> %vecinit3
} }

llvm/test/CodeGen/PowerPC/urem-vector-lkk.ll

Show All 16 Lines
; P9LE-NEXT: ori r5, r5, 33437 ; P9LE-NEXT: ori r5, r5, 33437
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31 ; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
; P9LE-NEXT: mulld r4, r4, r5 ; P9LE-NEXT: mulld r4, r4, r5
; P9LE-NEXT: lis r5, 16727 ; P9LE-NEXT: lis r5, 16727
; P9LE-NEXT: ori r5, r5, 2287 ; P9LE-NEXT: ori r5, r5, 2287
; P9LE-NEXT: rldicl r4, r4, 27, 37 ; P9LE-NEXT: rldicl r4, r4, 27, 37
; P9LE-NEXT: mulli r4, r4, 98 ; P9LE-NEXT: mulli r4, r4, 98
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31 ; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
; P9LE-NEXT: mulld r4, r4, r5 ; P9LE-NEXT: mulld r4, r4, r5
; P9LE-NEXT: lis r5, 8456 ; P9LE-NEXT: lis r5, 8456
; P9LE-NEXT: ori r5, r5, 16913 ; P9LE-NEXT: ori r5, r5, 16913
; P9LE-NEXT: rldicl r4, r4, 24, 40 ; P9LE-NEXT: rldicl r4, r4, 24, 40
; P9LE-NEXT: mulli r4, r4, 1003 ; P9LE-NEXT: mulli r4, r4, 1003
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0 ; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 30, 18, 31 ; P9LE-NEXT: rlwinm r4, r3, 30, 18, 31
; P9LE-NEXT: mulld r4, r4, r5 ; P9LE-NEXT: mulld r4, r4, r5
; P9LE-NEXT: rldicl r4, r4, 30, 34 ; P9LE-NEXT: rldicl r4, r4, 30, 34
; P9LE-NEXT: mulli r4, r4, 124 ; P9LE-NEXT: mulli r4, r4, 124
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31 ; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: lis r6, 22765 ; P9LE-NEXT: lis r6, 22765
; P9LE-NEXT: ori r6, r6, 8969 ; P9LE-NEXT: ori r6, r6, 8969
; P9LE-NEXT: vmrglh v3, v4, v3 ; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: clrldi r5, r4, 32 ; P9LE-NEXT: clrldi r5, r4, 32
; P9LE-NEXT: mulld r5, r5, r6 ; P9LE-NEXT: mulld r5, r5, r6
; P9LE-NEXT: rldicl r5, r5, 32, 32 ; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: subf r4, r5, r4 ; P9LE-NEXT: subf r4, r5, r4
; P9LE-NEXT: srwi r4, r4, 1 ; P9LE-NEXT: srwi r4, r4, 1
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: srwi r4, r4, 6 ; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0 ; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v4, v2 ; P9LE-NEXT: vmrglh v2, v4, v2
; P9LE-NEXT: vmrglw v2, v3, v2 ; P9LE-NEXT: vmrglw v2, v3, v2
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: fold_urem_vec_1: ; P9BE-LABEL: fold_urem_vec_1:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: lis r5, 16727 ; P9BE-NEXT: lis r5, 16727
; P9BE-NEXT: ori r5, r5, 2287 ; P9BE-NEXT: ori r5, r5, 2287
; P9BE-NEXT: clrldi r4, r3, 32 ; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5 ; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: lis r5, 21399 ; P9BE-NEXT: lis r5, 21399
; P9BE-NEXT: ori r5, r5, 33437 ; P9BE-NEXT: ori r5, r5, 33437
; P9BE-NEXT: rldicl r4, r4, 24, 40 ; P9BE-NEXT: rldicl r4, r4, 24, 40
; P9BE-NEXT: mulli r4, r4, 1003 ; P9BE-NEXT: mulli r4, r4, 1003
; P9BE-NEXT: subf r3, r4, r3 ; P9BE-NEXT: subf r3, r4, r3
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v3, r3 ; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32 ; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5 ; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: lis r5, 8456 ; P9BE-NEXT: lis r5, 8456
; P9BE-NEXT: ori r5, r5, 16913 ; P9BE-NEXT: ori r5, r5, 16913
; P9BE-NEXT: rldicl r4, r4, 27, 37 ; P9BE-NEXT: rldicl r4, r4, 27, 37
; P9BE-NEXT: mulli r4, r4, 98 ; P9BE-NEXT: mulli r4, r4, 98
; P9BE-NEXT: subf r3, r4, r3 ; P9BE-NEXT: subf r3, r4, r3
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: clrlwi r4, r3, 16 ; P9BE-NEXT: clrlwi r4, r3, 16
; P9BE-NEXT: rlwinm r3, r3, 30, 18, 31 ; P9BE-NEXT: rlwinm r3, r3, 30, 18, 31
; P9BE-NEXT: mulld r3, r3, r5 ; P9BE-NEXT: mulld r3, r3, r5
; P9BE-NEXT: lis r5, 22765 ; P9BE-NEXT: lis r5, 22765
; P9BE-NEXT: ori r5, r5, 8969 ; P9BE-NEXT: ori r5, r5, 8969
; P9BE-NEXT: rldicl r3, r3, 30, 34 ; P9BE-NEXT: rldicl r3, r3, 30, 34
; P9BE-NEXT: mulli r3, r3, 124 ; P9BE-NEXT: mulli r3, r3, 124
; P9BE-NEXT: subf r3, r3, r4 ; P9BE-NEXT: subf r3, r3, r4
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: vmrghh v3, v4, v3 ; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32 ; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5 ; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: rldicl r4, r4, 32, 32 ; P9BE-NEXT: rldicl r4, r4, 32, 32
; P9BE-NEXT: subf r5, r4, r3 ; P9BE-NEXT: subf r5, r4, r3
; P9BE-NEXT: srwi r5, r5, 1 ; P9BE-NEXT: srwi r5, r5, 1
; P9BE-NEXT: add r4, r5, r4 ; P9BE-NEXT: add r4, r5, r4
; P9BE-NEXT: srwi r4, r4, 6 ; P9BE-NEXT: srwi r4, r4, 6
; P9BE-NEXT: mulli r4, r4, 95 ; P9BE-NEXT: mulli r4, r4, 95
; P9BE-NEXT: subf r3, r4, r3 ; P9BE-NEXT: subf r3, r4, r3
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v2, r3 ; P9BE-NEXT: mtvsrd v2, r3
; P9BE-NEXT: vmrghh v2, v2, v4 ; P9BE-NEXT: vmrghh v2, v2, v4
; P9BE-NEXT: vmrghw v2, v2, v3 ; P9BE-NEXT: vmrghw v2, v2, v3
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: fold_urem_vec_1: ; P8LE-LABEL: fold_urem_vec_1:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r3, 22765 ; P8LE-NEXT: lis r3, 22765
; P8LE-NEXT: lis r8, 21399 ; P8LE-NEXT: lis r8, 21399
; P8LE-NEXT: ori r3, r3, 8969 ; P8LE-NEXT: ori r3, r3, 8969
; P8LE-NEXT: ori r8, r8, 33437 ; P8LE-NEXT: ori r8, r8, 33437
; P8LE-NEXT: mfvsrd r4, f0 ; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: clrldi r5, r4, 48 ; P8LE-NEXT: clrldi r5, r4, 48
; P8LE-NEXT: rldicl r9, r4, 32, 48 ; P8LE-NEXT: rldicl r9, r4, 32, 48
; P8LE-NEXT: rlwinm r6, r5, 0, 16, 31 ; P8LE-NEXT: clrlwi r6, r5, 16
; P8LE-NEXT: rldicl r10, r4, 16, 48 ; P8LE-NEXT: rldicl r10, r4, 16, 48
; P8LE-NEXT: rlwinm r11, r9, 0, 16, 31 ; P8LE-NEXT: rlwinm r11, r9, 0, 16, 31
; P8LE-NEXT: clrldi r7, r6, 32 ; P8LE-NEXT: clrldi r7, r6, 32
; P8LE-NEXT: rlwinm r12, r10, 0, 16, 31 ; P8LE-NEXT: rlwinm r12, r10, 0, 16, 31
; P8LE-NEXT: mulld r3, r7, r3 ; P8LE-NEXT: mulld r3, r7, r3
; P8LE-NEXT: lis r7, 16727 ; P8LE-NEXT: lis r7, 16727
; P8LE-NEXT: ori r7, r7, 2287 ; P8LE-NEXT: ori r7, r7, 2287
; P8LE-NEXT: mulld r8, r11, r8 ; P8LE-NEXT: mulld r8, r11, r8
Show All 12 Lines
; P8LE-NEXT: mulli r7, r8, 98 ; P8LE-NEXT: mulli r7, r8, 98
; P8LE-NEXT: srwi r3, r3, 6 ; P8LE-NEXT: srwi r3, r3, 6
; P8LE-NEXT: rldicl r8, r11, 30, 34 ; P8LE-NEXT: rldicl r8, r11, 30, 34
; P8LE-NEXT: mulli r6, r6, 1003 ; P8LE-NEXT: mulli r6, r6, 1003
; P8LE-NEXT: mulli r3, r3, 95 ; P8LE-NEXT: mulli r3, r3, 95
; P8LE-NEXT: mulli r8, r8, 124 ; P8LE-NEXT: mulli r8, r8, 124
; P8LE-NEXT: subf r7, r7, r9 ; P8LE-NEXT: subf r7, r7, r9
; P8LE-NEXT: subf r6, r6, r10 ; P8LE-NEXT: subf r6, r6, r10
; P8LE-NEXT: mtvsrd f0, r7 ; P8LE-NEXT: mtfprd f0, r7
; P8LE-NEXT: subf r3, r3, r5 ; P8LE-NEXT: subf r3, r3, r5
; P8LE-NEXT: subf r4, r8, r4 ; P8LE-NEXT: subf r4, r8, r4
; P8LE-NEXT: mtvsrd f1, r6 ; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: mtvsrd f2, r3 ; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: mtvsrd f3, r4 ; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v3, vs1 ; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2 ; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: xxswapd v5, vs3 ; P8LE-NEXT: xxswapd v5, vs3
; P8LE-NEXT: vmrglh v2, v3, v2 ; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: vmrglh v3, v5, v4 ; P8LE-NEXT: vmrglh v3, v5, v4
; P8LE-NEXT: vmrglw v2, v2, v3 ; P8LE-NEXT: vmrglw v2, v2, v3
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: fold_urem_vec_1: ; P8BE-LABEL: fold_urem_vec_1:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r4, v2 ; P8BE-NEXT: mfvsrd r4, v2
; P8BE-NEXT: lis r3, 22765 ; P8BE-NEXT: lis r3, 22765
; P8BE-NEXT: lis r9, 16727 ; P8BE-NEXT: lis r9, 16727
; P8BE-NEXT: ori r3, r3, 8969 ; P8BE-NEXT: ori r3, r3, 8969
; P8BE-NEXT: ori r9, r9, 2287 ; P8BE-NEXT: ori r9, r9, 2287
; P8BE-NEXT: rldicl r5, r4, 16, 48 ; P8BE-NEXT: rldicl r5, r4, 16, 48
; P8BE-NEXT: clrldi r6, r4, 48 ; P8BE-NEXT: clrldi r6, r4, 48
; P8BE-NEXT: rlwinm r5, r5, 0, 16, 31 ; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: rldicl r7, r4, 48, 48 ; P8BE-NEXT: rldicl r7, r4, 48, 48
; P8BE-NEXT: rlwinm r6, r6, 0, 16, 31 ; P8BE-NEXT: clrlwi r6, r6, 16
; P8BE-NEXT: clrldi r8, r5, 32 ; P8BE-NEXT: clrldi r8, r5, 32
; P8BE-NEXT: rlwinm r7, r7, 0, 16, 31 ; P8BE-NEXT: clrlwi r7, r7, 16
; P8BE-NEXT: mulld r3, r8, r3 ; P8BE-NEXT: mulld r3, r8, r3
; P8BE-NEXT: lis r8, 21399 ; P8BE-NEXT: lis r8, 21399
; P8BE-NEXT: clrldi r10, r6, 32 ; P8BE-NEXT: clrldi r10, r6, 32
; P8BE-NEXT: ori r8, r8, 33437 ; P8BE-NEXT: ori r8, r8, 33437
; P8BE-NEXT: clrldi r11, r7, 32 ; P8BE-NEXT: clrldi r11, r7, 32
; P8BE-NEXT: mulld r9, r10, r9 ; P8BE-NEXT: mulld r9, r10, r9
; P8BE-NEXT: lis r10, 8456 ; P8BE-NEXT: lis r10, 8456
; P8BE-NEXT: rldicl r4, r4, 32, 48 ; P8BE-NEXT: rldicl r4, r4, 32, 48
; P8BE-NEXT: mulld r8, r11, r8 ; P8BE-NEXT: mulld r8, r11, r8
; P8BE-NEXT: ori r10, r10, 16913 ; P8BE-NEXT: ori r10, r10, 16913
; P8BE-NEXT: rlwinm r11, r4, 30, 18, 31 ; P8BE-NEXT: rlwinm r11, r4, 30, 18, 31
; P8BE-NEXT: rldicl r3, r3, 32, 32 ; P8BE-NEXT: rldicl r3, r3, 32, 32
; P8BE-NEXT: rlwinm r4, r4, 0, 16, 31 ; P8BE-NEXT: clrlwi r4, r4, 16
; P8BE-NEXT: mulld r10, r11, r10 ; P8BE-NEXT: mulld r10, r11, r10
; P8BE-NEXT: subf r11, r3, r5 ; P8BE-NEXT: subf r11, r3, r5
; P8BE-NEXT: srwi r11, r11, 1 ; P8BE-NEXT: srwi r11, r11, 1
; P8BE-NEXT: rldicl r9, r9, 24, 40 ; P8BE-NEXT: rldicl r9, r9, 24, 40
; P8BE-NEXT: add r3, r11, r3 ; P8BE-NEXT: add r3, r11, r3
; P8BE-NEXT: rldicl r8, r8, 27, 37 ; P8BE-NEXT: rldicl r8, r8, 27, 37
; P8BE-NEXT: srwi r3, r3, 6 ; P8BE-NEXT: srwi r3, r3, 6
; P8BE-NEXT: mulli r9, r9, 1003 ; P8BE-NEXT: mulli r9, r9, 1003
Show All 21 Lines; P8BE-NEXT: blr
ret <4 x i16> %1 ret <4 x i16> %1
} }
define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) { define <4 x i16> @fold_urem_vec_2(<4 x i16> %x) {
; P9LE-LABEL: fold_urem_vec_2: ; P9LE-LABEL: fold_urem_vec_2:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31 ; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: lis r6, 22765 ; P9LE-NEXT: lis r6, 22765
; P9LE-NEXT: ori r6, r6, 8969 ; P9LE-NEXT: ori r6, r6, 8969
; P9LE-NEXT: clrldi r5, r4, 32 ; P9LE-NEXT: clrldi r5, r4, 32
; P9LE-NEXT: mulld r5, r5, r6 ; P9LE-NEXT: mulld r5, r5, r6
; P9LE-NEXT: rldicl r5, r5, 32, 32 ; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: subf r4, r5, r4 ; P9LE-NEXT: subf r4, r5, r4
; P9LE-NEXT: srwi r4, r4, 1 ; P9LE-NEXT: srwi r4, r4, 1
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: srwi r4, r4, 6 ; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31 ; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: clrldi r5, r4, 32 ; P9LE-NEXT: clrldi r5, r4, 32
; P9LE-NEXT: mulld r5, r5, r6 ; P9LE-NEXT: mulld r5, r5, r6
; P9LE-NEXT: rldicl r5, r5, 32, 32 ; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: subf r4, r5, r4 ; P9LE-NEXT: subf r4, r5, r4
; P9LE-NEXT: srwi r4, r4, 1 ; P9LE-NEXT: srwi r4, r4, 1
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: srwi r4, r4, 6 ; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0 ; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31 ; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: clrldi r5, r4, 32 ; P9LE-NEXT: clrldi r5, r4, 32
; P9LE-NEXT: mulld r5, r5, r6 ; P9LE-NEXT: mulld r5, r5, r6
; P9LE-NEXT: rldicl r5, r5, 32, 32 ; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: subf r4, r5, r4 ; P9LE-NEXT: subf r4, r5, r4
; P9LE-NEXT: srwi r4, r4, 1 ; P9LE-NEXT: srwi r4, r4, 1
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: srwi r4, r4, 6 ; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31 ; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: clrldi r5, r4, 32 ; P9LE-NEXT: clrldi r5, r4, 32
; P9LE-NEXT: mulld r5, r5, r6 ; P9LE-NEXT: mulld r5, r5, r6
; P9LE-NEXT: rldicl r5, r5, 32, 32 ; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: subf r4, r5, r4 ; P9LE-NEXT: subf r4, r5, r4
; P9LE-NEXT: srwi r4, r4, 1 ; P9LE-NEXT: srwi r4, r4, 1
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: srwi r4, r4, 6 ; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: vmrglh v3, v4, v3 ; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0 ; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v2, v4 ; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: fold_urem_vec_2: ; P9BE-LABEL: fold_urem_vec_2:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: lis r5, 22765 ; P9BE-NEXT: lis r5, 22765
; P9BE-NEXT: ori r5, r5, 8969 ; P9BE-NEXT: ori r5, r5, 8969
; P9BE-NEXT: clrldi r4, r3, 32 ; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5 ; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: rldicl r4, r4, 32, 32 ; P9BE-NEXT: rldicl r4, r4, 32, 32
; P9BE-NEXT: subf r6, r4, r3 ; P9BE-NEXT: subf r6, r4, r3
; P9BE-NEXT: srwi r6, r6, 1 ; P9BE-NEXT: srwi r6, r6, 1
; P9BE-NEXT: add r4, r6, r4 ; P9BE-NEXT: add r4, r6, r4
; P9BE-NEXT: srwi r4, r4, 6 ; P9BE-NEXT: srwi r4, r4, 6
; P9BE-NEXT: mulli r4, r4, 95 ; P9BE-NEXT: mulli r4, r4, 95
; P9BE-NEXT: subf r3, r4, r3 ; P9BE-NEXT: subf r3, r4, r3
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v3, r3 ; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32 ; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5 ; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: rldicl r4, r4, 32, 32 ; P9BE-NEXT: rldicl r4, r4, 32, 32
; P9BE-NEXT: subf r6, r4, r3 ; P9BE-NEXT: subf r6, r4, r3
; P9BE-NEXT: srwi r6, r6, 1 ; P9BE-NEXT: srwi r6, r6, 1
; P9BE-NEXT: add r4, r6, r4 ; P9BE-NEXT: add r4, r6, r4
; P9BE-NEXT: srwi r4, r4, 6 ; P9BE-NEXT: srwi r4, r4, 6
; P9BE-NEXT: mulli r4, r4, 95 ; P9BE-NEXT: mulli r4, r4, 95
; P9BE-NEXT: subf r3, r4, r3 ; P9BE-NEXT: subf r3, r4, r3
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32 ; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5 ; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: rldicl r4, r4, 32, 32 ; P9BE-NEXT: rldicl r4, r4, 32, 32
; P9BE-NEXT: subf r6, r4, r3 ; P9BE-NEXT: subf r6, r4, r3
; P9BE-NEXT: srwi r6, r6, 1 ; P9BE-NEXT: srwi r6, r6, 1
; P9BE-NEXT: add r4, r6, r4 ; P9BE-NEXT: add r4, r6, r4
; P9BE-NEXT: srwi r4, r4, 6 ; P9BE-NEXT: srwi r4, r4, 6
; P9BE-NEXT: mulli r4, r4, 95 ; P9BE-NEXT: mulli r4, r4, 95
; P9BE-NEXT: subf r3, r4, r3 ; P9BE-NEXT: subf r3, r4, r3
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: vmrghh v3, v4, v3 ; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32 ; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5 ; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: rldicl r4, r4, 32, 32 ; P9BE-NEXT: rldicl r4, r4, 32, 32
; P9BE-NEXT: subf r5, r4, r3 ; P9BE-NEXT: subf r5, r4, r3
; P9BE-NEXT: srwi r5, r5, 1 ; P9BE-NEXT: srwi r5, r5, 1
; P9BE-NEXT: add r4, r5, r4 ; P9BE-NEXT: add r4, r5, r4
; P9BE-NEXT: srwi r4, r4, 6 ; P9BE-NEXT: srwi r4, r4, 6
; P9BE-NEXT: mulli r4, r4, 95 ; P9BE-NEXT: mulli r4, r4, 95
; P9BE-NEXT: subf r3, r4, r3 ; P9BE-NEXT: subf r3, r4, r3
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v2, r3 ; P9BE-NEXT: mtvsrd v2, r3
; P9BE-NEXT: vmrghh v2, v2, v4 ; P9BE-NEXT: vmrghh v2, v2, v4
; P9BE-NEXT: vmrghw v2, v2, v3 ; P9BE-NEXT: vmrghw v2, v2, v3
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: fold_urem_vec_2: ; P8LE-LABEL: fold_urem_vec_2:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r4, 22765 ; P8LE-NEXT: lis r4, 22765
; P8LE-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; P8LE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r4, r4, 8969 ; P8LE-NEXT: ori r4, r4, 8969
; P8LE-NEXT: mfvsrd r5, f0 ; P8LE-NEXT: mffprd r5, f0
; P8LE-NEXT: clrldi r3, r5, 48 ; P8LE-NEXT: clrldi r3, r5, 48
; P8LE-NEXT: rldicl r6, r5, 48, 48 ; P8LE-NEXT: rldicl r6, r5, 48, 48
; P8LE-NEXT: rlwinm r8, r3, 0, 16, 31 ; P8LE-NEXT: clrlwi r8, r3, 16
; P8LE-NEXT: rldicl r7, r5, 32, 48 ; P8LE-NEXT: rldicl r7, r5, 32, 48
; P8LE-NEXT: rlwinm r9, r6, 0, 16, 31 ; P8LE-NEXT: clrlwi r9, r6, 16
; P8LE-NEXT: rldicl r5, r5, 16, 48 ; P8LE-NEXT: rldicl r5, r5, 16, 48
; P8LE-NEXT: clrldi r11, r8, 32 ; P8LE-NEXT: clrldi r11, r8, 32
; P8LE-NEXT: rlwinm r10, r7, 0, 16, 31 ; P8LE-NEXT: clrlwi r10, r7, 16
; P8LE-NEXT: rlwinm r12, r5, 0, 16, 31 ; P8LE-NEXT: clrlwi r12, r5, 16
; P8LE-NEXT: mulld r11, r11, r4 ; P8LE-NEXT: mulld r11, r11, r4
; P8LE-NEXT: clrldi r0, r9, 32 ; P8LE-NEXT: clrldi r0, r9, 32
; P8LE-NEXT: clrldi r30, r10, 32 ; P8LE-NEXT: clrldi r30, r10, 32
; P8LE-NEXT: clrldi r29, r12, 32 ; P8LE-NEXT: clrldi r29, r12, 32
; P8LE-NEXT: mulld r0, r0, r4 ; P8LE-NEXT: mulld r0, r0, r4
; P8LE-NEXT: mulld r30, r30, r4 ; P8LE-NEXT: mulld r30, r30, r4
; P8LE-NEXT: mulld r4, r29, r4 ; P8LE-NEXT: mulld r4, r29, r4
; P8LE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; P8LE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
Show All 19 Lines
; P8LE-NEXT: mulli r8, r8, 95 ; P8LE-NEXT: mulli r8, r8, 95
; P8LE-NEXT: srwi r10, r10, 6 ; P8LE-NEXT: srwi r10, r10, 6
; P8LE-NEXT: srwi r4, r4, 6 ; P8LE-NEXT: srwi r4, r4, 6
; P8LE-NEXT: mulli r9, r9, 95 ; P8LE-NEXT: mulli r9, r9, 95
; P8LE-NEXT: mulli r10, r10, 95 ; P8LE-NEXT: mulli r10, r10, 95
; P8LE-NEXT: mulli r4, r4, 95 ; P8LE-NEXT: mulli r4, r4, 95
; P8LE-NEXT: subf r3, r8, r3 ; P8LE-NEXT: subf r3, r8, r3
; P8LE-NEXT: subf r6, r9, r6 ; P8LE-NEXT: subf r6, r9, r6
; P8LE-NEXT: mtvsrd f0, r3 ; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r3, r10, r7 ; P8LE-NEXT: subf r3, r10, r7
; P8LE-NEXT: subf r4, r4, r5 ; P8LE-NEXT: subf r4, r4, r5
; P8LE-NEXT: mtvsrd f1, r6 ; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: mtvsrd f2, r3 ; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: mtvsrd f3, r4 ; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v3, vs1 ; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2 ; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: xxswapd v5, vs3 ; P8LE-NEXT: xxswapd v5, vs3
; P8LE-NEXT: vmrglh v2, v3, v2 ; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: vmrglh v3, v5, v4 ; P8LE-NEXT: vmrglh v3, v5, v4
; P8LE-NEXT: vmrglw v2, v3, v2 ; P8LE-NEXT: vmrglw v2, v3, v2
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: fold_urem_vec_2: ; P8BE-LABEL: fold_urem_vec_2:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r4, v2 ; P8BE-NEXT: mfvsrd r4, v2
; P8BE-NEXT: lis r3, 22765 ; P8BE-NEXT: lis r3, 22765
; P8BE-NEXT: ori r3, r3, 8969 ; P8BE-NEXT: ori r3, r3, 8969
; P8BE-NEXT: clrldi r5, r4, 48 ; P8BE-NEXT: clrldi r5, r4, 48
; P8BE-NEXT: rldicl r6, r4, 48, 48 ; P8BE-NEXT: rldicl r6, r4, 48, 48
; P8BE-NEXT: rlwinm r5, r5, 0, 16, 31 ; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: rldicl r7, r4, 32, 48 ; P8BE-NEXT: rldicl r7, r4, 32, 48
; P8BE-NEXT: rlwinm r6, r6, 0, 16, 31 ; P8BE-NEXT: clrlwi r6, r6, 16
; P8BE-NEXT: clrldi r8, r5, 32 ; P8BE-NEXT: clrldi r8, r5, 32
; P8BE-NEXT: rldicl r4, r4, 16, 48 ; P8BE-NEXT: rldicl r4, r4, 16, 48
; P8BE-NEXT: rlwinm r7, r7, 0, 16, 31 ; P8BE-NEXT: clrlwi r7, r7, 16
; P8BE-NEXT: clrldi r9, r6, 32 ; P8BE-NEXT: clrldi r9, r6, 32
; P8BE-NEXT: mulld r8, r8, r3 ; P8BE-NEXT: mulld r8, r8, r3
; P8BE-NEXT: rlwinm r4, r4, 0, 16, 31 ; P8BE-NEXT: clrlwi r4, r4, 16
; P8BE-NEXT: clrldi r10, r7, 32 ; P8BE-NEXT: clrldi r10, r7, 32
; P8BE-NEXT: mulld r9, r9, r3 ; P8BE-NEXT: mulld r9, r9, r3
; P8BE-NEXT: clrldi r11, r4, 32 ; P8BE-NEXT: clrldi r11, r4, 32
; P8BE-NEXT: mulld r10, r10, r3 ; P8BE-NEXT: mulld r10, r10, r3
; P8BE-NEXT: mulld r3, r11, r3 ; P8BE-NEXT: mulld r3, r11, r3
; P8BE-NEXT: rldicl r8, r8, 32, 32 ; P8BE-NEXT: rldicl r8, r8, 32, 32
; P8BE-NEXT: rldicl r9, r9, 32, 32 ; P8BE-NEXT: rldicl r9, r9, 32, 32
; P8BE-NEXT: subf r11, r8, r5 ; P8BE-NEXT: subf r11, r8, r5
Show All 40 Lines
; Don't fold if we can combine urem with udiv. ; Don't fold if we can combine urem with udiv.
define <4 x i16> @combine_urem_udiv(<4 x i16> %x) { define <4 x i16> @combine_urem_udiv(<4 x i16> %x) {
; P9LE-LABEL: combine_urem_udiv: ; P9LE-LABEL: combine_urem_udiv:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31 ; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: lis r6, 22765 ; P9LE-NEXT: lis r6, 22765
; P9LE-NEXT: ori r6, r6, 8969 ; P9LE-NEXT: ori r6, r6, 8969
; P9LE-NEXT: clrldi r5, r4, 32 ; P9LE-NEXT: clrldi r5, r4, 32
; P9LE-NEXT: mulld r5, r5, r6 ; P9LE-NEXT: mulld r5, r5, r6
; P9LE-NEXT: rldicl r5, r5, 32, 32 ; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: subf r4, r5, r4 ; P9LE-NEXT: subf r4, r5, r4
; P9LE-NEXT: srwi r4, r4, 1 ; P9LE-NEXT: srwi r4, r4, 1
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: srwi r4, r4, 6 ; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r5, r4, 95 ; P9LE-NEXT: mulli r5, r4, 95
; P9LE-NEXT: subf r3, r5, r3 ; P9LE-NEXT: subf r3, r5, r3
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r5, r3, 0, 16, 31 ; P9LE-NEXT: clrlwi r5, r3, 16
; P9LE-NEXT: clrldi r7, r5, 32 ; P9LE-NEXT: clrldi r7, r5, 32
; P9LE-NEXT: mulld r7, r7, r6 ; P9LE-NEXT: mulld r7, r7, r6
; P9LE-NEXT: rldicl r7, r7, 32, 32 ; P9LE-NEXT: rldicl r7, r7, 32, 32
; P9LE-NEXT: subf r5, r7, r5 ; P9LE-NEXT: subf r5, r7, r5
; P9LE-NEXT: srwi r5, r5, 1 ; P9LE-NEXT: srwi r5, r5, 1
; P9LE-NEXT: add r5, r5, r7 ; P9LE-NEXT: add r5, r5, r7
; P9LE-NEXT: srwi r5, r5, 6 ; P9LE-NEXT: srwi r5, r5, 6
; P9LE-NEXT: mulli r7, r5, 95 ; P9LE-NEXT: mulli r7, r5, 95
; P9LE-NEXT: subf r3, r7, r3 ; P9LE-NEXT: subf r3, r7, r3
; P9LE-NEXT: xxswapd v3, vs0 ; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r7, r3, 0, 16, 31 ; P9LE-NEXT: clrlwi r7, r3, 16
; P9LE-NEXT: clrldi r8, r7, 32 ; P9LE-NEXT: clrldi r8, r7, 32
; P9LE-NEXT: mulld r8, r8, r6 ; P9LE-NEXT: mulld r8, r8, r6
; P9LE-NEXT: rldicl r8, r8, 32, 32 ; P9LE-NEXT: rldicl r8, r8, 32, 32
; P9LE-NEXT: subf r7, r8, r7 ; P9LE-NEXT: subf r7, r8, r7
; P9LE-NEXT: srwi r7, r7, 1 ; P9LE-NEXT: srwi r7, r7, 1
; P9LE-NEXT: add r7, r7, r8 ; P9LE-NEXT: add r7, r7, r8
; P9LE-NEXT: srwi r7, r7, 6 ; P9LE-NEXT: srwi r7, r7, 6
; P9LE-NEXT: mulli r8, r7, 95 ; P9LE-NEXT: mulli r8, r7, 95
; P9LE-NEXT: subf r3, r8, r3 ; P9LE-NEXT: subf r3, r8, r3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r8, r3, 0, 16, 31 ; P9LE-NEXT: clrlwi r8, r3, 16
; P9LE-NEXT: clrldi r9, r8, 32 ; P9LE-NEXT: clrldi r9, r8, 32
; P9LE-NEXT: mulld r6, r9, r6 ; P9LE-NEXT: mulld r6, r9, r6
; P9LE-NEXT: rldicl r6, r6, 32, 32 ; P9LE-NEXT: rldicl r6, r6, 32, 32
; P9LE-NEXT: subf r8, r6, r8 ; P9LE-NEXT: subf r8, r6, r8
; P9LE-NEXT: srwi r8, r8, 1 ; P9LE-NEXT: srwi r8, r8, 1
; P9LE-NEXT: add r6, r8, r6 ; P9LE-NEXT: add r6, r8, r6
; P9LE-NEXT: srwi r6, r6, 6 ; P9LE-NEXT: srwi r6, r6, 6
; P9LE-NEXT: mulli r8, r6, 95 ; P9LE-NEXT: mulli r8, r6, 95
; P9LE-NEXT: subf r3, r8, r3 ; P9LE-NEXT: subf r3, r8, r3
; P9LE-NEXT: vmrglh v3, v4, v3 ; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0 ; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: mtvsrd f0, r4 ; P9LE-NEXT: mtfprd f0, r4
; P9LE-NEXT: vmrglh v2, v2, v4 ; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: xxswapd v3, vs0 ; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r5 ; P9LE-NEXT: mtfprd f0, r5
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r7 ; P9LE-NEXT: mtfprd f0, r7
; P9LE-NEXT: vmrglh v3, v4, v3 ; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r6 ; P9LE-NEXT: mtfprd f0, r6
; P9LE-NEXT: xxswapd v5, vs0 ; P9LE-NEXT: xxswapd v5, vs0
; P9LE-NEXT: vmrglh v4, v5, v4 ; P9LE-NEXT: vmrglh v4, v5, v4
; P9LE-NEXT: vmrglw v3, v4, v3 ; P9LE-NEXT: vmrglw v3, v4, v3
; P9LE-NEXT: vadduhm v2, v2, v3 ; P9LE-NEXT: vadduhm v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: combine_urem_udiv: ; P9BE-LABEL: combine_urem_udiv:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r4, r3, 0, 16, 31 ; P9BE-NEXT: clrlwi r4, r3, 16
; P9BE-NEXT: lis r6, 22765 ; P9BE-NEXT: lis r6, 22765
; P9BE-NEXT: ori r6, r6, 8969 ; P9BE-NEXT: ori r6, r6, 8969
; P9BE-NEXT: clrldi r5, r4, 32 ; P9BE-NEXT: clrldi r5, r4, 32
; P9BE-NEXT: mulld r5, r5, r6 ; P9BE-NEXT: mulld r5, r5, r6
; P9BE-NEXT: rldicl r5, r5, 32, 32 ; P9BE-NEXT: rldicl r5, r5, 32, 32
; P9BE-NEXT: subf r4, r5, r4 ; P9BE-NEXT: subf r4, r5, r4
; P9BE-NEXT: srwi r4, r4, 1 ; P9BE-NEXT: srwi r4, r4, 1
; P9BE-NEXT: add r4, r4, r5 ; P9BE-NEXT: add r4, r4, r5
; P9BE-NEXT: srwi r4, r4, 6 ; P9BE-NEXT: srwi r4, r4, 6
; P9BE-NEXT: mulli r5, r4, 95 ; P9BE-NEXT: mulli r5, r4, 95
; P9BE-NEXT: subf r3, r5, r3 ; P9BE-NEXT: subf r3, r5, r3
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v3, r3 ; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r5, r3, 0, 16, 31 ; P9BE-NEXT: clrlwi r5, r3, 16
; P9BE-NEXT: clrldi r7, r5, 32 ; P9BE-NEXT: clrldi r7, r5, 32
; P9BE-NEXT: mulld r7, r7, r6 ; P9BE-NEXT: mulld r7, r7, r6
; P9BE-NEXT: rldicl r7, r7, 32, 32 ; P9BE-NEXT: rldicl r7, r7, 32, 32
; P9BE-NEXT: subf r5, r7, r5 ; P9BE-NEXT: subf r5, r7, r5
; P9BE-NEXT: srwi r5, r5, 1 ; P9BE-NEXT: srwi r5, r5, 1
; P9BE-NEXT: add r5, r5, r7 ; P9BE-NEXT: add r5, r5, r7
; P9BE-NEXT: srwi r5, r5, 6 ; P9BE-NEXT: srwi r5, r5, 6
; P9BE-NEXT: mulli r7, r5, 95 ; P9BE-NEXT: mulli r7, r5, 95
; P9BE-NEXT: subf r3, r7, r3 ; P9BE-NEXT: subf r3, r7, r3
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r7, r3, 0, 16, 31 ; P9BE-NEXT: clrlwi r7, r3, 16
; P9BE-NEXT: clrldi r8, r7, 32 ; P9BE-NEXT: clrldi r8, r7, 32
; P9BE-NEXT: mulld r8, r8, r6 ; P9BE-NEXT: mulld r8, r8, r6
; P9BE-NEXT: rldicl r8, r8, 32, 32 ; P9BE-NEXT: rldicl r8, r8, 32, 32
; P9BE-NEXT: subf r7, r8, r7 ; P9BE-NEXT: subf r7, r8, r7
; P9BE-NEXT: srwi r7, r7, 1 ; P9BE-NEXT: srwi r7, r7, 1
; P9BE-NEXT: add r7, r7, r8 ; P9BE-NEXT: add r7, r7, r8
; P9BE-NEXT: srwi r7, r7, 6 ; P9BE-NEXT: srwi r7, r7, 6
; P9BE-NEXT: mulli r8, r7, 95 ; P9BE-NEXT: mulli r8, r7, 95
; P9BE-NEXT: subf r3, r8, r3 ; P9BE-NEXT: subf r3, r8, r3
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: vmrghh v3, v4, v3 ; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r8, r3, 32 ; P9BE-NEXT: clrldi r8, r3, 32
; P9BE-NEXT: mulld r6, r8, r6 ; P9BE-NEXT: mulld r6, r8, r6
; P9BE-NEXT: rldicl r6, r6, 32, 32 ; P9BE-NEXT: rldicl r6, r6, 32, 32
; P9BE-NEXT: subf r8, r6, r3 ; P9BE-NEXT: subf r8, r6, r3
; P9BE-NEXT: srwi r8, r8, 1 ; P9BE-NEXT: srwi r8, r8, 1
; P9BE-NEXT: add r6, r8, r6 ; P9BE-NEXT: add r6, r8, r6
; P9BE-NEXT: srwi r6, r6, 6 ; P9BE-NEXT: srwi r6, r6, 6
; P9BE-NEXT: mulli r8, r6, 95 ; P9BE-NEXT: mulli r8, r6, 95
Show All 18 Lines
; ;
; P8LE-LABEL: combine_urem_udiv: ; P8LE-LABEL: combine_urem_udiv:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r5, 22765 ; P8LE-NEXT: lis r5, 22765
; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P8LE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8LE-NEXT: std r29, -24(r1) # 8-byte Folded Spill ; P8LE-NEXT: std r29, -24(r1) # 8-byte Folded Spill
; P8LE-NEXT: ori r5, r5, 8969 ; P8LE-NEXT: ori r5, r5, 8969
; P8LE-NEXT: mfvsrd r6, f0 ; P8LE-NEXT: mffprd r6, f0
; P8LE-NEXT: clrldi r3, r6, 48 ; P8LE-NEXT: clrldi r3, r6, 48
; P8LE-NEXT: rldicl r4, r6, 48, 48 ; P8LE-NEXT: rldicl r4, r6, 48, 48
; P8LE-NEXT: rldicl r7, r6, 32, 48 ; P8LE-NEXT: rldicl r7, r6, 32, 48
; P8LE-NEXT: rlwinm r8, r3, 0, 16, 31 ; P8LE-NEXT: clrlwi r8, r3, 16
; P8LE-NEXT: rlwinm r9, r4, 0, 16, 31 ; P8LE-NEXT: clrlwi r9, r4, 16
; P8LE-NEXT: rldicl r6, r6, 16, 48 ; P8LE-NEXT: rldicl r6, r6, 16, 48
; P8LE-NEXT: rlwinm r10, r7, 0, 16, 31 ; P8LE-NEXT: clrlwi r10, r7, 16
; P8LE-NEXT: clrldi r11, r8, 32 ; P8LE-NEXT: clrldi r11, r8, 32
; P8LE-NEXT: rlwinm r12, r6, 0, 16, 31 ; P8LE-NEXT: clrlwi r12, r6, 16
; P8LE-NEXT: clrldi r0, r9, 32 ; P8LE-NEXT: clrldi r0, r9, 32
; P8LE-NEXT: clrldi r30, r10, 32 ; P8LE-NEXT: clrldi r30, r10, 32
; P8LE-NEXT: mulld r11, r11, r5 ; P8LE-NEXT: mulld r11, r11, r5
; P8LE-NEXT: clrldi r29, r12, 32 ; P8LE-NEXT: clrldi r29, r12, 32
; P8LE-NEXT: mulld r0, r0, r5 ; P8LE-NEXT: mulld r0, r0, r5
; P8LE-NEXT: mulld r30, r30, r5 ; P8LE-NEXT: mulld r30, r30, r5
; P8LE-NEXT: mulld r5, r29, r5 ; P8LE-NEXT: mulld r5, r29, r5
; P8LE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; P8LE-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
Show All 13 Lines
; P8LE-NEXT: srwi r8, r8, 6 ; P8LE-NEXT: srwi r8, r8, 6
; P8LE-NEXT: add r10, r10, r30 ; P8LE-NEXT: add r10, r10, r30
; P8LE-NEXT: srwi r11, r11, 1 ; P8LE-NEXT: srwi r11, r11, 1
; P8LE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; P8LE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; P8LE-NEXT: srwi r9, r9, 6 ; P8LE-NEXT: srwi r9, r9, 6
; P8LE-NEXT: mulli r12, r8, 95 ; P8LE-NEXT: mulli r12, r8, 95
; P8LE-NEXT: srwi r10, r10, 6 ; P8LE-NEXT: srwi r10, r10, 6
; P8LE-NEXT: add r5, r11, r5 ; P8LE-NEXT: add r5, r11, r5
; P8LE-NEXT: mtvsrd f0, r8 ; P8LE-NEXT: mtfprd f0, r8
; P8LE-NEXT: mulli r8, r9, 95 ; P8LE-NEXT: mulli r8, r9, 95
; P8LE-NEXT: mtvsrd f1, r9 ; P8LE-NEXT: mtfprd f1, r9
; P8LE-NEXT: mulli r9, r10, 95 ; P8LE-NEXT: mulli r9, r10, 95
; P8LE-NEXT: srwi r5, r5, 6 ; P8LE-NEXT: srwi r5, r5, 6
; P8LE-NEXT: mtvsrd f3, r5 ; P8LE-NEXT: mtfprd f3, r5
; P8LE-NEXT: mulli r5, r5, 95 ; P8LE-NEXT: mulli r5, r5, 95
; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v3, vs1 ; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: mtvsrd f2, r10 ; P8LE-NEXT: mtfprd f2, r10
; P8LE-NEXT: subf r3, r12, r3 ; P8LE-NEXT: subf r3, r12, r3
; P8LE-NEXT: xxswapd v6, vs3 ; P8LE-NEXT: xxswapd v6, vs3
; P8LE-NEXT: mtvsrd f0, r3 ; P8LE-NEXT: mtfprd f0, r3
; P8LE-NEXT: subf r3, r9, r7 ; P8LE-NEXT: subf r3, r9, r7
; P8LE-NEXT: subf r4, r8, r4 ; P8LE-NEXT: subf r4, r8, r4
; P8LE-NEXT: xxswapd v1, vs2 ; P8LE-NEXT: xxswapd v1, vs2
; P8LE-NEXT: mtvsrd f4, r3 ; P8LE-NEXT: mtfprd f4, r3
; P8LE-NEXT: subf r3, r5, r6 ; P8LE-NEXT: subf r3, r5, r6
; P8LE-NEXT: mtvsrd f1, r4 ; P8LE-NEXT: mtfprd f1, r4
; P8LE-NEXT: mtvsrd f5, r3 ; P8LE-NEXT: mtfprd f5, r3
; P8LE-NEXT: xxswapd v5, vs4 ; P8LE-NEXT: xxswapd v5, vs4
; P8LE-NEXT: vmrglh v2, v3, v2 ; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: xxswapd v3, vs0 ; P8LE-NEXT: xxswapd v3, vs0
; P8LE-NEXT: xxswapd v4, vs1 ; P8LE-NEXT: xxswapd v4, vs1
; P8LE-NEXT: xxswapd v0, vs5 ; P8LE-NEXT: xxswapd v0, vs5
; P8LE-NEXT: vmrglh v3, v4, v3 ; P8LE-NEXT: vmrglh v3, v4, v3
; P8LE-NEXT: vmrglh v4, v0, v5 ; P8LE-NEXT: vmrglh v4, v0, v5
; P8LE-NEXT: vmrglh v5, v6, v1 ; P8LE-NEXT: vmrglh v5, v6, v1
; P8LE-NEXT: vmrglw v3, v4, v3 ; P8LE-NEXT: vmrglw v3, v4, v3
; P8LE-NEXT: vmrglw v2, v5, v2 ; P8LE-NEXT: vmrglw v2, v5, v2
; P8LE-NEXT: vadduhm v2, v3, v2 ; P8LE-NEXT: vadduhm v2, v3, v2
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: combine_urem_udiv: ; P8BE-LABEL: combine_urem_udiv:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r6, v2 ; P8BE-NEXT: mfvsrd r6, v2
; P8BE-NEXT: lis r5, 22765 ; P8BE-NEXT: lis r5, 22765
; P8BE-NEXT: std r30, -16(r1) # 8-byte Folded Spill ; P8BE-NEXT: std r30, -16(r1) # 8-byte Folded Spill
; P8BE-NEXT: ori r5, r5, 8969 ; P8BE-NEXT: ori r5, r5, 8969
; P8BE-NEXT: clrldi r3, r6, 48 ; P8BE-NEXT: clrldi r3, r6, 48
; P8BE-NEXT: rldicl r4, r6, 48, 48 ; P8BE-NEXT: rldicl r4, r6, 48, 48
; P8BE-NEXT: rlwinm r8, r3, 0, 16, 31 ; P8BE-NEXT: clrlwi r8, r3, 16
; P8BE-NEXT: rldicl r7, r6, 32, 48 ; P8BE-NEXT: rldicl r7, r6, 32, 48
; P8BE-NEXT: rlwinm r9, r4, 0, 16, 31 ; P8BE-NEXT: clrlwi r9, r4, 16
; P8BE-NEXT: rldicl r6, r6, 16, 48 ; P8BE-NEXT: rldicl r6, r6, 16, 48
; P8BE-NEXT: clrldi r11, r8, 32 ; P8BE-NEXT: clrldi r11, r8, 32
; P8BE-NEXT: rlwinm r10, r7, 0, 16, 31 ; P8BE-NEXT: clrlwi r10, r7, 16
; P8BE-NEXT: rlwinm r6, r6, 0, 16, 31 ; P8BE-NEXT: clrlwi r6, r6, 16
; P8BE-NEXT: clrldi r12, r9, 32 ; P8BE-NEXT: clrldi r12, r9, 32
; P8BE-NEXT: mulld r11, r11, r5 ; P8BE-NEXT: mulld r11, r11, r5
; P8BE-NEXT: clrldi r0, r10, 32 ; P8BE-NEXT: clrldi r0, r10, 32
; P8BE-NEXT: clrldi r30, r6, 32 ; P8BE-NEXT: clrldi r30, r6, 32
; P8BE-NEXT: mulld r12, r12, r5 ; P8BE-NEXT: mulld r12, r12, r5
; P8BE-NEXT: mulld r0, r0, r5 ; P8BE-NEXT: mulld r0, r0, r5
; P8BE-NEXT: mulld r5, r30, r5 ; P8BE-NEXT: mulld r5, r30, r5
; P8BE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; P8BE-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
▲ Show 20 Lines • Show All 56 Lines • ▼ Show 20 Lines
} }
; Don't fold for divisors that are a power of two. ; Don't fold for divisors that are a power of two.
define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) { define <4 x i16> @dont_fold_urem_power_of_two(<4 x i16> %x) {
; P9LE-LABEL: dont_fold_urem_power_of_two: ; P9LE-LABEL: dont_fold_urem_power_of_two:
; P9LE: # %bb.0: ; P9LE: # %bb.0:
; P9LE-NEXT: li r3, 0 ; P9LE-NEXT: li r3, 0
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r3, r3, 0, 26, 31 ; P9LE-NEXT: clrlwi r3, r3, 26
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r3, r3, 0, 27, 31 ; P9LE-NEXT: clrlwi r3, r3, 27
; P9LE-NEXT: xxswapd v3, vs0 ; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31 ; P9LE-NEXT: clrlwi r4, r3, 16
; P9LE-NEXT: lis r6, 22765 ; P9LE-NEXT: lis r6, 22765
; P9LE-NEXT: ori r6, r6, 8969 ; P9LE-NEXT: ori r6, r6, 8969
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: vmrglh v3, v4, v3 ; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: clrldi r5, r4, 32 ; P9LE-NEXT: clrldi r5, r4, 32
; P9LE-NEXT: mulld r5, r5, r6 ; P9LE-NEXT: mulld r5, r5, r6
; P9LE-NEXT: rldicl r5, r5, 32, 32 ; P9LE-NEXT: rldicl r5, r5, 32, 32
; P9LE-NEXT: subf r4, r5, r4 ; P9LE-NEXT: subf r4, r5, r4
; P9LE-NEXT: srwi r4, r4, 1 ; P9LE-NEXT: srwi r4, r4, 1
; P9LE-NEXT: add r4, r4, r5 ; P9LE-NEXT: add r4, r4, r5
; P9LE-NEXT: srwi r4, r4, 6 ; P9LE-NEXT: srwi r4, r4, 6
; P9LE-NEXT: mulli r4, r4, 95 ; P9LE-NEXT: mulli r4, r4, 95
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 4 ; P9LE-NEXT: li r3, 4
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r3, r3, 0, 29, 31 ; P9LE-NEXT: clrlwi r3, r3, 29
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0 ; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v2, v4, v2 ; P9LE-NEXT: vmrglh v2, v4, v2
; P9LE-NEXT: vmrglw v2, v2, v3 ; P9LE-NEXT: vmrglw v2, v2, v3
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: dont_fold_urem_power_of_two: ; P9BE-LABEL: dont_fold_urem_power_of_two:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 27, 31 ; P9BE-NEXT: clrlwi r3, r3, 27
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v3, r3 ; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 0 ; P9BE-NEXT: li r3, 0
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 26, 31 ; P9BE-NEXT: clrlwi r3, r3, 26
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: lis r5, 22765 ; P9BE-NEXT: lis r5, 22765
; P9BE-NEXT: ori r5, r5, 8969 ; P9BE-NEXT: ori r5, r5, 8969
; P9BE-NEXT: vmrghh v3, v4, v3 ; P9BE-NEXT: vmrghh v3, v4, v3
; P9BE-NEXT: clrldi r4, r3, 32 ; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5 ; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: rldicl r4, r4, 32, 32 ; P9BE-NEXT: rldicl r4, r4, 32, 32
; P9BE-NEXT: subf r5, r4, r3 ; P9BE-NEXT: subf r5, r4, r3
; P9BE-NEXT: srwi r5, r5, 1 ; P9BE-NEXT: srwi r5, r5, 1
; P9BE-NEXT: add r4, r5, r4 ; P9BE-NEXT: add r4, r5, r4
; P9BE-NEXT: srwi r4, r4, 6 ; P9BE-NEXT: srwi r4, r4, 6
; P9BE-NEXT: mulli r4, r4, 95 ; P9BE-NEXT: mulli r4, r4, 95
; P9BE-NEXT: subf r3, r4, r3 ; P9BE-NEXT: subf r3, r4, r3
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 29, 31 ; P9BE-NEXT: clrlwi r3, r3, 29
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v2, r3 ; P9BE-NEXT: mtvsrd v2, r3
; P9BE-NEXT: vmrghh v2, v2, v4 ; P9BE-NEXT: vmrghh v2, v2, v4
; P9BE-NEXT: vmrghw v2, v3, v2 ; P9BE-NEXT: vmrghw v2, v3, v2
; P9BE-NEXT: blr ; P9BE-NEXT: blr
; ;
; P8LE-LABEL: dont_fold_urem_power_of_two: ; P8LE-LABEL: dont_fold_urem_power_of_two:
; P8LE: # %bb.0: ; P8LE: # %bb.0:
; P8LE-NEXT: xxswapd vs0, v2 ; P8LE-NEXT: xxswapd vs0, v2
; P8LE-NEXT: lis r3, 22765 ; P8LE-NEXT: lis r3, 22765
; P8LE-NEXT: ori r3, r3, 8969 ; P8LE-NEXT: ori r3, r3, 8969
; P8LE-NEXT: mfvsrd r4, f0 ; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r5, r4, 16, 48 ; P8LE-NEXT: rldicl r5, r4, 16, 48
; P8LE-NEXT: rlwinm r6, r5, 0, 16, 31 ; P8LE-NEXT: clrlwi r6, r5, 16
; P8LE-NEXT: clrldi r7, r6, 32 ; P8LE-NEXT: clrldi r7, r6, 32
; P8LE-NEXT: mulld r3, r7, r3 ; P8LE-NEXT: mulld r3, r7, r3
; P8LE-NEXT: rldicl r7, r4, 48, 48 ; P8LE-NEXT: rldicl r7, r4, 48, 48
; P8LE-NEXT: rlwinm r7, r7, 0, 27, 31 ; P8LE-NEXT: clrlwi r7, r7, 27
; P8LE-NEXT: mtvsrd f1, r7 ; P8LE-NEXT: mtfprd f1, r7
; P8LE-NEXT: rldicl r3, r3, 32, 32 ; P8LE-NEXT: rldicl r3, r3, 32, 32
; P8LE-NEXT: xxswapd v3, vs1 ; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: subf r6, r3, r6 ; P8LE-NEXT: subf r6, r3, r6
; P8LE-NEXT: srwi r6, r6, 1 ; P8LE-NEXT: srwi r6, r6, 1
; P8LE-NEXT: add r3, r6, r3 ; P8LE-NEXT: add r3, r6, r3
; P8LE-NEXT: clrldi r6, r4, 48 ; P8LE-NEXT: clrldi r6, r4, 48
; P8LE-NEXT: srwi r3, r3, 6 ; P8LE-NEXT: srwi r3, r3, 6
; P8LE-NEXT: rldicl r4, r4, 32, 48 ; P8LE-NEXT: rldicl r4, r4, 32, 48
; P8LE-NEXT: rlwinm r6, r6, 0, 26, 31 ; P8LE-NEXT: clrlwi r6, r6, 26
; P8LE-NEXT: mulli r3, r3, 95 ; P8LE-NEXT: mulli r3, r3, 95
; P8LE-NEXT: rlwinm r4, r4, 0, 29, 31 ; P8LE-NEXT: clrlwi r4, r4, 29
; P8LE-NEXT: mtvsrd f0, r6 ; P8LE-NEXT: mtfprd f0, r6
; P8LE-NEXT: mtvsrd f3, r4 ; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v5, vs3 ; P8LE-NEXT: xxswapd v5, vs3
; P8LE-NEXT: subf r3, r3, r5 ; P8LE-NEXT: subf r3, r3, r5
; P8LE-NEXT: mtvsrd f2, r3 ; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: vmrglh v2, v3, v2 ; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: xxswapd v4, vs2 ; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: vmrglh v3, v4, v5 ; P8LE-NEXT: vmrglh v3, v4, v5
; P8LE-NEXT: vmrglw v2, v3, v2 ; P8LE-NEXT: vmrglw v2, v3, v2
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: dont_fold_urem_power_of_two: ; P8BE-LABEL: dont_fold_urem_power_of_two:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r4, v2 ; P8BE-NEXT: mfvsrd r4, v2
; P8BE-NEXT: lis r3, 22765 ; P8BE-NEXT: lis r3, 22765
; P8BE-NEXT: ori r3, r3, 8969 ; P8BE-NEXT: ori r3, r3, 8969
; P8BE-NEXT: clrldi r5, r4, 48 ; P8BE-NEXT: clrldi r5, r4, 48
; P8BE-NEXT: rldicl r7, r4, 16, 48 ; P8BE-NEXT: rldicl r7, r4, 16, 48
; P8BE-NEXT: rlwinm r5, r5, 0, 16, 31 ; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: rlwinm r7, r7, 0, 26, 31 ; P8BE-NEXT: clrlwi r7, r7, 26
; P8BE-NEXT: clrldi r6, r5, 32 ; P8BE-NEXT: clrldi r6, r5, 32
; P8BE-NEXT: mulld r3, r6, r3 ; P8BE-NEXT: mulld r3, r6, r3
; P8BE-NEXT: rldicl r3, r3, 32, 32 ; P8BE-NEXT: rldicl r3, r3, 32, 32
; P8BE-NEXT: subf r6, r3, r5 ; P8BE-NEXT: subf r6, r3, r5
; P8BE-NEXT: srwi r6, r6, 1 ; P8BE-NEXT: srwi r6, r6, 1
; P8BE-NEXT: add r3, r6, r3 ; P8BE-NEXT: add r3, r6, r3
; P8BE-NEXT: rldicl r6, r4, 32, 48 ; P8BE-NEXT: rldicl r6, r4, 32, 48
; P8BE-NEXT: srwi r3, r3, 6 ; P8BE-NEXT: srwi r3, r3, 6
; P8BE-NEXT: rldicl r4, r4, 48, 48 ; P8BE-NEXT: rldicl r4, r4, 48, 48
; P8BE-NEXT: rlwinm r6, r6, 0, 27, 31 ; P8BE-NEXT: clrlwi r6, r6, 27
; P8BE-NEXT: mulli r3, r3, 95 ; P8BE-NEXT: mulli r3, r3, 95
; P8BE-NEXT: sldi r6, r6, 48 ; P8BE-NEXT: sldi r6, r6, 48
; P8BE-NEXT: rlwinm r4, r4, 0, 29, 31 ; P8BE-NEXT: clrlwi r4, r4, 29
; P8BE-NEXT: mtvsrd v2, r6 ; P8BE-NEXT: mtvsrd v2, r6
; P8BE-NEXT: sldi r6, r7, 48 ; P8BE-NEXT: sldi r6, r7, 48
; P8BE-NEXT: sldi r4, r4, 48 ; P8BE-NEXT: sldi r4, r4, 48
; P8BE-NEXT: mtvsrd v3, r6 ; P8BE-NEXT: mtvsrd v3, r6
; P8BE-NEXT: mtvsrd v5, r4 ; P8BE-NEXT: mtvsrd v5, r4
; P8BE-NEXT: subf r3, r3, r5 ; P8BE-NEXT: subf r3, r3, r5
; P8BE-NEXT: vmrghh v2, v3, v2 ; P8BE-NEXT: vmrghh v2, v3, v2
; P8BE-NEXT: sldi r3, r3, 48 ; P8BE-NEXT: sldi r3, r3, 48
Show All 18 Lines
; P9LE-NEXT: ori r5, r5, 30865 ; P9LE-NEXT: ori r5, r5, 30865
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31 ; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
; P9LE-NEXT: mulld r4, r4, r6 ; P9LE-NEXT: mulld r4, r4, r6
; P9LE-NEXT: lis r6, 24749 ; P9LE-NEXT: lis r6, 24749
; P9LE-NEXT: ori r6, r6, 47143 ; P9LE-NEXT: ori r6, r6, 47143
; P9LE-NEXT: rldicl r4, r4, 28, 36 ; P9LE-NEXT: rldicl r4, r4, 28, 36
; P9LE-NEXT: mulli r4, r4, 23 ; P9LE-NEXT: mulli r4, r4, 23
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 6 ; P9LE-NEXT: li r3, 6
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31 ; P9LE-NEXT: rlwinm r4, r3, 0, 16, 31
; P9LE-NEXT: mulld r4, r4, r6 ; P9LE-NEXT: mulld r4, r4, r6
; P9LE-NEXT: rldicl r4, r4, 21, 43 ; P9LE-NEXT: rldicl r4, r4, 21, 43
; P9LE-NEXT: mulli r4, r4, 5423 ; P9LE-NEXT: mulli r4, r4, 5423
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v3, vs0 ; P9LE-NEXT: xxswapd v3, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: li r3, 2 ; P9LE-NEXT: li r3, 2
; P9LE-NEXT: vextuhrx r3, r3, v2 ; P9LE-NEXT: vextuhrx r3, r3, v2
; P9LE-NEXT: rlwinm r4, r3, 31, 17, 31 ; P9LE-NEXT: rlwinm r4, r3, 31, 17, 31
; P9LE-NEXT: mulld r4, r4, r5 ; P9LE-NEXT: mulld r4, r4, r5
; P9LE-NEXT: rldicl r4, r4, 24, 40 ; P9LE-NEXT: rldicl r4, r4, 24, 40
; P9LE-NEXT: mulli r4, r4, 654 ; P9LE-NEXT: mulli r4, r4, 654
; P9LE-NEXT: subf r3, r4, r3 ; P9LE-NEXT: subf r3, r4, r3
; P9LE-NEXT: xxswapd v4, vs0 ; P9LE-NEXT: xxswapd v4, vs0
; P9LE-NEXT: mtvsrd f0, r3 ; P9LE-NEXT: mtfprd f0, r3
; P9LE-NEXT: xxswapd v2, vs0 ; P9LE-NEXT: xxswapd v2, vs0
; P9LE-NEXT: vmrglh v3, v4, v3 ; P9LE-NEXT: vmrglh v3, v4, v3
; P9LE-NEXT: xxlxor v4, v4, v4 ; P9LE-NEXT: xxlxor v4, v4, v4
; P9LE-NEXT: vmrglh v2, v2, v4 ; P9LE-NEXT: vmrglh v2, v2, v4
; P9LE-NEXT: vmrglw v2, v3, v2 ; P9LE-NEXT: vmrglw v2, v3, v2
; P9LE-NEXT: blr ; P9LE-NEXT: blr
; ;
; P9BE-LABEL: dont_fold_urem_one: ; P9BE-LABEL: dont_fold_urem_one:
; P9BE: # %bb.0: ; P9BE: # %bb.0:
; P9BE-NEXT: li r3, 6 ; P9BE-NEXT: li r3, 6
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: lis r5, 24749 ; P9BE-NEXT: lis r5, 24749
; P9BE-NEXT: ori r5, r5, 47143 ; P9BE-NEXT: ori r5, r5, 47143
; P9BE-NEXT: clrldi r4, r3, 32 ; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r5 ; P9BE-NEXT: mulld r4, r4, r5
; P9BE-NEXT: li r5, 0 ; P9BE-NEXT: li r5, 0
; P9BE-NEXT: oris r6, r5, 45590 ; P9BE-NEXT: oris r6, r5, 45590
; P9BE-NEXT: oris r5, r5, 51306 ; P9BE-NEXT: oris r5, r5, 51306
; P9BE-NEXT: ori r6, r6, 17097 ; P9BE-NEXT: ori r6, r6, 17097
; P9BE-NEXT: ori r5, r5, 30865 ; P9BE-NEXT: ori r5, r5, 30865
; P9BE-NEXT: rldicl r4, r4, 21, 43 ; P9BE-NEXT: rldicl r4, r4, 21, 43
; P9BE-NEXT: mulli r4, r4, 5423 ; P9BE-NEXT: mulli r4, r4, 5423
; P9BE-NEXT: subf r3, r4, r3 ; P9BE-NEXT: subf r3, r4, r3
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v3, r3 ; P9BE-NEXT: mtvsrd v3, r3
; P9BE-NEXT: li r3, 4 ; P9BE-NEXT: li r3, 4
; P9BE-NEXT: vextuhlx r3, r3, v2 ; P9BE-NEXT: vextuhlx r3, r3, v2
; P9BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; P9BE-NEXT: clrlwi r3, r3, 16
; P9BE-NEXT: clrldi r4, r3, 32 ; P9BE-NEXT: clrldi r4, r3, 32
; P9BE-NEXT: mulld r4, r4, r6 ; P9BE-NEXT: mulld r4, r4, r6
; P9BE-NEXT: rldicl r4, r4, 28, 36 ; P9BE-NEXT: rldicl r4, r4, 28, 36
; P9BE-NEXT: mulli r4, r4, 23 ; P9BE-NEXT: mulli r4, r4, 23
; P9BE-NEXT: subf r3, r4, r3 ; P9BE-NEXT: subf r3, r4, r3
; P9BE-NEXT: sldi r3, r3, 48 ; P9BE-NEXT: sldi r3, r3, 48
; P9BE-NEXT: mtvsrd v4, r3 ; P9BE-NEXT: mtvsrd v4, r3
; P9BE-NEXT: li r3, 2 ; P9BE-NEXT: li r3, 2
Show All 20 Lines
; P8LE-NEXT: li r3, 0 ; P8LE-NEXT: li r3, 0
; P8LE-NEXT: lis r8, 24749 ; P8LE-NEXT: lis r8, 24749
; P8LE-NEXT: xxlxor v5, v5, v5 ; P8LE-NEXT: xxlxor v5, v5, v5
; P8LE-NEXT: oris r5, r3, 45590 ; P8LE-NEXT: oris r5, r3, 45590
; P8LE-NEXT: ori r8, r8, 47143 ; P8LE-NEXT: ori r8, r8, 47143
; P8LE-NEXT: oris r3, r3, 51306 ; P8LE-NEXT: oris r3, r3, 51306
; P8LE-NEXT: ori r5, r5, 17097 ; P8LE-NEXT: ori r5, r5, 17097
; P8LE-NEXT: ori r3, r3, 30865 ; P8LE-NEXT: ori r3, r3, 30865
; P8LE-NEXT: mfvsrd r4, f0 ; P8LE-NEXT: mffprd r4, f0
; P8LE-NEXT: rldicl r6, r4, 32, 48 ; P8LE-NEXT: rldicl r6, r4, 32, 48
; P8LE-NEXT: rldicl r7, r4, 16, 48 ; P8LE-NEXT: rldicl r7, r4, 16, 48
; P8LE-NEXT: rlwinm r9, r6, 0, 16, 31 ; P8LE-NEXT: rlwinm r9, r6, 0, 16, 31
; P8LE-NEXT: rldicl r4, r4, 48, 48 ; P8LE-NEXT: rldicl r4, r4, 48, 48
; P8LE-NEXT: mulld r5, r9, r5 ; P8LE-NEXT: mulld r5, r9, r5
; P8LE-NEXT: rlwinm r9, r7, 0, 16, 31 ; P8LE-NEXT: rlwinm r9, r7, 0, 16, 31
; P8LE-NEXT: mulld r8, r9, r8 ; P8LE-NEXT: mulld r8, r9, r8
; P8LE-NEXT: rlwinm r9, r4, 31, 17, 31 ; P8LE-NEXT: rlwinm r9, r4, 31, 17, 31
; P8LE-NEXT: mulld r3, r9, r3 ; P8LE-NEXT: mulld r3, r9, r3
; P8LE-NEXT: rldicl r5, r5, 28, 36 ; P8LE-NEXT: rldicl r5, r5, 28, 36
; P8LE-NEXT: rldicl r8, r8, 21, 43 ; P8LE-NEXT: rldicl r8, r8, 21, 43
; P8LE-NEXT: mulli r5, r5, 23 ; P8LE-NEXT: mulli r5, r5, 23
; P8LE-NEXT: rldicl r3, r3, 24, 40 ; P8LE-NEXT: rldicl r3, r3, 24, 40
; P8LE-NEXT: mulli r8, r8, 5423 ; P8LE-NEXT: mulli r8, r8, 5423
; P8LE-NEXT: mulli r3, r3, 654 ; P8LE-NEXT: mulli r3, r3, 654
; P8LE-NEXT: subf r5, r5, r6 ; P8LE-NEXT: subf r5, r5, r6
; P8LE-NEXT: subf r6, r8, r7 ; P8LE-NEXT: subf r6, r8, r7
; P8LE-NEXT: mtvsrd f0, r5 ; P8LE-NEXT: mtfprd f0, r5
; P8LE-NEXT: subf r3, r3, r4 ; P8LE-NEXT: subf r3, r3, r4
; P8LE-NEXT: mtvsrd f1, r6 ; P8LE-NEXT: mtfprd f1, r6
; P8LE-NEXT: mtvsrd f2, r3 ; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: xxswapd v2, vs0 ; P8LE-NEXT: xxswapd v2, vs0
; P8LE-NEXT: xxswapd v3, vs1 ; P8LE-NEXT: xxswapd v3, vs1
; P8LE-NEXT: xxswapd v4, vs2 ; P8LE-NEXT: xxswapd v4, vs2
; P8LE-NEXT: vmrglh v2, v3, v2 ; P8LE-NEXT: vmrglh v2, v3, v2
; P8LE-NEXT: vmrglh v3, v4, v5 ; P8LE-NEXT: vmrglh v3, v4, v5
; P8LE-NEXT: vmrglw v2, v2, v3 ; P8LE-NEXT: vmrglw v2, v2, v3
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: dont_fold_urem_one: ; P8BE-LABEL: dont_fold_urem_one:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: mfvsrd r4, v2 ; P8BE-NEXT: mfvsrd r4, v2
; P8BE-NEXT: li r3, 0 ; P8BE-NEXT: li r3, 0
; P8BE-NEXT: lis r8, 24749 ; P8BE-NEXT: lis r8, 24749
; P8BE-NEXT: oris r6, r3, 51306 ; P8BE-NEXT: oris r6, r3, 51306
; P8BE-NEXT: ori r8, r8, 47143 ; P8BE-NEXT: ori r8, r8, 47143
; P8BE-NEXT: oris r3, r3, 45590 ; P8BE-NEXT: oris r3, r3, 45590
; P8BE-NEXT: rldicl r5, r4, 32, 48 ; P8BE-NEXT: rldicl r5, r4, 32, 48
; P8BE-NEXT: clrldi r7, r4, 48 ; P8BE-NEXT: clrldi r7, r4, 48
; P8BE-NEXT: ori r6, r6, 30865 ; P8BE-NEXT: ori r6, r6, 30865
; P8BE-NEXT: ori r3, r3, 17097 ; P8BE-NEXT: ori r3, r3, 17097
; P8BE-NEXT: rldicl r4, r4, 48, 48 ; P8BE-NEXT: rldicl r4, r4, 48, 48
; P8BE-NEXT: rlwinm r9, r5, 31, 17, 31 ; P8BE-NEXT: rlwinm r9, r5, 31, 17, 31
; P8BE-NEXT: rlwinm r7, r7, 0, 16, 31 ; P8BE-NEXT: clrlwi r7, r7, 16
; P8BE-NEXT: rlwinm r5, r5, 0, 16, 31 ; P8BE-NEXT: clrlwi r5, r5, 16
; P8BE-NEXT: rlwinm r4, r4, 0, 16, 31 ; P8BE-NEXT: clrlwi r4, r4, 16
; P8BE-NEXT: mulld r6, r9, r6 ; P8BE-NEXT: mulld r6, r9, r6
; P8BE-NEXT: clrldi r9, r7, 32 ; P8BE-NEXT: clrldi r9, r7, 32
; P8BE-NEXT: mulld r8, r9, r8 ; P8BE-NEXT: mulld r8, r9, r8
; P8BE-NEXT: clrldi r9, r4, 32 ; P8BE-NEXT: clrldi r9, r4, 32
; P8BE-NEXT: mulld r3, r9, r3 ; P8BE-NEXT: mulld r3, r9, r3
; P8BE-NEXT: li r9, 0 ; P8BE-NEXT: li r9, 0
; P8BE-NEXT: rldicl r6, r6, 24, 40 ; P8BE-NEXT: rldicl r6, r6, 24, 40
; P8BE-NEXT: mulli r6, r6, 654 ; P8BE-NEXT: mulli r6, r6, 654
▲ Show 20 Lines • Show All 121 Lines • ▼ Show 20 Lines
; P8LE-NEXT: mfvsrd r6, v2 ; P8LE-NEXT: mfvsrd r6, v2
; P8LE-NEXT: ori r3, r3, 34192 ; P8LE-NEXT: ori r3, r3, 34192
; P8LE-NEXT: ori r4, r4, 28749 ; P8LE-NEXT: ori r4, r4, 28749
; P8LE-NEXT: ori r5, r5, 15432 ; P8LE-NEXT: ori r5, r5, 15432
; P8LE-NEXT: mfvsrd r8, v3 ; P8LE-NEXT: mfvsrd r8, v3
; P8LE-NEXT: sldi r3, r3, 32 ; P8LE-NEXT: sldi r3, r3, 32
; P8LE-NEXT: sldi r4, r4, 32 ; P8LE-NEXT: sldi r4, r4, 32
; P8LE-NEXT: oris r3, r3, 45590 ; P8LE-NEXT: oris r3, r3, 45590
; P8LE-NEXT: mfvsrd r7, f0 ; P8LE-NEXT: mffprd r7, f0
; P8LE-NEXT: sldi r5, r5, 32 ; P8LE-NEXT: sldi r5, r5, 32
; P8LE-NEXT: oris r4, r4, 52170 ; P8LE-NEXT: oris r4, r4, 52170
; P8LE-NEXT: ori r3, r3, 17097 ; P8LE-NEXT: ori r3, r3, 17097
; P8LE-NEXT: oris r5, r5, 1603 ; P8LE-NEXT: oris r5, r5, 1603
; P8LE-NEXT: ori r4, r4, 12109 ; P8LE-NEXT: ori r4, r4, 12109
; P8LE-NEXT: mulhdu r3, r7, r3 ; P8LE-NEXT: mulhdu r3, r7, r3
; P8LE-NEXT: rldicl r9, r6, 63, 1 ; P8LE-NEXT: rldicl r9, r6, 63, 1
; P8LE-NEXT: ori r5, r5, 21445 ; P8LE-NEXT: ori r5, r5, 21445
; P8LE-NEXT: mulhdu r4, r8, r4 ; P8LE-NEXT: mulhdu r4, r8, r4
; P8LE-NEXT: mulhdu r5, r9, r5 ; P8LE-NEXT: mulhdu r5, r9, r5
; P8LE-NEXT: sub r9, r7, r3 ; P8LE-NEXT: sub r9, r7, r3
; P8LE-NEXT: rldicl r9, r9, 63, 1 ; P8LE-NEXT: rldicl r9, r9, 63, 1
; P8LE-NEXT: rldicl r4, r4, 52, 12 ; P8LE-NEXT: rldicl r4, r4, 52, 12
; P8LE-NEXT: add r3, r9, r3 ; P8LE-NEXT: add r3, r9, r3
; P8LE-NEXT: rldicl r5, r5, 57, 7 ; P8LE-NEXT: rldicl r5, r5, 57, 7
; P8LE-NEXT: mulli r4, r4, 5423 ; P8LE-NEXT: mulli r4, r4, 5423
; P8LE-NEXT: rldicl r3, r3, 60, 4 ; P8LE-NEXT: rldicl r3, r3, 60, 4
; P8LE-NEXT: mulli r5, r5, 654 ; P8LE-NEXT: mulli r5, r5, 654
; P8LE-NEXT: mulli r3, r3, 23 ; P8LE-NEXT: mulli r3, r3, 23
; P8LE-NEXT: sub r4, r8, r4 ; P8LE-NEXT: sub r4, r8, r4
; P8LE-NEXT: sub r5, r6, r5 ; P8LE-NEXT: sub r5, r6, r5
; P8LE-NEXT: mtvsrd f0, r4 ; P8LE-NEXT: mtfprd f0, r4
; P8LE-NEXT: sub r3, r7, r3 ; P8LE-NEXT: sub r3, r7, r3
; P8LE-NEXT: li r4, 0 ; P8LE-NEXT: li r4, 0
; P8LE-NEXT: mtvsrd f1, r5 ; P8LE-NEXT: mtfprd f1, r5
; P8LE-NEXT: mtvsrd f2, r3 ; P8LE-NEXT: mtfprd f2, r3
; P8LE-NEXT: mtvsrd f3, r4 ; P8LE-NEXT: mtfprd f3, r4
; P8LE-NEXT: xxmrghd v3, vs0, vs2 ; P8LE-NEXT: xxmrghd v3, vs0, vs2
; P8LE-NEXT: xxmrghd v2, vs1, vs3 ; P8LE-NEXT: xxmrghd v2, vs1, vs3
; P8LE-NEXT: blr ; P8LE-NEXT: blr
; ;
; P8BE-LABEL: dont_fold_urem_i64: ; P8BE-LABEL: dont_fold_urem_i64:
; P8BE: # %bb.0: ; P8BE: # %bb.0:
; P8BE-NEXT: lis r3, 25644 ; P8BE-NEXT: lis r3, 25644
; P8BE-NEXT: lis r4, -16037 ; P8BE-NEXT: lis r4, -16037
; P8BE-NEXT: xxswapd vs0, v3 ; P8BE-NEXT: xxswapd vs0, v3
; P8BE-NEXT: xxswapd vs1, v2 ; P8BE-NEXT: xxswapd vs1, v2
; P8BE-NEXT: lis r5, 25653 ; P8BE-NEXT: lis r5, 25653
; P8BE-NEXT: ori r3, r3, 34192 ; P8BE-NEXT: ori r3, r3, 34192
; P8BE-NEXT: ori r4, r4, 28749 ; P8BE-NEXT: ori r4, r4, 28749
; P8BE-NEXT: mfvsrd r6, v3 ; P8BE-NEXT: mfvsrd r6, v3
; P8BE-NEXT: ori r5, r5, 15432 ; P8BE-NEXT: ori r5, r5, 15432
; P8BE-NEXT: sldi r3, r3, 32 ; P8BE-NEXT: sldi r3, r3, 32
; P8BE-NEXT: sldi r4, r4, 32 ; P8BE-NEXT: sldi r4, r4, 32
; P8BE-NEXT: oris r3, r3, 45590 ; P8BE-NEXT: oris r3, r3, 45590
; P8BE-NEXT: sldi r5, r5, 32 ; P8BE-NEXT: sldi r5, r5, 32
; P8BE-NEXT: mfvsrd r7, f0 ; P8BE-NEXT: mffprd r7, f0
; P8BE-NEXT: oris r4, r4, 52170 ; P8BE-NEXT: oris r4, r4, 52170
; P8BE-NEXT: ori r3, r3, 17097 ; P8BE-NEXT: ori r3, r3, 17097
; P8BE-NEXT: mfvsrd r8, f1 ; P8BE-NEXT: mffprd r8, f1
; P8BE-NEXT: oris r5, r5, 1603 ; P8BE-NEXT: oris r5, r5, 1603
; P8BE-NEXT: ori r4, r4, 12109 ; P8BE-NEXT: ori r4, r4, 12109
; P8BE-NEXT: mulhdu r3, r6, r3 ; P8BE-NEXT: mulhdu r3, r6, r3
; P8BE-NEXT: ori r5, r5, 21445 ; P8BE-NEXT: ori r5, r5, 21445
; P8BE-NEXT: mulhdu r4, r7, r4 ; P8BE-NEXT: mulhdu r4, r7, r4
; P8BE-NEXT: rldicl r9, r8, 63, 1 ; P8BE-NEXT: rldicl r9, r8, 63, 1
; P8BE-NEXT: mulhdu r5, r9, r5 ; P8BE-NEXT: mulhdu r5, r9, r5
; P8BE-NEXT: sub r9, r6, r3 ; P8BE-NEXT: sub r9, r6, r3
; P8BE-NEXT: rldicl r9, r9, 63, 1 ; P8BE-NEXT: rldicl r9, r9, 63, 1
; P8BE-NEXT: rldicl r4, r4, 52, 12 ; P8BE-NEXT: rldicl r4, r4, 52, 12
; P8BE-NEXT: add r3, r9, r3 ; P8BE-NEXT: add r3, r9, r3
; P8BE-NEXT: mulli r4, r4, 5423 ; P8BE-NEXT: mulli r4, r4, 5423
; P8BE-NEXT: rldicl r5, r5, 57, 7 ; P8BE-NEXT: rldicl r5, r5, 57, 7
; P8BE-NEXT: rldicl r3, r3, 60, 4 ; P8BE-NEXT: rldicl r3, r3, 60, 4
; P8BE-NEXT: mulli r5, r5, 654 ; P8BE-NEXT: mulli r5, r5, 654
; P8BE-NEXT: mulli r3, r3, 23 ; P8BE-NEXT: mulli r3, r3, 23
; P8BE-NEXT: sub r4, r7, r4 ; P8BE-NEXT: sub r4, r7, r4
; P8BE-NEXT: mtvsrd f0, r4 ; P8BE-NEXT: mtfprd f0, r4
; P8BE-NEXT: sub r4, r8, r5 ; P8BE-NEXT: sub r4, r8, r5
; P8BE-NEXT: sub r3, r6, r3 ; P8BE-NEXT: sub r3, r6, r3
; P8BE-NEXT: mtvsrd f1, r4 ; P8BE-NEXT: mtfprd f1, r4
; P8BE-NEXT: li r4, 0 ; P8BE-NEXT: li r4, 0
; P8BE-NEXT: mtvsrd f2, r3 ; P8BE-NEXT: mtfprd f2, r3
; P8BE-NEXT: mtvsrd f3, r4 ; P8BE-NEXT: mtfprd f3, r4
; P8BE-NEXT: xxmrghd v3, vs2, vs0 ; P8BE-NEXT: xxmrghd v3, vs2, vs0
; P8BE-NEXT: xxmrghd v2, vs3, vs1 ; P8BE-NEXT: xxmrghd v2, vs3, vs1
; P8BE-NEXT: blr ; P8BE-NEXT: blr
%1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423> %1 = urem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>
ret <4 x i64> %1 ret <4 x i64> %1
} }

llvm/test/CodeGen/PowerPC/vec-min-max.ll

Show First 20 Lines • Show All 240 Lines • ▼ Show 20 Lines
; CHECK-LABEL: invalidv1i128: ; CHECK-LABEL: invalidv1i128:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: mfvsrd 3, 36 ; CHECK-NEXT: mfvsrd 3, 36
; CHECK-NEXT: xxswapd 0, 36 ; CHECK-NEXT: xxswapd 0, 36
; CHECK-NEXT: mfvsrd 4, 34 ; CHECK-NEXT: mfvsrd 4, 34
; CHECK-NEXT: xxswapd 1, 34 ; CHECK-NEXT: xxswapd 1, 34
; CHECK-NEXT: cmpld 4, 3 ; CHECK-NEXT: cmpld 4, 3
; CHECK-NEXT: cmpd 1, 4, 3 ; CHECK-NEXT: cmpd 1, 4, 3
; CHECK-NEXT: mfvsrd 3, 0 ; CHECK-NEXT: mffprd 3, 0
; CHECK-NEXT: crandc 20, 4, 2 ; CHECK-NEXT: crandc 20, 4, 2
; CHECK-NEXT: mfvsrd 4, 1 ; CHECK-NEXT: mffprd 4, 1
; CHECK-NEXT: cmpld 1, 4, 3 ; CHECK-NEXT: cmpld 1, 4, 3
; CHECK-NEXT: bc 12, 20, .LBB12_3 ; CHECK-NEXT: bc 12, 20, .LBB12_3
; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: crand 20, 2, 4 ; CHECK-NEXT: crand 20, 2, 4
; CHECK-NEXT: bc 12, 20, .LBB12_3 ; CHECK-NEXT: bc 12, 20, .LBB12_3
; CHECK-NEXT: # %bb.2: ; CHECK-NEXT: # %bb.2:
; CHECK-NEXT: vmr 2, 4 ; CHECK-NEXT: vmr 2, 4
; CHECK-NEXT: .LBB12_3: ; CHECK-NEXT: .LBB12_3:
; CHECK-NEXT: xxswapd 0, 34 ; CHECK-NEXT: xxswapd 0, 34
; CHECK-NEXT: mfvsrd 4, 34 ; CHECK-NEXT: mfvsrd 4, 34
; CHECK-NEXT: mfvsrd 3, 0 ; CHECK-NEXT: mffprd 3, 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; NOP8VEC-LABEL: invalidv1i128: ; NOP8VEC-LABEL: invalidv1i128:
; NOP8VEC: # %bb.0: ; NOP8VEC: # %bb.0:
; NOP8VEC-NEXT: cmpld 4, 8 ; NOP8VEC-NEXT: cmpld 4, 8
; NOP8VEC-NEXT: cmpd 1, 4, 8 ; NOP8VEC-NEXT: cmpd 1, 4, 8
; NOP8VEC-NEXT: addi 5, 1, -32 ; NOP8VEC-NEXT: addi 5, 1, -32
; NOP8VEC-NEXT: crandc 20, 4, 2 ; NOP8VEC-NEXT: crandc 20, 4, 2
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llvm/test/CodeGen/PowerPC/vec-trunc.ll

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
} }
define void @test2i8(<2 x i8>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) { define void @test2i8(<2 x i8>* nocapture %Sink, <2 x i16>* nocapture readonly %SrcPtr) {
; CHECK-LABEL: test2i8: ; CHECK-LABEL: test2i8:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lvx v2, 0, r4 ; CHECK-NEXT: lvx v2, 0, r4
; CHECK-NEXT: vpkuhum v2, v2, v2 ; CHECK-NEXT: vpkuhum v2, v2, v2
; CHECK-NEXT: xxswapd vs0, v2 ; CHECK-NEXT: xxswapd vs0, v2
; CHECK-NEXT: mfvsrd r4, f0 ; CHECK-NEXT: mffprd r4, f0
; CHECK-NEXT: clrldi r4, r4, 48 ; CHECK-NEXT: clrldi r4, r4, 48
; CHECK-NEXT: sth r4, 0(r3) ; CHECK-NEXT: sth r4, 0(r3)
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; ;
; CHECK-BE-LABEL: test2i8: ; CHECK-BE-LABEL: test2i8:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxvw4x v2, 0, r4 ; CHECK-BE-NEXT: lxvw4x v2, 0, r4
; CHECK-BE-NEXT: addi r5, r1, -16 ; CHECK-BE-NEXT: addi r5, r1, -16
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llvm/test/CodeGen/PowerPC/vec_add_sub_doubleword.ll

Show All 30 Lines
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%result = add <2 x i64> %x, <i64 1, i64 1> %result = add <2 x i64> %x, <i64 1, i64 1>
ret <2 x i64> %result ret <2 x i64> %result
} }
define <2 x i64> @increment_by_val(<2 x i64> %x, i64 %val) nounwind { define <2 x i64> @increment_by_val(<2 x i64> %x, i64 %val) nounwind {
; VSX-LABEL: increment_by_val: ; VSX-LABEL: increment_by_val:
; VSX: # %bb.0: ; VSX: # %bb.0:
; VSX-NEXT: mtvsrd 0, 5 ; VSX-NEXT: mtfprd 0, 5
; VSX-NEXT: xxspltd 35, 0, 0 ; VSX-NEXT: xxspltd 35, 0, 0
; VSX-NEXT: vaddudm 2, 2, 3 ; VSX-NEXT: vaddudm 2, 2, 3
; VSX-NEXT: blr ; VSX-NEXT: blr
; ;
; NOVSX-LABEL: increment_by_val: ; NOVSX-LABEL: increment_by_val:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: addi 3, 1, -16 ; NOVSX-NEXT: addi 3, 1, -16
; NOVSX-NEXT: std 5, -8(1) ; NOVSX-NEXT: std 5, -8(1)
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; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%result = sub <2 x i64> %x, <i64 -1, i64 -1> %result = sub <2 x i64> %x, <i64 -1, i64 -1>
ret <2 x i64> %result ret <2 x i64> %result
} }
define <2 x i64> @decrement_by_val(<2 x i64> %x, i64 %val) nounwind { define <2 x i64> @decrement_by_val(<2 x i64> %x, i64 %val) nounwind {
; VSX-LABEL: decrement_by_val: ; VSX-LABEL: decrement_by_val:
; VSX: # %bb.0: ; VSX: # %bb.0:
; VSX-NEXT: mtvsrd 0, 5 ; VSX-NEXT: mtfprd 0, 5
; VSX-NEXT: xxspltd 35, 0, 0 ; VSX-NEXT: xxspltd 35, 0, 0
; VSX-NEXT: vsubudm 2, 2, 3 ; VSX-NEXT: vsubudm 2, 2, 3
; VSX-NEXT: blr ; VSX-NEXT: blr
; ;
; NOVSX-LABEL: decrement_by_val: ; NOVSX-LABEL: decrement_by_val:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: addi 3, 1, -16 ; NOVSX-NEXT: addi 3, 1, -16
; NOVSX-NEXT: std 5, -8(1) ; NOVSX-NEXT: std 5, -8(1)
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llvm/test/CodeGen/PowerPC/vec_add_sub_quadword.ll

Show All 39 Lines
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%result = add <1 x i128> %x, <i128 1> %result = add <1 x i128> %x, <i128 1>
ret <1 x i128> %result ret <1 x i128> %result
} }
define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind { define <1 x i128> @increment_by_val(<1 x i128> %x, i128 %val) nounwind {
; VSX-LABEL: increment_by_val: ; VSX-LABEL: increment_by_val:
; VSX: # %bb.0: ; VSX: # %bb.0:
; VSX-NEXT: mtvsrd 0, 6 ; VSX-NEXT: mtfprd 0, 6
; VSX-NEXT: mtvsrd 1, 5 ; VSX-NEXT: mtfprd 1, 5
; VSX-NEXT: xxmrghd 35, 1, 0 ; VSX-NEXT: xxmrghd 35, 1, 0
; VSX-NEXT: vadduqm 2, 2, 3 ; VSX-NEXT: vadduqm 2, 2, 3
; VSX-NEXT: blr ; VSX-NEXT: blr
; ;
; NOVSX-LABEL: increment_by_val: ; NOVSX-LABEL: increment_by_val:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: addi 3, 1, -16 ; NOVSX-NEXT: addi 3, 1, -16
; NOVSX-NEXT: std 6, -8(1) ; NOVSX-NEXT: std 6, -8(1)
Show All 33 Lines
; NOVSX-NEXT: blr ; NOVSX-NEXT: blr
%result = sub <1 x i128> %x, <i128 1> %result = sub <1 x i128> %x, <i128 1>
ret <1 x i128> %result ret <1 x i128> %result
} }
define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind { define <1 x i128> @decrement_by_val(<1 x i128> %x, i128 %val) nounwind {
; VSX-LABEL: decrement_by_val: ; VSX-LABEL: decrement_by_val:
; VSX: # %bb.0: ; VSX: # %bb.0:
; VSX-NEXT: mtvsrd 0, 6 ; VSX-NEXT: mtfprd 0, 6
; VSX-NEXT: mtvsrd 1, 5 ; VSX-NEXT: mtfprd 1, 5
; VSX-NEXT: xxmrghd 35, 1, 0 ; VSX-NEXT: xxmrghd 35, 1, 0
; VSX-NEXT: vsubuqm 2, 2, 3 ; VSX-NEXT: vsubuqm 2, 2, 3
; VSX-NEXT: blr ; VSX-NEXT: blr
; ;
; NOVSX-LABEL: decrement_by_val: ; NOVSX-LABEL: decrement_by_val:
; NOVSX: # %bb.0: ; NOVSX: # %bb.0:
; NOVSX-NEXT: addi 3, 1, -16 ; NOVSX-NEXT: addi 3, 1, -16
; NOVSX-NEXT: std 6, -8(1) ; NOVSX-NEXT: std 6, -8(1)
▲ Show 20 Lines • Show All 79 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i16_elts.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P8 ; RUN: FileCheck %s --check-prefix=CHECK-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P9 ; RUN: FileCheck %s --check-prefix=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define i32 @test2elt(i64 %a.coerce) local_unnamed_addr #0 { define i32 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs1 ; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <2 x float> %0 = bitcast i64 %a.coerce to <2 x float>
Show All 11 Lines
; CHECK-P8-NEXT: xxsldwi vs3, v2, v2, 1 ; CHECK-P8-NEXT: xxsldwi vs3, v2, v2, 1
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xscvspdpn f2, vs2 ; CHECK-P8-NEXT: xscvspdpn f2, vs2
; CHECK-P8-NEXT: xscvspdpn f3, vs3 ; CHECK-P8-NEXT: xscvspdpn f3, vs3
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mtvsrd f1, r3 ; CHECK-P8-NEXT: mtfprd f1, r3
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mfvsrwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v4, vs1 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mfvsrwz r3, f3 ; CHECK-P8-NEXT: mffprwz r3, f3
; CHECK-P8-NEXT: mtvsrd f2, r4 ; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: mtvsrd f3, r3 ; CHECK-P8-NEXT: mtfprd f3, r3
; CHECK-P8-NEXT: xxswapd v3, vs2 ; CHECK-P8-NEXT: xxswapd v3, vs2
; CHECK-P8-NEXT: xxswapd v5, vs3 ; CHECK-P8-NEXT: xxswapd v5, vs3
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: vmrglh v3, v4, v5 ; CHECK-P8-NEXT: vmrglh v3, v4, v5
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, v2 ; CHECK-P9-NEXT: xscvspdpn f0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 1 ; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglh v2, v4, v2 ; CHECK-P9-NEXT: vmrglh v2, v4, v2
; CHECK-P9-NEXT: vmrglw v2, v2, v3 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xscvspdpn f0, v2 ; CHECK-BE-NEXT: xscvspdpn f0, v2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1 ; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: vmrghh v2, v4, v2 ; CHECK-BE-NEXT: vmrghh v2, v4, v2
; CHECK-BE-NEXT: vmrghw v2, v2, v3 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = fptoui <4 x float> %a to <4 x i16> %0 = fptoui <4 x float> %a to <4 x i16>
Show All 19 Lines
; CHECK-P8-NEXT: xscvspdpn f3, vs3 ; CHECK-P8-NEXT: xscvspdpn f3, vs3
; CHECK-P8-NEXT: xscvspdpn f5, vs5 ; CHECK-P8-NEXT: xscvspdpn f5, vs5
; CHECK-P8-NEXT: xscvdpsxws f4, f4 ; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvdpsxws f5, f5 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: mfvsrwz r4, f4 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: mfvsrwz r6, f1 ; CHECK-P8-NEXT: mffprwz r6, f1
; CHECK-P8-NEXT: mfvsrwz r5, f0 ; CHECK-P8-NEXT: mffprwz r5, f0
; CHECK-P8-NEXT: mtvsrd f1, r6 ; CHECK-P8-NEXT: mtfprd f1, r6
; CHECK-P8-NEXT: mtvsrd f0, r5 ; CHECK-P8-NEXT: mtfprd f0, r5
; CHECK-P8-NEXT: xxswapd v4, vs1 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1 ; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xscvspdpn f0, v2 ; CHECK-P8-NEXT: xscvspdpn f0, v2
; CHECK-P8-NEXT: mtvsrd f4, r4 ; CHECK-P8-NEXT: mtfprd f4, r4
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: mfvsrwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v1, vs4 ; CHECK-P8-NEXT: xxswapd v1, vs4
; CHECK-P8-NEXT: vmrglh v2, v4, v3 ; CHECK-P8-NEXT: vmrglh v2, v4, v3
; CHECK-P8-NEXT: mtvsrd f2, r4 ; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mfvsrwz r4, f5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xxswapd v5, vs2 ; CHECK-P8-NEXT: xxswapd v5, vs2
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: mtvsrd f1, r3 ; CHECK-P8-NEXT: mtfprd f1, r3
; CHECK-P8-NEXT: mfvsrwz r3, f3 ; CHECK-P8-NEXT: mffprwz r3, f3
; CHECK-P8-NEXT: mtvsrd f3, r4 ; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: xxswapd v4, vs1 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v6, vs3 ; CHECK-P8-NEXT: xxswapd v6, vs3
; CHECK-P8-NEXT: xxswapd v0, vs0 ; CHECK-P8-NEXT: xxswapd v0, vs0
; CHECK-P8-NEXT: vmrglh v3, v3, v4 ; CHECK-P8-NEXT: vmrglh v3, v3, v4
; CHECK-P8-NEXT: vmrglh v4, v0, v5 ; CHECK-P8-NEXT: vmrglh v4, v0, v5
; CHECK-P8-NEXT: vmrglh v5, v1, v6 ; CHECK-P8-NEXT: vmrglh v5, v1, v6
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: lxv vs0, 16(r3) ; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v2, vs2 ; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: xxswapd vs2, vs1 ; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xscvspdpn f2, vs1 ; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglh v3, v3, v4 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0 ; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0 ; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0 ; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5 ; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1 ; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghh v4, v4, v5 ; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-BE-NEXT: vmrghw v3, v4, v3 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd v2, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x float>, <8 x float>* %0, align 32 %a = load <8 x float>, <8 x float>* %0, align 32
Show All 36 Lines
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xxsldwi v3, v4, v4, 1 ; CHECK-P8-NEXT: xxsldwi v3, v4, v4, 1
; CHECK-P8-NEXT: xscvspdpn f10, vs10 ; CHECK-P8-NEXT: xscvspdpn f10, vs10
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvspdpn f9, vs9 ; CHECK-P8-NEXT: xscvspdpn f9, vs9
; CHECK-P8-NEXT: xscvdpsxws f6, f6 ; CHECK-P8-NEXT: xscvdpsxws f6, f6
; CHECK-P8-NEXT: xscvspdpn f12, vs12 ; CHECK-P8-NEXT: xscvspdpn f12, vs12
; CHECK-P8-NEXT: xscvdpsxws f5, f5 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvspdpn f11, vs11 ; CHECK-P8-NEXT: xscvspdpn f11, vs11
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvspdpn v2, v2 ; CHECK-P8-NEXT: xscvspdpn v2, v2
; CHECK-P8-NEXT: xscvdpsxws f8, f8 ; CHECK-P8-NEXT: xscvdpsxws f8, f8
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: mfvsrwz r4, f4 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws f7, f7 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
; CHECK-P8-NEXT: mfvsrwz r6, f2 ; CHECK-P8-NEXT: mffprwz r6, f2
; CHECK-P8-NEXT: xscvspdpn f13, vs13 ; CHECK-P8-NEXT: xscvspdpn f13, vs13
; CHECK-P8-NEXT: xscvspdpn v3, v3 ; CHECK-P8-NEXT: xscvspdpn v3, v3
; CHECK-P8-NEXT: xscvdpsxws f10, f10 ; CHECK-P8-NEXT: xscvdpsxws f10, f10
; CHECK-P8-NEXT: mtvsrd f4, r4 ; CHECK-P8-NEXT: mtfprd f4, r4
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f9, f9 ; CHECK-P8-NEXT: xscvdpsxws f9, f9
; CHECK-P8-NEXT: mtvsrd f2, r6 ; CHECK-P8-NEXT: mtfprd f2, r6
; CHECK-P8-NEXT: mfvsrwz r6, f6 ; CHECK-P8-NEXT: mffprwz r6, f6
; CHECK-P8-NEXT: xscvdpsxws f12, f12 ; CHECK-P8-NEXT: xscvdpsxws f12, f12
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: mfvsrwz r4, f5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xscvdpsxws f11, f11 ; CHECK-P8-NEXT: xscvdpsxws f11, f11
; CHECK-P8-NEXT: xxswapd v4, vs1 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: mtvsrd f6, r6 ; CHECK-P8-NEXT: mtfprd f6, r6
; CHECK-P8-NEXT: mfvsrwz r6, f3 ; CHECK-P8-NEXT: mffprwz r6, f3
; CHECK-P8-NEXT: xscvdpsxws v2, v2 ; CHECK-P8-NEXT: xscvdpsxws v2, v2
; CHECK-P8-NEXT: xxswapd v9, vs6 ; CHECK-P8-NEXT: xxswapd v9, vs6
; CHECK-P8-NEXT: mtvsrd f5, r4 ; CHECK-P8-NEXT: mtfprd f5, r4
; CHECK-P8-NEXT: mfvsrwz r4, f8 ; CHECK-P8-NEXT: mffprwz r4, f8
; CHECK-P8-NEXT: mtvsrd f3, r6 ; CHECK-P8-NEXT: mtfprd f3, r6
; CHECK-P8-NEXT: xxswapd v0, vs5 ; CHECK-P8-NEXT: xxswapd v0, vs5
; CHECK-P8-NEXT: mfvsrwz r6, f7 ; CHECK-P8-NEXT: mffprwz r6, f7
; CHECK-P8-NEXT: xscvdpsxws f13, f13 ; CHECK-P8-NEXT: xscvdpsxws f13, f13
; CHECK-P8-NEXT: xxswapd v5, vs3 ; CHECK-P8-NEXT: xxswapd v5, vs3
; CHECK-P8-NEXT: xscvdpsxws v3, v3 ; CHECK-P8-NEXT: xscvdpsxws v3, v3
; CHECK-P8-NEXT: mtvsrd f8, r4 ; CHECK-P8-NEXT: mtfprd f8, r4
; CHECK-P8-NEXT: mfvsrwz r4, f10 ; CHECK-P8-NEXT: mffprwz r4, f10
; CHECK-P8-NEXT: mtvsrd f7, r6 ; CHECK-P8-NEXT: mtfprd f7, r6
; CHECK-P8-NEXT: mfvsrwz r6, f9 ; CHECK-P8-NEXT: mffprwz r6, f9
; CHECK-P8-NEXT: mtvsrd f10, r4 ; CHECK-P8-NEXT: mtfprd f10, r4
; CHECK-P8-NEXT: mfvsrwz r4, f12 ; CHECK-P8-NEXT: mffprwz r4, f12
; CHECK-P8-NEXT: mtvsrd f9, r6 ; CHECK-P8-NEXT: mtfprd f9, r6
; CHECK-P8-NEXT: xxswapd v6, vs10 ; CHECK-P8-NEXT: xxswapd v6, vs10
; CHECK-P8-NEXT: mfvsrwz r6, f11 ; CHECK-P8-NEXT: mffprwz r6, f11
; CHECK-P8-NEXT: mtvsrd f12, r4 ; CHECK-P8-NEXT: mtfprd f12, r4
; CHECK-P8-NEXT: xxswapd v1, vs9 ; CHECK-P8-NEXT: xxswapd v1, vs9
; CHECK-P8-NEXT: mfvsrwz r4, v2 ; CHECK-P8-NEXT: mfvsrwz r4, v2
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: mtvsrd f11, r6 ; CHECK-P8-NEXT: mtfprd f11, r6
; CHECK-P8-NEXT: mfvsrwz r6, f13 ; CHECK-P8-NEXT: mffprwz r6, f13
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xxswapd v7, vs11 ; CHECK-P8-NEXT: xxswapd v7, vs11
; CHECK-P8-NEXT: mfvsrwz r4, v3 ; CHECK-P8-NEXT: mfvsrwz r4, v3
; CHECK-P8-NEXT: vmrglh v3, v5, v4 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: xxswapd v4, vs7 ; CHECK-P8-NEXT: xxswapd v4, vs7
; CHECK-P8-NEXT: vmrglh v2, v2, v0 ; CHECK-P8-NEXT: vmrglh v2, v2, v0
; CHECK-P8-NEXT: xxswapd v5, vs8 ; CHECK-P8-NEXT: xxswapd v5, vs8
; CHECK-P8-NEXT: xxswapd v0, vs2 ; CHECK-P8-NEXT: xxswapd v0, vs2
; CHECK-P8-NEXT: mtvsrd f13, r6 ; CHECK-P8-NEXT: mtfprd f13, r6
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v8, vs0 ; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: vmrglh v4, v5, v4 ; CHECK-P8-NEXT: vmrglh v4, v5, v4
; CHECK-P8-NEXT: vmrglh v5, v0, v1 ; CHECK-P8-NEXT: vmrglh v5, v0, v1
; CHECK-P8-NEXT: xxswapd v1, vs4 ; CHECK-P8-NEXT: xxswapd v1, vs4
; CHECK-P8-NEXT: vmrglh v0, v7, v6 ; CHECK-P8-NEXT: vmrglh v0, v7, v6
; CHECK-P8-NEXT: xxswapd v6, vs12 ; CHECK-P8-NEXT: xxswapd v6, vs12
; CHECK-P8-NEXT: xxswapd v7, vs13 ; CHECK-P8-NEXT: xxswapd v7, vs13
; CHECK-P8-NEXT: xxswapd v10, vs1 ; CHECK-P8-NEXT: xxswapd v10, vs1
Show All 28 Lines
; CHECK-P9-NEXT: xscvspdpn f6, vs6 ; CHECK-P9-NEXT: xscvspdpn f6, vs6
; CHECK-P9-NEXT: xxsldwi vs3, vs3, vs3, 1 ; CHECK-P9-NEXT: xxsldwi vs3, vs3, vs3, 1
; CHECK-P9-NEXT: xscvspdpn f7, vs7 ; CHECK-P9-NEXT: xscvspdpn f7, vs7
; CHECK-P9-NEXT: xscvspdpn f3, vs3 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f6, f6 ; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: mfvsrwz r5, f5 ; CHECK-P9-NEXT: mffprwz r5, f5
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f7, f7 ; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mtvsrd f5, r5 ; CHECK-P9-NEXT: mtfprd f5, r5
; CHECK-P9-NEXT: mfvsrwz r5, f8 ; CHECK-P9-NEXT: mffprwz r5, f8
; CHECK-P9-NEXT: mtvsrd f8, r5 ; CHECK-P9-NEXT: mtfprd f8, r5
; CHECK-P9-NEXT: mfvsrwz r5, f2 ; CHECK-P9-NEXT: mffprwz r5, f2
; CHECK-P9-NEXT: lxv vs0, 32(r4) ; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: xxsldwi vs9, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi vs9, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd vs10, vs0 ; CHECK-P9-NEXT: xxswapd vs10, vs0
; CHECK-P9-NEXT: xscvspdpn f9, vs9 ; CHECK-P9-NEXT: xscvspdpn f9, vs9
; CHECK-P9-NEXT: xscvspdpn f10, vs10 ; CHECK-P9-NEXT: xscvspdpn f10, vs10
; CHECK-P9-NEXT: xscvdpsxws f9, f9 ; CHECK-P9-NEXT: xscvdpsxws f9, f9
; CHECK-P9-NEXT: xscvdpsxws f10, f10 ; CHECK-P9-NEXT: xscvdpsxws f10, f10
; CHECK-P9-NEXT: mtvsrd f2, r5 ; CHECK-P9-NEXT: mtfprd f2, r5
; CHECK-P9-NEXT: mfvsrwz r5, f4 ; CHECK-P9-NEXT: mffprwz r5, f4
; CHECK-P9-NEXT: mtvsrd f4, r5 ; CHECK-P9-NEXT: mtfprd f4, r5
; CHECK-P9-NEXT: mfvsrwz r5, f1 ; CHECK-P9-NEXT: mffprwz r5, f1
; CHECK-P9-NEXT: mtvsrd f1, r5 ; CHECK-P9-NEXT: mtfprd f1, r5
; CHECK-P9-NEXT: mfvsrwz r5, f6 ; CHECK-P9-NEXT: mffprwz r5, f6
; CHECK-P9-NEXT: xxswapd v2, vs2 ; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: xxswapd v3, vs4 ; CHECK-P9-NEXT: xxswapd v3, vs4
; CHECK-P9-NEXT: xscvspdpn f2, vs0 ; CHECK-P9-NEXT: xscvspdpn f2, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f6, r5 ; CHECK-P9-NEXT: mtfprd f6, r5
; CHECK-P9-NEXT: mfvsrwz r5, f7 ; CHECK-P9-NEXT: mffprwz r5, f7
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: lxv vs1, 48(r4) ; CHECK-P9-NEXT: lxv vs1, 48(r4)
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs5 ; CHECK-P9-NEXT: xxswapd v3, vs5
; CHECK-P9-NEXT: mtvsrd f7, r5 ; CHECK-P9-NEXT: mtfprd f7, r5
; CHECK-P9-NEXT: mfvsrwz r5, f3 ; CHECK-P9-NEXT: mffprwz r5, f3
; CHECK-P9-NEXT: vmrglh v3, v3, v4 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs6 ; CHECK-P9-NEXT: xxswapd v4, vs6
; CHECK-P9-NEXT: xxswapd v5, vs7 ; CHECK-P9-NEXT: xxswapd v5, vs7
; CHECK-P9-NEXT: mtvsrd f3, r5 ; CHECK-P9-NEXT: mtfprd f3, r5
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xxswapd v0, vs3 ; CHECK-P9-NEXT: xxswapd v0, vs3
; CHECK-P9-NEXT: vmrglh v4, v5, v4 ; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: xxswapd v5, vs8 ; CHECK-P9-NEXT: xxswapd v5, vs8
; CHECK-P9-NEXT: vmrglh v5, v5, v0 ; CHECK-P9-NEXT: vmrglh v5, v5, v0
; CHECK-P9-NEXT: mfvsrwz r4, f2 ; CHECK-P9-NEXT: mffprwz r4, f2
; CHECK-P9-NEXT: mtvsrd f2, r4 ; CHECK-P9-NEXT: mtfprd f2, r4
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: vmrglw v3, v5, v4 ; CHECK-P9-NEXT: vmrglw v3, v5, v4
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xxmrgld vs2, v3, v2 ; CHECK-P9-NEXT: xxmrgld vs2, v3, v2
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, vs1 ; CHECK-P9-NEXT: xxswapd vs0, vs1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: vmrglh v2, v4, v2 ; CHECK-P9-NEXT: vmrglh v2, v4, v2
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs1 ; CHECK-P9-NEXT: xscvspdpn f0, vs1
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 1 ; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r5, f9 ; CHECK-P9-NEXT: mffprwz r5, f9
; CHECK-P9-NEXT: mtvsrd f9, r5 ; CHECK-P9-NEXT: mtfprd f9, r5
; CHECK-P9-NEXT: mfvsrwz r5, f10 ; CHECK-P9-NEXT: mffprwz r5, f10
; CHECK-P9-NEXT: mtvsrd f10, r5 ; CHECK-P9-NEXT: mtfprd f10, r5
; CHECK-P9-NEXT: xxswapd v0, vs9 ; CHECK-P9-NEXT: xxswapd v0, vs9
; CHECK-P9-NEXT: xxswapd v1, vs10 ; CHECK-P9-NEXT: xxswapd v1, vs10
; CHECK-P9-NEXT: vmrglh v0, v1, v0 ; CHECK-P9-NEXT: vmrglh v0, v1, v0
; CHECK-P9-NEXT: vmrglw v2, v2, v0 ; CHECK-P9-NEXT: vmrglw v2, v2, v0
; CHECK-P9-NEXT: stxv vs2, 0(r3) ; CHECK-P9-NEXT: stxv vs2, 0(r3)
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: xxswapd v5, vs0 ; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5 ; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld vs0, v3, v2 ; CHECK-P9-NEXT: xxmrgld vs0, v3, v2
; CHECK-P9-NEXT: stxv vs0, 16(r3) ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r4) ; CHECK-BE-NEXT: lxv vs1, 16(r4)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xxswapd vs3, vs1 ; CHECK-BE-NEXT: xxswapd vs3, vs1
; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mfvsrwz r5, f2 ; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: xscvspdpn f4, vs1 ; CHECK-BE-NEXT: xscvspdpn f4, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v2, r5 ; CHECK-BE-NEXT: mtvsrd v2, r5
; CHECK-BE-NEXT: mfvsrwz r5, f3 ; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f4 ; CHECK-BE-NEXT: xscvdpsxws f3, f4
; CHECK-BE-NEXT: lxv vs0, 0(r4) ; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mfvsrwz r5, f3 ; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: mfvsrwz r5, f1 ; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mfvsrwz r5, f2 ; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrwz r5, f1 ; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v5, r5 ; CHECK-BE-NEXT: mtvsrd v5, r5
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghh v4, v5, v4 ; CHECK-BE-NEXT: vmrghh v4, v5, v4
; CHECK-BE-NEXT: mfvsrwz r5, f1 ; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: lxv vs1, 48(r4) ; CHECK-BE-NEXT: lxv vs1, 48(r4)
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v5, r5 ; CHECK-BE-NEXT: mtvsrd v5, r5
; CHECK-BE-NEXT: mfvsrwz r5, f0 ; CHECK-BE-NEXT: mffprwz r5, f0
; CHECK-BE-NEXT: lxv vs0, 32(r4) ; CHECK-BE-NEXT: lxv vs0, 32(r4)
; CHECK-BE-NEXT: xscvspdpn f5, vs1 ; CHECK-BE-NEXT: xscvspdpn f5, vs1
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f5, f5 ; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xxswapd vs3, vs1 ; CHECK-BE-NEXT: xxswapd vs3, vs1
; CHECK-BE-NEXT: mtvsrd v0, r5 ; CHECK-BE-NEXT: mtvsrd v0, r5
; CHECK-BE-NEXT: vmrghh v5, v5, v0 ; CHECK-BE-NEXT: vmrghh v5, v5, v0
; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghw v3, v5, v4 ; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mfvsrwz r4, f5 ; CHECK-BE-NEXT: mffprwz r4, f5
; CHECK-BE-NEXT: xxmrghd vs4, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs4, v3, v2
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: mfvsrwz r4, f2 ; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: stxv vs4, 0(r3) ; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mfvsrwz r4, f3 ; CHECK-BE-NEXT: mffprwz r4, f3
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mfvsrwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mfvsrwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v2, v2, v4 ; CHECK-BE-NEXT: vmrghh v2, v2, v4
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghw v2, v2, v3 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mfvsrwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mfvsrwz r4, f0 ; CHECK-BE-NEXT: mffprwz r4, f0
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v5, r4 ; CHECK-BE-NEXT: mtvsrd v5, r4
; CHECK-BE-NEXT: vmrghh v4, v4, v5 ; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-BE-NEXT: vmrghw v3, v4, v3 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd vs0, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs0, v3, v2
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x float>, <16 x float>* %0, align 64 %a = load <16 x float>, <16 x float>* %0, align 64
%1 = fptoui <16 x float> %a to <16 x i16> %1 = fptoui <16 x float> %a to <16 x i16>
store <16 x i16> %1, <16 x i16>* %agg.result, align 32 store <16 x i16> %1, <16 x i16>* %agg.result, align 32
ret void ret void
} }
define i32 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 { define i32 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs1 ; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <2 x float> %0 = bitcast i64 %a.coerce to <2 x float>
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; CHECK-P8-NEXT: xxsldwi vs3, v2, v2, 1 ; CHECK-P8-NEXT: xxsldwi vs3, v2, v2, 1
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xscvspdpn f2, vs2 ; CHECK-P8-NEXT: xscvspdpn f2, vs2
; CHECK-P8-NEXT: xscvspdpn f3, vs3 ; CHECK-P8-NEXT: xscvspdpn f3, vs3
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mtvsrd f1, r3 ; CHECK-P8-NEXT: mtfprd f1, r3
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mfvsrwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v4, vs1 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mfvsrwz r3, f3 ; CHECK-P8-NEXT: mffprwz r3, f3
; CHECK-P8-NEXT: mtvsrd f2, r4 ; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: mtvsrd f3, r3 ; CHECK-P8-NEXT: mtfprd f3, r3
; CHECK-P8-NEXT: xxswapd v3, vs2 ; CHECK-P8-NEXT: xxswapd v3, vs2
; CHECK-P8-NEXT: xxswapd v5, vs3 ; CHECK-P8-NEXT: xxswapd v5, vs3
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: vmrglh v3, v4, v5 ; CHECK-P8-NEXT: vmrglh v3, v4, v5
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, v2 ; CHECK-P9-NEXT: xscvspdpn f0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 1 ; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglh v2, v4, v2 ; CHECK-P9-NEXT: vmrglh v2, v4, v2
; CHECK-P9-NEXT: vmrglw v2, v2, v3 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xscvspdpn f0, v2 ; CHECK-BE-NEXT: xscvspdpn f0, v2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1 ; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: vmrghh v2, v4, v2 ; CHECK-BE-NEXT: vmrghh v2, v4, v2
; CHECK-BE-NEXT: vmrghw v2, v2, v3 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = fptosi <4 x float> %a to <4 x i16> %0 = fptosi <4 x float> %a to <4 x i16>
Show All 19 Lines
; CHECK-P8-NEXT: xscvspdpn f3, vs3 ; CHECK-P8-NEXT: xscvspdpn f3, vs3
; CHECK-P8-NEXT: xscvspdpn f5, vs5 ; CHECK-P8-NEXT: xscvspdpn f5, vs5
; CHECK-P8-NEXT: xscvdpsxws f4, f4 ; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvdpsxws f5, f5 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: mfvsrwz r4, f4 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: mfvsrwz r6, f1 ; CHECK-P8-NEXT: mffprwz r6, f1
; CHECK-P8-NEXT: mfvsrwz r5, f0 ; CHECK-P8-NEXT: mffprwz r5, f0
; CHECK-P8-NEXT: mtvsrd f1, r6 ; CHECK-P8-NEXT: mtfprd f1, r6
; CHECK-P8-NEXT: mtvsrd f0, r5 ; CHECK-P8-NEXT: mtfprd f0, r5
; CHECK-P8-NEXT: xxswapd v4, vs1 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1 ; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xscvspdpn f0, v2 ; CHECK-P8-NEXT: xscvspdpn f0, v2
; CHECK-P8-NEXT: mtvsrd f4, r4 ; CHECK-P8-NEXT: mtfprd f4, r4
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: mfvsrwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v1, vs4 ; CHECK-P8-NEXT: xxswapd v1, vs4
; CHECK-P8-NEXT: vmrglh v2, v4, v3 ; CHECK-P8-NEXT: vmrglh v2, v4, v3
; CHECK-P8-NEXT: mtvsrd f2, r4 ; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mfvsrwz r4, f5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xxswapd v5, vs2 ; CHECK-P8-NEXT: xxswapd v5, vs2
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: mtvsrd f1, r3 ; CHECK-P8-NEXT: mtfprd f1, r3
; CHECK-P8-NEXT: mfvsrwz r3, f3 ; CHECK-P8-NEXT: mffprwz r3, f3
; CHECK-P8-NEXT: mtvsrd f3, r4 ; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: xxswapd v4, vs1 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v6, vs3 ; CHECK-P8-NEXT: xxswapd v6, vs3
; CHECK-P8-NEXT: xxswapd v0, vs0 ; CHECK-P8-NEXT: xxswapd v0, vs0
; CHECK-P8-NEXT: vmrglh v3, v3, v4 ; CHECK-P8-NEXT: vmrglh v3, v3, v4
; CHECK-P8-NEXT: vmrglh v4, v0, v5 ; CHECK-P8-NEXT: vmrglh v4, v0, v5
; CHECK-P8-NEXT: vmrglh v5, v1, v6 ; CHECK-P8-NEXT: vmrglh v5, v1, v6
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: lxv vs0, 16(r3) ; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v2, vs2 ; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: xxswapd vs2, vs1 ; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xscvspdpn f2, vs1 ; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglh v3, v3, v4 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0 ; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0 ; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0 ; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5 ; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1 ; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghh v4, v4, v5 ; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-BE-NEXT: vmrghw v3, v4, v3 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd v2, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x float>, <8 x float>* %0, align 32 %a = load <8 x float>, <8 x float>* %0, align 32
Show All 36 Lines
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xxsldwi v3, v4, v4, 1 ; CHECK-P8-NEXT: xxsldwi v3, v4, v4, 1
; CHECK-P8-NEXT: xscvspdpn f10, vs10 ; CHECK-P8-NEXT: xscvspdpn f10, vs10
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvspdpn f9, vs9 ; CHECK-P8-NEXT: xscvspdpn f9, vs9
; CHECK-P8-NEXT: xscvdpsxws f6, f6 ; CHECK-P8-NEXT: xscvdpsxws f6, f6
; CHECK-P8-NEXT: xscvspdpn f12, vs12 ; CHECK-P8-NEXT: xscvspdpn f12, vs12
; CHECK-P8-NEXT: xscvdpsxws f5, f5 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvspdpn f11, vs11 ; CHECK-P8-NEXT: xscvspdpn f11, vs11
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvspdpn v2, v2 ; CHECK-P8-NEXT: xscvspdpn v2, v2
; CHECK-P8-NEXT: xscvdpsxws f8, f8 ; CHECK-P8-NEXT: xscvdpsxws f8, f8
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: mfvsrwz r4, f4 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws f7, f7 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
; CHECK-P8-NEXT: mfvsrwz r6, f2 ; CHECK-P8-NEXT: mffprwz r6, f2
; CHECK-P8-NEXT: xscvspdpn f13, vs13 ; CHECK-P8-NEXT: xscvspdpn f13, vs13
; CHECK-P8-NEXT: xscvspdpn v3, v3 ; CHECK-P8-NEXT: xscvspdpn v3, v3
; CHECK-P8-NEXT: xscvdpsxws f10, f10 ; CHECK-P8-NEXT: xscvdpsxws f10, f10
; CHECK-P8-NEXT: mtvsrd f4, r4 ; CHECK-P8-NEXT: mtfprd f4, r4
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f9, f9 ; CHECK-P8-NEXT: xscvdpsxws f9, f9
; CHECK-P8-NEXT: mtvsrd f2, r6 ; CHECK-P8-NEXT: mtfprd f2, r6
; CHECK-P8-NEXT: mfvsrwz r6, f6 ; CHECK-P8-NEXT: mffprwz r6, f6
; CHECK-P8-NEXT: xscvdpsxws f12, f12 ; CHECK-P8-NEXT: xscvdpsxws f12, f12
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: mfvsrwz r4, f5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xscvdpsxws f11, f11 ; CHECK-P8-NEXT: xscvdpsxws f11, f11
; CHECK-P8-NEXT: xxswapd v4, vs1 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: mtvsrd f6, r6 ; CHECK-P8-NEXT: mtfprd f6, r6
; CHECK-P8-NEXT: mfvsrwz r6, f3 ; CHECK-P8-NEXT: mffprwz r6, f3
; CHECK-P8-NEXT: xscvdpsxws v2, v2 ; CHECK-P8-NEXT: xscvdpsxws v2, v2
; CHECK-P8-NEXT: xxswapd v9, vs6 ; CHECK-P8-NEXT: xxswapd v9, vs6
; CHECK-P8-NEXT: mtvsrd f5, r4 ; CHECK-P8-NEXT: mtfprd f5, r4
; CHECK-P8-NEXT: mfvsrwz r4, f8 ; CHECK-P8-NEXT: mffprwz r4, f8
; CHECK-P8-NEXT: mtvsrd f3, r6 ; CHECK-P8-NEXT: mtfprd f3, r6
; CHECK-P8-NEXT: xxswapd v0, vs5 ; CHECK-P8-NEXT: xxswapd v0, vs5
; CHECK-P8-NEXT: mfvsrwz r6, f7 ; CHECK-P8-NEXT: mffprwz r6, f7
; CHECK-P8-NEXT: xscvdpsxws f13, f13 ; CHECK-P8-NEXT: xscvdpsxws f13, f13
; CHECK-P8-NEXT: xxswapd v5, vs3 ; CHECK-P8-NEXT: xxswapd v5, vs3
; CHECK-P8-NEXT: xscvdpsxws v3, v3 ; CHECK-P8-NEXT: xscvdpsxws v3, v3
; CHECK-P8-NEXT: mtvsrd f8, r4 ; CHECK-P8-NEXT: mtfprd f8, r4
; CHECK-P8-NEXT: mfvsrwz r4, f10 ; CHECK-P8-NEXT: mffprwz r4, f10
; CHECK-P8-NEXT: mtvsrd f7, r6 ; CHECK-P8-NEXT: mtfprd f7, r6
; CHECK-P8-NEXT: mfvsrwz r6, f9 ; CHECK-P8-NEXT: mffprwz r6, f9
; CHECK-P8-NEXT: mtvsrd f10, r4 ; CHECK-P8-NEXT: mtfprd f10, r4
; CHECK-P8-NEXT: mfvsrwz r4, f12 ; CHECK-P8-NEXT: mffprwz r4, f12
; CHECK-P8-NEXT: mtvsrd f9, r6 ; CHECK-P8-NEXT: mtfprd f9, r6
; CHECK-P8-NEXT: xxswapd v6, vs10 ; CHECK-P8-NEXT: xxswapd v6, vs10
; CHECK-P8-NEXT: mfvsrwz r6, f11 ; CHECK-P8-NEXT: mffprwz r6, f11
; CHECK-P8-NEXT: mtvsrd f12, r4 ; CHECK-P8-NEXT: mtfprd f12, r4
; CHECK-P8-NEXT: xxswapd v1, vs9 ; CHECK-P8-NEXT: xxswapd v1, vs9
; CHECK-P8-NEXT: mfvsrwz r4, v2 ; CHECK-P8-NEXT: mfvsrwz r4, v2
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: mtvsrd f11, r6 ; CHECK-P8-NEXT: mtfprd f11, r6
; CHECK-P8-NEXT: mfvsrwz r6, f13 ; CHECK-P8-NEXT: mffprwz r6, f13
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xxswapd v7, vs11 ; CHECK-P8-NEXT: xxswapd v7, vs11
; CHECK-P8-NEXT: mfvsrwz r4, v3 ; CHECK-P8-NEXT: mfvsrwz r4, v3
; CHECK-P8-NEXT: vmrglh v3, v5, v4 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: xxswapd v4, vs7 ; CHECK-P8-NEXT: xxswapd v4, vs7
; CHECK-P8-NEXT: vmrglh v2, v2, v0 ; CHECK-P8-NEXT: vmrglh v2, v2, v0
; CHECK-P8-NEXT: xxswapd v5, vs8 ; CHECK-P8-NEXT: xxswapd v5, vs8
; CHECK-P8-NEXT: xxswapd v0, vs2 ; CHECK-P8-NEXT: xxswapd v0, vs2
; CHECK-P8-NEXT: mtvsrd f13, r6 ; CHECK-P8-NEXT: mtfprd f13, r6
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v8, vs0 ; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: vmrglh v4, v5, v4 ; CHECK-P8-NEXT: vmrglh v4, v5, v4
; CHECK-P8-NEXT: vmrglh v5, v0, v1 ; CHECK-P8-NEXT: vmrglh v5, v0, v1
; CHECK-P8-NEXT: xxswapd v1, vs4 ; CHECK-P8-NEXT: xxswapd v1, vs4
; CHECK-P8-NEXT: vmrglh v0, v7, v6 ; CHECK-P8-NEXT: vmrglh v0, v7, v6
; CHECK-P8-NEXT: xxswapd v6, vs12 ; CHECK-P8-NEXT: xxswapd v6, vs12
; CHECK-P8-NEXT: xxswapd v7, vs13 ; CHECK-P8-NEXT: xxswapd v7, vs13
; CHECK-P8-NEXT: xxswapd v10, vs1 ; CHECK-P8-NEXT: xxswapd v10, vs1
Show All 28 Lines
; CHECK-P9-NEXT: xscvspdpn f6, vs6 ; CHECK-P9-NEXT: xscvspdpn f6, vs6
; CHECK-P9-NEXT: xxsldwi vs3, vs3, vs3, 1 ; CHECK-P9-NEXT: xxsldwi vs3, vs3, vs3, 1
; CHECK-P9-NEXT: xscvspdpn f7, vs7 ; CHECK-P9-NEXT: xscvspdpn f7, vs7
; CHECK-P9-NEXT: xscvspdpn f3, vs3 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: xscvdpsxws f6, f6 ; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: mfvsrwz r5, f5 ; CHECK-P9-NEXT: mffprwz r5, f5
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f7, f7 ; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mtvsrd f5, r5 ; CHECK-P9-NEXT: mtfprd f5, r5
; CHECK-P9-NEXT: mfvsrwz r5, f8 ; CHECK-P9-NEXT: mffprwz r5, f8
; CHECK-P9-NEXT: mtvsrd f8, r5 ; CHECK-P9-NEXT: mtfprd f8, r5
; CHECK-P9-NEXT: mfvsrwz r5, f2 ; CHECK-P9-NEXT: mffprwz r5, f2
; CHECK-P9-NEXT: lxv vs0, 32(r4) ; CHECK-P9-NEXT: lxv vs0, 32(r4)
; CHECK-P9-NEXT: xxsldwi vs9, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi vs9, vs0, vs0, 3
; CHECK-P9-NEXT: xxswapd vs10, vs0 ; CHECK-P9-NEXT: xxswapd vs10, vs0
; CHECK-P9-NEXT: xscvspdpn f9, vs9 ; CHECK-P9-NEXT: xscvspdpn f9, vs9
; CHECK-P9-NEXT: xscvspdpn f10, vs10 ; CHECK-P9-NEXT: xscvspdpn f10, vs10
; CHECK-P9-NEXT: xscvdpsxws f9, f9 ; CHECK-P9-NEXT: xscvdpsxws f9, f9
; CHECK-P9-NEXT: xscvdpsxws f10, f10 ; CHECK-P9-NEXT: xscvdpsxws f10, f10
; CHECK-P9-NEXT: mtvsrd f2, r5 ; CHECK-P9-NEXT: mtfprd f2, r5
; CHECK-P9-NEXT: mfvsrwz r5, f4 ; CHECK-P9-NEXT: mffprwz r5, f4
; CHECK-P9-NEXT: mtvsrd f4, r5 ; CHECK-P9-NEXT: mtfprd f4, r5
; CHECK-P9-NEXT: mfvsrwz r5, f1 ; CHECK-P9-NEXT: mffprwz r5, f1
; CHECK-P9-NEXT: mtvsrd f1, r5 ; CHECK-P9-NEXT: mtfprd f1, r5
; CHECK-P9-NEXT: mfvsrwz r5, f6 ; CHECK-P9-NEXT: mffprwz r5, f6
; CHECK-P9-NEXT: xxswapd v2, vs2 ; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: xxswapd v3, vs4 ; CHECK-P9-NEXT: xxswapd v3, vs4
; CHECK-P9-NEXT: xscvspdpn f2, vs0 ; CHECK-P9-NEXT: xscvspdpn f2, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f6, r5 ; CHECK-P9-NEXT: mtfprd f6, r5
; CHECK-P9-NEXT: mfvsrwz r5, f7 ; CHECK-P9-NEXT: mffprwz r5, f7
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: lxv vs1, 48(r4) ; CHECK-P9-NEXT: lxv vs1, 48(r4)
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs5 ; CHECK-P9-NEXT: xxswapd v3, vs5
; CHECK-P9-NEXT: mtvsrd f7, r5 ; CHECK-P9-NEXT: mtfprd f7, r5
; CHECK-P9-NEXT: mfvsrwz r5, f3 ; CHECK-P9-NEXT: mffprwz r5, f3
; CHECK-P9-NEXT: vmrglh v3, v3, v4 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs6 ; CHECK-P9-NEXT: xxswapd v4, vs6
; CHECK-P9-NEXT: xxswapd v5, vs7 ; CHECK-P9-NEXT: xxswapd v5, vs7
; CHECK-P9-NEXT: mtvsrd f3, r5 ; CHECK-P9-NEXT: mtfprd f3, r5
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xxswapd v0, vs3 ; CHECK-P9-NEXT: xxswapd v0, vs3
; CHECK-P9-NEXT: vmrglh v4, v5, v4 ; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: xxswapd v5, vs8 ; CHECK-P9-NEXT: xxswapd v5, vs8
; CHECK-P9-NEXT: vmrglh v5, v5, v0 ; CHECK-P9-NEXT: vmrglh v5, v5, v0
; CHECK-P9-NEXT: mfvsrwz r4, f2 ; CHECK-P9-NEXT: mffprwz r4, f2
; CHECK-P9-NEXT: mtvsrd f2, r4 ; CHECK-P9-NEXT: mtfprd f2, r4
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: vmrglw v3, v5, v4 ; CHECK-P9-NEXT: vmrglw v3, v5, v4
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xxmrgld vs2, v3, v2 ; CHECK-P9-NEXT: xxmrgld vs2, v3, v2
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, vs1 ; CHECK-P9-NEXT: xxswapd vs0, vs1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: vmrglh v2, v4, v2 ; CHECK-P9-NEXT: vmrglh v2, v4, v2
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs1 ; CHECK-P9-NEXT: xscvspdpn f0, vs1
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 1 ; CHECK-P9-NEXT: xxsldwi vs0, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r5, f9 ; CHECK-P9-NEXT: mffprwz r5, f9
; CHECK-P9-NEXT: mtvsrd f9, r5 ; CHECK-P9-NEXT: mtfprd f9, r5
; CHECK-P9-NEXT: mfvsrwz r5, f10 ; CHECK-P9-NEXT: mffprwz r5, f10
; CHECK-P9-NEXT: mtvsrd f10, r5 ; CHECK-P9-NEXT: mtfprd f10, r5
; CHECK-P9-NEXT: xxswapd v0, vs9 ; CHECK-P9-NEXT: xxswapd v0, vs9
; CHECK-P9-NEXT: xxswapd v1, vs10 ; CHECK-P9-NEXT: xxswapd v1, vs10
; CHECK-P9-NEXT: vmrglh v0, v1, v0 ; CHECK-P9-NEXT: vmrglh v0, v1, v0
; CHECK-P9-NEXT: vmrglw v2, v2, v0 ; CHECK-P9-NEXT: vmrglw v2, v2, v0
; CHECK-P9-NEXT: stxv vs2, 0(r3) ; CHECK-P9-NEXT: stxv vs2, 0(r3)
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: xxswapd v5, vs0 ; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5 ; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld vs0, v3, v2 ; CHECK-P9-NEXT: xxmrgld vs0, v3, v2
; CHECK-P9-NEXT: stxv vs0, 16(r3) ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r4) ; CHECK-BE-NEXT: lxv vs1, 16(r4)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xxswapd vs3, vs1 ; CHECK-BE-NEXT: xxswapd vs3, vs1
; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mfvsrwz r5, f2 ; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: xscvspdpn f4, vs1 ; CHECK-BE-NEXT: xscvspdpn f4, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v2, r5 ; CHECK-BE-NEXT: mtvsrd v2, r5
; CHECK-BE-NEXT: mfvsrwz r5, f3 ; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f4 ; CHECK-BE-NEXT: xscvdpsxws f3, f4
; CHECK-BE-NEXT: lxv vs0, 0(r4) ; CHECK-BE-NEXT: lxv vs0, 0(r4)
; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs0, vs0, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mfvsrwz r5, f3 ; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: mfvsrwz r5, f1 ; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mfvsrwz r5, f2 ; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrwz r5, f1 ; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v5, r5 ; CHECK-BE-NEXT: mtvsrd v5, r5
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghh v4, v5, v4 ; CHECK-BE-NEXT: vmrghh v4, v5, v4
; CHECK-BE-NEXT: mfvsrwz r5, f1 ; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: lxv vs1, 48(r4) ; CHECK-BE-NEXT: lxv vs1, 48(r4)
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v5, r5 ; CHECK-BE-NEXT: mtvsrd v5, r5
; CHECK-BE-NEXT: mfvsrwz r5, f0 ; CHECK-BE-NEXT: mffprwz r5, f0
; CHECK-BE-NEXT: lxv vs0, 32(r4) ; CHECK-BE-NEXT: lxv vs0, 32(r4)
; CHECK-BE-NEXT: xscvspdpn f5, vs1 ; CHECK-BE-NEXT: xscvspdpn f5, vs1
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f5, f5 ; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xxswapd vs3, vs1 ; CHECK-BE-NEXT: xxswapd vs3, vs1
; CHECK-BE-NEXT: mtvsrd v0, r5 ; CHECK-BE-NEXT: mtvsrd v0, r5
; CHECK-BE-NEXT: vmrghh v5, v5, v0 ; CHECK-BE-NEXT: vmrghh v5, v5, v0
; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghw v3, v5, v4 ; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mfvsrwz r4, f5 ; CHECK-BE-NEXT: mffprwz r4, f5
; CHECK-BE-NEXT: xxmrghd vs4, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs4, v3, v2
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: mfvsrwz r4, f2 ; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: stxv vs4, 0(r3) ; CHECK-BE-NEXT: stxv vs4, 0(r3)
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mfvsrwz r4, f3 ; CHECK-BE-NEXT: mffprwz r4, f3
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mfvsrwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mfvsrwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghh v2, v2, v4 ; CHECK-BE-NEXT: vmrghh v2, v2, v4
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghw v2, v2, v3 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mfvsrwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mfvsrwz r4, f0 ; CHECK-BE-NEXT: mffprwz r4, f0
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v5, r4 ; CHECK-BE-NEXT: mtvsrd v5, r4
; CHECK-BE-NEXT: vmrghh v4, v4, v5 ; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-BE-NEXT: vmrghw v3, v4, v3 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd vs0, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs0, v3, v2
; CHECK-BE-NEXT: stxv vs0, 16(r3) ; CHECK-BE-NEXT: stxv vs0, 16(r3)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x float>, <16 x float>* %0, align 64 %a = load <16 x float>, <16 x float>* %0, align 64
%1 = fptosi <16 x float> %a to <16 x i16> %1 = fptosi <16 x float> %a to <16 x i16>
store <16 x i16> %1, <16 x i16>* %agg.result, align 32 store <16 x i16> %1, <16 x i16>* %agg.result, align 32
ret void ret void
} }

llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P8 ; RUN: FileCheck %s --check-prefix=CHECK-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P9 ; RUN: FileCheck %s --check-prefix=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define <2 x i64> @test2elt(i64 %a.coerce) local_unnamed_addr #0 { define <2 x i64> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 ; CHECK-P8-NEXT: xxmrglw vs0, v2, v2
; CHECK-P8-NEXT: xvcvspdp vs0, vs0 ; CHECK-P8-NEXT: xvcvspdp vs0, vs0
; CHECK-P8-NEXT: xvcvdpuxds v2, vs0 ; CHECK-P8-NEXT: xvcvdpuxds v2, vs0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxmrglw vs0, v2, v2 ; CHECK-P9-NEXT: xxmrglw vs0, v2, v2
; CHECK-P9-NEXT: xvcvspdp vs0, vs0 ; CHECK-P9-NEXT: xvcvspdp vs0, vs0
; CHECK-P9-NEXT: xvcvdpuxds v2, vs0 ; CHECK-P9-NEXT: xvcvdpuxds v2, vs0
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs0 ; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs0
; CHECK-BE-NEXT: xvcvspdp vs0, vs0 ; CHECK-BE-NEXT: xvcvspdp vs0, vs0
; CHECK-BE-NEXT: xvcvdpuxds v2, vs0 ; CHECK-BE-NEXT: xvcvdpuxds v2, vs0
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <2 x float> %0 = bitcast i64 %a.coerce to <2 x float>
%1 = fptoui <2 x float> %0 to <2 x i64> %1 = fptoui <2 x float> %0 to <2 x i64>
ret <2 x i64> %1 ret <2 x i64> %1
▲ Show 20 Lines • Show All 264 Lines • ▼ Show 20 Linesentry:
%1 = fptoui <16 x float> %a to <16 x i64> %1 = fptoui <16 x float> %a to <16 x i64>
store <16 x i64> %1, <16 x i64>* %agg.result, align 128 store <16 x i64> %1, <16 x i64>* %agg.result, align 128
ret void ret void
} }
define <2 x i64> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 { define <2 x i64> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw vs0, v2, v2 ; CHECK-P8-NEXT: xxmrglw vs0, v2, v2
; CHECK-P8-NEXT: xvcvspdp vs0, vs0 ; CHECK-P8-NEXT: xvcvspdp vs0, vs0
; CHECK-P8-NEXT: xvcvdpuxds v2, vs0 ; CHECK-P8-NEXT: xvcvdpuxds v2, vs0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxmrglw vs0, v2, v2 ; CHECK-P9-NEXT: xxmrglw vs0, v2, v2
; CHECK-P9-NEXT: xvcvspdp vs0, vs0 ; CHECK-P9-NEXT: xvcvspdp vs0, vs0
; CHECK-P9-NEXT: xvcvdpuxds v2, vs0 ; CHECK-P9-NEXT: xvcvdpuxds v2, vs0
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs0 ; CHECK-BE-NEXT: xxmrghw vs0, vs0, vs0
; CHECK-BE-NEXT: xvcvspdp vs0, vs0 ; CHECK-BE-NEXT: xvcvspdp vs0, vs0
; CHECK-BE-NEXT: xvcvdpuxds v2, vs0 ; CHECK-BE-NEXT: xvcvdpuxds v2, vs0
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <2 x float> %0 = bitcast i64 %a.coerce to <2 x float>
%1 = fptoui <2 x float> %0 to <2 x i64> %1 = fptoui <2 x float> %0 to <2 x i64>
ret <2 x i64> %1 ret <2 x i64> %1
▲ Show 20 Lines • Show All 268 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_fp32_to_i8_elts.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P8 ; RUN: FileCheck %s --check-prefix=CHECK-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P9 ; RUN: FileCheck %s --check-prefix=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define i16 @test2elt(i64 %a.coerce) local_unnamed_addr #0 { define i16 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vmrglb v2, v3, v2 ; CHECK-P8-NEXT: vmrglb v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 48 ; CHECK-P8-NEXT: clrldi r3, r3, 48
; CHECK-P8-NEXT: sth r3, -2(r1) ; CHECK-P8-NEXT: sth r3, -2(r1)
; CHECK-P8-NEXT: lhz r3, -2(r1) ; CHECK-P8-NEXT: lhz r3, -2(r1)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs1 ; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: vmrglb v2, v3, v2 ; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8 ; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8
; CHECK-P9-NEXT: addi r3, r1, -2 ; CHECK-P9-NEXT: addi r3, r1, -2
; CHECK-P9-NEXT: stxsihx v2, 0, r3 ; CHECK-P9-NEXT: stxsihx v2, 0, r3
; CHECK-P9-NEXT: lhz r3, -2(r1) ; CHECK-P9-NEXT: lhz r3, -2(r1)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: addi r3, r1, -2 ; CHECK-BE-NEXT: addi r3, r1, -2
; CHECK-BE-NEXT: vmrghb v2, v2, v3 ; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10 ; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10
; CHECK-BE-NEXT: stxsihx v2, 0, r3 ; CHECK-BE-NEXT: stxsihx v2, 0, r3
; CHECK-BE-NEXT: lhz r3, -2(r1) ; CHECK-BE-NEXT: lhz r3, -2(r1)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
Show All 13 Lines
; CHECK-P8-NEXT: xxsldwi vs3, v2, v2, 1 ; CHECK-P8-NEXT: xxsldwi vs3, v2, v2, 1
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xscvspdpn f2, vs2 ; CHECK-P8-NEXT: xscvspdpn f2, vs2
; CHECK-P8-NEXT: xscvspdpn f3, vs3 ; CHECK-P8-NEXT: xscvspdpn f3, vs3
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mtvsrd f1, r3 ; CHECK-P8-NEXT: mtfprd f1, r3
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mfvsrwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v4, vs1 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mfvsrwz r3, f3 ; CHECK-P8-NEXT: mffprwz r3, f3
; CHECK-P8-NEXT: mtvsrd f2, r4 ; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: mtvsrd f3, r3 ; CHECK-P8-NEXT: mtfprd f3, r3
; CHECK-P8-NEXT: xxswapd v3, vs2 ; CHECK-P8-NEXT: xxswapd v3, vs2
; CHECK-P8-NEXT: xxswapd v5, vs3 ; CHECK-P8-NEXT: xxswapd v5, vs3
; CHECK-P8-NEXT: vmrglb v2, v3, v2 ; CHECK-P8-NEXT: vmrglb v2, v3, v2
; CHECK-P8-NEXT: vmrglb v3, v4, v5 ; CHECK-P8-NEXT: vmrglb v3, v4, v5
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, v2 ; CHECK-P9-NEXT: xscvspdpn f0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3 ; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 1 ; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglb v2, v4, v2 ; CHECK-P9-NEXT: vmrglb v2, v4, v2
; CHECK-P9-NEXT: vmrglh v2, v2, v3 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xscvspdpn f0, v2 ; CHECK-BE-NEXT: xscvspdpn f0, v2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v4, v3 ; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1 ; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: vmrghb v2, v4, v2 ; CHECK-BE-NEXT: vmrghb v2, v4, v2
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
Show All 20 Lines
; CHECK-P8-NEXT: xscvspdpn f3, vs3 ; CHECK-P8-NEXT: xscvspdpn f3, vs3
; CHECK-P8-NEXT: xscvspdpn f5, vs5 ; CHECK-P8-NEXT: xscvspdpn f5, vs5
; CHECK-P8-NEXT: xscvdpsxws f4, f4 ; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvdpsxws f5, f5 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: mfvsrwz r4, f4 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: mfvsrwz r6, f1 ; CHECK-P8-NEXT: mffprwz r6, f1
; CHECK-P8-NEXT: mfvsrwz r5, f0 ; CHECK-P8-NEXT: mffprwz r5, f0
; CHECK-P8-NEXT: mtvsrd f1, r6 ; CHECK-P8-NEXT: mtfprd f1, r6
; CHECK-P8-NEXT: mtvsrd f0, r5 ; CHECK-P8-NEXT: mtfprd f0, r5
; CHECK-P8-NEXT: xxswapd v4, vs1 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1 ; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xscvspdpn f0, v2 ; CHECK-P8-NEXT: xscvspdpn f0, v2
; CHECK-P8-NEXT: mtvsrd f4, r4 ; CHECK-P8-NEXT: mtfprd f4, r4
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: mfvsrwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v1, vs4 ; CHECK-P8-NEXT: xxswapd v1, vs4
; CHECK-P8-NEXT: vmrglb v2, v4, v3 ; CHECK-P8-NEXT: vmrglb v2, v4, v3
; CHECK-P8-NEXT: mtvsrd f2, r4 ; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mfvsrwz r4, f5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xxswapd v5, vs2 ; CHECK-P8-NEXT: xxswapd v5, vs2
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: mtvsrd f1, r3 ; CHECK-P8-NEXT: mtfprd f1, r3
; CHECK-P8-NEXT: mfvsrwz r3, f3 ; CHECK-P8-NEXT: mffprwz r3, f3
; CHECK-P8-NEXT: mtvsrd f3, r4 ; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: xxswapd v4, vs1 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v6, vs3 ; CHECK-P8-NEXT: xxswapd v6, vs3
; CHECK-P8-NEXT: xxswapd v0, vs0 ; CHECK-P8-NEXT: xxswapd v0, vs0
; CHECK-P8-NEXT: vmrglb v3, v3, v4 ; CHECK-P8-NEXT: vmrglb v3, v3, v4
; CHECK-P8-NEXT: vmrglb v4, v0, v5 ; CHECK-P8-NEXT: vmrglb v4, v0, v5
; CHECK-P8-NEXT: vmrglb v5, v1, v6 ; CHECK-P8-NEXT: vmrglb v5, v1, v6
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: vmrglh v3, v5, v4 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: lxv vs0, 16(r3) ; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v2, vs2 ; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: xxswapd vs2, vs1 ; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xscvspdpn f2, vs1 ; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: vmrglb v2, v3, v2 ; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglb v3, v3, v4 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0 ; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0 ; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3 ; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0 ; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglb v4, v4, v5 ; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1 ; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v2, v3, v2 ; CHECK-BE-NEXT: vmrghb v2, v3, v2
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v3, v3, v4 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghb v3, v4, v3 ; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
Show All 25 Lines
; CHECK-P8-NEXT: xxsldwi vs8, v2, v2, 3 ; CHECK-P8-NEXT: xxsldwi vs8, v2, v2, 3
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xxswapd vs9, v2 ; CHECK-P8-NEXT: xxswapd vs9, v2
; CHECK-P8-NEXT: xscvdpsxws f4, f4 ; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: xscvspdpn f5, vs5 ; CHECK-P8-NEXT: xscvspdpn f5, vs5
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvspdpn f6, vs6 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xscvspdpn f7, vs7 ; CHECK-P8-NEXT: xscvspdpn f7, vs7
; CHECK-P8-NEXT: mtvsrd f2, r4 ; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: mfvsrwz r4, f4 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvspdpn f8, vs8 ; CHECK-P8-NEXT: xscvspdpn f8, vs8
; CHECK-P8-NEXT: mtvsrd f4, r4 ; CHECK-P8-NEXT: mtfprd f4, r4
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvdpsxws f0, f5 ; CHECK-P8-NEXT: xscvdpsxws f0, f5
; CHECK-P8-NEXT: xxswapd v0, vs4 ; CHECK-P8-NEXT: xxswapd v0, vs4
; CHECK-P8-NEXT: xscvspdpn f9, vs9 ; CHECK-P8-NEXT: xscvspdpn f9, vs9
; CHECK-P8-NEXT: mtvsrd f5, r4 ; CHECK-P8-NEXT: mtfprd f5, r4
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f1, f6 ; CHECK-P8-NEXT: xscvdpsxws f1, f6
; CHECK-P8-NEXT: xxswapd v3, vs5 ; CHECK-P8-NEXT: xxswapd v3, vs5
; CHECK-P8-NEXT: mtvsrd f6, r4 ; CHECK-P8-NEXT: mtfprd f6, r4
; CHECK-P8-NEXT: mfvsrwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: xscvdpsxws f3, f7 ; CHECK-P8-NEXT: xscvdpsxws f3, f7
; CHECK-P8-NEXT: xxswapd v4, vs6 ; CHECK-P8-NEXT: xxswapd v4, vs6
; CHECK-P8-NEXT: mtvsrd f7, r4 ; CHECK-P8-NEXT: mtfprd f7, r4
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvdpsxws f0, f8 ; CHECK-P8-NEXT: xscvdpsxws f0, f8
; CHECK-P8-NEXT: xxswapd v5, vs7 ; CHECK-P8-NEXT: xxswapd v5, vs7
; CHECK-P8-NEXT: mtvsrd f8, r4 ; CHECK-P8-NEXT: mtfprd f8, r4
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f1, f9 ; CHECK-P8-NEXT: xscvdpsxws f1, f9
; CHECK-P8-NEXT: xxswapd v1, vs8 ; CHECK-P8-NEXT: xxswapd v1, vs8
; CHECK-P8-NEXT: mtvsrd f9, r4 ; CHECK-P8-NEXT: mtfprd f9, r4
; CHECK-P8-NEXT: mfvsrwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: vmrglb v3, v4, v3 ; CHECK-P8-NEXT: vmrglb v3, v4, v3
; CHECK-P8-NEXT: xxswapd v4, vs2 ; CHECK-P8-NEXT: xxswapd v4, vs2
; CHECK-P8-NEXT: mtvsrd f3, r4 ; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: xxswapd v6, vs9 ; CHECK-P8-NEXT: xxswapd v6, vs9
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvspdpn f0, v2 ; CHECK-P8-NEXT: xscvspdpn f0, v2
; CHECK-P8-NEXT: xxswapd v7, vs3 ; CHECK-P8-NEXT: xxswapd v7, vs3
; CHECK-P8-NEXT: mtvsrd f5, r4 ; CHECK-P8-NEXT: mtfprd f5, r4
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: vmrglb v4, v4, v5 ; CHECK-P8-NEXT: vmrglb v4, v4, v5
; CHECK-P8-NEXT: xxswapd v5, vs5 ; CHECK-P8-NEXT: xxswapd v5, vs5
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: lvx v9, r3, r4 ; CHECK-P8-NEXT: lvx v9, r3, r4
; CHECK-P8-NEXT: vmrglb v1, v6, v1 ; CHECK-P8-NEXT: vmrglb v1, v6, v1
; CHECK-P8-NEXT: xxswapd v8, vs1 ; CHECK-P8-NEXT: xxswapd v8, vs1
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1 ; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1
; CHECK-P8-NEXT: xxsldwi vs2, v9, v9, 3 ; CHECK-P8-NEXT: xxsldwi vs2, v9, v9, 3
; CHECK-P8-NEXT: xscvspdpn f4, v9 ; CHECK-P8-NEXT: xscvspdpn f4, v9
; CHECK-P8-NEXT: xxswapd vs3, v9 ; CHECK-P8-NEXT: xxswapd vs3, v9
; CHECK-P8-NEXT: xxsldwi vs5, v9, v9, 1 ; CHECK-P8-NEXT: xxsldwi vs5, v9, v9, 1
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: xscvspdpn f2, vs2 ; CHECK-P8-NEXT: xscvspdpn f2, vs2
; CHECK-P8-NEXT: xscvspdpn f3, vs3 ; CHECK-P8-NEXT: xscvspdpn f3, vs3
; CHECK-P8-NEXT: xscvspdpn f5, vs5 ; CHECK-P8-NEXT: xscvspdpn f5, vs5
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f4, f4 ; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvdpsxws f5, f5 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mfvsrwz r4, f4 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtvsrd f4, r4 ; CHECK-P8-NEXT: mtfprd f4, r4
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mfvsrwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v9, vs4 ; CHECK-P8-NEXT: xxswapd v9, vs4
; CHECK-P8-NEXT: mtvsrd f1, r3 ; CHECK-P8-NEXT: mtfprd f1, r3
; CHECK-P8-NEXT: mfvsrwz r3, f3 ; CHECK-P8-NEXT: mffprwz r3, f3
; CHECK-P8-NEXT: mtvsrd f2, r4 ; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xxswapd v6, vs1 ; CHECK-P8-NEXT: xxswapd v6, vs1
; CHECK-P8-NEXT: mfvsrwz r4, f5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: vmrglb v2, v0, v7 ; CHECK-P8-NEXT: vmrglb v2, v0, v7
; CHECK-P8-NEXT: xxswapd v0, vs0 ; CHECK-P8-NEXT: xxswapd v0, vs0
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v7, vs2 ; CHECK-P8-NEXT: xxswapd v7, vs2
; CHECK-P8-NEXT: mtvsrd f3, r4 ; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: vmrglb v5, v8, v5 ; CHECK-P8-NEXT: vmrglb v5, v8, v5
; CHECK-P8-NEXT: xxswapd v8, vs0 ; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: xxswapd v10, vs3 ; CHECK-P8-NEXT: xxswapd v10, vs3
; CHECK-P8-NEXT: vmrglb v0, v0, v6 ; CHECK-P8-NEXT: vmrglb v0, v0, v6
; CHECK-P8-NEXT: vmrglh v3, v4, v3 ; CHECK-P8-NEXT: vmrglh v3, v4, v3
; CHECK-P8-NEXT: vmrglb v6, v8, v7 ; CHECK-P8-NEXT: vmrglb v6, v8, v7
; CHECK-P8-NEXT: vmrglb v7, v9, v10 ; CHECK-P8-NEXT: vmrglb v7, v9, v10
; CHECK-P8-NEXT: vmrglh v2, v2, v1 ; CHECK-P8-NEXT: vmrglh v2, v2, v1
; CHECK-P8-NEXT: vmrglh v4, v0, v5 ; CHECK-P8-NEXT: vmrglh v4, v0, v5
; CHECK-P8-NEXT: vmrglh v5, v7, v6 ; CHECK-P8-NEXT: vmrglh v5, v7, v6
; CHECK-P8-NEXT: vmrglw v2, v2, v3 ; CHECK-P8-NEXT: vmrglw v2, v2, v3
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt: ; CHECK-P9-LABEL: test16elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 0(r3) ; CHECK-P9-NEXT: lxv vs2, 0(r3)
; CHECK-P9-NEXT: xxsldwi vs3, vs2, vs2, 3 ; CHECK-P9-NEXT: xxsldwi vs3, vs2, vs2, 3
; CHECK-P9-NEXT: xscvspdpn f3, vs3 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs4, 16(r3) ; CHECK-P9-NEXT: lxv vs4, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v2, vs3 ; CHECK-P9-NEXT: xxswapd v2, vs3
; CHECK-P9-NEXT: xxswapd vs3, vs2 ; CHECK-P9-NEXT: xxswapd vs3, vs2
; CHECK-P9-NEXT: xscvspdpn f3, vs3 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v3, vs3 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: xscvspdpn f3, vs2 ; CHECK-P9-NEXT: xscvspdpn f3, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1 ; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs4, vs4, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs4, vs4, 3
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: vmrglb v2, v3, v2 ; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs3 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: vmrglb v3, v3, v4 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xxswapd vs2, vs4 ; CHECK-P9-NEXT: xxswapd vs2, vs4
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xscvspdpn f2, vs4 ; CHECK-P9-NEXT: xscvspdpn f2, vs4
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3 ; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs4, vs4, 1 ; CHECK-P9-NEXT: xxsldwi vs2, vs4, vs4, 1
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v5, vs2 ; CHECK-P9-NEXT: xxswapd v5, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: vmrglb v4, v4, v5 ; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xxswapd vs2, vs1 ; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xscvspdpn f2, vs1 ; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs1 ; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: vmrglb v3, v4, v3 ; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: vmrglb v4, v4, v5 ; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0 ; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs1 ; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0 ; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v4, v5, v4 ; CHECK-P9-NEXT: vmrglb v4, v5, v4
; CHECK-P9-NEXT: xxswapd v5, vs1 ; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xxswapd v0, vs0 ; CHECK-P9-NEXT: xxswapd v0, vs0
; CHECK-P9-NEXT: vmrglb v5, v5, v0 ; CHECK-P9-NEXT: vmrglb v5, v5, v0
; CHECK-P9-NEXT: vmrglh v4, v5, v4 ; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xxsldwi vs4, vs3, vs3, 3 ; CHECK-BE-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-BE-NEXT: xscvspdpn f4, vs4 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: xxswapd vs4, vs3 ; CHECK-BE-NEXT: xxswapd vs4, vs3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f4, vs4 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: mfvsrwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: xscvspdpn f4, vs3 ; CHECK-BE-NEXT: xscvspdpn f4, vs3
; CHECK-BE-NEXT: xxsldwi vs3, vs3, vs3, 1 ; CHECK-BE-NEXT: xxsldwi vs3, vs3, vs3, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: vmrghb v2, v3, v2 ; CHECK-BE-NEXT: vmrghb v2, v3, v2
; CHECK-BE-NEXT: mfvsrwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xxsldwi vs3, vs2, vs2, 3 ; CHECK-BE-NEXT: xxsldwi vs3, vs2, vs2, 3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xxswapd vs3, vs2 ; CHECK-BE-NEXT: xxswapd vs3, vs2
; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: vmrghb v3, v3, v4 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvspdpn f3, vs2 ; CHECK-BE-NEXT: xscvspdpn f3, vs2
; CHECK-BE-NEXT: xxsldwi vs2, vs2, vs2, 1 ; CHECK-BE-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghb v3, v4, v3 ; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1 ; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghb v4, v4, v5 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v3, v4, v3 ; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v4, v4, v5 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghb v4, v5, v4 ; CHECK-BE-NEXT: vmrghb v4, v5, v4
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v0, r3 ; CHECK-BE-NEXT: mtvsrd v0, r3
; CHECK-BE-NEXT: vmrghb v5, v5, v0 ; CHECK-BE-NEXT: vmrghb v5, v5, v0
; CHECK-BE-NEXT: vmrghh v4, v5, v4 ; CHECK-BE-NEXT: vmrghh v4, v5, v4
; CHECK-BE-NEXT: vmrghw v3, v4, v3 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd v2, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x float>, <16 x float>* %0, align 64 %a = load <16 x float>, <16 x float>* %0, align 64
%1 = fptoui <16 x float> %a to <16 x i8> %1 = fptoui <16 x float> %a to <16 x i8>
ret <16 x i8> %1 ret <16 x i8> %1
} }
define i16 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 { define i16 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vmrglb v2, v3, v2 ; CHECK-P8-NEXT: vmrglb v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 48 ; CHECK-P8-NEXT: clrldi r3, r3, 48
; CHECK-P8-NEXT: sth r3, -2(r1) ; CHECK-P8-NEXT: sth r3, -2(r1)
; CHECK-P8-NEXT: lhz r3, -2(r1) ; CHECK-P8-NEXT: lhz r3, -2(r1)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs1, v2, v2, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs1 ; CHECK-P9-NEXT: xxswapd v2, vs1
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: vmrglb v2, v3, v2 ; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8 ; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8
; CHECK-P9-NEXT: addi r3, r1, -2 ; CHECK-P9-NEXT: addi r3, r1, -2
; CHECK-P9-NEXT: stxsihx v2, 0, r3 ; CHECK-P9-NEXT: stxsihx v2, 0, r3
; CHECK-P9-NEXT: lhz r3, -2(r1) ; CHECK-P9-NEXT: lhz r3, -2(r1)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: addi r3, r1, -2 ; CHECK-BE-NEXT: addi r3, r1, -2
; CHECK-BE-NEXT: vmrghb v2, v2, v3 ; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10 ; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10
; CHECK-BE-NEXT: stxsihx v2, 0, r3 ; CHECK-BE-NEXT: stxsihx v2, 0, r3
; CHECK-BE-NEXT: lhz r3, -2(r1) ; CHECK-BE-NEXT: lhz r3, -2(r1)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
Show All 13 Lines
; CHECK-P8-NEXT: xxsldwi vs3, v2, v2, 1 ; CHECK-P8-NEXT: xxsldwi vs3, v2, v2, 1
; CHECK-P8-NEXT: xscvspdpn f0, vs0 ; CHECK-P8-NEXT: xscvspdpn f0, vs0
; CHECK-P8-NEXT: xscvspdpn f2, vs2 ; CHECK-P8-NEXT: xscvspdpn f2, vs2
; CHECK-P8-NEXT: xscvspdpn f3, vs3 ; CHECK-P8-NEXT: xscvspdpn f3, vs3
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mtvsrd f1, r3 ; CHECK-P8-NEXT: mtfprd f1, r3
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mfvsrwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v4, vs1 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mfvsrwz r3, f3 ; CHECK-P8-NEXT: mffprwz r3, f3
; CHECK-P8-NEXT: mtvsrd f2, r4 ; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: mtvsrd f3, r3 ; CHECK-P8-NEXT: mtfprd f3, r3
; CHECK-P8-NEXT: xxswapd v3, vs2 ; CHECK-P8-NEXT: xxswapd v3, vs2
; CHECK-P8-NEXT: xxswapd v5, vs3 ; CHECK-P8-NEXT: xxswapd v5, vs3
; CHECK-P8-NEXT: vmrglb v2, v3, v2 ; CHECK-P8-NEXT: vmrglb v2, v3, v2
; CHECK-P8-NEXT: vmrglb v3, v4, v5 ; CHECK-P8-NEXT: vmrglb v3, v4, v5
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xscvspdpn f0, v2 ; CHECK-P9-NEXT: xscvspdpn f0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3 ; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 1 ; CHECK-P9-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglb v2, v4, v2 ; CHECK-P9-NEXT: vmrglb v2, v4, v2
; CHECK-P9-NEXT: vmrglh v2, v2, v3 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3 ; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 3
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xscvspdpn f0, v2 ; CHECK-BE-NEXT: xscvspdpn f0, v2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v4, v3 ; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1 ; CHECK-BE-NEXT: xxsldwi vs0, v2, v2, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: vmrghb v2, v4, v2 ; CHECK-BE-NEXT: vmrghb v2, v4, v2
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
Show All 20 Lines
; CHECK-P8-NEXT: xscvspdpn f3, vs3 ; CHECK-P8-NEXT: xscvspdpn f3, vs3
; CHECK-P8-NEXT: xscvspdpn f5, vs5 ; CHECK-P8-NEXT: xscvspdpn f5, vs5
; CHECK-P8-NEXT: xscvdpsxws f4, f4 ; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvdpsxws f5, f5 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: mfvsrwz r4, f4 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: mfvsrwz r6, f1 ; CHECK-P8-NEXT: mffprwz r6, f1
; CHECK-P8-NEXT: mfvsrwz r5, f0 ; CHECK-P8-NEXT: mffprwz r5, f0
; CHECK-P8-NEXT: mtvsrd f1, r6 ; CHECK-P8-NEXT: mtfprd f1, r6
; CHECK-P8-NEXT: mtvsrd f0, r5 ; CHECK-P8-NEXT: mtfprd f0, r5
; CHECK-P8-NEXT: xxswapd v4, vs1 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1 ; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xscvspdpn f0, v2 ; CHECK-P8-NEXT: xscvspdpn f0, v2
; CHECK-P8-NEXT: mtvsrd f4, r4 ; CHECK-P8-NEXT: mtfprd f4, r4
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: mfvsrwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v1, vs4 ; CHECK-P8-NEXT: xxswapd v1, vs4
; CHECK-P8-NEXT: vmrglb v2, v4, v3 ; CHECK-P8-NEXT: vmrglb v2, v4, v3
; CHECK-P8-NEXT: mtvsrd f2, r4 ; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mfvsrwz r4, f5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xxswapd v5, vs2 ; CHECK-P8-NEXT: xxswapd v5, vs2
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: mtvsrd f1, r3 ; CHECK-P8-NEXT: mtfprd f1, r3
; CHECK-P8-NEXT: mfvsrwz r3, f3 ; CHECK-P8-NEXT: mffprwz r3, f3
; CHECK-P8-NEXT: mtvsrd f3, r4 ; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: xxswapd v4, vs1 ; CHECK-P8-NEXT: xxswapd v4, vs1
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v6, vs3 ; CHECK-P8-NEXT: xxswapd v6, vs3
; CHECK-P8-NEXT: xxswapd v0, vs0 ; CHECK-P8-NEXT: xxswapd v0, vs0
; CHECK-P8-NEXT: vmrglb v3, v3, v4 ; CHECK-P8-NEXT: vmrglb v3, v3, v4
; CHECK-P8-NEXT: vmrglb v4, v0, v5 ; CHECK-P8-NEXT: vmrglb v4, v0, v5
; CHECK-P8-NEXT: vmrglb v5, v1, v6 ; CHECK-P8-NEXT: vmrglb v5, v1, v6
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: vmrglh v3, v5, v4 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: lxv vs0, 16(r3) ; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v2, vs2 ; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: xxswapd vs2, vs1 ; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xscvspdpn f2, vs1 ; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: vmrglb v2, v3, v2 ; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglb v3, v3, v4 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0 ; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0 ; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3 ; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0 ; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglb v4, v4, v5 ; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1 ; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v2, v3, v2 ; CHECK-BE-NEXT: vmrghb v2, v3, v2
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v3, v3, v4 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghb v3, v4, v3 ; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
Show All 25 Lines
; CHECK-P8-NEXT: xxsldwi vs8, v2, v2, 3 ; CHECK-P8-NEXT: xxsldwi vs8, v2, v2, 3
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xxswapd vs9, v2 ; CHECK-P8-NEXT: xxswapd vs9, v2
; CHECK-P8-NEXT: xscvdpsxws f4, f4 ; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: xscvspdpn f5, vs5 ; CHECK-P8-NEXT: xscvspdpn f5, vs5
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvspdpn f6, vs6 ; CHECK-P8-NEXT: xscvspdpn f6, vs6
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xscvspdpn f7, vs7 ; CHECK-P8-NEXT: xscvspdpn f7, vs7
; CHECK-P8-NEXT: mtvsrd f2, r4 ; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: mfvsrwz r4, f4 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvspdpn f8, vs8 ; CHECK-P8-NEXT: xscvspdpn f8, vs8
; CHECK-P8-NEXT: mtvsrd f4, r4 ; CHECK-P8-NEXT: mtfprd f4, r4
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvdpsxws f0, f5 ; CHECK-P8-NEXT: xscvdpsxws f0, f5
; CHECK-P8-NEXT: xxswapd v0, vs4 ; CHECK-P8-NEXT: xxswapd v0, vs4
; CHECK-P8-NEXT: xscvspdpn f9, vs9 ; CHECK-P8-NEXT: xscvspdpn f9, vs9
; CHECK-P8-NEXT: mtvsrd f5, r4 ; CHECK-P8-NEXT: mtfprd f5, r4
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f1, f6 ; CHECK-P8-NEXT: xscvdpsxws f1, f6
; CHECK-P8-NEXT: xxswapd v3, vs5 ; CHECK-P8-NEXT: xxswapd v3, vs5
; CHECK-P8-NEXT: mtvsrd f6, r4 ; CHECK-P8-NEXT: mtfprd f6, r4
; CHECK-P8-NEXT: mfvsrwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: xscvdpsxws f3, f7 ; CHECK-P8-NEXT: xscvdpsxws f3, f7
; CHECK-P8-NEXT: xxswapd v4, vs6 ; CHECK-P8-NEXT: xxswapd v4, vs6
; CHECK-P8-NEXT: mtvsrd f7, r4 ; CHECK-P8-NEXT: mtfprd f7, r4
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvdpsxws f0, f8 ; CHECK-P8-NEXT: xscvdpsxws f0, f8
; CHECK-P8-NEXT: xxswapd v5, vs7 ; CHECK-P8-NEXT: xxswapd v5, vs7
; CHECK-P8-NEXT: mtvsrd f8, r4 ; CHECK-P8-NEXT: mtfprd f8, r4
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xscvdpsxws f1, f9 ; CHECK-P8-NEXT: xscvdpsxws f1, f9
; CHECK-P8-NEXT: xxswapd v1, vs8 ; CHECK-P8-NEXT: xxswapd v1, vs8
; CHECK-P8-NEXT: mtvsrd f9, r4 ; CHECK-P8-NEXT: mtfprd f9, r4
; CHECK-P8-NEXT: mfvsrwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: vmrglb v3, v4, v3 ; CHECK-P8-NEXT: vmrglb v3, v4, v3
; CHECK-P8-NEXT: xxswapd v4, vs2 ; CHECK-P8-NEXT: xxswapd v4, vs2
; CHECK-P8-NEXT: mtvsrd f3, r4 ; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: xxswapd v6, vs9 ; CHECK-P8-NEXT: xxswapd v6, vs9
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvspdpn f0, v2 ; CHECK-P8-NEXT: xscvspdpn f0, v2
; CHECK-P8-NEXT: xxswapd v7, vs3 ; CHECK-P8-NEXT: xxswapd v7, vs3
; CHECK-P8-NEXT: mtvsrd f5, r4 ; CHECK-P8-NEXT: mtfprd f5, r4
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: vmrglb v4, v4, v5 ; CHECK-P8-NEXT: vmrglb v4, v4, v5
; CHECK-P8-NEXT: xxswapd v5, vs5 ; CHECK-P8-NEXT: xxswapd v5, vs5
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: li r4, 48 ; CHECK-P8-NEXT: li r4, 48
; CHECK-P8-NEXT: lvx v9, r3, r4 ; CHECK-P8-NEXT: lvx v9, r3, r4
; CHECK-P8-NEXT: vmrglb v1, v6, v1 ; CHECK-P8-NEXT: vmrglb v1, v6, v1
; CHECK-P8-NEXT: xxswapd v8, vs1 ; CHECK-P8-NEXT: xxswapd v8, vs1
; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1 ; CHECK-P8-NEXT: xxsldwi vs1, v2, v2, 1
; CHECK-P8-NEXT: xxsldwi vs2, v9, v9, 3 ; CHECK-P8-NEXT: xxsldwi vs2, v9, v9, 3
; CHECK-P8-NEXT: xscvspdpn f4, v9 ; CHECK-P8-NEXT: xscvspdpn f4, v9
; CHECK-P8-NEXT: xxswapd vs3, v9 ; CHECK-P8-NEXT: xxswapd vs3, v9
; CHECK-P8-NEXT: xxsldwi vs5, v9, v9, 1 ; CHECK-P8-NEXT: xxsldwi vs5, v9, v9, 1
; CHECK-P8-NEXT: xscvspdpn f1, vs1 ; CHECK-P8-NEXT: xscvspdpn f1, vs1
; CHECK-P8-NEXT: xscvspdpn f2, vs2 ; CHECK-P8-NEXT: xscvspdpn f2, vs2
; CHECK-P8-NEXT: xscvspdpn f3, vs3 ; CHECK-P8-NEXT: xscvspdpn f3, vs3
; CHECK-P8-NEXT: xscvspdpn f5, vs5 ; CHECK-P8-NEXT: xscvspdpn f5, vs5
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f4, f4 ; CHECK-P8-NEXT: xscvdpsxws f4, f4
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xscvdpsxws f5, f5 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mfvsrwz r4, f4 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtvsrd f4, r4 ; CHECK-P8-NEXT: mtfprd f4, r4
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mfvsrwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: xxswapd v9, vs4 ; CHECK-P8-NEXT: xxswapd v9, vs4
; CHECK-P8-NEXT: mtvsrd f1, r3 ; CHECK-P8-NEXT: mtfprd f1, r3
; CHECK-P8-NEXT: mfvsrwz r3, f3 ; CHECK-P8-NEXT: mffprwz r3, f3
; CHECK-P8-NEXT: mtvsrd f2, r4 ; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: xxswapd v6, vs1 ; CHECK-P8-NEXT: xxswapd v6, vs1
; CHECK-P8-NEXT: mfvsrwz r4, f5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: vmrglb v2, v0, v7 ; CHECK-P8-NEXT: vmrglb v2, v0, v7
; CHECK-P8-NEXT: xxswapd v0, vs0 ; CHECK-P8-NEXT: xxswapd v0, vs0
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v7, vs2 ; CHECK-P8-NEXT: xxswapd v7, vs2
; CHECK-P8-NEXT: mtvsrd f3, r4 ; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: vmrglb v5, v8, v5 ; CHECK-P8-NEXT: vmrglb v5, v8, v5
; CHECK-P8-NEXT: xxswapd v8, vs0 ; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: xxswapd v10, vs3 ; CHECK-P8-NEXT: xxswapd v10, vs3
; CHECK-P8-NEXT: vmrglb v0, v0, v6 ; CHECK-P8-NEXT: vmrglb v0, v0, v6
; CHECK-P8-NEXT: vmrglh v3, v4, v3 ; CHECK-P8-NEXT: vmrglh v3, v4, v3
; CHECK-P8-NEXT: vmrglb v6, v8, v7 ; CHECK-P8-NEXT: vmrglb v6, v8, v7
; CHECK-P8-NEXT: vmrglb v7, v9, v10 ; CHECK-P8-NEXT: vmrglb v7, v9, v10
; CHECK-P8-NEXT: vmrglh v2, v2, v1 ; CHECK-P8-NEXT: vmrglh v2, v2, v1
; CHECK-P8-NEXT: vmrglh v4, v0, v5 ; CHECK-P8-NEXT: vmrglh v4, v0, v5
; CHECK-P8-NEXT: vmrglh v5, v7, v6 ; CHECK-P8-NEXT: vmrglh v5, v7, v6
; CHECK-P8-NEXT: vmrglw v2, v2, v3 ; CHECK-P8-NEXT: vmrglw v2, v2, v3
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test16elt_signed: ; CHECK-P9-LABEL: test16elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs2, 0(r3) ; CHECK-P9-NEXT: lxv vs2, 0(r3)
; CHECK-P9-NEXT: xxsldwi vs3, vs2, vs2, 3 ; CHECK-P9-NEXT: xxsldwi vs3, vs2, vs2, 3
; CHECK-P9-NEXT: xscvspdpn f3, vs3 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs4, 16(r3) ; CHECK-P9-NEXT: lxv vs4, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v2, vs3 ; CHECK-P9-NEXT: xxswapd v2, vs3
; CHECK-P9-NEXT: xxswapd vs3, vs2 ; CHECK-P9-NEXT: xxswapd vs3, vs2
; CHECK-P9-NEXT: xscvspdpn f3, vs3 ; CHECK-P9-NEXT: xscvspdpn f3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v3, vs3 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: xscvspdpn f3, vs2 ; CHECK-P9-NEXT: xscvspdpn f3, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1 ; CHECK-P9-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs4, vs4, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs4, vs4, 3
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: vmrglb v2, v3, v2 ; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs3 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: vmrglb v3, v3, v4 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xxswapd vs2, vs4 ; CHECK-P9-NEXT: xxswapd vs2, vs4
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xscvspdpn f2, vs4 ; CHECK-P9-NEXT: xscvspdpn f2, vs4
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: vmrglb v3, v4, v3 ; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs4, vs4, 1 ; CHECK-P9-NEXT: xxsldwi vs2, vs4, vs4, 1
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v5, vs2 ; CHECK-P9-NEXT: xxswapd v5, vs2
; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-P9-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: vmrglb v4, v4, v5 ; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xxswapd vs2, vs1 ; CHECK-P9-NEXT: xxswapd vs2, vs1
; CHECK-P9-NEXT: xscvspdpn f2, vs2 ; CHECK-P9-NEXT: xscvspdpn f2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xscvspdpn f2, vs1 ; CHECK-P9-NEXT: xscvspdpn f2, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-P9-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs1 ; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-P9-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: vmrglb v3, v4, v3 ; CHECK-P9-NEXT: vmrglb v3, v4, v3
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: vmrglb v4, v4, v5 ; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd vs1, vs0 ; CHECK-P9-NEXT: xxswapd vs1, vs0
; CHECK-P9-NEXT: xscvspdpn f1, vs1 ; CHECK-P9-NEXT: xscvspdpn f1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs1 ; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xscvspdpn f1, vs0 ; CHECK-P9-NEXT: xscvspdpn f1, vs0
; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-P9-NEXT: xscvspdpn f0, vs0 ; CHECK-P9-NEXT: xscvspdpn f0, vs0
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v4, v5, v4 ; CHECK-P9-NEXT: vmrglb v4, v5, v4
; CHECK-P9-NEXT: xxswapd v5, vs1 ; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xxswapd v0, vs0 ; CHECK-P9-NEXT: xxswapd v0, vs0
; CHECK-P9-NEXT: vmrglb v5, v5, v0 ; CHECK-P9-NEXT: vmrglb v5, v5, v0
; CHECK-P9-NEXT: vmrglh v4, v5, v4 ; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xxsldwi vs4, vs3, vs3, 3 ; CHECK-BE-NEXT: xxsldwi vs4, vs3, vs3, 3
; CHECK-BE-NEXT: xscvspdpn f4, vs4 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: xxswapd vs4, vs3 ; CHECK-BE-NEXT: xxswapd vs4, vs3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f4, vs4 ; CHECK-BE-NEXT: xscvspdpn f4, vs4
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: mfvsrwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: xscvspdpn f4, vs3 ; CHECK-BE-NEXT: xscvspdpn f4, vs3
; CHECK-BE-NEXT: xxsldwi vs3, vs3, vs3, 1 ; CHECK-BE-NEXT: xxsldwi vs3, vs3, vs3, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: vmrghb v2, v3, v2 ; CHECK-BE-NEXT: vmrghb v2, v3, v2
; CHECK-BE-NEXT: mfvsrwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xxsldwi vs3, vs2, vs2, 3 ; CHECK-BE-NEXT: xxsldwi vs3, vs2, vs2, 3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xxswapd vs3, vs2 ; CHECK-BE-NEXT: xxswapd vs3, vs2
; CHECK-BE-NEXT: xscvspdpn f3, vs3 ; CHECK-BE-NEXT: xscvspdpn f3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: vmrghb v3, v3, v4 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvspdpn f3, vs2 ; CHECK-BE-NEXT: xscvspdpn f3, vs2
; CHECK-BE-NEXT: xxsldwi vs2, vs2, vs2, 1 ; CHECK-BE-NEXT: xxsldwi vs2, vs2, vs2, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghb v3, v4, v3 ; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3 ; CHECK-BE-NEXT: xxsldwi vs2, vs1, vs1, 3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs1 ; CHECK-BE-NEXT: xxswapd vs2, vs1
; CHECK-BE-NEXT: xscvspdpn f2, vs2 ; CHECK-BE-NEXT: xscvspdpn f2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghb v4, v4, v5 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvspdpn f2, vs1 ; CHECK-BE-NEXT: xscvspdpn f2, vs1
; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1 ; CHECK-BE-NEXT: xxsldwi vs1, vs1, vs1, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v3, v4, v3 ; CHECK-BE-NEXT: vmrghb v3, v4, v3
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3 ; CHECK-BE-NEXT: xxsldwi vs1, vs0, vs0, 3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xxswapd vs1, vs0 ; CHECK-BE-NEXT: xxswapd vs1, vs0
; CHECK-BE-NEXT: xscvspdpn f1, vs1 ; CHECK-BE-NEXT: xscvspdpn f1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: vmrghb v4, v4, v5 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvspdpn f1, vs0 ; CHECK-BE-NEXT: xscvspdpn f1, vs0
; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1 ; CHECK-BE-NEXT: xxsldwi vs0, vs0, vs0, 1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: xscvspdpn f0, vs0 ; CHECK-BE-NEXT: xscvspdpn f0, vs0
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: vmrghb v4, v5, v4 ; CHECK-BE-NEXT: vmrghb v4, v5, v4
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v0, r3 ; CHECK-BE-NEXT: mtvsrd v0, r3
; CHECK-BE-NEXT: vmrghb v5, v5, v0 ; CHECK-BE-NEXT: vmrghb v5, v5, v0
; CHECK-BE-NEXT: vmrghh v4, v5, v4 ; CHECK-BE-NEXT: vmrghh v4, v5, v4
; CHECK-BE-NEXT: vmrghw v3, v4, v3 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd v2, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x float>, <16 x float>* %0, align 64 %a = load <16 x float>, <16 x float>* %0, align 64
%1 = fptosi <16 x float> %a to <16 x i8> %1 = fptosi <16 x float> %a to <16 x i8>
ret <16 x i8> %1 ret <16 x i8> %1
} }

llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i16_elts.ll

Show All 9 Lines
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define i32 @test2elt(<2 x double> %a) local_unnamed_addr #0 { define i32 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xscvdpsxws f1, v2 ; CHECK-P8-NEXT: xscvdpsxws f1, v2
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglh v2, v2, v3 ; CHECK-P8-NEXT: vmrglh v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpsxws f0, v2 ; CHECK-P9-NEXT: xscvdpsxws f0, v2
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xscvdpsxws f0, v2 ; CHECK-BE-NEXT: xscvdpsxws f0, v2
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = fptoui <2 x double> %a to <2 x i16> %0 = fptoui <2 x double> %a to <2 x i16>
%1 = bitcast <2 x i16> %0 to i32 %1 = bitcast <2 x i16> %0 to i32
ret i32 %1 ret i32 %1
} }
define i64 @test4elt(<4 x double>* nocapture readonly) local_unnamed_addr #1 { define i64 @test4elt(<4 x double>* nocapture readonly) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt: ; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs1, r3, r4
; CHECK-P8-NEXT: xscvdpsxws f2, f0 ; CHECK-P8-NEXT: xscvdpsxws f2, f0
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xscvdpsxws f3, f1 ; CHECK-P8-NEXT: xscvdpsxws f3, f1
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r3, f2 ; CHECK-P8-NEXT: mffprwz r3, f2
; CHECK-P8-NEXT: mfvsrwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: mtvsrd f2, r3 ; CHECK-P8-NEXT: mtfprd f2, r3
; CHECK-P8-NEXT: mtvsrd f3, r4 ; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xxswapd v2, vs2 ; CHECK-P8-NEXT: xxswapd v2, vs2
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xxswapd v4, vs3 ; CHECK-P8-NEXT: xxswapd v4, vs3
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xxswapd v5, vs1 ; CHECK-P8-NEXT: xxswapd v5, vs1
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: vmrglh v3, v5, v4 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f2, f1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs0, 16(r3) ; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: xxswapd v2, vs2 ; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglh v2, v2, v3 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: vmrglh v3, v3, v4 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <4 x double>, <4 x double>* %0, align 32 %a = load <4 x double>, <4 x double>* %0, align 32
Show All 17 Lines
; CHECK-P8-NEXT: xscvdpsxws f5, f1 ; CHECK-P8-NEXT: xscvdpsxws f5, f1
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xscvdpsxws f6, f2 ; CHECK-P8-NEXT: xscvdpsxws f6, f2
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xscvdpsxws f7, f3 ; CHECK-P8-NEXT: xscvdpsxws f7, f3
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r3, f4 ; CHECK-P8-NEXT: mffprwz r3, f4
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: mfvsrwz r4, f5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: mtvsrd f4, r3 ; CHECK-P8-NEXT: mtfprd f4, r3
; CHECK-P8-NEXT: mfvsrwz r3, f6 ; CHECK-P8-NEXT: mffprwz r3, f6
; CHECK-P8-NEXT: mtvsrd f5, r4 ; CHECK-P8-NEXT: mtfprd f5, r4
; CHECK-P8-NEXT: xxswapd v2, vs4 ; CHECK-P8-NEXT: xxswapd v2, vs4
; CHECK-P8-NEXT: mfvsrwz r4, f7 ; CHECK-P8-NEXT: mffprwz r4, f7
; CHECK-P8-NEXT: mtvsrd f6, r3 ; CHECK-P8-NEXT: mtfprd f6, r3
; CHECK-P8-NEXT: xxswapd v3, vs5 ; CHECK-P8-NEXT: xxswapd v3, vs5
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mtvsrd f7, r4 ; CHECK-P8-NEXT: mtfprd f7, r4
; CHECK-P8-NEXT: xxswapd v4, vs6 ; CHECK-P8-NEXT: xxswapd v4, vs6
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v1, vs7 ; CHECK-P8-NEXT: xxswapd v1, vs7
; CHECK-P8-NEXT: mfvsrwz r3, f2 ; CHECK-P8-NEXT: mffprwz r3, f2
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v5, vs0 ; CHECK-P8-NEXT: xxswapd v5, vs0
; CHECK-P8-NEXT: mfvsrwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: mtvsrd f2, r3 ; CHECK-P8-NEXT: mtfprd f2, r3
; CHECK-P8-NEXT: xxswapd v0, vs1 ; CHECK-P8-NEXT: xxswapd v0, vs1
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xxswapd v6, vs2 ; CHECK-P8-NEXT: xxswapd v6, vs2
; CHECK-P8-NEXT: vmrglh v2, v5, v2 ; CHECK-P8-NEXT: vmrglh v2, v5, v2
; CHECK-P8-NEXT: xxswapd v5, vs0 ; CHECK-P8-NEXT: xxswapd v5, vs0
; CHECK-P8-NEXT: vmrglh v3, v0, v3 ; CHECK-P8-NEXT: vmrglh v3, v0, v3
; CHECK-P8-NEXT: vmrglh v4, v6, v4 ; CHECK-P8-NEXT: vmrglh v4, v6, v4
; CHECK-P8-NEXT: vmrglh v5, v5, v1 ; CHECK-P8-NEXT: vmrglh v5, v5, v1
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f3 ; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3 ; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs2, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f4 ; CHECK-P9-NEXT: mffprwz r3, f4
; CHECK-P9-NEXT: mtvsrd f4, r3 ; CHECK-P9-NEXT: mtfprd f4, r3
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: xxswapd v2, vs4 ; CHECK-P9-NEXT: xxswapd v2, vs4
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v3, vs3 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2 ; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: vmrglh v2, v2, v3 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs3 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: vmrglh v3, v3, v4 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v3, v4 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0 ; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5 ; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f3 ; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3 ; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghh v4, v4, v5 ; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-BE-NEXT: vmrghw v3, v4, v3 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd v2, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x double>, <8 x double>* %0, align 64 %a = load <8 x double>, <8 x double>* %0, align 64
Show All 28 Lines
; CHECK-P8-NEXT: lxvd2x vs11, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs11, r4, r6
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: xscvdpsxws f12, f5 ; CHECK-P8-NEXT: xscvdpsxws f12, f5
; CHECK-P8-NEXT: xxswapd vs5, vs5 ; CHECK-P8-NEXT: xxswapd vs5, vs5
; CHECK-P8-NEXT: xscvdpsxws f13, f7 ; CHECK-P8-NEXT: xscvdpsxws f13, f7
; CHECK-P8-NEXT: xxswapd vs7, vs7 ; CHECK-P8-NEXT: xxswapd vs7, vs7
; CHECK-P8-NEXT: xscvdpsxws v2, f9 ; CHECK-P8-NEXT: xscvdpsxws v2, f9
; CHECK-P8-NEXT: xxswapd vs9, vs9 ; CHECK-P8-NEXT: xxswapd vs9, vs9
; CHECK-P8-NEXT: mfvsrwz r4, f4 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws v3, f11 ; CHECK-P8-NEXT: xscvdpsxws v3, f11
; CHECK-P8-NEXT: xxswapd vs11, vs11 ; CHECK-P8-NEXT: xxswapd vs11, vs11
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mfvsrwz r6, f6 ; CHECK-P8-NEXT: mffprwz r6, f6
; CHECK-P8-NEXT: mtvsrd f4, r4 ; CHECK-P8-NEXT: mtfprd f4, r4
; CHECK-P8-NEXT: mfvsrwz r4, f8 ; CHECK-P8-NEXT: mffprwz r4, f8
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xxswapd v4, vs4 ; CHECK-P8-NEXT: xxswapd v4, vs4
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: mtvsrd f6, r6 ; CHECK-P8-NEXT: mtfprd f6, r6
; CHECK-P8-NEXT: mfvsrwz r6, f10 ; CHECK-P8-NEXT: mffprwz r6, f10
; CHECK-P8-NEXT: mtvsrd f8, r4 ; CHECK-P8-NEXT: mtfprd f8, r4
; CHECK-P8-NEXT: xxswapd v5, vs6 ; CHECK-P8-NEXT: xxswapd v5, vs6
; CHECK-P8-NEXT: mfvsrwz r4, f12 ; CHECK-P8-NEXT: mffprwz r4, f12
; CHECK-P8-NEXT: xscvdpsxws f5, f5 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: xxswapd v0, vs8 ; CHECK-P8-NEXT: xxswapd v0, vs8
; CHECK-P8-NEXT: mtvsrd f10, r6 ; CHECK-P8-NEXT: mtfprd f10, r6
; CHECK-P8-NEXT: mfvsrwz r6, f13 ; CHECK-P8-NEXT: mffprwz r6, f13
; CHECK-P8-NEXT: mtvsrd f12, r4 ; CHECK-P8-NEXT: mtfprd f12, r4
; CHECK-P8-NEXT: xxswapd v1, vs10 ; CHECK-P8-NEXT: xxswapd v1, vs10
; CHECK-P8-NEXT: mfvsrwz r4, v2 ; CHECK-P8-NEXT: mfvsrwz r4, v2
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xxswapd v6, vs12 ; CHECK-P8-NEXT: xxswapd v6, vs12
; CHECK-P8-NEXT: xscvdpsxws f9, f9 ; CHECK-P8-NEXT: xscvdpsxws f9, f9
; CHECK-P8-NEXT: mtvsrd f13, r6 ; CHECK-P8-NEXT: mtfprd f13, r6
; CHECK-P8-NEXT: mfvsrwz r6, v3 ; CHECK-P8-NEXT: mfvsrwz r6, v3
; CHECK-P8-NEXT: mtvsrd v2, r4 ; CHECK-P8-NEXT: mtvsrd v2, r4
; CHECK-P8-NEXT: xxswapd v7, vs13 ; CHECK-P8-NEXT: xxswapd v7, vs13
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvdpsxws f7, f7 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
; CHECK-P8-NEXT: xxswapd v2, v2 ; CHECK-P8-NEXT: xxswapd v2, v2
; CHECK-P8-NEXT: xscvdpsxws f11, f11 ; CHECK-P8-NEXT: xscvdpsxws f11, f11
; CHECK-P8-NEXT: mtvsrd v3, r6 ; CHECK-P8-NEXT: mtvsrd v3, r6
; CHECK-P8-NEXT: mfvsrwz r6, f1 ; CHECK-P8-NEXT: mffprwz r6, f1
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xxswapd v3, v3 ; CHECK-P8-NEXT: xxswapd v3, v3
; CHECK-P8-NEXT: mfvsrwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: mtvsrd f1, r6 ; CHECK-P8-NEXT: mtfprd f1, r6
; CHECK-P8-NEXT: xxswapd v8, vs0 ; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: mtvsrd f2, r4 ; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: mfvsrwz r4, f5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xxswapd v9, vs1 ; CHECK-P8-NEXT: xxswapd v9, vs1
; CHECK-P8-NEXT: mfvsrwz r6, f3 ; CHECK-P8-NEXT: mffprwz r6, f3
; CHECK-P8-NEXT: xxswapd v10, vs2 ; CHECK-P8-NEXT: xxswapd v10, vs2
; CHECK-P8-NEXT: mtvsrd f5, r4 ; CHECK-P8-NEXT: mtfprd f5, r4
; CHECK-P8-NEXT: mfvsrwz r4, f9 ; CHECK-P8-NEXT: mffprwz r4, f9
; CHECK-P8-NEXT: mtvsrd f3, r6 ; CHECK-P8-NEXT: mtfprd f3, r6
; CHECK-P8-NEXT: mfvsrwz r6, f7 ; CHECK-P8-NEXT: mffprwz r6, f7
; CHECK-P8-NEXT: mtvsrd f9, r4 ; CHECK-P8-NEXT: mtfprd f9, r4
; CHECK-P8-NEXT: mfvsrwz r4, f11 ; CHECK-P8-NEXT: mffprwz r4, f11
; CHECK-P8-NEXT: vmrglh v4, v8, v4 ; CHECK-P8-NEXT: vmrglh v4, v8, v4
; CHECK-P8-NEXT: xxswapd v8, vs3 ; CHECK-P8-NEXT: xxswapd v8, vs3
; CHECK-P8-NEXT: vmrglh v5, v9, v5 ; CHECK-P8-NEXT: vmrglh v5, v9, v5
; CHECK-P8-NEXT: xxswapd v9, vs5 ; CHECK-P8-NEXT: xxswapd v9, vs5
; CHECK-P8-NEXT: mtvsrd f7, r6 ; CHECK-P8-NEXT: mtfprd f7, r6
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: vmrglh v0, v10, v0 ; CHECK-P8-NEXT: vmrglh v0, v10, v0
; CHECK-P8-NEXT: xxswapd v10, vs7 ; CHECK-P8-NEXT: xxswapd v10, vs7
; CHECK-P8-NEXT: vmrglh v1, v8, v1 ; CHECK-P8-NEXT: vmrglh v1, v8, v1
; CHECK-P8-NEXT: xxswapd v8, vs9 ; CHECK-P8-NEXT: xxswapd v8, vs9
; CHECK-P8-NEXT: vmrglh v6, v9, v6 ; CHECK-P8-NEXT: vmrglh v6, v9, v6
; CHECK-P8-NEXT: xxswapd v9, vs0 ; CHECK-P8-NEXT: xxswapd v9, vs0
; CHECK-P8-NEXT: vmrglh v7, v10, v7 ; CHECK-P8-NEXT: vmrglh v7, v10, v7
; CHECK-P8-NEXT: vmrglh v2, v8, v2 ; CHECK-P8-NEXT: vmrglh v2, v8, v2
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; CHECK-P9-NEXT: xscvdpsxws f5, f4 ; CHECK-P9-NEXT: xscvdpsxws f5, f4
; CHECK-P9-NEXT: lxv vs1, 48(r4) ; CHECK-P9-NEXT: lxv vs1, 48(r4)
; CHECK-P9-NEXT: xscvdpsxws f6, f3 ; CHECK-P9-NEXT: xscvdpsxws f6, f3
; CHECK-P9-NEXT: lxv vs0, 64(r4) ; CHECK-P9-NEXT: lxv vs0, 64(r4)
; CHECK-P9-NEXT: xscvdpsxws f7, f2 ; CHECK-P9-NEXT: xscvdpsxws f7, f2
; CHECK-P9-NEXT: xscvdpsxws f8, f1 ; CHECK-P9-NEXT: xscvdpsxws f8, f1
; CHECK-P9-NEXT: xxswapd vs4, vs4 ; CHECK-P9-NEXT: xxswapd vs4, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: mfvsrwz r5, f5 ; CHECK-P9-NEXT: mffprwz r5, f5
; CHECK-P9-NEXT: xscvdpsxws f9, f0 ; CHECK-P9-NEXT: xscvdpsxws f9, f0
; CHECK-P9-NEXT: xxswapd vs3, vs3 ; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mtvsrd f5, r5 ; CHECK-P9-NEXT: mtfprd f5, r5
; CHECK-P9-NEXT: mfvsrwz r5, f6 ; CHECK-P9-NEXT: mffprwz r5, f6
; CHECK-P9-NEXT: xxswapd vs2, vs2 ; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f6, r5 ; CHECK-P9-NEXT: mtfprd f6, r5
; CHECK-P9-NEXT: mfvsrwz r5, f7 ; CHECK-P9-NEXT: mffprwz r5, f7
; CHECK-P9-NEXT: mtvsrd f7, r5 ; CHECK-P9-NEXT: mtfprd f7, r5
; CHECK-P9-NEXT: mfvsrwz r5, f8 ; CHECK-P9-NEXT: mffprwz r5, f8
; CHECK-P9-NEXT: mtvsrd f8, r5 ; CHECK-P9-NEXT: mtfprd f8, r5
; CHECK-P9-NEXT: mfvsrwz r5, f9 ; CHECK-P9-NEXT: mffprwz r5, f9
; CHECK-P9-NEXT: mtvsrd f9, r5 ; CHECK-P9-NEXT: mtfprd f9, r5
; CHECK-P9-NEXT: mfvsrwz r5, f4 ; CHECK-P9-NEXT: mffprwz r5, f4
; CHECK-P9-NEXT: mtvsrd f4, r5 ; CHECK-P9-NEXT: mtfprd f4, r5
; CHECK-P9-NEXT: mfvsrwz r5, f3 ; CHECK-P9-NEXT: mffprwz r5, f3
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xxswapd v2, vs5 ; CHECK-P9-NEXT: xxswapd v2, vs5
; CHECK-P9-NEXT: xxswapd v5, vs8 ; CHECK-P9-NEXT: xxswapd v5, vs8
; CHECK-P9-NEXT: xxswapd v0, vs9 ; CHECK-P9-NEXT: xxswapd v0, vs9
; CHECK-P9-NEXT: mtvsrd f3, r5 ; CHECK-P9-NEXT: mtfprd f3, r5
; CHECK-P9-NEXT: mfvsrwz r5, f2 ; CHECK-P9-NEXT: mffprwz r5, f2
; CHECK-P9-NEXT: mtvsrd f2, r5 ; CHECK-P9-NEXT: mtfprd f2, r5
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xxswapd v1, vs2 ; CHECK-P9-NEXT: xxswapd v1, vs2
; CHECK-P9-NEXT: lxv vs2, 80(r4) ; CHECK-P9-NEXT: lxv vs2, 80(r4)
; CHECK-P9-NEXT: xxswapd v3, vs4 ; CHECK-P9-NEXT: xxswapd v3, vs4
; CHECK-P9-NEXT: vmrglh v2, v2, v3 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs6 ; CHECK-P9-NEXT: xxswapd v3, vs6
; CHECK-P9-NEXT: xxswapd v4, vs3 ; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2 ; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: mfvsrwz r5, f1 ; CHECK-P9-NEXT: mffprwz r5, f1
; CHECK-P9-NEXT: vmrglh v3, v3, v4 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs7 ; CHECK-P9-NEXT: xxswapd v4, vs7
; CHECK-P9-NEXT: mtvsrd f1, r5 ; CHECK-P9-NEXT: mtfprd f1, r5
; CHECK-P9-NEXT: mfvsrwz r5, f0 ; CHECK-P9-NEXT: mffprwz r5, f0
; CHECK-P9-NEXT: vmrglh v4, v4, v1 ; CHECK-P9-NEXT: vmrglh v4, v4, v1
; CHECK-P9-NEXT: xxswapd v1, vs1 ; CHECK-P9-NEXT: xxswapd v1, vs1
; CHECK-P9-NEXT: mtvsrd f0, r5 ; CHECK-P9-NEXT: mtfprd f0, r5
; CHECK-P9-NEXT: vmrglh v5, v5, v1 ; CHECK-P9-NEXT: vmrglh v5, v5, v1
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xxswapd v1, vs0 ; CHECK-P9-NEXT: xxswapd v1, vs0
; CHECK-P9-NEXT: lxv vs0, 112(r4) ; CHECK-P9-NEXT: lxv vs0, 112(r4)
; CHECK-P9-NEXT: lxv vs1, 96(r4) ; CHECK-P9-NEXT: lxv vs1, 96(r4)
; CHECK-P9-NEXT: mfvsrwz r4, f3 ; CHECK-P9-NEXT: mffprwz r4, f3
; CHECK-P9-NEXT: mtvsrd f3, r4 ; CHECK-P9-NEXT: mtfprd f3, r4
; CHECK-P9-NEXT: mfvsrwz r4, f2 ; CHECK-P9-NEXT: mffprwz r4, f2
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: vmrglw v3, v5, v4 ; CHECK-P9-NEXT: vmrglw v3, v5, v4
; CHECK-P9-NEXT: xxmrgld vs4, v3, v2 ; CHECK-P9-NEXT: xxmrgld vs4, v3, v2
; CHECK-P9-NEXT: xxswapd v2, vs3 ; CHECK-P9-NEXT: xxswapd v2, vs3
; CHECK-P9-NEXT: vmrglh v0, v0, v1 ; CHECK-P9-NEXT: vmrglh v0, v0, v1
; CHECK-P9-NEXT: mtvsrd f2, r4 ; CHECK-P9-NEXT: mtfprd f2, r4
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r4, f2 ; CHECK-P9-NEXT: mffprwz r4, f2
; CHECK-P9-NEXT: mtvsrd f2, r4 ; CHECK-P9-NEXT: mtfprd f2, r4
; CHECK-P9-NEXT: mfvsrwz r4, f1 ; CHECK-P9-NEXT: mffprwz r4, f1
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: mtfprd f1, r4
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r4, f1 ; CHECK-P9-NEXT: mffprwz r4, f1
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: mtfprd f1, r4
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: vmrglh v2, v2, v3 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglh v3, v3, v4 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: vmrglw v2, v2, v0 ; CHECK-P9-NEXT: vmrglw v2, v2, v0
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: xxswapd v5, vs0 ; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5 ; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld vs0, v3, v2 ; CHECK-P9-NEXT: xxmrgld vs0, v3, v2
; CHECK-P9-NEXT: stxv vs0, 16(r3) ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: stxv vs4, 0(r3) ; CHECK-P9-NEXT: stxv vs4, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs4, 48(r4) ; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: xscvdpsxws f5, f4 ; CHECK-BE-NEXT: xscvdpsxws f5, f4
; CHECK-BE-NEXT: xxswapd vs4, vs4 ; CHECK-BE-NEXT: xxswapd vs4, vs4
; CHECK-BE-NEXT: lxv vs3, 32(r4) ; CHECK-BE-NEXT: lxv vs3, 32(r4)
; CHECK-BE-NEXT: xscvdpsxws f6, f3 ; CHECK-BE-NEXT: xscvdpsxws f6, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3 ; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: mfvsrwz r5, f5 ; CHECK-BE-NEXT: mffprwz r5, f5
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs2, 16(r4) ; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f7, f2 ; CHECK-BE-NEXT: xscvdpsxws f7, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v2, r5 ; CHECK-BE-NEXT: mtvsrd v2, r5
; CHECK-BE-NEXT: mfvsrwz r5, f4 ; CHECK-BE-NEXT: mffprwz r5, f4
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs1, 0(r4) ; CHECK-BE-NEXT: lxv vs1, 0(r4)
; CHECK-BE-NEXT: xscvdpsxws f4, f1 ; CHECK-BE-NEXT: xscvdpsxws f4, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: mfvsrwz r5, f6 ; CHECK-BE-NEXT: mffprwz r5, f6
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs0, 112(r4) ; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: mfvsrwz r5, f3 ; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f0 ; CHECK-BE-NEXT: xscvdpsxws f3, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mfvsrwz r5, f7 ; CHECK-BE-NEXT: mffprwz r5, f7
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mfvsrwz r5, f4 ; CHECK-BE-NEXT: mffprwz r5, f4
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v5, r5 ; CHECK-BE-NEXT: mtvsrd v5, r5
; CHECK-BE-NEXT: mfvsrwz r5, f3 ; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v0, r5 ; CHECK-BE-NEXT: mtvsrd v0, r5
; CHECK-BE-NEXT: mfvsrwz r5, f2 ; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: lxv vs2, 96(r4) ; CHECK-BE-NEXT: lxv vs2, 96(r4)
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v1, r5 ; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: mfvsrwz r5, f1 ; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: lxv vs1, 80(r4) ; CHECK-BE-NEXT: lxv vs1, 80(r4)
; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v4, v4, v1 ; CHECK-BE-NEXT: vmrghh v4, v4, v1
; CHECK-BE-NEXT: mtvsrd v1, r5 ; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghh v5, v5, v1 ; CHECK-BE-NEXT: vmrghh v5, v5, v1
; CHECK-BE-NEXT: mfvsrwz r5, f0 ; CHECK-BE-NEXT: mffprwz r5, f0
; CHECK-BE-NEXT: lxv vs0, 64(r4) ; CHECK-BE-NEXT: lxv vs0, 64(r4)
; CHECK-BE-NEXT: mfvsrwz r4, f3 ; CHECK-BE-NEXT: mffprwz r4, f3
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghw v3, v5, v4 ; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: xxmrghd vs3, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs3, v3, v2
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: mfvsrwz r4, f2 ; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: mfvsrwz r4, f2 ; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mfvsrwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mfvsrwz r4, f0 ; CHECK-BE-NEXT: mffprwz r4, f0
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v1, r5 ; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: vmrghh v0, v0, v1 ; CHECK-BE-NEXT: vmrghh v0, v0, v1
; CHECK-BE-NEXT: vmrghw v2, v2, v0 ; CHECK-BE-NEXT: vmrghw v2, v2, v0
; CHECK-BE-NEXT: stxv vs3, 0(r3) ; CHECK-BE-NEXT: stxv vs3, 0(r3)
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v5, r4 ; CHECK-BE-NEXT: mtvsrd v5, r4
; CHECK-BE-NEXT: vmrghh v4, v4, v5 ; CHECK-BE-NEXT: vmrghh v4, v4, v5
Show All 9 Lines
} }
define i32 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 { define i32 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xscvdpsxws f1, v2 ; CHECK-P8-NEXT: xscvdpsxws f1, v2
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglh v2, v2, v3 ; CHECK-P8-NEXT: vmrglh v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpsxws f0, v2 ; CHECK-P9-NEXT: xscvdpsxws f0, v2
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xscvdpsxws f0, v2 ; CHECK-BE-NEXT: xscvdpsxws f0, v2
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = fptosi <2 x double> %a to <2 x i16> %0 = fptosi <2 x double> %a to <2 x i16>
%1 = bitcast <2 x i16> %0 to i32 %1 = bitcast <2 x i16> %0 to i32
ret i32 %1 ret i32 %1
} }
define i64 @test4elt_signed(<4 x double>* nocapture readonly) local_unnamed_addr #1 { define i64 @test4elt_signed(<4 x double>* nocapture readonly) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs1, r3, r4
; CHECK-P8-NEXT: xscvdpsxws f2, f0 ; CHECK-P8-NEXT: xscvdpsxws f2, f0
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xscvdpsxws f3, f1 ; CHECK-P8-NEXT: xscvdpsxws f3, f1
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r3, f2 ; CHECK-P8-NEXT: mffprwz r3, f2
; CHECK-P8-NEXT: mfvsrwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: mtvsrd f2, r3 ; CHECK-P8-NEXT: mtfprd f2, r3
; CHECK-P8-NEXT: mtvsrd f3, r4 ; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xxswapd v2, vs2 ; CHECK-P8-NEXT: xxswapd v2, vs2
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xxswapd v4, vs3 ; CHECK-P8-NEXT: xxswapd v4, vs3
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xxswapd v5, vs1 ; CHECK-P8-NEXT: xxswapd v5, vs1
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: vmrglh v3, v5, v4 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f2, f1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs0, 16(r3) ; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: xxswapd v2, vs2 ; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglh v2, v2, v3 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: vmrglh v3, v3, v4 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <4 x double>, <4 x double>* %0, align 32 %a = load <4 x double>, <4 x double>* %0, align 32
Show All 17 Lines
; CHECK-P8-NEXT: xscvdpsxws f5, f1 ; CHECK-P8-NEXT: xscvdpsxws f5, f1
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xscvdpsxws f6, f2 ; CHECK-P8-NEXT: xscvdpsxws f6, f2
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xscvdpsxws f7, f3 ; CHECK-P8-NEXT: xscvdpsxws f7, f3
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r3, f4 ; CHECK-P8-NEXT: mffprwz r3, f4
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: mfvsrwz r4, f5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: mtvsrd f4, r3 ; CHECK-P8-NEXT: mtfprd f4, r3
; CHECK-P8-NEXT: mfvsrwz r3, f6 ; CHECK-P8-NEXT: mffprwz r3, f6
; CHECK-P8-NEXT: mtvsrd f5, r4 ; CHECK-P8-NEXT: mtfprd f5, r4
; CHECK-P8-NEXT: xxswapd v2, vs4 ; CHECK-P8-NEXT: xxswapd v2, vs4
; CHECK-P8-NEXT: mfvsrwz r4, f7 ; CHECK-P8-NEXT: mffprwz r4, f7
; CHECK-P8-NEXT: mtvsrd f6, r3 ; CHECK-P8-NEXT: mtfprd f6, r3
; CHECK-P8-NEXT: xxswapd v3, vs5 ; CHECK-P8-NEXT: xxswapd v3, vs5
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mtvsrd f7, r4 ; CHECK-P8-NEXT: mtfprd f7, r4
; CHECK-P8-NEXT: xxswapd v4, vs6 ; CHECK-P8-NEXT: xxswapd v4, vs6
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v1, vs7 ; CHECK-P8-NEXT: xxswapd v1, vs7
; CHECK-P8-NEXT: mfvsrwz r3, f2 ; CHECK-P8-NEXT: mffprwz r3, f2
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v5, vs0 ; CHECK-P8-NEXT: xxswapd v5, vs0
; CHECK-P8-NEXT: mfvsrwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: mtvsrd f2, r3 ; CHECK-P8-NEXT: mtfprd f2, r3
; CHECK-P8-NEXT: xxswapd v0, vs1 ; CHECK-P8-NEXT: xxswapd v0, vs1
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xxswapd v6, vs2 ; CHECK-P8-NEXT: xxswapd v6, vs2
; CHECK-P8-NEXT: vmrglh v2, v5, v2 ; CHECK-P8-NEXT: vmrglh v2, v5, v2
; CHECK-P8-NEXT: xxswapd v5, vs0 ; CHECK-P8-NEXT: xxswapd v5, vs0
; CHECK-P8-NEXT: vmrglh v3, v0, v3 ; CHECK-P8-NEXT: vmrglh v3, v0, v3
; CHECK-P8-NEXT: vmrglh v4, v6, v4 ; CHECK-P8-NEXT: vmrglh v4, v6, v4
; CHECK-P8-NEXT: vmrglh v5, v5, v1 ; CHECK-P8-NEXT: vmrglh v5, v5, v1
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: vmrglw v3, v5, v4 ; CHECK-P8-NEXT: vmrglw v3, v5, v4
; CHECK-P8-NEXT: xxmrgld v2, v3, v2 ; CHECK-P8-NEXT: xxmrgld v2, v3, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f3 ; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3 ; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs2, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f4 ; CHECK-P9-NEXT: mffprwz r3, f4
; CHECK-P9-NEXT: mtvsrd f4, r3 ; CHECK-P9-NEXT: mtfprd f4, r3
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: xxswapd v2, vs4 ; CHECK-P9-NEXT: xxswapd v2, vs4
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v3, vs3 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2 ; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: vmrglh v2, v2, v3 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs3 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: vmrglh v3, v3, v4 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglh v3, v3, v4 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0 ; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5 ; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f3 ; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3 ; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 48 ; CHECK-BE-NEXT: sldi r3, r3, 48
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghh v4, v4, v5 ; CHECK-BE-NEXT: vmrghh v4, v4, v5
; CHECK-BE-NEXT: vmrghw v3, v4, v3 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd v2, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <8 x double>, <8 x double>* %0, align 64 %a = load <8 x double>, <8 x double>* %0, align 64
Show All 28 Lines
; CHECK-P8-NEXT: lxvd2x vs11, r4, r6 ; CHECK-P8-NEXT: lxvd2x vs11, r4, r6
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: xscvdpsxws f12, f5 ; CHECK-P8-NEXT: xscvdpsxws f12, f5
; CHECK-P8-NEXT: xxswapd vs5, vs5 ; CHECK-P8-NEXT: xxswapd vs5, vs5
; CHECK-P8-NEXT: xscvdpsxws f13, f7 ; CHECK-P8-NEXT: xscvdpsxws f13, f7
; CHECK-P8-NEXT: xxswapd vs7, vs7 ; CHECK-P8-NEXT: xxswapd vs7, vs7
; CHECK-P8-NEXT: xscvdpsxws v2, f9 ; CHECK-P8-NEXT: xscvdpsxws v2, f9
; CHECK-P8-NEXT: xxswapd vs9, vs9 ; CHECK-P8-NEXT: xxswapd vs9, vs9
; CHECK-P8-NEXT: mfvsrwz r4, f4 ; CHECK-P8-NEXT: mffprwz r4, f4
; CHECK-P8-NEXT: xscvdpsxws v3, f11 ; CHECK-P8-NEXT: xscvdpsxws v3, f11
; CHECK-P8-NEXT: xxswapd vs11, vs11 ; CHECK-P8-NEXT: xxswapd vs11, vs11
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mfvsrwz r6, f6 ; CHECK-P8-NEXT: mffprwz r6, f6
; CHECK-P8-NEXT: mtvsrd f4, r4 ; CHECK-P8-NEXT: mtfprd f4, r4
; CHECK-P8-NEXT: mfvsrwz r4, f8 ; CHECK-P8-NEXT: mffprwz r4, f8
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xxswapd v4, vs4 ; CHECK-P8-NEXT: xxswapd v4, vs4
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: mtvsrd f6, r6 ; CHECK-P8-NEXT: mtfprd f6, r6
; CHECK-P8-NEXT: mfvsrwz r6, f10 ; CHECK-P8-NEXT: mffprwz r6, f10
; CHECK-P8-NEXT: mtvsrd f8, r4 ; CHECK-P8-NEXT: mtfprd f8, r4
; CHECK-P8-NEXT: xxswapd v5, vs6 ; CHECK-P8-NEXT: xxswapd v5, vs6
; CHECK-P8-NEXT: mfvsrwz r4, f12 ; CHECK-P8-NEXT: mffprwz r4, f12
; CHECK-P8-NEXT: xscvdpsxws f5, f5 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: xxswapd v0, vs8 ; CHECK-P8-NEXT: xxswapd v0, vs8
; CHECK-P8-NEXT: mtvsrd f10, r6 ; CHECK-P8-NEXT: mtfprd f10, r6
; CHECK-P8-NEXT: mfvsrwz r6, f13 ; CHECK-P8-NEXT: mffprwz r6, f13
; CHECK-P8-NEXT: mtvsrd f12, r4 ; CHECK-P8-NEXT: mtfprd f12, r4
; CHECK-P8-NEXT: xxswapd v1, vs10 ; CHECK-P8-NEXT: xxswapd v1, vs10
; CHECK-P8-NEXT: mfvsrwz r4, v2 ; CHECK-P8-NEXT: mfvsrwz r4, v2
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xxswapd v6, vs12 ; CHECK-P8-NEXT: xxswapd v6, vs12
; CHECK-P8-NEXT: xscvdpsxws f9, f9 ; CHECK-P8-NEXT: xscvdpsxws f9, f9
; CHECK-P8-NEXT: mtvsrd f13, r6 ; CHECK-P8-NEXT: mtfprd f13, r6
; CHECK-P8-NEXT: mfvsrwz r6, v3 ; CHECK-P8-NEXT: mfvsrwz r6, v3
; CHECK-P8-NEXT: mtvsrd v2, r4 ; CHECK-P8-NEXT: mtvsrd v2, r4
; CHECK-P8-NEXT: xxswapd v7, vs13 ; CHECK-P8-NEXT: xxswapd v7, vs13
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: xscvdpsxws f7, f7 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
; CHECK-P8-NEXT: xxswapd v2, v2 ; CHECK-P8-NEXT: xxswapd v2, v2
; CHECK-P8-NEXT: xscvdpsxws f11, f11 ; CHECK-P8-NEXT: xscvdpsxws f11, f11
; CHECK-P8-NEXT: mtvsrd v3, r6 ; CHECK-P8-NEXT: mtvsrd v3, r6
; CHECK-P8-NEXT: mfvsrwz r6, f1 ; CHECK-P8-NEXT: mffprwz r6, f1
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xxswapd v3, v3 ; CHECK-P8-NEXT: xxswapd v3, v3
; CHECK-P8-NEXT: mfvsrwz r4, f2 ; CHECK-P8-NEXT: mffprwz r4, f2
; CHECK-P8-NEXT: mtvsrd f1, r6 ; CHECK-P8-NEXT: mtfprd f1, r6
; CHECK-P8-NEXT: xxswapd v8, vs0 ; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: mtvsrd f2, r4 ; CHECK-P8-NEXT: mtfprd f2, r4
; CHECK-P8-NEXT: mfvsrwz r4, f5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: xxswapd v9, vs1 ; CHECK-P8-NEXT: xxswapd v9, vs1
; CHECK-P8-NEXT: mfvsrwz r6, f3 ; CHECK-P8-NEXT: mffprwz r6, f3
; CHECK-P8-NEXT: xxswapd v10, vs2 ; CHECK-P8-NEXT: xxswapd v10, vs2
; CHECK-P8-NEXT: mtvsrd f5, r4 ; CHECK-P8-NEXT: mtfprd f5, r4
; CHECK-P8-NEXT: mfvsrwz r4, f9 ; CHECK-P8-NEXT: mffprwz r4, f9
; CHECK-P8-NEXT: mtvsrd f3, r6 ; CHECK-P8-NEXT: mtfprd f3, r6
; CHECK-P8-NEXT: mfvsrwz r6, f7 ; CHECK-P8-NEXT: mffprwz r6, f7
; CHECK-P8-NEXT: mtvsrd f9, r4 ; CHECK-P8-NEXT: mtfprd f9, r4
; CHECK-P8-NEXT: mfvsrwz r4, f11 ; CHECK-P8-NEXT: mffprwz r4, f11
; CHECK-P8-NEXT: vmrglh v4, v8, v4 ; CHECK-P8-NEXT: vmrglh v4, v8, v4
; CHECK-P8-NEXT: xxswapd v8, vs3 ; CHECK-P8-NEXT: xxswapd v8, vs3
; CHECK-P8-NEXT: vmrglh v5, v9, v5 ; CHECK-P8-NEXT: vmrglh v5, v9, v5
; CHECK-P8-NEXT: xxswapd v9, vs5 ; CHECK-P8-NEXT: xxswapd v9, vs5
; CHECK-P8-NEXT: mtvsrd f7, r6 ; CHECK-P8-NEXT: mtfprd f7, r6
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: vmrglh v0, v10, v0 ; CHECK-P8-NEXT: vmrglh v0, v10, v0
; CHECK-P8-NEXT: xxswapd v10, vs7 ; CHECK-P8-NEXT: xxswapd v10, vs7
; CHECK-P8-NEXT: vmrglh v1, v8, v1 ; CHECK-P8-NEXT: vmrglh v1, v8, v1
; CHECK-P8-NEXT: xxswapd v8, vs9 ; CHECK-P8-NEXT: xxswapd v8, vs9
; CHECK-P8-NEXT: vmrglh v6, v9, v6 ; CHECK-P8-NEXT: vmrglh v6, v9, v6
; CHECK-P8-NEXT: xxswapd v9, vs0 ; CHECK-P8-NEXT: xxswapd v9, vs0
; CHECK-P8-NEXT: vmrglh v7, v10, v7 ; CHECK-P8-NEXT: vmrglh v7, v10, v7
; CHECK-P8-NEXT: vmrglh v2, v8, v2 ; CHECK-P8-NEXT: vmrglh v2, v8, v2
Show All 16 Lines
; CHECK-P9-NEXT: xscvdpsxws f5, f4 ; CHECK-P9-NEXT: xscvdpsxws f5, f4
; CHECK-P9-NEXT: lxv vs1, 48(r4) ; CHECK-P9-NEXT: lxv vs1, 48(r4)
; CHECK-P9-NEXT: xscvdpsxws f6, f3 ; CHECK-P9-NEXT: xscvdpsxws f6, f3
; CHECK-P9-NEXT: lxv vs0, 64(r4) ; CHECK-P9-NEXT: lxv vs0, 64(r4)
; CHECK-P9-NEXT: xscvdpsxws f7, f2 ; CHECK-P9-NEXT: xscvdpsxws f7, f2
; CHECK-P9-NEXT: xscvdpsxws f8, f1 ; CHECK-P9-NEXT: xscvdpsxws f8, f1
; CHECK-P9-NEXT: xxswapd vs4, vs4 ; CHECK-P9-NEXT: xxswapd vs4, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: mfvsrwz r5, f5 ; CHECK-P9-NEXT: mffprwz r5, f5
; CHECK-P9-NEXT: xscvdpsxws f9, f0 ; CHECK-P9-NEXT: xscvdpsxws f9, f0
; CHECK-P9-NEXT: xxswapd vs3, vs3 ; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: mtvsrd f5, r5 ; CHECK-P9-NEXT: mtfprd f5, r5
; CHECK-P9-NEXT: mfvsrwz r5, f6 ; CHECK-P9-NEXT: mffprwz r5, f6
; CHECK-P9-NEXT: xxswapd vs2, vs2 ; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mtvsrd f6, r5 ; CHECK-P9-NEXT: mtfprd f6, r5
; CHECK-P9-NEXT: mfvsrwz r5, f7 ; CHECK-P9-NEXT: mffprwz r5, f7
; CHECK-P9-NEXT: mtvsrd f7, r5 ; CHECK-P9-NEXT: mtfprd f7, r5
; CHECK-P9-NEXT: mfvsrwz r5, f8 ; CHECK-P9-NEXT: mffprwz r5, f8
; CHECK-P9-NEXT: mtvsrd f8, r5 ; CHECK-P9-NEXT: mtfprd f8, r5
; CHECK-P9-NEXT: mfvsrwz r5, f9 ; CHECK-P9-NEXT: mffprwz r5, f9
; CHECK-P9-NEXT: mtvsrd f9, r5 ; CHECK-P9-NEXT: mtfprd f9, r5
; CHECK-P9-NEXT: mfvsrwz r5, f4 ; CHECK-P9-NEXT: mffprwz r5, f4
; CHECK-P9-NEXT: mtvsrd f4, r5 ; CHECK-P9-NEXT: mtfprd f4, r5
; CHECK-P9-NEXT: mfvsrwz r5, f3 ; CHECK-P9-NEXT: mffprwz r5, f3
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: xxswapd v2, vs5 ; CHECK-P9-NEXT: xxswapd v2, vs5
; CHECK-P9-NEXT: xxswapd v5, vs8 ; CHECK-P9-NEXT: xxswapd v5, vs8
; CHECK-P9-NEXT: xxswapd v0, vs9 ; CHECK-P9-NEXT: xxswapd v0, vs9
; CHECK-P9-NEXT: mtvsrd f3, r5 ; CHECK-P9-NEXT: mtfprd f3, r5
; CHECK-P9-NEXT: mfvsrwz r5, f2 ; CHECK-P9-NEXT: mffprwz r5, f2
; CHECK-P9-NEXT: mtvsrd f2, r5 ; CHECK-P9-NEXT: mtfprd f2, r5
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: xxswapd v1, vs2 ; CHECK-P9-NEXT: xxswapd v1, vs2
; CHECK-P9-NEXT: lxv vs2, 80(r4) ; CHECK-P9-NEXT: lxv vs2, 80(r4)
; CHECK-P9-NEXT: xxswapd v3, vs4 ; CHECK-P9-NEXT: xxswapd v3, vs4
; CHECK-P9-NEXT: vmrglh v2, v2, v3 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs6 ; CHECK-P9-NEXT: xxswapd v3, vs6
; CHECK-P9-NEXT: xxswapd v4, vs3 ; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2 ; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: mfvsrwz r5, f1 ; CHECK-P9-NEXT: mffprwz r5, f1
; CHECK-P9-NEXT: vmrglh v3, v3, v4 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs7 ; CHECK-P9-NEXT: xxswapd v4, vs7
; CHECK-P9-NEXT: mtvsrd f1, r5 ; CHECK-P9-NEXT: mtfprd f1, r5
; CHECK-P9-NEXT: mfvsrwz r5, f0 ; CHECK-P9-NEXT: mffprwz r5, f0
; CHECK-P9-NEXT: vmrglh v4, v4, v1 ; CHECK-P9-NEXT: vmrglh v4, v4, v1
; CHECK-P9-NEXT: xxswapd v1, vs1 ; CHECK-P9-NEXT: xxswapd v1, vs1
; CHECK-P9-NEXT: mtvsrd f0, r5 ; CHECK-P9-NEXT: mtfprd f0, r5
; CHECK-P9-NEXT: vmrglh v5, v5, v1 ; CHECK-P9-NEXT: vmrglh v5, v5, v1
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: xxswapd v1, vs0 ; CHECK-P9-NEXT: xxswapd v1, vs0
; CHECK-P9-NEXT: lxv vs0, 112(r4) ; CHECK-P9-NEXT: lxv vs0, 112(r4)
; CHECK-P9-NEXT: lxv vs1, 96(r4) ; CHECK-P9-NEXT: lxv vs1, 96(r4)
; CHECK-P9-NEXT: mfvsrwz r4, f3 ; CHECK-P9-NEXT: mffprwz r4, f3
; CHECK-P9-NEXT: mtvsrd f3, r4 ; CHECK-P9-NEXT: mtfprd f3, r4
; CHECK-P9-NEXT: mfvsrwz r4, f2 ; CHECK-P9-NEXT: mffprwz r4, f2
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: vmrglw v3, v5, v4 ; CHECK-P9-NEXT: vmrglw v3, v5, v4
; CHECK-P9-NEXT: xxmrgld vs4, v3, v2 ; CHECK-P9-NEXT: xxmrgld vs4, v3, v2
; CHECK-P9-NEXT: xxswapd v2, vs3 ; CHECK-P9-NEXT: xxswapd v2, vs3
; CHECK-P9-NEXT: vmrglh v0, v0, v1 ; CHECK-P9-NEXT: vmrglh v0, v0, v1
; CHECK-P9-NEXT: mtvsrd f2, r4 ; CHECK-P9-NEXT: mtfprd f2, r4
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r4, f2 ; CHECK-P9-NEXT: mffprwz r4, f2
; CHECK-P9-NEXT: mtvsrd f2, r4 ; CHECK-P9-NEXT: mtfprd f2, r4
; CHECK-P9-NEXT: mfvsrwz r4, f1 ; CHECK-P9-NEXT: mffprwz r4, f1
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: mtfprd f1, r4
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r4, f1 ; CHECK-P9-NEXT: mffprwz r4, f1
; CHECK-P9-NEXT: mtvsrd f1, r4 ; CHECK-P9-NEXT: mtfprd f1, r4
; CHECK-P9-NEXT: mfvsrwz r4, f0 ; CHECK-P9-NEXT: mffprwz r4, f0
; CHECK-P9-NEXT: vmrglh v2, v2, v3 ; CHECK-P9-NEXT: vmrglh v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: vmrglh v3, v3, v4 ; CHECK-P9-NEXT: vmrglh v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: vmrglw v2, v2, v0 ; CHECK-P9-NEXT: vmrglw v2, v2, v0
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: xxswapd v5, vs0 ; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglh v4, v4, v5 ; CHECK-P9-NEXT: vmrglh v4, v4, v5
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld vs0, v3, v2 ; CHECK-P9-NEXT: xxmrgld vs0, v3, v2
; CHECK-P9-NEXT: stxv vs0, 16(r3) ; CHECK-P9-NEXT: stxv vs0, 16(r3)
; CHECK-P9-NEXT: stxv vs4, 0(r3) ; CHECK-P9-NEXT: stxv vs4, 0(r3)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs4, 48(r4) ; CHECK-BE-NEXT: lxv vs4, 48(r4)
; CHECK-BE-NEXT: xscvdpsxws f5, f4 ; CHECK-BE-NEXT: xscvdpsxws f5, f4
; CHECK-BE-NEXT: xxswapd vs4, vs4 ; CHECK-BE-NEXT: xxswapd vs4, vs4
; CHECK-BE-NEXT: lxv vs3, 32(r4) ; CHECK-BE-NEXT: lxv vs3, 32(r4)
; CHECK-BE-NEXT: xscvdpsxws f6, f3 ; CHECK-BE-NEXT: xscvdpsxws f6, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3 ; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: mfvsrwz r5, f5 ; CHECK-BE-NEXT: mffprwz r5, f5
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs2, 16(r4) ; CHECK-BE-NEXT: lxv vs2, 16(r4)
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: xscvdpsxws f7, f2 ; CHECK-BE-NEXT: xscvdpsxws f7, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v2, r5 ; CHECK-BE-NEXT: mtvsrd v2, r5
; CHECK-BE-NEXT: mfvsrwz r5, f4 ; CHECK-BE-NEXT: mffprwz r5, f4
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs1, 0(r4) ; CHECK-BE-NEXT: lxv vs1, 0(r4)
; CHECK-BE-NEXT: xscvdpsxws f4, f1 ; CHECK-BE-NEXT: xscvdpsxws f4, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: mfvsrwz r5, f6 ; CHECK-BE-NEXT: mffprwz r5, f6
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: lxv vs0, 112(r4) ; CHECK-BE-NEXT: lxv vs0, 112(r4)
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: mtvsrd v3, r5 ; CHECK-BE-NEXT: mtvsrd v3, r5
; CHECK-BE-NEXT: mfvsrwz r5, f3 ; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f0 ; CHECK-BE-NEXT: xscvdpsxws f3, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mfvsrwz r5, f7 ; CHECK-BE-NEXT: mffprwz r5, f7
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mtvsrd v4, r5 ; CHECK-BE-NEXT: mtvsrd v4, r5
; CHECK-BE-NEXT: mfvsrwz r5, f4 ; CHECK-BE-NEXT: mffprwz r5, f4
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v5, r5 ; CHECK-BE-NEXT: mtvsrd v5, r5
; CHECK-BE-NEXT: mfvsrwz r5, f3 ; CHECK-BE-NEXT: mffprwz r5, f3
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v0, r5 ; CHECK-BE-NEXT: mtvsrd v0, r5
; CHECK-BE-NEXT: mfvsrwz r5, f2 ; CHECK-BE-NEXT: mffprwz r5, f2
; CHECK-BE-NEXT: lxv vs2, 96(r4) ; CHECK-BE-NEXT: lxv vs2, 96(r4)
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v1, r5 ; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: mfvsrwz r5, f1 ; CHECK-BE-NEXT: mffprwz r5, f1
; CHECK-BE-NEXT: lxv vs1, 80(r4) ; CHECK-BE-NEXT: lxv vs1, 80(r4)
; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: vmrghh v4, v4, v1 ; CHECK-BE-NEXT: vmrghh v4, v4, v1
; CHECK-BE-NEXT: mtvsrd v1, r5 ; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: vmrghh v5, v5, v1 ; CHECK-BE-NEXT: vmrghh v5, v5, v1
; CHECK-BE-NEXT: mfvsrwz r5, f0 ; CHECK-BE-NEXT: mffprwz r5, f0
; CHECK-BE-NEXT: lxv vs0, 64(r4) ; CHECK-BE-NEXT: lxv vs0, 64(r4)
; CHECK-BE-NEXT: mfvsrwz r4, f3 ; CHECK-BE-NEXT: mffprwz r4, f3
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: vmrghw v3, v5, v4 ; CHECK-BE-NEXT: vmrghw v3, v5, v4
; CHECK-BE-NEXT: xxmrghd vs3, v3, v2 ; CHECK-BE-NEXT: xxmrghd vs3, v3, v2
; CHECK-BE-NEXT: mtvsrd v2, r4 ; CHECK-BE-NEXT: mtvsrd v2, r4
; CHECK-BE-NEXT: mfvsrwz r4, f2 ; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: vmrghh v2, v2, v3 ; CHECK-BE-NEXT: vmrghh v2, v2, v3
; CHECK-BE-NEXT: mfvsrwz r4, f2 ; CHECK-BE-NEXT: mffprwz r4, f2
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v3, r4 ; CHECK-BE-NEXT: mtvsrd v3, r4
; CHECK-BE-NEXT: mfvsrwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: vmrghh v3, v3, v4 ; CHECK-BE-NEXT: vmrghh v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r4, f1 ; CHECK-BE-NEXT: mffprwz r4, f1
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v4, r4 ; CHECK-BE-NEXT: mtvsrd v4, r4
; CHECK-BE-NEXT: mfvsrwz r4, f0 ; CHECK-BE-NEXT: mffprwz r4, f0
; CHECK-BE-NEXT: sldi r5, r5, 48 ; CHECK-BE-NEXT: sldi r5, r5, 48
; CHECK-BE-NEXT: mtvsrd v1, r5 ; CHECK-BE-NEXT: mtvsrd v1, r5
; CHECK-BE-NEXT: vmrghh v0, v0, v1 ; CHECK-BE-NEXT: vmrghh v0, v0, v1
; CHECK-BE-NEXT: vmrghw v2, v2, v0 ; CHECK-BE-NEXT: vmrghw v2, v2, v0
; CHECK-BE-NEXT: stxv vs3, 0(r3) ; CHECK-BE-NEXT: stxv vs3, 0(r3)
; CHECK-BE-NEXT: sldi r4, r4, 48 ; CHECK-BE-NEXT: sldi r4, r4, 48
; CHECK-BE-NEXT: mtvsrd v5, r4 ; CHECK-BE-NEXT: mtvsrd v5, r4
; CHECK-BE-NEXT: vmrghh v4, v4, v5 ; CHECK-BE-NEXT: vmrghh v4, v4, v5
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llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i32_elts.ll

Show All 9 Lines
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define i64 @test2elt(<2 x double> %a) local_unnamed_addr #0 { define i64 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xscvdpuxws f1, v2 ; CHECK-P8-NEXT: xscvdpuxws f1, v2
; CHECK-P8-NEXT: xscvdpuxws f0, f0 ; CHECK-P8-NEXT: xscvdpuxws f0, f0
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglw v2, v2, v3 ; CHECK-P8-NEXT: vmrglw v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpuxws f0, v2 ; CHECK-P9-NEXT: xscvdpuxws f0, v2
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: mtvsrws v3, r3 ; CHECK-P9-NEXT: mtvsrws v3, r3
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} }
define i64 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 { define i64 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xscvdpsxws f1, v2 ; CHECK-P8-NEXT: xscvdpsxws f1, v2
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglw v2, v2, v3 ; CHECK-P8-NEXT: vmrglw v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpsxws f0, v2 ; CHECK-P9-NEXT: xscvdpsxws f0, v2
; CHECK-P9-NEXT: mffprwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: mtvsrws v3, r3 ; CHECK-P9-NEXT: mtvsrws v3, r3
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llvm/test/CodeGen/PowerPC/vec_conv_fp64_to_i8_elts.ll

Show All 9 Lines
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define i16 @test2elt(<2 x double> %a) local_unnamed_addr #0 { define i16 @test2elt(<2 x double> %a) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xscvdpsxws f1, v2 ; CHECK-P8-NEXT: xscvdpsxws f1, v2
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglb v2, v2, v3 ; CHECK-P8-NEXT: vmrglb v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 48 ; CHECK-P8-NEXT: clrldi r3, r3, 48
; CHECK-P8-NEXT: sth r3, -2(r1) ; CHECK-P8-NEXT: sth r3, -2(r1)
; CHECK-P8-NEXT: lhz r3, -2(r1) ; CHECK-P8-NEXT: lhz r3, -2(r1)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpsxws f0, v2 ; CHECK-P9-NEXT: xscvdpsxws f0, v2
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: addi r3, r1, -2 ; CHECK-P9-NEXT: addi r3, r1, -2
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglb v2, v3, v2 ; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8 ; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8
; CHECK-P9-NEXT: stxsihx v2, 0, r3 ; CHECK-P9-NEXT: stxsihx v2, 0, r3
; CHECK-P9-NEXT: lhz r3, -2(r1) ; CHECK-P9-NEXT: lhz r3, -2(r1)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xscvdpsxws f0, v2 ; CHECK-BE-NEXT: xscvdpsxws f0, v2
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: addi r3, r1, -2 ; CHECK-BE-NEXT: addi r3, r1, -2
; CHECK-BE-NEXT: vmrghb v2, v3, v2 ; CHECK-BE-NEXT: vmrghb v2, v3, v2
; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10 ; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10
; CHECK-BE-NEXT: stxsihx v2, 0, r3 ; CHECK-BE-NEXT: stxsihx v2, 0, r3
; CHECK-BE-NEXT: lhz r3, -2(r1) ; CHECK-BE-NEXT: lhz r3, -2(r1)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
Show All 10 Lines
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs1, r3, r4
; CHECK-P8-NEXT: xscvdpsxws f2, f0 ; CHECK-P8-NEXT: xscvdpsxws f2, f0
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xscvdpsxws f3, f1 ; CHECK-P8-NEXT: xscvdpsxws f3, f1
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r3, f2 ; CHECK-P8-NEXT: mffprwz r3, f2
; CHECK-P8-NEXT: mfvsrwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: mtvsrd f2, r3 ; CHECK-P8-NEXT: mtfprd f2, r3
; CHECK-P8-NEXT: mtvsrd f3, r4 ; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xxswapd v2, vs2 ; CHECK-P8-NEXT: xxswapd v2, vs2
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xxswapd v4, vs3 ; CHECK-P8-NEXT: xxswapd v4, vs3
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xxswapd v5, vs1 ; CHECK-P8-NEXT: xxswapd v5, vs1
; CHECK-P8-NEXT: vmrglb v2, v3, v2 ; CHECK-P8-NEXT: vmrglb v2, v3, v2
; CHECK-P8-NEXT: vmrglb v3, v5, v4 ; CHECK-P8-NEXT: vmrglb v3, v5, v4
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f2, f1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs0, 16(r3) ; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: xxswapd v2, vs2 ; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v2, v2, v3 ; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: vmrglb v3, v3, v4 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt: ; CHECK-BE-LABEL: test4elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghb v2, v2, v3 ; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: vmrghb v3, v3, v4 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
Show All 18 Lines
; CHECK-P8-NEXT: xscvdpsxws f5, f1 ; CHECK-P8-NEXT: xscvdpsxws f5, f1
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xscvdpsxws f6, f2 ; CHECK-P8-NEXT: xscvdpsxws f6, f2
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xscvdpsxws f7, f3 ; CHECK-P8-NEXT: xscvdpsxws f7, f3
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r3, f4 ; CHECK-P8-NEXT: mffprwz r3, f4
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: mfvsrwz r4, f5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: mtvsrd f4, r3 ; CHECK-P8-NEXT: mtfprd f4, r3
; CHECK-P8-NEXT: mfvsrwz r3, f6 ; CHECK-P8-NEXT: mffprwz r3, f6
; CHECK-P8-NEXT: mtvsrd f5, r4 ; CHECK-P8-NEXT: mtfprd f5, r4
; CHECK-P8-NEXT: xxswapd v2, vs4 ; CHECK-P8-NEXT: xxswapd v2, vs4
; CHECK-P8-NEXT: mfvsrwz r4, f7 ; CHECK-P8-NEXT: mffprwz r4, f7
; CHECK-P8-NEXT: mtvsrd f6, r3 ; CHECK-P8-NEXT: mtfprd f6, r3
; CHECK-P8-NEXT: xxswapd v3, vs5 ; CHECK-P8-NEXT: xxswapd v3, vs5
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mtvsrd f7, r4 ; CHECK-P8-NEXT: mtfprd f7, r4
; CHECK-P8-NEXT: xxswapd v4, vs6 ; CHECK-P8-NEXT: xxswapd v4, vs6
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v1, vs7 ; CHECK-P8-NEXT: xxswapd v1, vs7
; CHECK-P8-NEXT: mfvsrwz r3, f2 ; CHECK-P8-NEXT: mffprwz r3, f2
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v5, vs0 ; CHECK-P8-NEXT: xxswapd v5, vs0
; CHECK-P8-NEXT: mfvsrwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: mtvsrd f2, r3 ; CHECK-P8-NEXT: mtfprd f2, r3
; CHECK-P8-NEXT: xxswapd v0, vs1 ; CHECK-P8-NEXT: xxswapd v0, vs1
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xxswapd v6, vs2 ; CHECK-P8-NEXT: xxswapd v6, vs2
; CHECK-P8-NEXT: vmrglb v2, v5, v2 ; CHECK-P8-NEXT: vmrglb v2, v5, v2
; CHECK-P8-NEXT: xxswapd v5, vs0 ; CHECK-P8-NEXT: xxswapd v5, vs0
; CHECK-P8-NEXT: vmrglb v3, v0, v3 ; CHECK-P8-NEXT: vmrglb v3, v0, v3
; CHECK-P8-NEXT: vmrglb v4, v6, v4 ; CHECK-P8-NEXT: vmrglb v4, v6, v4
; CHECK-P8-NEXT: vmrglb v5, v5, v1 ; CHECK-P8-NEXT: vmrglb v5, v5, v1
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: vmrglh v3, v5, v4 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f3 ; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3 ; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs2, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f4 ; CHECK-P9-NEXT: mffprwz r3, f4
; CHECK-P9-NEXT: mtvsrd f4, r3 ; CHECK-P9-NEXT: mtfprd f4, r3
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: xxswapd v2, vs4 ; CHECK-P9-NEXT: xxswapd v2, vs4
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v3, vs3 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2 ; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: vmrglb v2, v2, v3 ; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs3 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: vmrglb v3, v3, v4 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v3, v4 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0 ; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglb v4, v4, v5 ; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt: ; CHECK-BE-LABEL: test8elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f3 ; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3 ; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghb v2, v2, v3 ; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
Show All 30 Lines
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: lxvd2x vs11, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs11, r3, r4
; CHECK-P8-NEXT: xscvdpsxws f12, f5 ; CHECK-P8-NEXT: xscvdpsxws f12, f5
; CHECK-P8-NEXT: xxswapd vs5, vs5 ; CHECK-P8-NEXT: xxswapd vs5, vs5
; CHECK-P8-NEXT: xscvdpsxws f13, f7 ; CHECK-P8-NEXT: xscvdpsxws f13, f7
; CHECK-P8-NEXT: xxswapd vs7, vs7 ; CHECK-P8-NEXT: xxswapd vs7, vs7
; CHECK-P8-NEXT: xscvdpsxws v2, f9 ; CHECK-P8-NEXT: xscvdpsxws v2, f9
; CHECK-P8-NEXT: xxswapd vs9, vs9 ; CHECK-P8-NEXT: xxswapd vs9, vs9
; CHECK-P8-NEXT: mfvsrwz r3, f4 ; CHECK-P8-NEXT: mffprwz r3, f4
; CHECK-P8-NEXT: xscvdpsxws v3, f11 ; CHECK-P8-NEXT: xscvdpsxws v3, f11
; CHECK-P8-NEXT: xxswapd vs11, vs11 ; CHECK-P8-NEXT: xxswapd vs11, vs11
; CHECK-P8-NEXT: mfvsrwz r4, f6 ; CHECK-P8-NEXT: mffprwz r4, f6
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mtvsrd f4, r3 ; CHECK-P8-NEXT: mtfprd f4, r3
; CHECK-P8-NEXT: mfvsrwz r3, f8 ; CHECK-P8-NEXT: mffprwz r3, f8
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xxswapd v4, vs4 ; CHECK-P8-NEXT: xxswapd v4, vs4
; CHECK-P8-NEXT: mtvsrd f6, r4 ; CHECK-P8-NEXT: mtfprd f6, r4
; CHECK-P8-NEXT: mfvsrwz r4, f10 ; CHECK-P8-NEXT: mffprwz r4, f10
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xxswapd v5, vs6 ; CHECK-P8-NEXT: xxswapd v5, vs6
; CHECK-P8-NEXT: mtvsrd f8, r3 ; CHECK-P8-NEXT: mtfprd f8, r3
; CHECK-P8-NEXT: mfvsrwz r3, f12 ; CHECK-P8-NEXT: mffprwz r3, f12
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xxswapd v0, vs8 ; CHECK-P8-NEXT: xxswapd v0, vs8
; CHECK-P8-NEXT: mtvsrd f10, r4 ; CHECK-P8-NEXT: mtfprd f10, r4
; CHECK-P8-NEXT: mfvsrwz r4, f13 ; CHECK-P8-NEXT: mffprwz r4, f13
; CHECK-P8-NEXT: xscvdpsxws f5, f5 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: xxswapd v1, vs10 ; CHECK-P8-NEXT: xxswapd v1, vs10
; CHECK-P8-NEXT: mtvsrd f12, r3 ; CHECK-P8-NEXT: mtfprd f12, r3
; CHECK-P8-NEXT: mfvsrwz r3, v2 ; CHECK-P8-NEXT: mfvsrwz r3, v2
; CHECK-P8-NEXT: xscvdpsxws f7, f7 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
; CHECK-P8-NEXT: xxswapd v6, vs12 ; CHECK-P8-NEXT: xxswapd v6, vs12
; CHECK-P8-NEXT: mtvsrd f13, r4 ; CHECK-P8-NEXT: mtfprd f13, r4
; CHECK-P8-NEXT: mfvsrwz r4, v3 ; CHECK-P8-NEXT: mfvsrwz r4, v3
; CHECK-P8-NEXT: mtvsrd v2, r3 ; CHECK-P8-NEXT: mtvsrd v2, r3
; CHECK-P8-NEXT: xxswapd v7, vs13 ; CHECK-P8-NEXT: xxswapd v7, vs13
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xscvdpsxws f9, f9 ; CHECK-P8-NEXT: xscvdpsxws f9, f9
; CHECK-P8-NEXT: xxswapd v2, v2 ; CHECK-P8-NEXT: xxswapd v2, v2
; CHECK-P8-NEXT: xscvdpsxws f11, f11 ; CHECK-P8-NEXT: xscvdpsxws f11, f11
; CHECK-P8-NEXT: mtvsrd v3, r4 ; CHECK-P8-NEXT: mtvsrd v3, r4
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v3, v3 ; CHECK-P8-NEXT: xxswapd v3, v3
; CHECK-P8-NEXT: mfvsrwz r3, f2 ; CHECK-P8-NEXT: mffprwz r3, f2
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v8, vs0 ; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: mfvsrwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: mtvsrd f2, r3 ; CHECK-P8-NEXT: mtfprd f2, r3
; CHECK-P8-NEXT: xxswapd v9, vs1 ; CHECK-P8-NEXT: xxswapd v9, vs1
; CHECK-P8-NEXT: mfvsrwz r3, f5 ; CHECK-P8-NEXT: mffprwz r3, f5
; CHECK-P8-NEXT: mtvsrd f3, r4 ; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: xxswapd v10, vs2 ; CHECK-P8-NEXT: xxswapd v10, vs2
; CHECK-P8-NEXT: mfvsrwz r4, f7 ; CHECK-P8-NEXT: mffprwz r4, f7
; CHECK-P8-NEXT: mtvsrd f5, r3 ; CHECK-P8-NEXT: mtfprd f5, r3
; CHECK-P8-NEXT: mfvsrwz r3, f9 ; CHECK-P8-NEXT: mffprwz r3, f9
; CHECK-P8-NEXT: mtvsrd f7, r4 ; CHECK-P8-NEXT: mtfprd f7, r4
; CHECK-P8-NEXT: mfvsrwz r4, f11 ; CHECK-P8-NEXT: mffprwz r4, f11
; CHECK-P8-NEXT: vmrglb v4, v8, v4 ; CHECK-P8-NEXT: vmrglb v4, v8, v4
; CHECK-P8-NEXT: xxswapd v8, vs3 ; CHECK-P8-NEXT: xxswapd v8, vs3
; CHECK-P8-NEXT: vmrglb v5, v9, v5 ; CHECK-P8-NEXT: vmrglb v5, v9, v5
; CHECK-P8-NEXT: xxswapd v9, vs5 ; CHECK-P8-NEXT: xxswapd v9, vs5
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: vmrglb v0, v10, v0 ; CHECK-P8-NEXT: vmrglb v0, v10, v0
; CHECK-P8-NEXT: xxswapd v10, vs7 ; CHECK-P8-NEXT: xxswapd v10, vs7
; CHECK-P8-NEXT: vmrglb v1, v8, v1 ; CHECK-P8-NEXT: vmrglb v1, v8, v1
; CHECK-P8-NEXT: xxswapd v8, vs0 ; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: vmrglb v6, v9, v6 ; CHECK-P8-NEXT: vmrglb v6, v9, v6
; CHECK-P8-NEXT: xxswapd v9, vs1 ; CHECK-P8-NEXT: xxswapd v9, vs1
; CHECK-P8-NEXT: vmrglb v7, v10, v7 ; CHECK-P8-NEXT: vmrglb v7, v10, v7
; CHECK-P8-NEXT: vmrglb v2, v8, v2 ; CHECK-P8-NEXT: vmrglb v2, v8, v2
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; CHECK-P9-NEXT: xscvdpsxws f7, f7 ; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: lxv vs0, 112(r3) ; CHECK-P9-NEXT: lxv vs0, 112(r3)
; CHECK-P9-NEXT: lxv vs1, 96(r3) ; CHECK-P9-NEXT: lxv vs1, 96(r3)
; CHECK-P9-NEXT: lxv vs2, 80(r3) ; CHECK-P9-NEXT: lxv vs2, 80(r3)
; CHECK-P9-NEXT: lxv vs3, 64(r3) ; CHECK-P9-NEXT: lxv vs3, 64(r3)
; CHECK-P9-NEXT: lxv vs4, 48(r3) ; CHECK-P9-NEXT: lxv vs4, 48(r3)
; CHECK-P9-NEXT: lxv vs5, 32(r3) ; CHECK-P9-NEXT: lxv vs5, 32(r3)
; CHECK-P9-NEXT: lxv vs6, 16(r3) ; CHECK-P9-NEXT: lxv vs6, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f8 ; CHECK-P9-NEXT: mffprwz r3, f8
; CHECK-P9-NEXT: mtvsrd f8, r3 ; CHECK-P9-NEXT: mtfprd f8, r3
; CHECK-P9-NEXT: mfvsrwz r3, f7 ; CHECK-P9-NEXT: mffprwz r3, f7
; CHECK-P9-NEXT: xxswapd v2, vs8 ; CHECK-P9-NEXT: xxswapd v2, vs8
; CHECK-P9-NEXT: mtvsrd f7, r3 ; CHECK-P9-NEXT: mtfprd f7, r3
; CHECK-P9-NEXT: xxswapd v3, vs7 ; CHECK-P9-NEXT: xxswapd v3, vs7
; CHECK-P9-NEXT: xscvdpsxws f7, f6 ; CHECK-P9-NEXT: xscvdpsxws f7, f6
; CHECK-P9-NEXT: xxswapd vs6, vs6 ; CHECK-P9-NEXT: xxswapd vs6, vs6
; CHECK-P9-NEXT: xscvdpsxws f6, f6 ; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: mfvsrwz r3, f7 ; CHECK-P9-NEXT: mffprwz r3, f7
; CHECK-P9-NEXT: mtvsrd f7, r3 ; CHECK-P9-NEXT: mtfprd f7, r3
; CHECK-P9-NEXT: mfvsrwz r3, f6 ; CHECK-P9-NEXT: mffprwz r3, f6
; CHECK-P9-NEXT: mtvsrd f6, r3 ; CHECK-P9-NEXT: mtfprd f6, r3
; CHECK-P9-NEXT: xxswapd v4, vs6 ; CHECK-P9-NEXT: xxswapd v4, vs6
; CHECK-P9-NEXT: xscvdpsxws f6, f5 ; CHECK-P9-NEXT: xscvdpsxws f6, f5
; CHECK-P9-NEXT: xxswapd vs5, vs5 ; CHECK-P9-NEXT: xxswapd vs5, vs5
; CHECK-P9-NEXT: xscvdpsxws f5, f5 ; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: mfvsrwz r3, f6 ; CHECK-P9-NEXT: mffprwz r3, f6
; CHECK-P9-NEXT: mtvsrd f6, r3 ; CHECK-P9-NEXT: mtfprd f6, r3
; CHECK-P9-NEXT: mfvsrwz r3, f5 ; CHECK-P9-NEXT: mffprwz r3, f5
; CHECK-P9-NEXT: vmrglb v2, v2, v3 ; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs7 ; CHECK-P9-NEXT: xxswapd v3, vs7
; CHECK-P9-NEXT: vmrglb v3, v3, v4 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs6 ; CHECK-P9-NEXT: xxswapd v3, vs6
; CHECK-P9-NEXT: mtvsrd f5, r3 ; CHECK-P9-NEXT: mtfprd f5, r3
; CHECK-P9-NEXT: xxswapd v4, vs5 ; CHECK-P9-NEXT: xxswapd v4, vs5
; CHECK-P9-NEXT: xscvdpsxws f5, f4 ; CHECK-P9-NEXT: xscvdpsxws f5, f4
; CHECK-P9-NEXT: xxswapd vs4, vs4 ; CHECK-P9-NEXT: xxswapd vs4, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: mfvsrwz r3, f5 ; CHECK-P9-NEXT: mffprwz r3, f5
; CHECK-P9-NEXT: mtvsrd f5, r3 ; CHECK-P9-NEXT: mtfprd f5, r3
; CHECK-P9-NEXT: mfvsrwz r3, f4 ; CHECK-P9-NEXT: mffprwz r3, f4
; CHECK-P9-NEXT: mtvsrd f4, r3 ; CHECK-P9-NEXT: mtfprd f4, r3
; CHECK-P9-NEXT: xxswapd v5, vs4 ; CHECK-P9-NEXT: xxswapd v5, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f3 ; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3 ; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: vmrglb v3, v3, v4 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs5 ; CHECK-P9-NEXT: xxswapd v4, vs5
; CHECK-P9-NEXT: vmrglb v4, v4, v5 ; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: mfvsrwz r3, f4 ; CHECK-P9-NEXT: mffprwz r3, f4
; CHECK-P9-NEXT: mtvsrd f4, r3 ; CHECK-P9-NEXT: mtfprd f4, r3
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v4, vs3 ; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2 ; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v5, vs2 ; CHECK-P9-NEXT: xxswapd v5, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs4 ; CHECK-P9-NEXT: xxswapd v3, vs4
; CHECK-P9-NEXT: vmrglb v3, v3, v4 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs3 ; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: vmrglb v4, v4, v5 ; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs1 ; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v4, v4, v5 ; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: xxswapd v5, vs1 ; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xxswapd v0, vs0 ; CHECK-P9-NEXT: xxswapd v0, vs0
; CHECK-P9-NEXT: vmrglb v5, v5, v0 ; CHECK-P9-NEXT: vmrglb v5, v5, v0
; CHECK-P9-NEXT: vmrglh v4, v5, v4 ; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt: ; CHECK-BE-LABEL: test16elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs7, 112(r3) ; CHECK-BE-NEXT: lxv vs7, 112(r3)
; CHECK-BE-NEXT: xscvdpsxws f8, f7 ; CHECK-BE-NEXT: xscvdpsxws f8, f7
; CHECK-BE-NEXT: xxswapd vs7, vs7 ; CHECK-BE-NEXT: xxswapd vs7, vs7
; CHECK-BE-NEXT: xscvdpsxws f7, f7 ; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: lxv vs6, 96(r3) ; CHECK-BE-NEXT: lxv vs6, 96(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs4, 64(r3) ; CHECK-BE-NEXT: lxv vs4, 64(r3)
; CHECK-BE-NEXT: lxv vs5, 80(r3) ; CHECK-BE-NEXT: lxv vs5, 80(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f8 ; CHECK-BE-NEXT: mffprwz r3, f8
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f7 ; CHECK-BE-NEXT: mffprwz r3, f7
; CHECK-BE-NEXT: xscvdpsxws f7, f6 ; CHECK-BE-NEXT: xscvdpsxws f7, f6
; CHECK-BE-NEXT: xxswapd vs6, vs6 ; CHECK-BE-NEXT: xxswapd vs6, vs6
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f6, f6 ; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghb v2, v2, v3 ; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: mfvsrwz r3, f7 ; CHECK-BE-NEXT: mffprwz r3, f7
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f6 ; CHECK-BE-NEXT: mffprwz r3, f6
; CHECK-BE-NEXT: xscvdpsxws f6, f5 ; CHECK-BE-NEXT: xscvdpsxws f6, f5
; CHECK-BE-NEXT: xxswapd vs5, vs5 ; CHECK-BE-NEXT: xxswapd vs5, vs5
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f5, f5 ; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f6 ; CHECK-BE-NEXT: mffprwz r3, f6
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f5 ; CHECK-BE-NEXT: mffprwz r3, f5
; CHECK-BE-NEXT: xscvdpsxws f5, f4 ; CHECK-BE-NEXT: xscvdpsxws f5, f4
; CHECK-BE-NEXT: xxswapd vs4, vs4 ; CHECK-BE-NEXT: xxswapd vs4, vs4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f5 ; CHECK-BE-NEXT: mffprwz r3, f5
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: xscvdpsxws f4, f3 ; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3 ; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: mfvsrwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v0, r3 ; CHECK-BE-NEXT: mtvsrd v0, r3
; CHECK-BE-NEXT: vmrghb v5, v5, v0 ; CHECK-BE-NEXT: vmrghb v5, v5, v0
; CHECK-BE-NEXT: vmrghh v4, v5, v4 ; CHECK-BE-NEXT: vmrghh v4, v5, v4
; CHECK-BE-NEXT: vmrghw v3, v4, v3 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd v2, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x double>, <16 x double>* %0, align 128 %a = load <16 x double>, <16 x double>* %0, align 128
%1 = fptoui <16 x double> %a to <16 x i8> %1 = fptoui <16 x double> %a to <16 x i8>
ret <16 x i8> %1 ret <16 x i8> %1
} }
define i16 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 { define i16 @test2elt_signed(<2 x double> %a) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: xscvdpsxws f1, v2 ; CHECK-P8-NEXT: xscvdpsxws f1, v2
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mfvsrwz r3, f1 ; CHECK-P8-NEXT: mffprwz r3, f1
; CHECK-P8-NEXT: mfvsrwz r4, f0 ; CHECK-P8-NEXT: mffprwz r4, f0
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxswapd v3, vs1 ; CHECK-P8-NEXT: xxswapd v3, vs1
; CHECK-P8-NEXT: vmrglb v2, v2, v3 ; CHECK-P8-NEXT: vmrglb v2, v2, v3
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r3, r3, 48 ; CHECK-P8-NEXT: clrldi r3, r3, 48
; CHECK-P8-NEXT: sth r3, -2(r1) ; CHECK-P8-NEXT: sth r3, -2(r1)
; CHECK-P8-NEXT: lhz r3, -2(r1) ; CHECK-P8-NEXT: lhz r3, -2(r1)
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xscvdpsxws f0, v2 ; CHECK-P9-NEXT: xscvdpsxws f0, v2
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v3, vs0 ; CHECK-P9-NEXT: xxswapd v3, vs0
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: addi r3, r1, -2 ; CHECK-P9-NEXT: addi r3, r1, -2
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglb v2, v3, v2 ; CHECK-P9-NEXT: vmrglb v2, v3, v2
; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8 ; CHECK-P9-NEXT: vsldoi v2, v2, v2, 8
; CHECK-P9-NEXT: stxsihx v2, 0, r3 ; CHECK-P9-NEXT: stxsihx v2, 0, r3
; CHECK-P9-NEXT: lhz r3, -2(r1) ; CHECK-P9-NEXT: lhz r3, -2(r1)
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: xscvdpsxws f0, v2 ; CHECK-BE-NEXT: xscvdpsxws f0, v2
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: xxswapd vs0, v2 ; CHECK-BE-NEXT: xxswapd vs0, v2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: addi r3, r1, -2 ; CHECK-BE-NEXT: addi r3, r1, -2
; CHECK-BE-NEXT: vmrghb v2, v3, v2 ; CHECK-BE-NEXT: vmrghb v2, v3, v2
; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10 ; CHECK-BE-NEXT: vsldoi v2, v2, v2, 10
; CHECK-BE-NEXT: stxsihx v2, 0, r3 ; CHECK-BE-NEXT: stxsihx v2, 0, r3
; CHECK-BE-NEXT: lhz r3, -2(r1) ; CHECK-BE-NEXT: lhz r3, -2(r1)
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
Show All 10 Lines
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: lxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs1, r3, r4
; CHECK-P8-NEXT: xscvdpsxws f2, f0 ; CHECK-P8-NEXT: xscvdpsxws f2, f0
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xscvdpsxws f3, f1 ; CHECK-P8-NEXT: xscvdpsxws f3, f1
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r3, f2 ; CHECK-P8-NEXT: mffprwz r3, f2
; CHECK-P8-NEXT: mfvsrwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: mtvsrd f2, r3 ; CHECK-P8-NEXT: mtfprd f2, r3
; CHECK-P8-NEXT: mtvsrd f3, r4 ; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xxswapd v2, vs2 ; CHECK-P8-NEXT: xxswapd v2, vs2
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: xxswapd v4, vs3 ; CHECK-P8-NEXT: xxswapd v4, vs3
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: xxswapd v5, vs1 ; CHECK-P8-NEXT: xxswapd v5, vs1
; CHECK-P8-NEXT: vmrglb v2, v3, v2 ; CHECK-P8-NEXT: vmrglb v2, v3, v2
; CHECK-P8-NEXT: vmrglb v3, v5, v4 ; CHECK-P8-NEXT: vmrglb v3, v5, v4
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs1, 0(r3) ; CHECK-P9-NEXT: lxv vs1, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f2, f1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: lxv vs0, 16(r3) ; CHECK-P9-NEXT: lxv vs0, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: xxswapd v2, vs2 ; CHECK-P9-NEXT: xxswapd v2, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v2, v2, v3 ; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs1 ; CHECK-P9-NEXT: xxswapd v3, vs1
; CHECK-P9-NEXT: xxswapd v4, vs0 ; CHECK-P9-NEXT: xxswapd v4, vs0
; CHECK-P9-NEXT: vmrglb v3, v3, v4 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextuwrx r3, r3, v2 ; CHECK-P9-NEXT: vextuwrx r3, r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghb v2, v2, v3 ; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: vmrghb v3, v3, v4 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: vextuwlx r3, r3, v2 ; CHECK-BE-NEXT: vextuwlx r3, r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
Show All 18 Lines
; CHECK-P8-NEXT: xscvdpsxws f5, f1 ; CHECK-P8-NEXT: xscvdpsxws f5, f1
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: xscvdpsxws f6, f2 ; CHECK-P8-NEXT: xscvdpsxws f6, f2
; CHECK-P8-NEXT: xxswapd vs2, vs2 ; CHECK-P8-NEXT: xxswapd vs2, vs2
; CHECK-P8-NEXT: xscvdpsxws f7, f3 ; CHECK-P8-NEXT: xscvdpsxws f7, f3
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: mfvsrwz r3, f4 ; CHECK-P8-NEXT: mffprwz r3, f4
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: mfvsrwz r4, f5 ; CHECK-P8-NEXT: mffprwz r4, f5
; CHECK-P8-NEXT: mtvsrd f4, r3 ; CHECK-P8-NEXT: mtfprd f4, r3
; CHECK-P8-NEXT: mfvsrwz r3, f6 ; CHECK-P8-NEXT: mffprwz r3, f6
; CHECK-P8-NEXT: mtvsrd f5, r4 ; CHECK-P8-NEXT: mtfprd f5, r4
; CHECK-P8-NEXT: xxswapd v2, vs4 ; CHECK-P8-NEXT: xxswapd v2, vs4
; CHECK-P8-NEXT: mfvsrwz r4, f7 ; CHECK-P8-NEXT: mffprwz r4, f7
; CHECK-P8-NEXT: mtvsrd f6, r3 ; CHECK-P8-NEXT: mtfprd f6, r3
; CHECK-P8-NEXT: xxswapd v3, vs5 ; CHECK-P8-NEXT: xxswapd v3, vs5
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: mtvsrd f7, r4 ; CHECK-P8-NEXT: mtfprd f7, r4
; CHECK-P8-NEXT: xxswapd v4, vs6 ; CHECK-P8-NEXT: xxswapd v4, vs6
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v1, vs7 ; CHECK-P8-NEXT: xxswapd v1, vs7
; CHECK-P8-NEXT: mfvsrwz r3, f2 ; CHECK-P8-NEXT: mffprwz r3, f2
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v5, vs0 ; CHECK-P8-NEXT: xxswapd v5, vs0
; CHECK-P8-NEXT: mfvsrwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: mtvsrd f2, r3 ; CHECK-P8-NEXT: mtfprd f2, r3
; CHECK-P8-NEXT: xxswapd v0, vs1 ; CHECK-P8-NEXT: xxswapd v0, vs1
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: xxswapd v6, vs2 ; CHECK-P8-NEXT: xxswapd v6, vs2
; CHECK-P8-NEXT: vmrglb v2, v5, v2 ; CHECK-P8-NEXT: vmrglb v2, v5, v2
; CHECK-P8-NEXT: xxswapd v5, vs0 ; CHECK-P8-NEXT: xxswapd v5, vs0
; CHECK-P8-NEXT: vmrglb v3, v0, v3 ; CHECK-P8-NEXT: vmrglb v3, v0, v3
; CHECK-P8-NEXT: vmrglb v4, v6, v4 ; CHECK-P8-NEXT: vmrglb v4, v6, v4
; CHECK-P8-NEXT: vmrglb v5, v5, v1 ; CHECK-P8-NEXT: vmrglb v5, v5, v1
; CHECK-P8-NEXT: vmrglh v2, v3, v2 ; CHECK-P8-NEXT: vmrglh v2, v3, v2
; CHECK-P8-NEXT: vmrglh v3, v5, v4 ; CHECK-P8-NEXT: vmrglh v3, v5, v4
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: lxv vs3, 0(r3) ; CHECK-P9-NEXT: lxv vs3, 0(r3)
; CHECK-P9-NEXT: xscvdpsxws f4, f3 ; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3 ; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: lxv vs0, 48(r3) ; CHECK-P9-NEXT: lxv vs0, 48(r3)
; CHECK-P9-NEXT: lxv vs1, 32(r3) ; CHECK-P9-NEXT: lxv vs1, 32(r3)
; CHECK-P9-NEXT: lxv vs2, 16(r3) ; CHECK-P9-NEXT: lxv vs2, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f4 ; CHECK-P9-NEXT: mffprwz r3, f4
; CHECK-P9-NEXT: mtvsrd f4, r3 ; CHECK-P9-NEXT: mtfprd f4, r3
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: xxswapd v2, vs4 ; CHECK-P9-NEXT: xxswapd v2, vs4
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v3, vs3 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2 ; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: vmrglb v2, v2, v3 ; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs3 ; CHECK-P9-NEXT: xxswapd v3, vs3
; CHECK-P9-NEXT: vmrglb v3, v3, v4 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs2 ; CHECK-P9-NEXT: xxswapd v3, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v3, v3, v4 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs1 ; CHECK-P9-NEXT: xxswapd v4, vs1
; CHECK-P9-NEXT: xxswapd v5, vs0 ; CHECK-P9-NEXT: xxswapd v5, vs0
; CHECK-P9-NEXT: vmrglb v4, v4, v5 ; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test8elt_signed: ; CHECK-BE-LABEL: test8elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: xscvdpsxws f4, f3 ; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3 ; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghb v2, v2, v3 ; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
Show All 30 Lines
; CHECK-P8-NEXT: xxswapd vs3, vs3 ; CHECK-P8-NEXT: xxswapd vs3, vs3
; CHECK-P8-NEXT: lxvd2x vs11, r3, r4 ; CHECK-P8-NEXT: lxvd2x vs11, r3, r4
; CHECK-P8-NEXT: xscvdpsxws f12, f5 ; CHECK-P8-NEXT: xscvdpsxws f12, f5
; CHECK-P8-NEXT: xxswapd vs5, vs5 ; CHECK-P8-NEXT: xxswapd vs5, vs5
; CHECK-P8-NEXT: xscvdpsxws f13, f7 ; CHECK-P8-NEXT: xscvdpsxws f13, f7
; CHECK-P8-NEXT: xxswapd vs7, vs7 ; CHECK-P8-NEXT: xxswapd vs7, vs7
; CHECK-P8-NEXT: xscvdpsxws v2, f9 ; CHECK-P8-NEXT: xscvdpsxws v2, f9
; CHECK-P8-NEXT: xxswapd vs9, vs9 ; CHECK-P8-NEXT: xxswapd vs9, vs9
; CHECK-P8-NEXT: mfvsrwz r3, f4 ; CHECK-P8-NEXT: mffprwz r3, f4
; CHECK-P8-NEXT: xscvdpsxws v3, f11 ; CHECK-P8-NEXT: xscvdpsxws v3, f11
; CHECK-P8-NEXT: xxswapd vs11, vs11 ; CHECK-P8-NEXT: xxswapd vs11, vs11
; CHECK-P8-NEXT: mfvsrwz r4, f6 ; CHECK-P8-NEXT: mffprwz r4, f6
; CHECK-P8-NEXT: xscvdpsxws f0, f0 ; CHECK-P8-NEXT: xscvdpsxws f0, f0
; CHECK-P8-NEXT: mtvsrd f4, r3 ; CHECK-P8-NEXT: mtfprd f4, r3
; CHECK-P8-NEXT: mfvsrwz r3, f8 ; CHECK-P8-NEXT: mffprwz r3, f8
; CHECK-P8-NEXT: xscvdpsxws f1, f1 ; CHECK-P8-NEXT: xscvdpsxws f1, f1
; CHECK-P8-NEXT: xxswapd v4, vs4 ; CHECK-P8-NEXT: xxswapd v4, vs4
; CHECK-P8-NEXT: mtvsrd f6, r4 ; CHECK-P8-NEXT: mtfprd f6, r4
; CHECK-P8-NEXT: mfvsrwz r4, f10 ; CHECK-P8-NEXT: mffprwz r4, f10
; CHECK-P8-NEXT: xscvdpsxws f2, f2 ; CHECK-P8-NEXT: xscvdpsxws f2, f2
; CHECK-P8-NEXT: xxswapd v5, vs6 ; CHECK-P8-NEXT: xxswapd v5, vs6
; CHECK-P8-NEXT: mtvsrd f8, r3 ; CHECK-P8-NEXT: mtfprd f8, r3
; CHECK-P8-NEXT: mfvsrwz r3, f12 ; CHECK-P8-NEXT: mffprwz r3, f12
; CHECK-P8-NEXT: xscvdpsxws f3, f3 ; CHECK-P8-NEXT: xscvdpsxws f3, f3
; CHECK-P8-NEXT: xxswapd v0, vs8 ; CHECK-P8-NEXT: xxswapd v0, vs8
; CHECK-P8-NEXT: mtvsrd f10, r4 ; CHECK-P8-NEXT: mtfprd f10, r4
; CHECK-P8-NEXT: mfvsrwz r4, f13 ; CHECK-P8-NEXT: mffprwz r4, f13
; CHECK-P8-NEXT: xscvdpsxws f5, f5 ; CHECK-P8-NEXT: xscvdpsxws f5, f5
; CHECK-P8-NEXT: xxswapd v1, vs10 ; CHECK-P8-NEXT: xxswapd v1, vs10
; CHECK-P8-NEXT: mtvsrd f12, r3 ; CHECK-P8-NEXT: mtfprd f12, r3
; CHECK-P8-NEXT: mfvsrwz r3, v2 ; CHECK-P8-NEXT: mfvsrwz r3, v2
; CHECK-P8-NEXT: xscvdpsxws f7, f7 ; CHECK-P8-NEXT: xscvdpsxws f7, f7
; CHECK-P8-NEXT: xxswapd v6, vs12 ; CHECK-P8-NEXT: xxswapd v6, vs12
; CHECK-P8-NEXT: mtvsrd f13, r4 ; CHECK-P8-NEXT: mtfprd f13, r4
; CHECK-P8-NEXT: mfvsrwz r4, v3 ; CHECK-P8-NEXT: mfvsrwz r4, v3
; CHECK-P8-NEXT: mtvsrd v2, r3 ; CHECK-P8-NEXT: mtvsrd v2, r3
; CHECK-P8-NEXT: xxswapd v7, vs13 ; CHECK-P8-NEXT: xxswapd v7, vs13
; CHECK-P8-NEXT: mfvsrwz r3, f0 ; CHECK-P8-NEXT: mffprwz r3, f0
; CHECK-P8-NEXT: xscvdpsxws f9, f9 ; CHECK-P8-NEXT: xscvdpsxws f9, f9
; CHECK-P8-NEXT: xxswapd v2, v2 ; CHECK-P8-NEXT: xxswapd v2, v2
; CHECK-P8-NEXT: xscvdpsxws f11, f11 ; CHECK-P8-NEXT: xscvdpsxws f11, f11
; CHECK-P8-NEXT: mtvsrd v3, r4 ; CHECK-P8-NEXT: mtvsrd v3, r4
; CHECK-P8-NEXT: mfvsrwz r4, f1 ; CHECK-P8-NEXT: mffprwz r4, f1
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v3, v3 ; CHECK-P8-NEXT: xxswapd v3, v3
; CHECK-P8-NEXT: mfvsrwz r3, f2 ; CHECK-P8-NEXT: mffprwz r3, f2
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxswapd v8, vs0 ; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: mfvsrwz r4, f3 ; CHECK-P8-NEXT: mffprwz r4, f3
; CHECK-P8-NEXT: mtvsrd f2, r3 ; CHECK-P8-NEXT: mtfprd f2, r3
; CHECK-P8-NEXT: xxswapd v9, vs1 ; CHECK-P8-NEXT: xxswapd v9, vs1
; CHECK-P8-NEXT: mfvsrwz r3, f5 ; CHECK-P8-NEXT: mffprwz r3, f5
; CHECK-P8-NEXT: mtvsrd f3, r4 ; CHECK-P8-NEXT: mtfprd f3, r4
; CHECK-P8-NEXT: xxswapd v10, vs2 ; CHECK-P8-NEXT: xxswapd v10, vs2
; CHECK-P8-NEXT: mfvsrwz r4, f7 ; CHECK-P8-NEXT: mffprwz r4, f7
; CHECK-P8-NEXT: mtvsrd f5, r3 ; CHECK-P8-NEXT: mtfprd f5, r3
; CHECK-P8-NEXT: mfvsrwz r3, f9 ; CHECK-P8-NEXT: mffprwz r3, f9
; CHECK-P8-NEXT: mtvsrd f7, r4 ; CHECK-P8-NEXT: mtfprd f7, r4
; CHECK-P8-NEXT: mfvsrwz r4, f11 ; CHECK-P8-NEXT: mffprwz r4, f11
; CHECK-P8-NEXT: vmrglb v4, v8, v4 ; CHECK-P8-NEXT: vmrglb v4, v8, v4
; CHECK-P8-NEXT: xxswapd v8, vs3 ; CHECK-P8-NEXT: xxswapd v8, vs3
; CHECK-P8-NEXT: vmrglb v5, v9, v5 ; CHECK-P8-NEXT: vmrglb v5, v9, v5
; CHECK-P8-NEXT: xxswapd v9, vs5 ; CHECK-P8-NEXT: xxswapd v9, vs5
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtvsrd f1, r4 ; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: vmrglb v0, v10, v0 ; CHECK-P8-NEXT: vmrglb v0, v10, v0
; CHECK-P8-NEXT: xxswapd v10, vs7 ; CHECK-P8-NEXT: xxswapd v10, vs7
; CHECK-P8-NEXT: vmrglb v1, v8, v1 ; CHECK-P8-NEXT: vmrglb v1, v8, v1
; CHECK-P8-NEXT: xxswapd v8, vs0 ; CHECK-P8-NEXT: xxswapd v8, vs0
; CHECK-P8-NEXT: vmrglb v6, v9, v6 ; CHECK-P8-NEXT: vmrglb v6, v9, v6
; CHECK-P8-NEXT: xxswapd v9, vs1 ; CHECK-P8-NEXT: xxswapd v9, vs1
; CHECK-P8-NEXT: vmrglb v7, v10, v7 ; CHECK-P8-NEXT: vmrglb v7, v10, v7
; CHECK-P8-NEXT: vmrglb v2, v8, v2 ; CHECK-P8-NEXT: vmrglb v2, v8, v2
Show All 15 Lines
; CHECK-P9-NEXT: xscvdpsxws f7, f7 ; CHECK-P9-NEXT: xscvdpsxws f7, f7
; CHECK-P9-NEXT: lxv vs0, 112(r3) ; CHECK-P9-NEXT: lxv vs0, 112(r3)
; CHECK-P9-NEXT: lxv vs1, 96(r3) ; CHECK-P9-NEXT: lxv vs1, 96(r3)
; CHECK-P9-NEXT: lxv vs2, 80(r3) ; CHECK-P9-NEXT: lxv vs2, 80(r3)
; CHECK-P9-NEXT: lxv vs3, 64(r3) ; CHECK-P9-NEXT: lxv vs3, 64(r3)
; CHECK-P9-NEXT: lxv vs4, 48(r3) ; CHECK-P9-NEXT: lxv vs4, 48(r3)
; CHECK-P9-NEXT: lxv vs5, 32(r3) ; CHECK-P9-NEXT: lxv vs5, 32(r3)
; CHECK-P9-NEXT: lxv vs6, 16(r3) ; CHECK-P9-NEXT: lxv vs6, 16(r3)
; CHECK-P9-NEXT: mfvsrwz r3, f8 ; CHECK-P9-NEXT: mffprwz r3, f8
; CHECK-P9-NEXT: mtvsrd f8, r3 ; CHECK-P9-NEXT: mtfprd f8, r3
; CHECK-P9-NEXT: mfvsrwz r3, f7 ; CHECK-P9-NEXT: mffprwz r3, f7
; CHECK-P9-NEXT: xxswapd v2, vs8 ; CHECK-P9-NEXT: xxswapd v2, vs8
; CHECK-P9-NEXT: mtvsrd f7, r3 ; CHECK-P9-NEXT: mtfprd f7, r3
; CHECK-P9-NEXT: xxswapd v3, vs7 ; CHECK-P9-NEXT: xxswapd v3, vs7
; CHECK-P9-NEXT: xscvdpsxws f7, f6 ; CHECK-P9-NEXT: xscvdpsxws f7, f6
; CHECK-P9-NEXT: xxswapd vs6, vs6 ; CHECK-P9-NEXT: xxswapd vs6, vs6
; CHECK-P9-NEXT: xscvdpsxws f6, f6 ; CHECK-P9-NEXT: xscvdpsxws f6, f6
; CHECK-P9-NEXT: mfvsrwz r3, f7 ; CHECK-P9-NEXT: mffprwz r3, f7
; CHECK-P9-NEXT: mtvsrd f7, r3 ; CHECK-P9-NEXT: mtfprd f7, r3
; CHECK-P9-NEXT: mfvsrwz r3, f6 ; CHECK-P9-NEXT: mffprwz r3, f6
; CHECK-P9-NEXT: mtvsrd f6, r3 ; CHECK-P9-NEXT: mtfprd f6, r3
; CHECK-P9-NEXT: xxswapd v4, vs6 ; CHECK-P9-NEXT: xxswapd v4, vs6
; CHECK-P9-NEXT: xscvdpsxws f6, f5 ; CHECK-P9-NEXT: xscvdpsxws f6, f5
; CHECK-P9-NEXT: xxswapd vs5, vs5 ; CHECK-P9-NEXT: xxswapd vs5, vs5
; CHECK-P9-NEXT: xscvdpsxws f5, f5 ; CHECK-P9-NEXT: xscvdpsxws f5, f5
; CHECK-P9-NEXT: mfvsrwz r3, f6 ; CHECK-P9-NEXT: mffprwz r3, f6
; CHECK-P9-NEXT: mtvsrd f6, r3 ; CHECK-P9-NEXT: mtfprd f6, r3
; CHECK-P9-NEXT: mfvsrwz r3, f5 ; CHECK-P9-NEXT: mffprwz r3, f5
; CHECK-P9-NEXT: vmrglb v2, v2, v3 ; CHECK-P9-NEXT: vmrglb v2, v2, v3
; CHECK-P9-NEXT: xxswapd v3, vs7 ; CHECK-P9-NEXT: xxswapd v3, vs7
; CHECK-P9-NEXT: vmrglb v3, v3, v4 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: vmrglh v2, v3, v2 ; CHECK-P9-NEXT: vmrglh v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs6 ; CHECK-P9-NEXT: xxswapd v3, vs6
; CHECK-P9-NEXT: mtvsrd f5, r3 ; CHECK-P9-NEXT: mtfprd f5, r3
; CHECK-P9-NEXT: xxswapd v4, vs5 ; CHECK-P9-NEXT: xxswapd v4, vs5
; CHECK-P9-NEXT: xscvdpsxws f5, f4 ; CHECK-P9-NEXT: xscvdpsxws f5, f4
; CHECK-P9-NEXT: xxswapd vs4, vs4 ; CHECK-P9-NEXT: xxswapd vs4, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f4 ; CHECK-P9-NEXT: xscvdpsxws f4, f4
; CHECK-P9-NEXT: mfvsrwz r3, f5 ; CHECK-P9-NEXT: mffprwz r3, f5
; CHECK-P9-NEXT: mtvsrd f5, r3 ; CHECK-P9-NEXT: mtfprd f5, r3
; CHECK-P9-NEXT: mfvsrwz r3, f4 ; CHECK-P9-NEXT: mffprwz r3, f4
; CHECK-P9-NEXT: mtvsrd f4, r3 ; CHECK-P9-NEXT: mtfprd f4, r3
; CHECK-P9-NEXT: xxswapd v5, vs4 ; CHECK-P9-NEXT: xxswapd v5, vs4
; CHECK-P9-NEXT: xscvdpsxws f4, f3 ; CHECK-P9-NEXT: xscvdpsxws f4, f3
; CHECK-P9-NEXT: xxswapd vs3, vs3 ; CHECK-P9-NEXT: xxswapd vs3, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f3 ; CHECK-P9-NEXT: xscvdpsxws f3, f3
; CHECK-P9-NEXT: vmrglb v3, v3, v4 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs5 ; CHECK-P9-NEXT: xxswapd v4, vs5
; CHECK-P9-NEXT: vmrglb v4, v4, v5 ; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: mfvsrwz r3, f4 ; CHECK-P9-NEXT: mffprwz r3, f4
; CHECK-P9-NEXT: mtvsrd f4, r3 ; CHECK-P9-NEXT: mtfprd f4, r3
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: xxswapd v4, vs3 ; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: xscvdpsxws f3, f2 ; CHECK-P9-NEXT: xscvdpsxws f3, f2
; CHECK-P9-NEXT: xxswapd vs2, vs2 ; CHECK-P9-NEXT: xxswapd vs2, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f2 ; CHECK-P9-NEXT: xscvdpsxws f2, f2
; CHECK-P9-NEXT: mfvsrwz r3, f3 ; CHECK-P9-NEXT: mffprwz r3, f3
; CHECK-P9-NEXT: mtvsrd f3, r3 ; CHECK-P9-NEXT: mtfprd f3, r3
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: xxswapd v5, vs2 ; CHECK-P9-NEXT: xxswapd v5, vs2
; CHECK-P9-NEXT: xscvdpsxws f2, f1 ; CHECK-P9-NEXT: xscvdpsxws f2, f1
; CHECK-P9-NEXT: xxswapd vs1, vs1 ; CHECK-P9-NEXT: xxswapd vs1, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f1 ; CHECK-P9-NEXT: xscvdpsxws f1, f1
; CHECK-P9-NEXT: vmrglw v2, v3, v2 ; CHECK-P9-NEXT: vmrglw v2, v3, v2
; CHECK-P9-NEXT: xxswapd v3, vs4 ; CHECK-P9-NEXT: xxswapd v3, vs4
; CHECK-P9-NEXT: vmrglb v3, v3, v4 ; CHECK-P9-NEXT: vmrglb v3, v3, v4
; CHECK-P9-NEXT: xxswapd v4, vs3 ; CHECK-P9-NEXT: xxswapd v4, vs3
; CHECK-P9-NEXT: vmrglb v4, v4, v5 ; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: vmrglh v3, v4, v3 ; CHECK-P9-NEXT: vmrglh v3, v4, v3
; CHECK-P9-NEXT: mfvsrwz r3, f2 ; CHECK-P9-NEXT: mffprwz r3, f2
; CHECK-P9-NEXT: mtvsrd f2, r3 ; CHECK-P9-NEXT: mtfprd f2, r3
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: xxswapd v4, vs2 ; CHECK-P9-NEXT: xxswapd v4, vs2
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: xxswapd v5, vs1 ; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xscvdpsxws f1, f0 ; CHECK-P9-NEXT: xscvdpsxws f1, f0
; CHECK-P9-NEXT: xxswapd vs0, vs0 ; CHECK-P9-NEXT: xxswapd vs0, vs0
; CHECK-P9-NEXT: xscvdpsxws f0, f0 ; CHECK-P9-NEXT: xscvdpsxws f0, f0
; CHECK-P9-NEXT: mfvsrwz r3, f1 ; CHECK-P9-NEXT: mffprwz r3, f1
; CHECK-P9-NEXT: mtvsrd f1, r3 ; CHECK-P9-NEXT: mtfprd f1, r3
; CHECK-P9-NEXT: mfvsrwz r3, f0 ; CHECK-P9-NEXT: mffprwz r3, f0
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: vmrglb v4, v4, v5 ; CHECK-P9-NEXT: vmrglb v4, v4, v5
; CHECK-P9-NEXT: xxswapd v5, vs1 ; CHECK-P9-NEXT: xxswapd v5, vs1
; CHECK-P9-NEXT: xxswapd v0, vs0 ; CHECK-P9-NEXT: xxswapd v0, vs0
; CHECK-P9-NEXT: vmrglb v5, v5, v0 ; CHECK-P9-NEXT: vmrglb v5, v5, v0
; CHECK-P9-NEXT: vmrglh v4, v5, v4 ; CHECK-P9-NEXT: vmrglh v4, v5, v4
; CHECK-P9-NEXT: vmrglw v3, v4, v3 ; CHECK-P9-NEXT: vmrglw v3, v4, v3
; CHECK-P9-NEXT: xxmrgld v2, v3, v2 ; CHECK-P9-NEXT: xxmrgld v2, v3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test16elt_signed: ; CHECK-BE-LABEL: test16elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: lxv vs7, 112(r3) ; CHECK-BE-NEXT: lxv vs7, 112(r3)
; CHECK-BE-NEXT: xscvdpsxws f8, f7 ; CHECK-BE-NEXT: xscvdpsxws f8, f7
; CHECK-BE-NEXT: xxswapd vs7, vs7 ; CHECK-BE-NEXT: xxswapd vs7, vs7
; CHECK-BE-NEXT: xscvdpsxws f7, f7 ; CHECK-BE-NEXT: xscvdpsxws f7, f7
; CHECK-BE-NEXT: lxv vs6, 96(r3) ; CHECK-BE-NEXT: lxv vs6, 96(r3)
; CHECK-BE-NEXT: lxv vs0, 0(r3) ; CHECK-BE-NEXT: lxv vs0, 0(r3)
; CHECK-BE-NEXT: lxv vs1, 16(r3) ; CHECK-BE-NEXT: lxv vs1, 16(r3)
; CHECK-BE-NEXT: lxv vs2, 32(r3) ; CHECK-BE-NEXT: lxv vs2, 32(r3)
; CHECK-BE-NEXT: lxv vs3, 48(r3) ; CHECK-BE-NEXT: lxv vs3, 48(r3)
; CHECK-BE-NEXT: lxv vs4, 64(r3) ; CHECK-BE-NEXT: lxv vs4, 64(r3)
; CHECK-BE-NEXT: lxv vs5, 80(r3) ; CHECK-BE-NEXT: lxv vs5, 80(r3)
; CHECK-BE-NEXT: mfvsrwz r3, f8 ; CHECK-BE-NEXT: mffprwz r3, f8
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v2, r3 ; CHECK-BE-NEXT: mtvsrd v2, r3
; CHECK-BE-NEXT: mfvsrwz r3, f7 ; CHECK-BE-NEXT: mffprwz r3, f7
; CHECK-BE-NEXT: xscvdpsxws f7, f6 ; CHECK-BE-NEXT: xscvdpsxws f7, f6
; CHECK-BE-NEXT: xxswapd vs6, vs6 ; CHECK-BE-NEXT: xxswapd vs6, vs6
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f6, f6 ; CHECK-BE-NEXT: xscvdpsxws f6, f6
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: vmrghb v2, v2, v3 ; CHECK-BE-NEXT: vmrghb v2, v2, v3
; CHECK-BE-NEXT: mfvsrwz r3, f7 ; CHECK-BE-NEXT: mffprwz r3, f7
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f6 ; CHECK-BE-NEXT: mffprwz r3, f6
; CHECK-BE-NEXT: xscvdpsxws f6, f5 ; CHECK-BE-NEXT: xscvdpsxws f6, f5
; CHECK-BE-NEXT: xxswapd vs5, vs5 ; CHECK-BE-NEXT: xxswapd vs5, vs5
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f5, f5 ; CHECK-BE-NEXT: xscvdpsxws f5, f5
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f6 ; CHECK-BE-NEXT: mffprwz r3, f6
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v2, v3, v2 ; CHECK-BE-NEXT: vmrghh v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f5 ; CHECK-BE-NEXT: mffprwz r3, f5
; CHECK-BE-NEXT: xscvdpsxws f5, f4 ; CHECK-BE-NEXT: xscvdpsxws f5, f4
; CHECK-BE-NEXT: xxswapd vs4, vs4 ; CHECK-BE-NEXT: xxswapd vs4, vs4
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f4, f4 ; CHECK-BE-NEXT: xscvdpsxws f4, f4
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f5 ; CHECK-BE-NEXT: mffprwz r3, f5
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: xscvdpsxws f4, f3 ; CHECK-BE-NEXT: xscvdpsxws f4, f3
; CHECK-BE-NEXT: xxswapd vs3, vs3 ; CHECK-BE-NEXT: xxswapd vs3, vs3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f3, f3 ; CHECK-BE-NEXT: xscvdpsxws f3, f3
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: mfvsrwz r3, f4 ; CHECK-BE-NEXT: mffprwz r3, f4
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghw v2, v3, v2 ; CHECK-BE-NEXT: vmrghw v2, v3, v2
; CHECK-BE-NEXT: mtvsrd v3, r3 ; CHECK-BE-NEXT: mtvsrd v3, r3
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: xscvdpsxws f3, f2 ; CHECK-BE-NEXT: xscvdpsxws f3, f2
; CHECK-BE-NEXT: xxswapd vs2, vs2 ; CHECK-BE-NEXT: xxswapd vs2, vs2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f2, f2 ; CHECK-BE-NEXT: xscvdpsxws f2, f2
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: vmrghb v3, v3, v4 ; CHECK-BE-NEXT: vmrghb v3, v3, v4
; CHECK-BE-NEXT: mfvsrwz r3, f3 ; CHECK-BE-NEXT: mffprwz r3, f3
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: xscvdpsxws f2, f1 ; CHECK-BE-NEXT: xscvdpsxws f2, f1
; CHECK-BE-NEXT: xxswapd vs1, vs1 ; CHECK-BE-NEXT: xxswapd vs1, vs1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f1, f1 ; CHECK-BE-NEXT: xscvdpsxws f1, f1
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: mfvsrwz r3, f2 ; CHECK-BE-NEXT: mffprwz r3, f2
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: vmrghh v3, v4, v3 ; CHECK-BE-NEXT: vmrghh v3, v4, v3
; CHECK-BE-NEXT: mtvsrd v4, r3 ; CHECK-BE-NEXT: mtvsrd v4, r3
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: xscvdpsxws f1, f0 ; CHECK-BE-NEXT: xscvdpsxws f1, f0
; CHECK-BE-NEXT: xxswapd vs0, vs0 ; CHECK-BE-NEXT: xxswapd vs0, vs0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: xscvdpsxws f0, f0 ; CHECK-BE-NEXT: xscvdpsxws f0, f0
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: vmrghb v4, v4, v5 ; CHECK-BE-NEXT: vmrghb v4, v4, v5
; CHECK-BE-NEXT: mfvsrwz r3, f1 ; CHECK-BE-NEXT: mffprwz r3, f1
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v5, r3 ; CHECK-BE-NEXT: mtvsrd v5, r3
; CHECK-BE-NEXT: mfvsrwz r3, f0 ; CHECK-BE-NEXT: mffprwz r3, f0
; CHECK-BE-NEXT: sldi r3, r3, 56 ; CHECK-BE-NEXT: sldi r3, r3, 56
; CHECK-BE-NEXT: mtvsrd v0, r3 ; CHECK-BE-NEXT: mtvsrd v0, r3
; CHECK-BE-NEXT: vmrghb v5, v5, v0 ; CHECK-BE-NEXT: vmrghb v5, v5, v0
; CHECK-BE-NEXT: vmrghh v4, v5, v4 ; CHECK-BE-NEXT: vmrghh v4, v5, v4
; CHECK-BE-NEXT: vmrghw v3, v4, v3 ; CHECK-BE-NEXT: vmrghw v3, v4, v3
; CHECK-BE-NEXT: xxmrghd v2, v3, v2 ; CHECK-BE-NEXT: xxmrghd v2, v3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%a = load <16 x double>, <16 x double>* %0, align 128 %a = load <16 x double>, <16 x double>* %0, align 128
%1 = fptosi <16 x double> %a to <16 x i8> %1 = fptosi <16 x double> %a to <16 x i8>
ret <16 x i8> %1 ret <16 x i8> %1
} }

llvm/test/CodeGen/PowerPC/vec_conv_fp_to_i_4byte_elts.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P8 ; RUN: FileCheck %s --check-prefix=CHECK-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P9 ; RUN: FileCheck %s --check-prefix=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define i64 @test2elt(i64 %a.coerce) local_unnamed_addr #0 { define i64 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xvcvspuxws vs0, v2 ; CHECK-P8-NEXT: xvcvspuxws vs0, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xvcvspuxws vs0, v2 ; CHECK-P9-NEXT: xvcvspuxws vs0, v2
; CHECK-P9-NEXT: mfvsrld r3, vs0 ; CHECK-P9-NEXT: mfvsrld r3, vs0
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xvcvspuxws vs0, vs0 ; CHECK-BE-NEXT: xvcvspuxws vs0, vs0
; CHECK-BE-NEXT: mfvsrd r3, f0 ; CHECK-BE-NEXT: mffprd r3, f0
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <2 x float> %0 = bitcast i64 %a.coerce to <2 x float>
%1 = fptoui <2 x float> %0 to <2 x i32> %1 = fptoui <2 x float> %0 to <2 x i32>
%2 = bitcast <2 x i32> %1 to i64 %2 = bitcast <2 x i32> %1 to i64
ret i64 %2 ret i64 %2
} }
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Linesentry:
%1 = fptoui <16 x float> %a to <16 x i32> %1 = fptoui <16 x float> %a to <16 x i32>
store <16 x i32> %1, <16 x i32>* %agg.result, align 64 store <16 x i32> %1, <16 x i32>* %agg.result, align 64
ret void ret void
} }
define i64 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 { define i64 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xvcvspsxws vs0, v2 ; CHECK-P8-NEXT: xvcvspsxws vs0, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xvcvspsxws vs0, v2 ; CHECK-P9-NEXT: xvcvspsxws vs0, v2
; CHECK-P9-NEXT: mfvsrld r3, vs0 ; CHECK-P9-NEXT: mfvsrld r3, vs0
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xvcvspsxws vs0, vs0 ; CHECK-BE-NEXT: xvcvspsxws vs0, vs0
; CHECK-BE-NEXT: mfvsrd r3, f0 ; CHECK-BE-NEXT: mffprd r3, f0
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <2 x float> %0 = bitcast i64 %a.coerce to <2 x float>
%1 = fptosi <2 x float> %0 to <2 x i32> %1 = fptosi <2 x float> %0 to <2 x i32>
%2 = bitcast <2 x i32> %1 to i64 %2 = bitcast <2 x i32> %1 to i64
ret i64 %2 ret i64 %2
} }
▲ Show 20 Lines • Show All 115 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp32_elts.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P8 ; RUN: FileCheck %s --check-prefix=CHECK-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P9 ; RUN: FileCheck %s --check-prefix=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 { define i64 @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r4, r3, 48 ; CHECK-P8-NEXT: clrldi r4, r3, 48
; CHECK-P8-NEXT: rldicl r3, r3, 48, 48 ; CHECK-P8-NEXT: rldicl r3, r3, 48, 48
; CHECK-P8-NEXT: rlwinm r4, r4, 0, 16, 31 ; CHECK-P8-NEXT: clrlwi r4, r4, 16
; CHECK-P8-NEXT: rlwinm r3, r3, 0, 16, 31 ; CHECK-P8-NEXT: clrlwi r3, r3, 16
; CHECK-P8-NEXT: mtfprwz f0, r4 ; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: mtfprwz f1, r3 ; CHECK-P8-NEXT: mtfprwz f1, r3
; CHECK-P8-NEXT: xscvuxdsp f0, f0 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: xscvuxdsp f1, f1 ; CHECK-P8-NEXT: xscvuxdsp f1, f1
; CHECK-P8-NEXT: xscvdpspn vs0, f0 ; CHECK-P8-NEXT: xscvdpspn vs0, f0
; CHECK-P8-NEXT: xscvdpspn vs1, f1 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextuhrx r3, r3, v2 ; CHECK-P9-NEXT: vextuhrx r3, r3, v2
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 16, 31 ; CHECK-P9-NEXT: clrlwi r3, r3, 16
; CHECK-P9-NEXT: mtfprwz f0, r3 ; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: li r3, 2 ; CHECK-P9-NEXT: li r3, 2
; CHECK-P9-NEXT: xscvuxdsp f0, f0 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: vextuhrx r3, r3, v2 ; CHECK-P9-NEXT: vextuhrx r3, r3, v2
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 16, 31 ; CHECK-P9-NEXT: clrlwi r3, r3, 16
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-P9-NEXT: mtfprwz f0, r3 ; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: xscvuxdsp f0, f0 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P9-NEXT: vmrglw v2, v2, v3 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: li r3, 2 ; CHECK-BE-NEXT: li r3, 2
; CHECK-BE-NEXT: vextuhlx r3, r3, v2 ; CHECK-BE-NEXT: vextuhlx r3, r3, v2
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; CHECK-BE-NEXT: clrlwi r3, r3, 16
; CHECK-BE-NEXT: mtfprwz f0, r3 ; CHECK-BE-NEXT: mtfprwz f0, r3
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: xscvuxdsp f0, f0 ; CHECK-BE-NEXT: xscvuxdsp f0, f0
; CHECK-BE-NEXT: vextuhlx r3, r3, v2 ; CHECK-BE-NEXT: vextuhlx r3, r3, v2
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 16, 31 ; CHECK-BE-NEXT: clrlwi r3, r3, 16
; CHECK-BE-NEXT: xscvdpspn v3, f0 ; CHECK-BE-NEXT: xscvdpspn v3, f0
; CHECK-BE-NEXT: mtfprwz f0, r3 ; CHECK-BE-NEXT: mtfprwz f0, r3
; CHECK-BE-NEXT: xscvuxdsp f0, f0 ; CHECK-BE-NEXT: xscvuxdsp f0, f0
; CHECK-BE-NEXT: xscvdpspn v2, f0 ; CHECK-BE-NEXT: xscvdpspn v2, f0
; CHECK-BE-NEXT: vmrghw v2, v2, v3 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i32 %a.coerce to <2 x i16> %0 = bitcast i32 %a.coerce to <2 x i16>
%1 = uitofp <2 x i16> %0 to <2 x float> %1 = uitofp <2 x i16> %0 to <2 x float>
%2 = bitcast <2 x float> %1 to i64 %2 = bitcast <2 x float> %1 to i64
ret i64 %2 ret i64 %2
} }
define <4 x float> @test4elt(i64 %a.coerce) local_unnamed_addr #1 { define <4 x float> @test4elt(i64 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt: ; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI1_0@toc@l ; CHECK-P8-NEXT: addi r3, r4, .LCPI1_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-P8-NEXT: xvcvuxwsp v2, v2 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: addis r3, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l ; CHECK-P9-NEXT: addi r3, r3, .LCPI1_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r3 ; CHECK-P9-NEXT: lxvx v3, 0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: vperm v2, v4, v2, v3 ; CHECK-P9-NEXT: vperm v2, v4, v2, v3
; CHECK-P9-NEXT: xvcvuxwsp v2, v2 ; CHECK-P9-NEXT: xvcvuxwsp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
▲ Show 20 Lines • Show All 155 Lines • ▼ Show 20 Linesentry:
%1 = uitofp <16 x i16> %a to <16 x float> %1 = uitofp <16 x i16> %a to <16 x float>
store <16 x float> %1, <16 x float>* %agg.result, align 64 store <16 x float> %1, <16 x float>* %agg.result, align 64
ret void ret void
} }
define i64 @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 { define i64 @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r4, r3, 48 ; CHECK-P8-NEXT: clrldi r4, r3, 48
; CHECK-P8-NEXT: rldicl r3, r3, 48, 48 ; CHECK-P8-NEXT: rldicl r3, r3, 48, 48
; CHECK-P8-NEXT: extsh r4, r4 ; CHECK-P8-NEXT: extsh r4, r4
; CHECK-P8-NEXT: extsh r3, r3 ; CHECK-P8-NEXT: extsh r3, r3
; CHECK-P8-NEXT: mtfprwa f0, r4 ; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: mtfprwa f1, r3 ; CHECK-P8-NEXT: mtfprwa f1, r3
; CHECK-P8-NEXT: xscvsxdsp f0, f0 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: xscvsxdsp f1, f1 ; CHECK-P8-NEXT: xscvsxdsp f1, f1
; CHECK-P8-NEXT: xscvdpspn vs0, f0 ; CHECK-P8-NEXT: xscvdpspn vs0, f0
; CHECK-P8-NEXT: xscvdpspn vs1, f1 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextuhrx r3, r3, v2 ; CHECK-P9-NEXT: vextuhrx r3, r3, v2
; CHECK-P9-NEXT: extsh r3, r3 ; CHECK-P9-NEXT: extsh r3, r3
Show All 35 Linesentry:
%1 = sitofp <2 x i16> %0 to <2 x float> %1 = sitofp <2 x i16> %0 to <2 x float>
%2 = bitcast <2 x float> %1 to i64 %2 = bitcast <2 x float> %1 to i64
ret i64 %2 ret i64 %2
} }
define <4 x float> @test4elt_signed(i64 %a.coerce) local_unnamed_addr #1 { define <4 x float> @test4elt_signed(i64 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: vspltisw v3, 8 ; CHECK-P8-NEXT: vspltisw v3, 8
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: vadduwm v3, v3, v3 ; CHECK-P8-NEXT: vadduwm v3, v3, v3
; CHECK-P8-NEXT: vmrglh v2, v2, v2 ; CHECK-P8-NEXT: vmrglh v2, v2, v2
; CHECK-P8-NEXT: vslw v2, v2, v3 ; CHECK-P8-NEXT: vslw v2, v2, v3
; CHECK-P8-NEXT: vsraw v2, v2, v3 ; CHECK-P8-NEXT: vsraw v2, v2, v3
; CHECK-P8-NEXT: xvcvsxwsp v2, v2 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vmrglh v2, v2, v2 ; CHECK-P9-NEXT: vmrglh v2, v2, v2
; CHECK-P9-NEXT: vextsh2w v2, v2 ; CHECK-P9-NEXT: vextsh2w v2, v2
; CHECK-P9-NEXT: xvcvsxwsp v2, v2 ; CHECK-P9-NEXT: xvcvsxwsp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test4elt_signed: ; CHECK-BE-LABEL: test4elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
▲ Show 20 Lines • Show All 147 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i16_to_fp64_elts.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P8 ; RUN: FileCheck %s --check-prefix=CHECK-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P9 ; RUN: FileCheck %s --check-prefix=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define <2 x double> @test2elt(i32 %a.coerce) local_unnamed_addr #0 { define <2 x double> @test2elt(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI0_0@toc@l ; CHECK-P8-NEXT: addi r3, r4, .LCPI0_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-P8-NEXT: xvcvuxddp v2, v2 ; CHECK-P8-NEXT: xvcvuxddp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
Show All 23 Linesentry:
%1 = uitofp <2 x i16> %0 to <2 x double> %1 = uitofp <2 x i16> %0 to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
} }
define void @test4elt(<4 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 { define void @test4elt(<4 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt: ; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: lvx v2, 0, r5
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: lvx v5, 0, r4 ; CHECK-P8-NEXT: lvx v5, 0, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: vperm v2, v4, v3, v2 ; CHECK-P8-NEXT: vperm v2, v4, v3, v2
; CHECK-P8-NEXT: vperm v3, v4, v3, v5 ; CHECK-P8-NEXT: vperm v3, v4, v3, v5
; CHECK-P8-NEXT: xvcvuxddp vs0, v2 ; CHECK-P8-NEXT: xvcvuxddp vs0, v2
; CHECK-P8-NEXT: xvcvuxddp vs1, v3 ; CHECK-P8-NEXT: xvcvuxddp vs1, v3
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt: ; CHECK-P9-LABEL: test4elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
▲ Show 20 Lines • Show All 279 Lines • ▼ Show 20 Linesentry:
store <16 x double> %1, <16 x double>* %agg.result, align 128 store <16 x double> %1, <16 x double>* %agg.result, align 128
ret void ret void
} }
define <2 x double> @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 { define <2 x double> @test2elt_signed(i32 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI4_0@toc@l ; CHECK-P8-NEXT: addi r3, r4, .LCPI4_0@toc@l
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
Show All 28 Linesentry:
%1 = sitofp <2 x i16> %0 to <2 x double> %1 = sitofp <2 x i16> %0 to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
} }
define void @test4elt_signed(<4 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 { define void @test4elt_signed(<4 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI5_2@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_2@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI5_2@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI5_2@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: lvx v2, 0, r5
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: lvx v4, 0, r4 ; CHECK-P8-NEXT: lvx v4, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l
Show All 11 Lines
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: xxswapd vs1, vs1 ; CHECK-P8-NEXT: xxswapd vs1, vs1
; CHECK-P8-NEXT: stxvd2x vs1, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test4elt_signed: ; CHECK-P9-LABEL: test4elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI5_1@toc@l
; CHECK-P9-NEXT: vextsh2d v3, v3 ; CHECK-P9-NEXT: vextsh2d v3, v3
▲ Show 20 Lines • Show All 337 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i32_to_fp64_elts.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P8 ; RUN: FileCheck %s --check-prefix=CHECK-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P9 ; RUN: FileCheck %s --check-prefix=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define <2 x double> @test2elt(i64 %a.coerce) local_unnamed_addr #0 { define <2 x double> @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw v2, v2, v2 ; CHECK-P8-NEXT: xxmrglw v2, v2, v2
; CHECK-P8-NEXT: xvcvuxwdp v2, v2 ; CHECK-P8-NEXT: xvcvuxwdp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxmrglw v2, v2, v2 ; CHECK-P9-NEXT: xxmrglw v2, v2, v2
; CHECK-P9-NEXT: xvcvuxwdp v2, v2 ; CHECK-P9-NEXT: xvcvuxwdp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0 ; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
; CHECK-BE-NEXT: xvcvuxwdp v2, v2 ; CHECK-BE-NEXT: xvcvuxwdp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <2 x i32> %0 = bitcast i64 %a.coerce to <2 x i32>
%1 = uitofp <2 x i32> %0 to <2 x double> %1 = uitofp <2 x i32> %0 to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
} }
▲ Show 20 Lines • Show All 221 Lines • ▼ Show 20 Linesentry:
%1 = uitofp <16 x i32> %a to <16 x double> %1 = uitofp <16 x i32> %a to <16 x double>
store <16 x double> %1, <16 x double>* %agg.result, align 128 store <16 x double> %1, <16 x double>* %agg.result, align 128
ret void ret void
} }
define <2 x double> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 { define <2 x double> @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xxmrglw v2, v2, v2 ; CHECK-P8-NEXT: xxmrglw v2, v2, v2
; CHECK-P8-NEXT: xvcvsxwdp v2, v2 ; CHECK-P8-NEXT: xvcvsxwdp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxmrglw v2, v2, v2 ; CHECK-P9-NEXT: xxmrglw v2, v2, v2
; CHECK-P9-NEXT: xvcvsxwdp v2, v2 ; CHECK-P9-NEXT: xvcvsxwdp v2, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0 ; CHECK-BE-NEXT: xxmrghw v2, vs0, vs0
; CHECK-BE-NEXT: xvcvsxwdp v2, v2 ; CHECK-BE-NEXT: xvcvsxwdp v2, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <2 x i32> %0 = bitcast i64 %a.coerce to <2 x i32>
%1 = sitofp <2 x i32> %0 to <2 x double> %1 = sitofp <2 x i32> %0 to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
} }
▲ Show 20 Lines • Show All 225 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i64_to_fp32_elts.ll

Show All 16 Lines
; CHECK-P8-NEXT: xscvuxdsp f1, f1 ; CHECK-P8-NEXT: xscvuxdsp f1, f1
; CHECK-P8-NEXT: xscvuxdsp f0, f0 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: xscvdpspn vs1, f1 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
; CHECK-P8-NEXT: xscvdpspn vs0, f0 ; CHECK-P8-NEXT: xscvdpspn vs0, f0
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvuxdsp f0, f0 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
▲ Show 20 Lines • Show All 276 Lines • ▼ Show 20 Lines
; CHECK-P8-NEXT: xscvsxdsp f1, f1 ; CHECK-P8-NEXT: xscvsxdsp f1, f1
; CHECK-P8-NEXT: xscvsxdsp f0, f0 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: xscvdpspn vs1, f1 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
; CHECK-P8-NEXT: xscvdpspn vs0, f0 ; CHECK-P8-NEXT: xscvdpspn vs0, f0
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: xxswapd vs0, v2 ; CHECK-P9-NEXT: xxswapd vs0, v2
; CHECK-P9-NEXT: xscvsxdsp f0, f0 ; CHECK-P9-NEXT: xscvsxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
▲ Show 20 Lines • Show All 270 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp32_elts.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P8 ; RUN: FileCheck %s --check-prefix=CHECK-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P9 ; RUN: FileCheck %s --check-prefix=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 { define i64 @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r4, r3, 56 ; CHECK-P8-NEXT: clrldi r4, r3, 56
; CHECK-P8-NEXT: rldicl r3, r3, 56, 56 ; CHECK-P8-NEXT: rldicl r3, r3, 56, 56
; CHECK-P8-NEXT: rlwinm r4, r4, 0, 24, 31 ; CHECK-P8-NEXT: clrlwi r4, r4, 24
; CHECK-P8-NEXT: rlwinm r3, r3, 0, 24, 31 ; CHECK-P8-NEXT: clrlwi r3, r3, 24
; CHECK-P8-NEXT: mtfprwz f0, r4 ; CHECK-P8-NEXT: mtfprwz f0, r4
; CHECK-P8-NEXT: mtfprwz f1, r3 ; CHECK-P8-NEXT: mtfprwz f1, r3
; CHECK-P8-NEXT: xscvuxdsp f0, f0 ; CHECK-P8-NEXT: xscvuxdsp f0, f0
; CHECK-P8-NEXT: xscvuxdsp f1, f1 ; CHECK-P8-NEXT: xscvuxdsp f1, f1
; CHECK-P8-NEXT: xscvdpspn vs0, f0 ; CHECK-P8-NEXT: xscvdpspn vs0, f0
; CHECK-P8-NEXT: xscvdpspn vs1, f1 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextubrx r3, r3, v2 ; CHECK-P9-NEXT: vextubrx r3, r3, v2
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 24, 31 ; CHECK-P9-NEXT: clrlwi r3, r3, 24
; CHECK-P9-NEXT: mtfprwz f0, r3 ; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: li r3, 1 ; CHECK-P9-NEXT: li r3, 1
; CHECK-P9-NEXT: xscvuxdsp f0, f0 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: vextubrx r3, r3, v2 ; CHECK-P9-NEXT: vextubrx r3, r3, v2
; CHECK-P9-NEXT: rlwinm r3, r3, 0, 24, 31 ; CHECK-P9-NEXT: clrlwi r3, r3, 24
; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi v3, vs0, vs0, 1
; CHECK-P9-NEXT: mtfprwz f0, r3 ; CHECK-P9-NEXT: mtfprwz f0, r3
; CHECK-P9-NEXT: xscvuxdsp f0, f0 ; CHECK-P9-NEXT: xscvuxdsp f0, f0
; CHECK-P9-NEXT: xscvdpspn vs0, f0 ; CHECK-P9-NEXT: xscvdpspn vs0, f0
; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1 ; CHECK-P9-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P9-NEXT: vmrglw v2, v2, v3 ; CHECK-P9-NEXT: vmrglw v2, v2, v3
; CHECK-P9-NEXT: mfvsrld r3, v2 ; CHECK-P9-NEXT: mfvsrld r3, v2
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrws v2, r3 ; CHECK-BE-NEXT: mtvsrws v2, r3
; CHECK-BE-NEXT: li r3, 1 ; CHECK-BE-NEXT: li r3, 1
; CHECK-BE-NEXT: vextublx r3, r3, v2 ; CHECK-BE-NEXT: vextublx r3, r3, v2
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 24, 31 ; CHECK-BE-NEXT: clrlwi r3, r3, 24
; CHECK-BE-NEXT: mtfprwz f0, r3 ; CHECK-BE-NEXT: mtfprwz f0, r3
; CHECK-BE-NEXT: li r3, 0 ; CHECK-BE-NEXT: li r3, 0
; CHECK-BE-NEXT: xscvuxdsp f0, f0 ; CHECK-BE-NEXT: xscvuxdsp f0, f0
; CHECK-BE-NEXT: vextublx r3, r3, v2 ; CHECK-BE-NEXT: vextublx r3, r3, v2
; CHECK-BE-NEXT: rlwinm r3, r3, 0, 24, 31 ; CHECK-BE-NEXT: clrlwi r3, r3, 24
; CHECK-BE-NEXT: xscvdpspn v3, f0 ; CHECK-BE-NEXT: xscvdpspn v3, f0
; CHECK-BE-NEXT: mtfprwz f0, r3 ; CHECK-BE-NEXT: mtfprwz f0, r3
; CHECK-BE-NEXT: xscvuxdsp f0, f0 ; CHECK-BE-NEXT: xscvuxdsp f0, f0
; CHECK-BE-NEXT: xscvdpspn v2, f0 ; CHECK-BE-NEXT: xscvdpspn v2, f0
; CHECK-BE-NEXT: vmrghw v2, v2, v3 ; CHECK-BE-NEXT: vmrghw v2, v2, v3
; CHECK-BE-NEXT: mfvsrd r3, v2 ; CHECK-BE-NEXT: mfvsrd r3, v2
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i16 %a.coerce to <2 x i8> %0 = bitcast i16 %a.coerce to <2 x i8>
%1 = uitofp <2 x i8> %0 to <2 x float> %1 = uitofp <2 x i8> %0 to <2 x float>
%2 = bitcast <2 x float> %1 to i64 %2 = bitcast <2 x float> %1 to i64
ret i64 %2 ret i64 %2
} }
define <4 x float> @test4elt(i32 %a.coerce) local_unnamed_addr #1 { define <4 x float> @test4elt(i32 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt: ; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI1_0@toc@l ; CHECK-P8-NEXT: addi r3, r4, .LCPI1_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-P8-NEXT: xvcvuxwsp v2, v2 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
Show All 23 Linesentry:
%1 = uitofp <4 x i8> %0 to <4 x float> %1 = uitofp <4 x i8> %0 to <4 x float>
ret <4 x float> %1 ret <4 x float> %1
} }
define void @test8elt(<8 x float>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #2 { define void @test8elt(<8 x float>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt: ; CHECK-P8-LABEL: test8elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: lvx v2, 0, r5
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: lvx v5, 0, r4 ; CHECK-P8-NEXT: lvx v5, 0, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: vperm v2, v4, v3, v2 ; CHECK-P8-NEXT: vperm v2, v4, v3, v2
; CHECK-P8-NEXT: vperm v3, v4, v3, v5 ; CHECK-P8-NEXT: vperm v3, v4, v3, v5
; CHECK-P8-NEXT: xvcvuxwsp v2, v2 ; CHECK-P8-NEXT: xvcvuxwsp v2, v2
; CHECK-P8-NEXT: xvcvuxwsp v3, v3 ; CHECK-P8-NEXT: xvcvuxwsp v3, v3
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stvx v2, 0, r3
; CHECK-P8-NEXT: stvx v3, r3, r4 ; CHECK-P8-NEXT: stvx v3, r3, r4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
▲ Show 20 Lines • Show All 123 Lines • ▼ Show 20 Linesentry:
%0 = uitofp <16 x i8> %a to <16 x float> %0 = uitofp <16 x i8> %a to <16 x float>
store <16 x float> %0, <16 x float>* %agg.result, align 64 store <16 x float> %0, <16 x float>* %agg.result, align 64
ret void ret void
} }
define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 { define i64 @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: clrldi r4, r3, 56 ; CHECK-P8-NEXT: clrldi r4, r3, 56
; CHECK-P8-NEXT: rldicl r3, r3, 56, 56 ; CHECK-P8-NEXT: rldicl r3, r3, 56, 56
; CHECK-P8-NEXT: extsb r4, r4 ; CHECK-P8-NEXT: extsb r4, r4
; CHECK-P8-NEXT: extsb r3, r3 ; CHECK-P8-NEXT: extsb r3, r3
; CHECK-P8-NEXT: mtfprwa f0, r4 ; CHECK-P8-NEXT: mtfprwa f0, r4
; CHECK-P8-NEXT: mtfprwa f1, r3 ; CHECK-P8-NEXT: mtfprwa f1, r3
; CHECK-P8-NEXT: xscvsxdsp f0, f0 ; CHECK-P8-NEXT: xscvsxdsp f0, f0
; CHECK-P8-NEXT: xscvsxdsp f1, f1 ; CHECK-P8-NEXT: xscvsxdsp f1, f1
; CHECK-P8-NEXT: xscvdpspn vs0, f0 ; CHECK-P8-NEXT: xscvdpspn vs0, f0
; CHECK-P8-NEXT: xscvdpspn vs1, f1 ; CHECK-P8-NEXT: xscvdpspn vs1, f1
; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1 ; CHECK-P8-NEXT: xxsldwi v2, vs0, vs0, 1
; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1 ; CHECK-P8-NEXT: xxsldwi v3, vs1, vs1, 1
; CHECK-P8-NEXT: vmrglw v2, v3, v2 ; CHECK-P8-NEXT: vmrglw v2, v3, v2
; CHECK-P8-NEXT: xxswapd vs0, v2 ; CHECK-P8-NEXT: xxswapd vs0, v2
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrws v2, r3 ; CHECK-P9-NEXT: mtvsrws v2, r3
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: vextubrx r3, r3, v2 ; CHECK-P9-NEXT: vextubrx r3, r3, v2
; CHECK-P9-NEXT: extsb r3, r3 ; CHECK-P9-NEXT: extsb r3, r3
Show All 36 Linesentry:
%2 = bitcast <2 x float> %1 to i64 %2 = bitcast <2 x float> %1 to i64
ret i64 %2 ret i64 %2
} }
define <4 x float> @test4elt_signed(i32 %a.coerce) local_unnamed_addr #1 { define <4 x float> @test4elt_signed(i32 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI5_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI5_0@toc@l ; CHECK-P8-NEXT: addi r3, r4, .LCPI5_0@toc@l
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-NEXT: vspltisw v3, 12 ; CHECK-P8-NEXT: vspltisw v3, 12
; CHECK-P8-NEXT: vadduwm v3, v3, v3 ; CHECK-P8-NEXT: vadduwm v3, v3, v3
; CHECK-P8-NEXT: vslw v2, v2, v3 ; CHECK-P8-NEXT: vslw v2, v2, v3
; CHECK-P8-NEXT: vsraw v2, v2, v3 ; CHECK-P8-NEXT: vsraw v2, v2, v3
Show All 26 Linesentry:
%1 = sitofp <4 x i8> %0 to <4 x float> %1 = sitofp <4 x i8> %0 to <4 x float>
ret <4 x float> %1 ret <4 x float> %1
} }
define void @test8elt_signed(<8 x float>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #2 { define void @test8elt_signed(<8 x float>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #2 {
; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8-LABEL: test8elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-P8-NEXT: vspltisw v5, 12 ; CHECK-P8-NEXT: vspltisw v5, 12
; CHECK-P8-NEXT: addi r5, r5, .LCPI6_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: lvx v2, 0, r5
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: lvx v4, 0, r4 ; CHECK-P8-NEXT: lvx v4, 0, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: vperm v2, v3, v3, v2 ; CHECK-P8-NEXT: vperm v2, v3, v3, v2
; CHECK-P8-NEXT: vperm v3, v3, v3, v4 ; CHECK-P8-NEXT: vperm v3, v3, v3, v4
; CHECK-P8-NEXT: vadduwm v4, v5, v5 ; CHECK-P8-NEXT: vadduwm v4, v5, v5
; CHECK-P8-NEXT: vslw v2, v2, v4 ; CHECK-P8-NEXT: vslw v2, v2, v4
; CHECK-P8-NEXT: vslw v3, v3, v4 ; CHECK-P8-NEXT: vslw v3, v3, v4
; CHECK-P8-NEXT: vsraw v2, v2, v4 ; CHECK-P8-NEXT: vsraw v2, v2, v4
; CHECK-P8-NEXT: vsraw v3, v3, v4 ; CHECK-P8-NEXT: vsraw v3, v3, v4
; CHECK-P8-NEXT: xvcvsxwsp v2, v2 ; CHECK-P8-NEXT: xvcvsxwsp v2, v2
; CHECK-P8-NEXT: xvcvsxwsp v3, v3 ; CHECK-P8-NEXT: xvcvsxwsp v3, v3
; CHECK-P8-NEXT: stvx v2, 0, r3 ; CHECK-P8-NEXT: stvx v2, 0, r3
; CHECK-P8-NEXT: stvx v3, r3, r4 ; CHECK-P8-NEXT: stvx v3, r3, r4
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-P9-NEXT: vextsb2w v3, v3 ; CHECK-P9-NEXT: vextsb2w v3, v3
▲ Show 20 Lines • Show All 146 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i8_to_fp64_elts.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P8 ; RUN: FileCheck %s --check-prefix=CHECK-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P9 ; RUN: FileCheck %s --check-prefix=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define <2 x double> @test2elt(i16 %a.coerce) local_unnamed_addr #0 { define <2 x double> @test2elt(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI0_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI0_0@toc@l ; CHECK-P8-NEXT: addi r3, r4, .LCPI0_0@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: vperm v2, v4, v2, v3 ; CHECK-P8-NEXT: vperm v2, v4, v2, v3
; CHECK-P8-NEXT: xvcvuxddp v2, v2 ; CHECK-P8-NEXT: xvcvuxddp v2, v2
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
Show All 23 Linesentry:
%1 = uitofp <2 x i8> %0 to <2 x double> %1 = uitofp <2 x i8> %0 to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
} }
define void @test4elt(<4 x double>* noalias nocapture sret %agg.result, i32 %a.coerce) local_unnamed_addr #1 { define void @test4elt(<4 x double>* noalias nocapture sret %agg.result, i32 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt: ; CHECK-P8-LABEL: test4elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI1_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI1_1@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI1_1@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI1_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI1_1@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI1_1@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: lvx v2, 0, r5
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: lvx v5, 0, r4 ; CHECK-P8-NEXT: lvx v5, 0, r4
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Linesentry:
store <4 x double> %1, <4 x double>* %agg.result, align 32 store <4 x double> %1, <4 x double>* %agg.result, align 32
ret void ret void
} }
define void @test8elt(<8 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 { define void @test8elt(<8 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test8elt: ; CHECK-P8-LABEL: test8elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI2_2@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_2@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI2_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI2_2@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI2_2@toc@l
; CHECK-P8-NEXT: xxlxor v4, v4, v4 ; CHECK-P8-NEXT: xxlxor v4, v4, v4
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: lvx v2, 0, r5
; CHECK-P8-NEXT: addis r5, r2, .LCPI2_3@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI2_3@toc@ha
; CHECK-P8-NEXT: lvx v5, 0, r4 ; CHECK-P8-NEXT: lvx v5, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI2_1@toc@ha
Show All 20 Lines
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt: ; CHECK-P9-LABEL: test8elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xxlxor v4, v4, v4 ; CHECK-P9-NEXT: xxlxor v4, v4, v4
; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI2_1@toc@l
; CHECK-P9-NEXT: vperm v3, v4, v2, v3 ; CHECK-P9-NEXT: vperm v3, v4, v2, v3
▲ Show 20 Lines • Show All 232 Lines • ▼ Show 20 Linesentry:
store <16 x double> %0, <16 x double>* %agg.result, align 128 store <16 x double> %0, <16 x double>* %agg.result, align 128
ret void ret void
} }
define <2 x double> @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 { define <2 x double> @test2elt_signed(i16 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI4_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: addi r3, r4, .LCPI4_0@toc@l ; CHECK-P8-NEXT: addi r3, r4, .LCPI4_0@toc@l
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: lvx v3, 0, r3 ; CHECK-P8-NEXT: lvx v3, 0, r3
; CHECK-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha ; CHECK-P8-NEXT: addis r3, r2, .LCPI4_1@toc@ha
; CHECK-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l ; CHECK-P8-NEXT: addi r3, r3, .LCPI4_1@toc@l
; CHECK-P8-NEXT: lxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: lxvd2x vs0, 0, r3
; CHECK-P8-NEXT: vperm v2, v2, v2, v3 ; CHECK-P8-NEXT: vperm v2, v2, v2, v3
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
Show All 28 Linesentry:
%1 = sitofp <2 x i8> %0 to <2 x double> %1 = sitofp <2 x i8> %0 to <2 x double>
ret <2 x double> %1 ret <2 x double> %1
} }
define void @test4elt_signed(<4 x double>* noalias nocapture sret %agg.result, i32 %a.coerce) local_unnamed_addr #1 { define void @test4elt_signed(<4 x double>* noalias nocapture sret %agg.result, i32 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test4elt_signed: ; CHECK-P8-LABEL: test4elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI5_0@toc@ha
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI5_2@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_2@toc@ha
; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI5_0@toc@l
; CHECK-P8-NEXT: addi r4, r4, .LCPI5_2@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI5_2@toc@l
; CHECK-P8-NEXT: lvx v2, 0, r5 ; CHECK-P8-NEXT: lvx v2, 0, r5
; CHECK-P8-NEXT: xxswapd v3, vs0 ; CHECK-P8-NEXT: xxswapd v3, vs0
; CHECK-P8-NEXT: lvx v4, 0, r4 ; CHECK-P8-NEXT: lvx v4, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI5_1@toc@ha
; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI5_1@toc@l
▲ Show 20 Lines • Show All 57 Lines • ▼ Show 20 Linesentry:
%1 = sitofp <4 x i8> %0 to <4 x double> %1 = sitofp <4 x i8> %0 to <4 x double>
store <4 x double> %1, <4 x double>* %agg.result, align 32 store <4 x double> %1, <4 x double>* %agg.result, align 32
ret void ret void
} }
define void @test8elt_signed(<8 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 { define void @test8elt_signed(<8 x double>* noalias nocapture sret %agg.result, i64 %a.coerce) local_unnamed_addr #1 {
; CHECK-P8-LABEL: test8elt_signed: ; CHECK-P8-LABEL: test8elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r4 ; CHECK-P8-NEXT: mtfprd f0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI6_2@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI6_2@toc@ha
; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha ; CHECK-P8-NEXT: addis r5, r2, .LCPI6_0@toc@ha
; CHECK-P8-NEXT: addis r6, r2, .LCPI6_3@toc@ha ; CHECK-P8-NEXT: addis r6, r2, .LCPI6_3@toc@ha
; CHECK-P8-NEXT: addi r4, r4, .LCPI6_2@toc@l ; CHECK-P8-NEXT: addi r4, r4, .LCPI6_2@toc@l
; CHECK-P8-NEXT: addi r5, r5, .LCPI6_0@toc@l ; CHECK-P8-NEXT: addi r5, r5, .LCPI6_0@toc@l
; CHECK-P8-NEXT: addi r6, r6, .LCPI6_3@toc@l ; CHECK-P8-NEXT: addi r6, r6, .LCPI6_3@toc@l
; CHECK-P8-NEXT: lvx v4, 0, r4 ; CHECK-P8-NEXT: lvx v4, 0, r4
; CHECK-P8-NEXT: addis r4, r2, .LCPI6_4@toc@ha ; CHECK-P8-NEXT: addis r4, r2, .LCPI6_4@toc@ha
Show All 32 Lines
; CHECK-P8-NEXT: li r4, 16 ; CHECK-P8-NEXT: li r4, 16
; CHECK-P8-NEXT: stxvd2x vs1, r3, r5 ; CHECK-P8-NEXT: stxvd2x vs1, r3, r5
; CHECK-P8-NEXT: stxvd2x vs3, r3, r4 ; CHECK-P8-NEXT: stxvd2x vs3, r3, r4
; CHECK-P8-NEXT: stxvd2x vs0, 0, r3 ; CHECK-P8-NEXT: stxvd2x vs0, 0, r3
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test8elt_signed: ; CHECK-P9-LABEL: test8elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r4 ; CHECK-P9-NEXT: mtfprd f0, r4
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_0@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_0@toc@l
; CHECK-P9-NEXT: lxvx v3, 0, r4 ; CHECK-P9-NEXT: lxvx v3, 0, r4
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: vperm v3, v2, v2, v3 ; CHECK-P9-NEXT: vperm v3, v2, v2, v3
; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha ; CHECK-P9-NEXT: addis r4, r2, .LCPI6_1@toc@ha
; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l ; CHECK-P9-NEXT: addi r4, r4, .LCPI6_1@toc@l
; CHECK-P9-NEXT: vextsb2d v3, v3 ; CHECK-P9-NEXT: vextsb2d v3, v3
▲ Show 20 Lines • Show All 276 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vec_conv_i_to_fp_4byte_elts.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P8 ; RUN: FileCheck %s --check-prefix=CHECK-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-P9 ; RUN: FileCheck %s --check-prefix=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \ ; RUN: -mcpu=pwr9 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
; RUN: FileCheck %s --check-prefix=CHECK-BE ; RUN: FileCheck %s --check-prefix=CHECK-BE
define i64 @test2elt(i64 %a.coerce) local_unnamed_addr #0 { define i64 @test2elt(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt: ; CHECK-P8-LABEL: test2elt:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xvcvuxwsp vs0, v2 ; CHECK-P8-NEXT: xvcvuxwsp vs0, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt: ; CHECK-P9-LABEL: test2elt:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xvcvuxwsp vs0, v2 ; CHECK-P9-NEXT: xvcvuxwsp vs0, v2
; CHECK-P9-NEXT: mfvsrld r3, vs0 ; CHECK-P9-NEXT: mfvsrld r3, vs0
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt: ; CHECK-BE-LABEL: test2elt:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xvcvuxwsp vs0, vs0 ; CHECK-BE-NEXT: xvcvuxwsp vs0, vs0
; CHECK-BE-NEXT: mfvsrd r3, f0 ; CHECK-BE-NEXT: mffprd r3, f0
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <2 x i32> %0 = bitcast i64 %a.coerce to <2 x i32>
%1 = uitofp <2 x i32> %0 to <2 x float> %1 = uitofp <2 x i32> %0 to <2 x float>
%2 = bitcast <2 x float> %1 to i64 %2 = bitcast <2 x float> %1 to i64
ret i64 %2 ret i64 %2
} }
▲ Show 20 Lines • Show All 111 Lines • ▼ Show 20 Linesentry:
%1 = uitofp <16 x i32> %a to <16 x float> %1 = uitofp <16 x i32> %a to <16 x float>
store <16 x float> %1, <16 x float>* %agg.result, align 64 store <16 x float> %1, <16 x float>* %agg.result, align 64
ret void ret void
} }
define i64 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 { define i64 @test2elt_signed(i64 %a.coerce) local_unnamed_addr #0 {
; CHECK-P8-LABEL: test2elt_signed: ; CHECK-P8-LABEL: test2elt_signed:
; CHECK-P8: # %bb.0: # %entry ; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtvsrd f0, r3 ; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: xxswapd v2, vs0 ; CHECK-P8-NEXT: xxswapd v2, vs0
; CHECK-P8-NEXT: xvcvsxwsp vs0, v2 ; CHECK-P8-NEXT: xvcvsxwsp vs0, v2
; CHECK-P8-NEXT: xxswapd vs0, vs0 ; CHECK-P8-NEXT: xxswapd vs0, vs0
; CHECK-P8-NEXT: mfvsrd r3, f0 ; CHECK-P8-NEXT: mffprd r3, f0
; CHECK-P8-NEXT: blr ; CHECK-P8-NEXT: blr
; ;
; CHECK-P9-LABEL: test2elt_signed: ; CHECK-P9-LABEL: test2elt_signed:
; CHECK-P9: # %bb.0: # %entry ; CHECK-P9: # %bb.0: # %entry
; CHECK-P9-NEXT: mtvsrd f0, r3 ; CHECK-P9-NEXT: mtfprd f0, r3
; CHECK-P9-NEXT: xxswapd v2, vs0 ; CHECK-P9-NEXT: xxswapd v2, vs0
; CHECK-P9-NEXT: xvcvsxwsp vs0, v2 ; CHECK-P9-NEXT: xvcvsxwsp vs0, v2
; CHECK-P9-NEXT: mfvsrld r3, vs0 ; CHECK-P9-NEXT: mfvsrld r3, vs0
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
; ;
; CHECK-BE-LABEL: test2elt_signed: ; CHECK-BE-LABEL: test2elt_signed:
; CHECK-BE: # %bb.0: # %entry ; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrd f0, r3 ; CHECK-BE-NEXT: mtfprd f0, r3
; CHECK-BE-NEXT: xvcvsxwsp vs0, vs0 ; CHECK-BE-NEXT: xvcvsxwsp vs0, vs0
; CHECK-BE-NEXT: mfvsrd r3, f0 ; CHECK-BE-NEXT: mffprd r3, f0
; CHECK-BE-NEXT: blr ; CHECK-BE-NEXT: blr
entry: entry:
%0 = bitcast i64 %a.coerce to <2 x i32> %0 = bitcast i64 %a.coerce to <2 x i32>
%1 = sitofp <2 x i32> %0 to <2 x float> %1 = sitofp <2 x i32> %0 to <2 x float>
%2 = bitcast <2 x float> %1 to i64 %2 = bitcast <2 x float> %1 to i64
ret i64 %2 ret i64 %2
} }
▲ Show 20 Lines • Show All 115 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/vsx.ll

Show First 20 Lines • Show All 2,431 Lines • ▼ Show 20 Lines
; CHECK-FISL-NEXT: addis r4, r2, .LCPI65_0@toc@ha ; CHECK-FISL-NEXT: addis r4, r2, .LCPI65_0@toc@ha
; CHECK-FISL-NEXT: addi r4, r4, .LCPI65_0@toc@l ; CHECK-FISL-NEXT: addi r4, r4, .LCPI65_0@toc@l
; CHECK-FISL-NEXT: lxvw4x v3, 0, r4 ; CHECK-FISL-NEXT: lxvw4x v3, 0, r4
; CHECK-FISL-NEXT: vadduwm v2, v2, v3 ; CHECK-FISL-NEXT: vadduwm v2, v2, v3
; CHECK-FISL-NEXT: blr ; CHECK-FISL-NEXT: blr
; ;
; CHECK-LE-LABEL: test80: ; CHECK-LE-LABEL: test80:
; CHECK-LE: # %bb.0: ; CHECK-LE: # %bb.0:
; CHECK-LE-NEXT: mtvsrd f0, r3 ; CHECK-LE-NEXT: mtfprd f0, r3
; CHECK-LE-NEXT: addis r4, r2, .LCPI65_0@toc@ha ; CHECK-LE-NEXT: addis r4, r2, .LCPI65_0@toc@ha
; CHECK-LE-NEXT: addi r3, r4, .LCPI65_0@toc@l ; CHECK-LE-NEXT: addi r3, r4, .LCPI65_0@toc@l
; CHECK-LE-NEXT: xxswapd vs0, vs0 ; CHECK-LE-NEXT: xxswapd vs0, vs0
; CHECK-LE-NEXT: lvx v3, 0, r3 ; CHECK-LE-NEXT: lvx v3, 0, r3
; CHECK-LE-NEXT: xxspltw v2, vs0, 3 ; CHECK-LE-NEXT: xxspltw v2, vs0, 3
; CHECK-LE-NEXT: vadduwm v2, v2, v3 ; CHECK-LE-NEXT: vadduwm v2, v2, v3
; CHECK-LE-NEXT: blr ; CHECK-LE-NEXT: blr
%b1 = insertelement <2 x i32> undef, i32 %v, i32 0 %b1 = insertelement <2 x i32> undef, i32 %v, i32 0
▲ Show 20 Lines • Show All 76 Lines • Show Last 20 Lines

llvm/test/CodeGen/PowerPC/xray-conditional-return.ll

; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s ; RUN: llc -filetype=asm -o - -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s
define void @Foo(i32 signext %a, i32 signext %b) #0 { define void @Foo(i32 signext %a, i32 signext %b) #0 {
; CHECK-LABEL: @Foo ; CHECK-LABEL: @Foo
; CHECK: cmpw [[CR:[0-9]+]] ; CHECK: cmpw
; CHECK-NEXT: ble [[CR]], [[LABEL:\.[a-zA-Z0-9]+]] ; CHECK-NEXT: ble 0, [[LABEL:\.[a-zA-Z0-9]+]]
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}: ; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}:
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: std 0 ; CHECK-NEXT: std 0
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: bl __xray_FunctionExit ; CHECK-NEXT: bl __xray_FunctionExit
; CHECK-NEXT: nop ; CHECK-NEXT: nop
Show All 19 Linesif.end:
br label %return br label %return
return: return:
ret void ret void
} }
define void @Foo2(i32 signext %a, i32 signext %b) #0 { define void @Foo2(i32 signext %a, i32 signext %b) #0 {
; CHECK-LABEL: @Foo2 ; CHECK-LABEL: @Foo2
; CHECK: cmpw [[CR:[0-9]+]] ; CHECK: cmpw
; CHECK-NEXT: bge [[CR]], [[LABEL:\.[a-zA-Z0-9]+]] ; CHECK-NEXT: bge 0, [[LABEL:\.[a-zA-Z0-9]+]]
steven.zhangUnsubmitted
Done
ReplyInline Actions

I don't see this change relative with alias.

steven.zhang: I don't see this change relative with alias.
ZhangKangAuthorUnsubmitted
Done
ReplyInline Actions

In fact, the old assembly is:

cmpw 0, R1, R2
beq 0, Target

The new assembly is:

cmpw R1, R2
beq 0, Target

Because cmpw R1, R2 has omit CR0, I must specify beq use the CR0.

In fact, the beq 0, Target should also omit CR0 to beq Target, but it's not this patch should do.

ZhangKang: In fact, the old assembly is: ``` cmpw 0, R1, R2 beq 0, Target ``` The new assembly is: ```…
; CHECK-NEXT: .p2align 3 ; CHECK-NEXT: .p2align 3
; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}: ; CHECK-NEXT: {{\.[a-zA-Z0-9]+}}:
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: std 0 ; CHECK-NEXT: std 0
; CHECK-NEXT: mflr 0 ; CHECK-NEXT: mflr 0
; CHECK-NEXT: bl __xray_FunctionExit ; CHECK-NEXT: bl __xray_FunctionExit
; CHECK-NEXT: nop ; CHECK-NEXT: nop
Show All 28 Lines