Fix for rL280668, Intel(R) Memory Protection Extensions (Intel(R) MPX) support.

[valentinagiusti]

Summary

Signed-off-by: Valentina Giusti <[e-mail]>

[labath]

I have a couple of questions I'd like to be answered before this goes in. Apart from the inline comments, all my questions from the previous version of this commit still stand.

packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile

5 ↗

(On Diff #70398)

This should not be necessary. Makefile.rules already correctly appends -m32 when needed. Maybe CFLAGS_EXTRAS would work instead (?)

packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py

297 ↗

(On Diff #70398)

Do we want to allow a register set with no name? It looks like the root of the problem is elsewhere.

[valentinagiusti]

Hi, inline there are my other replies.

packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile

5 ↗

(On Diff #70398)

Unfortunately it doesn't append -m32 to all the instances when also a linker is needed in the build process. In fact, in the test logs it shows that only the first call of the g++ command has such a flag, and therefore the inferior code build ends with an error.
If there is a better way to do the same with CFLAGS_EXTRAS please let me know!

packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py

297 ↗

(On Diff #70398)

These lines of code are just to detect if there are AVX or MPX register sets, so I don't think there is the need to do anything about nameless sets here. If you don't like this solution, I think an alternative is to just check if there are the register names that belong to one set or the other, it just takes a bit longer - or I could just look for the first register in the set.

[clayborg]

Just switch to using CFLAGS_EXTRAS and LD_EXTRAS and this is good to go.

packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile

6–11 ↗

(On Diff #70398)

It would be nice to not modify the CXXFLAGS or LDFLAGS directly. You should modify CFLAGS_EXTRAS and LD_EXTRAS. I am not sure if there is a CXXFLAGS_EXTRAS, but feel free to add it if you can't use CFLAGS_EXTRAS

[valentinagiusti]

Improved TestMPXRegisters.py and Makefile according to review.

[labath]

packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile

5 ↗

(On Diff #70398)

I don't see how that is possible. I just made the following test:

$ cat Makefile
LEVEL = ../../../make

CXX_SOURCES := main.cpp

CFLAGS_EXTRAS += -Wzero-as-null-pointer-constant

include $(LEVEL)/Makefile.rules
 $ make
g++  -std=c++11  -g -O0 -fno-builtin -m64  -Wzero-as-null-pointer-constant -I/usr/local/google/home/labath/ll/lldb/packages/Python/lldbsuite/test/make/../../../../../include -include /usr/local/google/home/labath/ll/lldb/packages/Python/lldbsuite/test/make/test_common.h  -c -o main.o main.cpp
g++  main.o -g -O0 -fno-builtin -m64  -Wzero-as-null-pointer-constant -I/usr/local/google/home/labath/ll/lldb/packages/Python/lldbsuite/test/make/../../../../../include -include /usr/local/google/home/labath/ll/lldb/packages/Python/lldbsuite/test/make/test_common.h    -o "a.out"
$ make ARCH=i386
g++  -std=c++11  -g -O0 -fno-builtin -m32  -Wzero-as-null-pointer-constant -I/usr/local/google/home/labath/ll/lldb/packages/Python/lldbsuite/test/make/../../../../../include -include /usr/local/google/home/labath/ll/lldb/packages/Python/lldbsuite/test/make/test_common.h  -c -o main.o main.cpp
g++  main.o -g -O0 -fno-builtin -m32  -Wzero-as-null-pointer-constant -I/usr/local/google/home/labath/ll/lldb/packages/Python/lldbsuite/test/make/../../../../../include -include /usr/local/google/home/labath/ll/lldb/packages/Python/lldbsuite/test/make/test_common.h    -o "a.out"

As you see CFLAGS_EXTRAS was added to both compiler and linker command lines for both 32-bit and 64-bit cases (so, setting LD_EXTRAS is not necessary). Also, Makefile.rules already correctly appended the correct -m32/64 switch to all compiler and linker executions (so, you should not need to set it yourself).

If this does not work for you, then we need to figure out why and fix it. I don't believe we should be adding complex rules to these Makefiles, as it increases the maintenance burden down the line.

packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py

297 ↗

(On Diff #70398)

I was referring to the addition of the if registerSet.GetName() pre-check. I know in the previous version of the commit this test failed here due to register set name being None. So this also implicitly checked that each register set has a name. Now, you've circumvented that check. This seems to be unnecessary because the test passes even when I remove that, so I think we should do that. I think it's a reasonable expectation that each register set has a name.

[valentinagiusti]

packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile

6 ↗

(On Diff #70507)

You are right, if I use CFLAGS_EXTRAS I don't have to check for the arch or use LD_EXTRAS. I wish I knew this from the beginning...

[labath]

I think we're approaching the end now. If you could upload the new version (you'll have to reformat the changes), I'll give it a final pass.

packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile

6 ↗

(On Diff #70507)

Yeah, I don't blame you. :) The test suite is not an easy thing to wrap your head around. I am sorry if some of my comments sounded a bit harsh.

[valentinagiusti]

Improved MPX test Makefile and removed workaround for unnamed register sets, and rebased according to the new coding style.

[valentinagiusti]

packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile

7 ↗

(On Diff #70695)

Np, thanks for the review and explanations ;)

[labath]

LGTM, thanks.

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/Makefile

-LEVEL = ../../make
-
-CXX_SOURCES := main.cpp a.cpp
-
-include $(LEVEL)/Makefile.rules

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/TestRegisters.py

-"""
-Test the 'register' command.
-"""
-
-from __future__ import print_function
-
-
-import os
-import sys
-import time
-import re
-import lldb
-from lldbsuite.test.decorators import *
-from lldbsuite.test.lldbtest import *
-from lldbsuite.test import lldbutil
-
-
-class RegisterCommandsTestCase(TestBase):
-
-    mydir = TestBase.compute_mydir(__file__)
-
-    def setUp(self):
-        TestBase.setUp(self)
-        self.has_teardown = False
-
-    def tearDown(self):
-        self.dbg.GetSelectedTarget().GetProcess().Destroy()
-        TestBase.tearDown(self)
-
-    @skipIfiOSSimulator
-    @skipIf(archs=no_match(['amd64', 'arm', 'i386', 'x86_64']))
-    def test_register_commands(self):
-        """Test commands related to registers, in particular vector registers."""
-        self.build()
-        self.common_setup()
-
-        # verify that logging does not assert
-        self.log_enable("registers")
-
-        self.expect("register read -a", MISSING_EXPECTED_REGISTERS,
-                    substrs=['registers were unavailable'], matching=False)
-
-        if self.getArchitecture() in ['amd64', 'i386', 'x86_64']:
-            self.runCmd("register read xmm0")
-            self.runCmd("register read ymm15")  # may be available
-        elif self.getArchitecture() in ['arm']:
-            self.runCmd("register read s0")
-            self.runCmd("register read q15")  # may be available
-
-        self.expect(
-            "register read -s 3",
-            substrs=['invalid register set index: 3'],
-            error=True)
-
-    @skipIfiOSSimulator
-    # Writing of mxcsr register fails, presumably due to a kernel/hardware
-    # problem
-    @skipIfTargetAndroid(archs=["i386"])
-    @skipIf(archs=no_match(['amd64', 'arm', 'i386', 'x86_64']))
-    def test_fp_register_write(self):
-        """Test commands that write to registers, in particular floating-point registers."""
-        self.build()
-        self.fp_register_write()
-
-    @skipIfiOSSimulator
-    # "register read fstat" always return 0xffff
-    @expectedFailureAndroid(archs=["i386"])
-    @skipIfFreeBSD  # llvm.org/pr25057
-    @skipIf(archs=no_match(['amd64', 'i386', 'x86_64']))
-    def test_fp_special_purpose_register_read(self):
-        """Test commands that read fpu special purpose registers."""
-        self.build()
-        self.fp_special_purpose_register_read()
-
-    @skipIfiOSSimulator
-    @skipIf(archs=no_match(['amd64', 'arm', 'i386', 'x86_64']))
-    def test_register_expressions(self):
-        """Test expression evaluation with commands related to registers."""
-        self.build()
-        self.common_setup()
-
-        if self.getArchitecture() in ['amd64', 'i386', 'x86_64']:
-            gpr = "eax"
-            vector = "xmm0"
-        elif self.getArchitecture() in ['arm']:
-            gpr = "r0"
-            vector = "q0"
-
-        self.expect("expr/x $%s" % gpr, substrs=['unsigned int', ' = 0x'])
-        self.expect("expr $%s" % vector, substrs=['vector_type'])
-        self.expect(
-            "expr (unsigned int)$%s[0]" %
-            vector, substrs=['unsigned int'])
-
-        if self.getArchitecture() in ['amd64', 'x86_64']:
-            self.expect(
-                "expr -- ($rax & 0xffffffff) == $eax",
-                substrs=['true'])
-
-    @skipIfiOSSimulator
-    @skipIf(archs=no_match(['amd64', 'x86_64']))
-    def test_convenience_registers(self):
-        """Test convenience registers."""
-        self.build()
-        self.convenience_registers()
-
-    @skipIfiOSSimulator
-    @skipIf(archs=no_match(['amd64', 'x86_64']))
-    def test_convenience_registers_with_process_attach(self):
-        """Test convenience registers after a 'process attach'."""
-        self.build()
-        self.convenience_registers_with_process_attach(test_16bit_regs=False)
-
-    @skipIfiOSSimulator
-    @skipIf(archs=no_match(['amd64', 'x86_64']))
-    def test_convenience_registers_16bit_with_process_attach(self):
-        """Test convenience registers after a 'process attach'."""
-        self.build()
-        self.convenience_registers_with_process_attach(test_16bit_regs=True)
-
-    def common_setup(self):
-        exe = os.path.join(os.getcwd(), "a.out")
-
-        self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET)
-
-        # Break in main().
-        lldbutil.run_break_set_by_symbol(
-            self, "main", num_expected_locations=-1)
-
-        self.runCmd("run", RUN_SUCCEEDED)
-
-        # The stop reason of the thread should be breakpoint.
-        self.expect("thread list", STOPPED_DUE_TO_BREAKPOINT,
-                    substrs=['stopped', 'stop reason = breakpoint'])
-
-    # platform specific logging of the specified category
-    def log_enable(self, category):
-        # This intentionally checks the host platform rather than the target
-        # platform as logging is host side.
-        self.platform = ""
-        if sys.platform.startswith("darwin"):
-            self.platform = ""  # TODO: add support for "log enable darwin registers"
-
-        if sys.platform.startswith("freebsd"):
-            self.platform = "freebsd"
-
-        if sys.platform.startswith("linux"):
-            self.platform = "linux"
-
-        if sys.platform.startswith("netbsd"):
-            self.platform = "netbsd"
-
-        if self.platform != "":
-            self.log_file = os.path.join(os.getcwd(), 'TestRegisters.log')
-            self.runCmd(
-                "log enable " +
-                self.platform +
-                " " +
-                str(category) +
-                " registers -v -f " +
-                self.log_file,
-                RUN_SUCCEEDED)
-            if not self.has_teardown:
-                def remove_log(self):
-                    if os.path.exists(self.log_file):
-                        os.remove(self.log_file)
-                self.has_teardown = True
-                self.addTearDownHook(remove_log)
-
-    def write_and_read(self, frame, register, new_value, must_exist=True):
-        value = frame.FindValue(register, lldb.eValueTypeRegister)
-        if must_exist:
-            self.assertTrue(
-                value.IsValid(),
-                "finding a value for register " +
-                register)
-        elif not value.IsValid():
-            return  # If register doesn't exist, skip this test
-
-        self.runCmd("register write " + register + " \'" + new_value + "\'")
-        self.expect(
-            "register read " +
-            register,
-            substrs=[
-                register +
-                ' = ',
-                new_value])
-
-    def fp_special_purpose_register_read(self):
-        exe = os.path.join(os.getcwd(), "a.out")
-
-        # Create a target by the debugger.
-        target = self.dbg.CreateTarget(exe)
-        self.assertTrue(target, VALID_TARGET)
-
-        # Launch the process and stop.
-        self.expect("run", PROCESS_STOPPED, substrs=['stopped'])
-
-        # Check stop reason; Should be either signal SIGTRAP or EXC_BREAKPOINT
-        output = self.res.GetOutput()
-        matched = False
-        substrs = [
-            'stop reason = EXC_BREAKPOINT',
-            'stop reason = signal SIGTRAP']
-        for str1 in substrs:
-            matched = output.find(str1) != -1
-            with recording(self, False) as sbuf:
-                print("%s sub string: %s" % ('Expecting', str1), file=sbuf)
-                print("Matched" if matched else "Not Matched", file=sbuf)
-            if matched:
-                break
-        self.assertTrue(matched, STOPPED_DUE_TO_SIGNAL)
-
-        process = target.GetProcess()
-        self.assertTrue(process.GetState() == lldb.eStateStopped,
-                        PROCESS_STOPPED)
-
-        thread = process.GetThreadAtIndex(0)
-        self.assertTrue(thread.IsValid(), "current thread is valid")
-
-        currentFrame = thread.GetFrameAtIndex(0)
-        self.assertTrue(currentFrame.IsValid(), "current frame is valid")
-
-        # Extract the value of fstat and ftag flag at the point just before
-        # we start pushing floating point values on st% register stack
-        value = currentFrame.FindValue("fstat", lldb.eValueTypeRegister)
-        error = lldb.SBError()
-        reg_value_fstat_initial = value.GetValueAsUnsigned(error, 0)
-
-        self.assertTrue(error.Success(), "reading a value for fstat")
-        value = currentFrame.FindValue("ftag", lldb.eValueTypeRegister)
-        error = lldb.SBError()
-        reg_value_ftag_initial = value.GetValueAsUnsigned(error, 0)
-
-        self.assertTrue(error.Success(), "reading a value for ftag")
-        fstat_top_pointer_initial = (reg_value_fstat_initial & 0x3800) >> 11
-
-        # Execute 'si' aka 'thread step-inst' instruction 5 times and with
-        # every execution verify the value of fstat and ftag registers
-        for x in range(0, 5):
-            # step into the next instruction to push a value on 'st' register
-            # stack
-            self.runCmd("si", RUN_SUCCEEDED)
-
-            # Verify fstat and save it to be used for verification in next
-            # execution of 'si' command
-            if not (reg_value_fstat_initial & 0x3800):
-                self.expect("register read fstat", substrs=[
-                            'fstat' + ' = ', str("0x%0.4x" % ((reg_value_fstat_initial & ~(0x3800)) | 0x3800))])
-                reg_value_fstat_initial = (
-                    (reg_value_fstat_initial & ~(0x3800)) | 0x3800)
-                fstat_top_pointer_initial = 7
-            else:
-                self.expect("register read fstat", substrs=[
-                            'fstat' + ' = ', str("0x%0.4x" % (reg_value_fstat_initial - 0x0800))])
-                reg_value_fstat_initial = (reg_value_fstat_initial - 0x0800)
-                fstat_top_pointer_initial -= 1
-
-            # Verify ftag and save it to be used for verification in next
-            # execution of 'si' command
-            self.expect(
-                "register read ftag", substrs=[
-                    'ftag' + ' = ', str(
-                        "0x%0.2x" %
-                        (reg_value_ftag_initial | (
-                            1 << fstat_top_pointer_initial)))])
-            reg_value_ftag_initial = reg_value_ftag_initial | (
-                1 << fstat_top_pointer_initial)
-
-    def fp_register_write(self):
-        exe = os.path.join(os.getcwd(), "a.out")
-
-        # Create a target by the debugger.
-        target = self.dbg.CreateTarget(exe)
-        self.assertTrue(target, VALID_TARGET)
-
-        lldbutil.run_break_set_by_symbol(
-            self, "main", num_expected_locations=-1)
-
-        # Launch the process, and do not stop at the entry point.
-        process = target.LaunchSimple(
-            None, None, self.get_process_working_directory())
-
-        process = target.GetProcess()
-        self.assertTrue(
-            process.GetState() == lldb.eStateStopped,
-            PROCESS_STOPPED)
-
-        thread = process.GetThreadAtIndex(0)
-        self.assertTrue(thread.IsValid(), "current thread is valid")
-
-        currentFrame = thread.GetFrameAtIndex(0)
-        self.assertTrue(currentFrame.IsValid(), "current frame is valid")
-
-        if self.getArchitecture() in ['amd64', 'i386', 'x86_64']:
-            reg_list = [
-                # reg          value        must-have
-                ("fcw", "0x0000ff0e", False),
-                ("fsw", "0x0000ff0e", False),
-                ("ftw", "0x0000ff0e", False),
-                ("ip", "0x0000ff0e", False),
-                ("dp", "0x0000ff0e", False),
-                ("mxcsr", "0x0000ff0e", False),
-                ("mxcsrmask", "0x0000ff0e", False),
-            ]
-
-            st0regname = None
-            if currentFrame.FindRegister("st0").IsValid():
-                st0regname = "st0"
-            elif currentFrame.FindRegister("stmm0").IsValid():
-                st0regname = "stmm0"
-            if st0regname is not None:
-                # reg          value
-                # must-have
-                reg_list.append(
-                    (st0regname, "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00}", True))
-                reg_list.append(
-                    ("xmm0",
-                     "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x2f 0x2f}",
-                     True))
-                reg_list.append(
-                    ("xmm15",
-                     "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f}",
-                     False))
-        elif self.getArchitecture() in ['arm']:
-            reg_list = [
-                # reg      value
-                # must-have
-                ("fpscr", "0xfbf79f9f", True),
-                ("s0", "1.25", True),
-                ("s31", "0.75", True),
-                ("d1", "123", True),
-                ("d17", "987", False),
-                ("q1", "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x2f 0x2f}", True),
-                ("q14",
-                 "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f}",
-                 False),
-            ]
-
-        for (reg, val, must) in reg_list:
-            self.write_and_read(currentFrame, reg, val, must)
-
-        if self.getArchitecture() in ['amd64', 'i386', 'x86_64']:
-            self.runCmd(
-                "register write " +
-                st0regname +
-                " \"{0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}\"")
-            self.expect(
-                "register read " +
-                st0regname +
-                " --format f",
-                substrs=[
-                    st0regname +
-                    ' = 0'])
-
-            has_avx = False
-            # Returns an SBValueList.
-            registerSets = currentFrame.GetRegisters()
-            for registerSet in registerSets:
-                if 'advanced vector extensions' in registerSet.GetName().lower():
-                    has_avx = True
-                    break
-
-            if has_avx:
-                new_value = "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0c 0x0d 0x0e 0x0f}"
-                self.write_and_read(currentFrame, "ymm0", new_value)
-                self.write_and_read(currentFrame, "ymm7", new_value)
-                self.expect("expr $ymm0", substrs=['vector_type'])
-            else:
-                self.runCmd("register read ymm0")
-
-    def convenience_registers(self):
-        """Test convenience registers."""
-        self.common_setup()
-
-        # The command "register read -a" does output a derived register like
-        # eax...
-        self.expect("register read -a", matching=True,
-                    substrs=['eax'])
-
-        # ...however, the vanilla "register read" command should not output derived registers like eax.
-        self.expect("register read", matching=False,
-                    substrs=['eax'])
-
-        # Test reading of rax and eax.
-        self.expect("register read rax eax",
-                    substrs=['rax = 0x', 'eax = 0x'])
-
-        # Now write rax with a unique bit pattern and test that eax indeed
-        # represents the lower half of rax.
-        self.runCmd("register write rax 0x1234567887654321")
-        self.expect("register read rax 0x1234567887654321",
-                    substrs=['0x1234567887654321'])
-
-    def convenience_registers_with_process_attach(self, test_16bit_regs):
-        """Test convenience registers after a 'process attach'."""
-        exe = os.path.join(os.getcwd(), "a.out")
-
-        # Spawn a new process
-        pid = self.spawnSubprocess(exe, ['wait_for_attach']).pid
-        self.addTearDownHook(self.cleanupSubprocesses)
-
-        if self.TraceOn():
-            print("pid of spawned process: %d" % pid)
-
-        self.runCmd("process attach -p %d" % pid)
-
-        # Check that "register read eax" works.
-        self.runCmd("register read eax")
-
-        if self.getArchitecture() in ['amd64', 'x86_64']:
-            self.expect("expr -- ($rax & 0xffffffff) == $eax",
-                        substrs=['true'])
-
-        if test_16bit_regs:
-            self.expect("expr -- $ax == (($ah << 8) | $al)",
-                        substrs=['true'])

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/a.cpp

-//===-- a.cpp ------------------------------------------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-#include <stdio.h>
-
-long double
-return_long_double (long double value)
-{
-#if defined (__i386__) || defined (__x86_64__)
-    float a=2, b=4,c=8, d=16, e=32, f=64, k=128, l=256, add=0;
-    __asm__ (
-        "int3 ;"
-        "flds %1 ;"
-        "flds %2 ;"
-        "flds %3 ;"
-        "flds %4 ;"
-        "flds %5 ;"
-        "flds %6 ;"
-        "flds %7 ;"
-        "faddp ;" : "=g" (add) : "g" (a), "g" (b), "g" (c), "g" (d), "g" (e), "g" (f), "g" (k), "g" (l) );  // Set break point at this line.
-#endif    // #if defined (__i386__) || defined (__x86_64__)
-    return value;
-}
-
-long double
-outer_return_long_double (long double value)
-{
-    long double val = return_long_double(value);
-    val *= 2 ;
-    return val;
-}
-
-long double
-outermost_return_long_double (long double value)
-{
-    long double val = outer_return_long_double(value);
-    val *= 2 ;
-    return val;
-}

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/Makefile

+LEVEL = ../../../make
+
+CXX_SOURCES := main.cpp
+
+CFLAGS_EXTRAS += -mmpx -fcheck-pointer-bounds -fuse-ld=bfd
+
+include $(LEVEL)/Makefile.rules

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/TestMPXRegisters.py

+"""
+Test the MPX registers.
+"""
+
+from __future__ import print_function
+
+
+import os
+import sys
+import time
+import re
+import lldb
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+
+
+class RegisterCommandsTestCase(TestBase):
+
+    mydir = TestBase.compute_mydir(__file__)
+
+    def setUp(self):
+        TestBase.setUp(self)
+        self.has_teardown = False
+
+    def tearDown(self):
+        self.dbg.GetSelectedTarget().GetProcess().Destroy()
+        TestBase.tearDown(self)
+
+    @skipIf(compiler="clang")
+    @skipIf(oslist=["linux"], compiler="gcc", compiler_version=["<", "5"]) #GCC version >= 5 supports MPX.
+    @skipIf(oslist=no_match(['linux']))
+    @skipIf(archs=no_match(['i386', 'x86_64']))
+    def test_mpx_registers_with_example_code(self):
+        """Test MPX registers with example code."""
+        self.build()
+        self.mpx_registers_with_example_code()
+
+    def mpx_registers_with_example_code(self):
+        """Test MPX registers after running example code."""
+        self.line = line_number('main.cpp', '// Set a break point here.')
+
+        exe = os.path.join(os.getcwd(), "a.out")
+        self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET)
+
+        lldbutil.run_break_set_by_file_and_line(self, "main.cpp", self.line, num_expected_locations=1)
+        self.runCmd("run", RUN_SUCCEEDED)
+
+        target = self.dbg.GetSelectedTarget()
+        process = target.GetProcess()
+
+        if (process.GetState() == lldb.eStateExited):
+            self.skipTest("HW doesn't support MPX feature.")
+        else:
+            self.expect("thread backtrace", STOPPED_DUE_TO_BREAKPOINT,
+                        substrs = ["stop reason = breakpoint 1."])
+
+        if self.getArchitecture() == 'x86_64':
+            self.expect("register read -s 3",
+                        substrs = ['bnd0 = {0x0000000000000010 0xffffffffffffffe6}',
+                                   'bnd1 = {0x0000000000000020 0xffffffffffffffd6}',
+                                   'bnd2 = {0x0000000000000030 0xffffffffffffffc6}',
+                                   'bnd3 = {0x0000000000000040 0xffffffffffffffb6}',
+                                   'bndcfgu = {0x01 0x80 0xb5 0x76 0xff 0x7f 0x00 0x00}',
+                                   'bndstatus = {0x02 0x80 0xb5 0x76 0xff 0x7f 0x00 0x00}'])
+        if self.getArchitecture() == 'i386':
+            self.expect("register read -s 3",
+                        substrs = ['bnd0 = {0x0000000000000010 0x00000000ffffffe6}',
+                                   'bnd1 = {0x0000000000000020 0x00000000ffffffd6}',
+                                   'bnd2 = {0x0000000000000030 0x00000000ffffffc6}',
+                                   'bnd3 = {0x0000000000000040 0x00000000ffffffb6}',
+                                   'bndcfgu = {0x01 0xd0 0x7d 0xf7 0x00 0x00 0x00 0x00}',
+                                   'bndstatus = {0x02 0xd0 0x7d 0xf7 0x00 0x00 0x00 0x00}'])
+

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/intel_xtended_registers/main.cpp

+//===-- main.cpp ------------------------------------------------*- C++ -*-===//
+////
+////                     The LLVM Compiler Infrastructure
+////
+//// This file is distributed under the University of Illinois Open Source
+//// License. See LICENSE.TXT for details.
+////
+////===----------------------------------------------------------------------===//
+//
+
+#include <cpuid.h>
+#include <cstddef>
+
+int
+main(int argc, char const *argv[])
+{
+    unsigned int rax, rbx, rcx, rdx;
+
+    // Check if XSAVE is enabled.
+    if (!__get_cpuid(1, &rax, &rbx, &rcx, &rdx) || (rcx & bit_OSXSAVE) != bit_OSXSAVE)
+        return -1;
+
+    // Check if MPX is enabled.
+    if (__get_cpuid_max(0, NULL) > 7)
+    {
+        __cpuid_count(7, 0, rax, rbx, rcx, rdx);
+        if ((rbx & bit_MPX) != bit_MPX)
+            return -1;
+    }
+    else
+        return -1;
+
+// Run MPX test code.
+#if defined(__x86_64__)
+    asm("mov $16, %rax\n\t"
+        "mov $9, %rdx\n\t"
+        "bndmk (%rax,%rdx), %bnd0\n\t"
+        "mov $32, %rax\n\t"
+        "mov $9, %rdx\n\t"
+        "bndmk (%rax,%rdx), %bnd1\n\t"
+        "mov $48, %rax\n\t"
+        "mov $9, %rdx\n\t"
+        "bndmk (%rax,%rdx), %bnd2\n\t"
+        "mov $64, %rax\n\t"
+        "mov $9, %rdx\n\t"
+        "bndmk (%rax,%rdx), %bnd3\n\t"
+        "bndstx %bnd3, (%rax) \n\t"
+        "nop\n\t");
+#endif
+#if defined(__i386__)
+    asm("mov $16, %eax\n\t"
+        "mov $9, %edx\n\t"
+        "bndmk (%eax,%edx), %bnd0\n\t"
+        "mov $32, %eax\n\t"
+        "mov $9, %edx\n\t"
+        "bndmk (%eax,%edx), %bnd1\n\t"
+        "mov $48, %eax\n\t"
+        "mov $9, %edx\n\t"
+        "bndmk (%eax,%edx), %bnd2\n\t"
+        "mov $64, %eax\n\t"
+        "mov $9, %edx\n\t"
+        "bndmk (%eax,%edx), %bnd3\n\t"
+        "bndstx  %bnd3, (%eax)\n\t"
+        "nop\n\t");
+#endif
+    asm("nop\n\t"); // Set a break point here.
+
+    return 0;
+}

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/main.cpp

-//===-- main.cpp ------------------------------------------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-#include <stdio.h>
-
-#include <chrono>
-#include <thread>
-
-long double outermost_return_long_double (long double my_long_double);
-
-int main (int argc, char const *argv[])
-{
-    lldb_enable_attach();
-
-    char my_string[] = {'a', 'b', 'c', 'd', 'e', 'f', 'g', 0};
-    double my_double = 1234.5678;
-    long double my_long_double = 1234.5678;
-
-    // For simplicity assume that any cmdline argument means wait for attach.
-    if (argc > 1)
-    {
-        volatile int wait_for_attach=1;
-        while (wait_for_attach)
-            std::this_thread::sleep_for(std::chrono::microseconds(1));
-    }
-
-    printf("my_string=%s\n", my_string);
-    printf("my_double=%g\n", my_double);
-    outermost_return_long_double (my_long_double);
-    return 0;
-}

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/Makefile

+LEVEL = ../../../make
+
+CXX_SOURCES := main.cpp a.cpp
+
+include $(LEVEL)/Makefile.rules

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/TestRegisters.py

+"""
+Test the 'register' command.
+"""
+
+from __future__ import print_function
+
+
+import os
+import sys
+import time
+import re
+import lldb
+from lldbsuite.test.decorators import *
+from lldbsuite.test.lldbtest import *
+from lldbsuite.test import lldbutil
+
+
+class RegisterCommandsTestCase(TestBase):
+
+    mydir = TestBase.compute_mydir(__file__)
+
+    def setUp(self):
+        TestBase.setUp(self)
+        self.has_teardown = False
+
+    def tearDown(self):
+        self.dbg.GetSelectedTarget().GetProcess().Destroy()
+        TestBase.tearDown(self)
+
+    @skipIfiOSSimulator
+    @skipIf(archs=no_match(['amd64', 'arm', 'i386', 'x86_64']))
+    def test_register_commands(self):
+        """Test commands related to registers, in particular vector registers."""
+        self.build()
+        self.common_setup()
+
+        # verify that logging does not assert
+        self.log_enable("registers")
+
+        self.expect("register read -a", MISSING_EXPECTED_REGISTERS,
+                    substrs=['registers were unavailable'], matching=False)
+
+        if self.getArchitecture() in ['amd64', 'i386', 'x86_64']:
+            self.runCmd("register read xmm0")
+            self.runCmd("register read ymm15")  # may be available
+            self.runCmd("register read bnd0")  # may be available
+        elif self.getArchitecture() in ['arm']:
+            self.runCmd("register read s0")
+            self.runCmd("register read q15")  # may be available
+
+        self.expect(
+            "register read -s 4",
+            substrs=['invalid register set index: 4'],
+            error=True)
+
+    @skipIfiOSSimulator
+    # Writing of mxcsr register fails, presumably due to a kernel/hardware
+    # problem
+    @skipIfTargetAndroid(archs=["i386"])
+    @skipIf(archs=no_match(['amd64', 'arm', 'i386', 'x86_64']))
+    def test_fp_register_write(self):
+        """Test commands that write to registers, in particular floating-point registers."""
+        self.build()
+        self.fp_register_write()
+
+    @skipIfiOSSimulator
+    # "register read fstat" always return 0xffff
+    @expectedFailureAndroid(archs=["i386"])
+    @skipIfFreeBSD  # llvm.org/pr25057
+    @skipIf(archs=no_match(['amd64', 'i386', 'x86_64']))
+    def test_fp_special_purpose_register_read(self):
+        """Test commands that read fpu special purpose registers."""
+        self.build()
+        self.fp_special_purpose_register_read()
+
+    @skipIfiOSSimulator
+    @skipIf(archs=no_match(['amd64', 'arm', 'i386', 'x86_64']))
+    def test_register_expressions(self):
+        """Test expression evaluation with commands related to registers."""
+        self.build()
+        self.common_setup()
+
+        if self.getArchitecture() in ['amd64', 'i386', 'x86_64']:
+            gpr = "eax"
+            vector = "xmm0"
+        elif self.getArchitecture() in ['arm']:
+            gpr = "r0"
+            vector = "q0"
+
+        self.expect("expr/x $%s" % gpr, substrs=['unsigned int', ' = 0x'])
+        self.expect("expr $%s" % vector, substrs=['vector_type'])
+        self.expect(
+            "expr (unsigned int)$%s[0]" %
+            vector, substrs=['unsigned int'])
+
+        if self.getArchitecture() in ['amd64', 'x86_64']:
+            self.expect(
+                "expr -- ($rax & 0xffffffff) == $eax",
+                substrs=['true'])
+
+    @skipIfiOSSimulator
+    @skipIf(archs=no_match(['amd64', 'x86_64']))
+    def test_convenience_registers(self):
+        """Test convenience registers."""
+        self.build()
+        self.convenience_registers()
+
+    @skipIfiOSSimulator
+    @skipIf(archs=no_match(['amd64', 'x86_64']))
+    def test_convenience_registers_with_process_attach(self):
+        """Test convenience registers after a 'process attach'."""
+        self.build()
+        self.convenience_registers_with_process_attach(test_16bit_regs=False)
+
+    @skipIfiOSSimulator
+    @skipIf(archs=no_match(['amd64', 'x86_64']))
+    def test_convenience_registers_16bit_with_process_attach(self):
+        """Test convenience registers after a 'process attach'."""
+        self.build()
+        self.convenience_registers_with_process_attach(test_16bit_regs=True)
+
+    def common_setup(self):
+        exe = os.path.join(os.getcwd(), "a.out")
+
+        self.runCmd("file " + exe, CURRENT_EXECUTABLE_SET)
+
+        # Break in main().
+        lldbutil.run_break_set_by_symbol(
+            self, "main", num_expected_locations=-1)
+
+        self.runCmd("run", RUN_SUCCEEDED)
+
+        # The stop reason of the thread should be breakpoint.
+        self.expect("thread list", STOPPED_DUE_TO_BREAKPOINT,
+                    substrs=['stopped', 'stop reason = breakpoint'])
+
+    # platform specific logging of the specified category
+    def log_enable(self, category):
+        # This intentionally checks the host platform rather than the target
+        # platform as logging is host side.
+        self.platform = ""
+        if sys.platform.startswith("darwin"):
+            self.platform = ""  # TODO: add support for "log enable darwin registers"
+
+        if sys.platform.startswith("freebsd"):
+            self.platform = "freebsd"
+
+        if sys.platform.startswith("linux"):
+            self.platform = "linux"
+
+        if sys.platform.startswith("netbsd"):
+            self.platform = "netbsd"
+
+        if self.platform != "":
+            self.log_file = os.path.join(os.getcwd(), 'TestRegisters.log')
+            self.runCmd(
+                "log enable " +
+                self.platform +
+                " " +
+                str(category) +
+                " registers -v -f " +
+                self.log_file,
+                RUN_SUCCEEDED)
+            if not self.has_teardown:
+                def remove_log(self):
+                    if os.path.exists(self.log_file):
+                        os.remove(self.log_file)
+                self.has_teardown = True
+                self.addTearDownHook(remove_log)
+
+    def write_and_read(self, frame, register, new_value, must_exist=True):
+        value = frame.FindValue(register, lldb.eValueTypeRegister)
+        if must_exist:
+            self.assertTrue(
+                value.IsValid(),
+                "finding a value for register " +
+                register)
+        elif not value.IsValid():
+            return  # If register doesn't exist, skip this test
+
+        self.runCmd("register write " + register + " \'" + new_value + "\'")
+        self.expect(
+            "register read " +
+            register,
+            substrs=[
+                register +
+                ' = ',
+                new_value])
+
+    def fp_special_purpose_register_read(self):
+        exe = os.path.join(os.getcwd(), "a.out")
+
+        # Create a target by the debugger.
+        target = self.dbg.CreateTarget(exe)
+        self.assertTrue(target, VALID_TARGET)
+
+        # Launch the process and stop.
+        self.expect("run", PROCESS_STOPPED, substrs=['stopped'])
+
+        # Check stop reason; Should be either signal SIGTRAP or EXC_BREAKPOINT
+        output = self.res.GetOutput()
+        matched = False
+        substrs = [
+            'stop reason = EXC_BREAKPOINT',
+            'stop reason = signal SIGTRAP']
+        for str1 in substrs:
+            matched = output.find(str1) != -1
+            with recording(self, False) as sbuf:
+                print("%s sub string: %s" % ('Expecting', str1), file=sbuf)
+                print("Matched" if matched else "Not Matched", file=sbuf)
+            if matched:
+                break
+        self.assertTrue(matched, STOPPED_DUE_TO_SIGNAL)
+
+        process = target.GetProcess()
+        self.assertTrue(process.GetState() == lldb.eStateStopped,
+                        PROCESS_STOPPED)
+
+        thread = process.GetThreadAtIndex(0)
+        self.assertTrue(thread.IsValid(), "current thread is valid")
+
+        currentFrame = thread.GetFrameAtIndex(0)
+        self.assertTrue(currentFrame.IsValid(), "current frame is valid")
+
+        # Extract the value of fstat and ftag flag at the point just before
+        # we start pushing floating point values on st% register stack
+        value = currentFrame.FindValue("fstat", lldb.eValueTypeRegister)
+        error = lldb.SBError()
+        reg_value_fstat_initial = value.GetValueAsUnsigned(error, 0)
+
+        self.assertTrue(error.Success(), "reading a value for fstat")
+        value = currentFrame.FindValue("ftag", lldb.eValueTypeRegister)
+        error = lldb.SBError()
+        reg_value_ftag_initial = value.GetValueAsUnsigned(error, 0)
+
+        self.assertTrue(error.Success(), "reading a value for ftag")
+        fstat_top_pointer_initial = (reg_value_fstat_initial & 0x3800) >> 11
+
+        # Execute 'si' aka 'thread step-inst' instruction 5 times and with
+        # every execution verify the value of fstat and ftag registers
+        for x in range(0, 5):
+            # step into the next instruction to push a value on 'st' register
+            # stack
+            self.runCmd("si", RUN_SUCCEEDED)
+
+            # Verify fstat and save it to be used for verification in next
+            # execution of 'si' command
+            if not (reg_value_fstat_initial & 0x3800):
+                self.expect("register read fstat", substrs=[
+                            'fstat' + ' = ', str("0x%0.4x" % ((reg_value_fstat_initial & ~(0x3800)) | 0x3800))])
+                reg_value_fstat_initial = (
+                    (reg_value_fstat_initial & ~(0x3800)) | 0x3800)
+                fstat_top_pointer_initial = 7
+            else:
+                self.expect("register read fstat", substrs=[
+                            'fstat' + ' = ', str("0x%0.4x" % (reg_value_fstat_initial - 0x0800))])
+                reg_value_fstat_initial = (reg_value_fstat_initial - 0x0800)
+                fstat_top_pointer_initial -= 1
+
+            # Verify ftag and save it to be used for verification in next
+            # execution of 'si' command
+            self.expect(
+                "register read ftag", substrs=[
+                    'ftag' + ' = ', str(
+                        "0x%0.2x" %
+                        (reg_value_ftag_initial | (
+                            1 << fstat_top_pointer_initial)))])
+            reg_value_ftag_initial = reg_value_ftag_initial | (
+                1 << fstat_top_pointer_initial)
+
+    def fp_register_write(self):
+        exe = os.path.join(os.getcwd(), "a.out")
+
+        # Create a target by the debugger.
+        target = self.dbg.CreateTarget(exe)
+        self.assertTrue(target, VALID_TARGET)
+
+        lldbutil.run_break_set_by_symbol(
+            self, "main", num_expected_locations=-1)
+
+        # Launch the process, and do not stop at the entry point.
+        process = target.LaunchSimple(
+            None, None, self.get_process_working_directory())
+
+        process = target.GetProcess()
+        self.assertTrue(
+            process.GetState() == lldb.eStateStopped,
+            PROCESS_STOPPED)
+
+        thread = process.GetThreadAtIndex(0)
+        self.assertTrue(thread.IsValid(), "current thread is valid")
+
+        currentFrame = thread.GetFrameAtIndex(0)
+        self.assertTrue(currentFrame.IsValid(), "current frame is valid")
+
+        if self.getArchitecture() in ['amd64', 'i386', 'x86_64']:
+            reg_list = [
+                # reg          value        must-have
+                ("fcw", "0x0000ff0e", False),
+                ("fsw", "0x0000ff0e", False),
+                ("ftw", "0x0000ff0e", False),
+                ("ip", "0x0000ff0e", False),
+                ("dp", "0x0000ff0e", False),
+                ("mxcsr", "0x0000ff0e", False),
+                ("mxcsrmask", "0x0000ff0e", False),
+            ]
+
+            st0regname = None
+            if currentFrame.FindRegister("st0").IsValid():
+                st0regname = "st0"
+            elif currentFrame.FindRegister("stmm0").IsValid():
+                st0regname = "stmm0"
+            if st0regname is not None:
+                # reg          value
+                # must-have
+                reg_list.append(
+                    (st0regname, "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00}", True))
+                reg_list.append(
+                    ("xmm0",
+                     "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x2f 0x2f}",
+                     True))
+                reg_list.append(
+                    ("xmm15",
+                     "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f}",
+                     False))
+        elif self.getArchitecture() in ['arm']:
+            reg_list = [
+                # reg      value
+                # must-have
+                ("fpscr", "0xfbf79f9f", True),
+                ("s0", "1.25", True),
+                ("s31", "0.75", True),
+                ("d1", "123", True),
+                ("d17", "987", False),
+                ("q1", "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x2f 0x2f}", True),
+                ("q14",
+                 "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f}",
+                 False),
+            ]
+
+        for (reg, val, must) in reg_list:
+            self.write_and_read(currentFrame, reg, val, must)
+
+        if self.getArchitecture() in ['amd64', 'i386', 'x86_64']:
+            self.runCmd(
+                "register write " +
+                st0regname +
+                " \"{0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00}\"")
+            self.expect(
+                "register read " +
+                st0regname +
+                " --format f",
+                substrs=[
+                    st0regname +
+                    ' = 0'])
+
+            has_avx = False
+            has_mpx = False
+            # Returns an SBValueList.
+            registerSets = currentFrame.GetRegisters()
+            for registerSet in registerSets:
+                if 'advanced vector extensions' in registerSet.GetName().lower():
+                    has_avx = True
+                if 'memory protection extension' in registerSet.GetName().lower():
+                    has_mpx = True
+
+            if has_avx:
+                new_value = "{0x01 0x02 0x03 0x00 0x00 0x00 0x00 0x00 0x09 0x0a 0x2f 0x2f 0x2f 0x2f 0x0e 0x0f 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0c 0x0d 0x0e 0x0f}"
+                self.write_and_read(currentFrame, "ymm0", new_value)
+                self.write_and_read(currentFrame, "ymm7", new_value)
+                self.expect("expr $ymm0", substrs=['vector_type'])
+            else:
+                self.runCmd("register read ymm0")
+
+            if has_mpx:
+                # Test write and read for bnd0.
+                new_value_w = "{0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0x0f 0x10}"
+                self.runCmd("register write bnd0 \'" + new_value_w + "\'")
+                new_value_r = "{0x0807060504030201 0x100f0e0d0c0b0a09}"
+                self.expect("register read bnd0", substrs = ['bnd0 = ', new_value_r])
+                self.expect("expr $bnd0", substrs = ['vector_type'])
+
+                # Test write and for bndstatus.
+                new_value = "{0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08}"
+                self.write_and_read(currentFrame, "bndstatus", new_value)
+                self.expect("expr $bndstatus", substrs = ['vector_type'])
+            else:
+                self.runCmd("register read bnd0")
+
+    def convenience_registers(self):
+        """Test convenience registers."""
+        self.common_setup()
+
+        # The command "register read -a" does output a derived register like
+        # eax...
+        self.expect("register read -a", matching=True,
+                    substrs=['eax'])
+
+        # ...however, the vanilla "register read" command should not output derived registers like eax.
+        self.expect("register read", matching=False,
+                    substrs=['eax'])
+
+        # Test reading of rax and eax.
+        self.expect("register read rax eax",
+                    substrs=['rax = 0x', 'eax = 0x'])
+
+        # Now write rax with a unique bit pattern and test that eax indeed
+        # represents the lower half of rax.
+        self.runCmd("register write rax 0x1234567887654321")
+        self.expect("register read rax 0x1234567887654321",
+                    substrs=['0x1234567887654321'])
+
+    def convenience_registers_with_process_attach(self, test_16bit_regs):
+        """Test convenience registers after a 'process attach'."""
+        exe = os.path.join(os.getcwd(), "a.out")
+
+        # Spawn a new process
+        pid = self.spawnSubprocess(exe, ['wait_for_attach']).pid
+        self.addTearDownHook(self.cleanupSubprocesses)
+
+        if self.TraceOn():
+            print("pid of spawned process: %d" % pid)
+
+        self.runCmd("process attach -p %d" % pid)
+
+        # Check that "register read eax" works.
+        self.runCmd("register read eax")
+
+        if self.getArchitecture() in ['amd64', 'x86_64']:
+            self.expect("expr -- ($rax & 0xffffffff) == $eax",
+                        substrs=['true'])
+
+        if test_16bit_regs:
+            self.expect("expr -- $ax == (($ah << 8) | $al)",
+                        substrs=['true'])

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/a.cpp

+//===-- a.cpp ------------------------------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+#include <stdio.h>
+
+long double
+return_long_double (long double value)
+{
+#if defined (__i386__) || defined (__x86_64__)
+    float a=2, b=4,c=8, d=16, e=32, f=64, k=128, l=256, add=0;
+    __asm__ (
+        "int3 ;"
+        "flds %1 ;"
+        "flds %2 ;"
+        "flds %3 ;"
+        "flds %4 ;"
+        "flds %5 ;"
+        "flds %6 ;"
+        "flds %7 ;"
+        "faddp ;" : "=g" (add) : "g" (a), "g" (b), "g" (c), "g" (d), "g" (e), "g" (f), "g" (k), "g" (l) );  // Set break point at this line.
+#endif    // #if defined (__i386__) || defined (__x86_64__)
+    return value;
+}
+
+long double
+outer_return_long_double (long double value)
+{
+    long double val = return_long_double(value);
+    val *= 2 ;
+    return val;
+}
+
+long double
+outermost_return_long_double (long double value)
+{
+    long double val = outer_return_long_double(value);
+    val *= 2 ;
+    return val;
+}

lldb/trunk/packages/Python/lldbsuite/test/functionalities/register/register_command/main.cpp

+//===-- main.cpp ------------------------------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+#include <stdio.h>
+
+#include <chrono>
+#include <thread>
+
+long double outermost_return_long_double (long double my_long_double);
+
+int main (int argc, char const *argv[])
+{
+    lldb_enable_attach();
+
+    char my_string[] = {'a', 'b', 'c', 'd', 'e', 'f', 'g', 0};
+    double my_double = 1234.5678;
+    long double my_long_double = 1234.5678;
+
+    // For simplicity assume that any cmdline argument means wait for attach.
+    if (argc > 1)
+    {
+        volatile int wait_for_attach=1;
+        while (wait_for_attach)
+            std::this_thread::sleep_for(std::chrono::microseconds(1));
+    }
+
+    printf("my_string=%s\n", my_string);
+    printf("my_double=%g\n", my_double);
+    outermost_return_long_double (my_long_double);
+    return 0;
+}

lldb/trunk/source/Plugins/ABI/SysV-i386/ABISysV_i386.cpp

enum dwarf_regnums {
 
   dwarf_mm0 = 29,
   dwarf_mm1,
   dwarf_mm2,
   dwarf_mm3,
   dwarf_mm4,
   dwarf_mm5,
   dwarf_mm6,
-  dwarf_mm7
+  dwarf_mm7,
+
+  dwarf_bnd0 = 101,
+  dwarf_bnd1,
+  dwarf_bnd2,
+  dwarf_bnd3
 };
 
 static RegisterInfo g_register_infos[] = {
     //  NAME      ALT         SZ OFF ENCODING         FORMAT
     //  EH_FRAME                 DWARF                      GENERIC
     //  PROCESS PLUGIN          LLDB NATIVE            VALUE REGS    INVALIDATE
     //  REGS
     //  ======    =======     == === =============    ============
static RegisterInfo g_register_infos[] = {
      0,
      eEncodingVector,
      eFormatVectorOfUInt8,
      {LLDB_INVALID_REGNUM, dwarf_ymm7, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
       LLDB_INVALID_REGNUM},
      nullptr,
      nullptr,
      nullptr,
+     0},
+    {"bnd0",
+     nullptr,
+     16,
+     0,
+     eEncodingVector,
+     eFormatVectorOfUInt64,
+     {dwarf_bnd0, dwarf_bnd0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+      LLDB_INVALID_REGNUM },
+     nullptr,
+     nullptr,
+     nullptr,
+     0},
+    {"bnd1",
+     nullptr,
+     16,
+     0,
+     eEncodingVector,
+     eFormatVectorOfUInt64,
+     {dwarf_bnd1, dwarf_bnd1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+      LLDB_INVALID_REGNUM },
+     nullptr,
+     nullptr,
+     nullptr,
+     0},
+    {"bnd2",
+     nullptr,
+     16,
+     0,
+     eEncodingVector,
+     eFormatVectorOfUInt64,
+     {dwarf_bnd2, dwarf_bnd2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+      LLDB_INVALID_REGNUM },
+     nullptr,
+     nullptr,
+     nullptr,
+     0},
+    {"bnd3",
+     nullptr,
+     16,
+     0,
+     eEncodingVector,
+     eFormatVectorOfUInt64,
+     {dwarf_bnd3, dwarf_bnd3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+      LLDB_INVALID_REGNUM },
+     nullptr,
+     nullptr,
+     nullptr,
+     0},
+    {"bndcfgu",
+     nullptr,
+     8,
+     0,
+     eEncodingVector,
+     eFormatVectorOfUInt8,
+     {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+      LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
+     nullptr,
+     nullptr,
+     nullptr,
+     0},
+    {"bndstatus",
+     nullptr,
+     8,
+     0,
+     eEncodingVector,
+     eFormatVectorOfUInt8,
+     {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+      LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
+     nullptr,
+     nullptr,
+     nullptr,
      0}};
 
 static const uint32_t k_num_register_infos =
     llvm::array_lengthof(g_register_infos);
 static bool g_register_info_names_constified = false;
 
 const lldb_private::RegisterInfo *
 ABISysV_i386::GetRegisterInfoArray(uint32_t &count) {

lldb/trunk/source/Plugins/ABI/SysV-x86_64/ABISysV_x86_64.cpp

enum dwarf_regnums {
   dwarf_ymm7,
   dwarf_ymm8,
   dwarf_ymm9,
   dwarf_ymm10,
   dwarf_ymm11,
   dwarf_ymm12,
   dwarf_ymm13,
   dwarf_ymm14,
-  dwarf_ymm15
+  dwarf_ymm15,
+  dwarf_bnd0 = 126,
+  dwarf_bnd1,
+  dwarf_bnd2,
+  dwarf_bnd3
 };
 
 static RegisterInfo g_register_infos[] = {
     //  NAME      ALT      SZ OFF ENCODING         FORMAT              EH_FRAME
     //  DWARF                 GENERIC                     PROCESS PLUGIN
     //  LLDB NATIVE
     //  ========  =======  == === =============    ===================
     //  ======================= =====================
static RegisterInfo g_register_infos[] = {
      0,
      eEncodingVector,
      eFormatVectorOfUInt8,
      {dwarf_ymm15, dwarf_ymm15, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
       LLDB_INVALID_REGNUM},
      nullptr,
      nullptr,
      nullptr,
+     0},
+    {"bnd0",
+     nullptr,
+     16,
+     0,
+     eEncodingVector,
+     eFormatVectorOfUInt64,
+     {dwarf_bnd0, dwarf_bnd0, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+      LLDB_INVALID_REGNUM},
+     nullptr,
+     nullptr,
+     nullptr,
+     0},
+    {"bnd1",
+     nullptr,
+     16,
+     0,
+     eEncodingVector,
+     eFormatVectorOfUInt64,
+     {dwarf_bnd1, dwarf_bnd1, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+      LLDB_INVALID_REGNUM},
+     nullptr,
+     nullptr,
+     nullptr,
+     0},
+    {"bnd2",
+     nullptr,
+     16,
+     0,
+     eEncodingVector,
+     eFormatVectorOfUInt64,
+     {dwarf_bnd2, dwarf_bnd2, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+      LLDB_INVALID_REGNUM},
+     nullptr,
+     nullptr,
+     nullptr,
+     0},
+    {"bnd3",
+     nullptr,
+     16,
+     0,
+     eEncodingVector,
+     eFormatVectorOfUInt64,
+     {dwarf_bnd3, dwarf_bnd3, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+      LLDB_INVALID_REGNUM},
+     nullptr,
+     nullptr,
+     nullptr,
+     0},
+    {"bndcfgu",
+     nullptr,
+     8,
+     0,
+     eEncodingVector,
+     eFormatVectorOfUInt8,
+     {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+      LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
+     nullptr,
+     nullptr,
+     nullptr,
+     0},
+    {"bndstatus",
+     nullptr,
+     8,
+     0,
+     eEncodingVector,
+     eFormatVectorOfUInt8,
+     {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,
+      LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM},
+     nullptr,
+     nullptr,
+     nullptr,
      0}};
 
 static const uint32_t k_num_register_infos =
     llvm::array_lengthof(g_register_infos);
 static bool g_register_info_names_constified = false;
 
 const lldb_private::RegisterInfo *
 ABISysV_x86_64::GetRegisterInfoArray(uint32_t &count) {

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.h

private:
   enum FPRType { eFPRTypeNotValid = 0, eFPRTypeFXSAVE, eFPRTypeXSAVE };
 
   // Info about register ranges.
   struct RegInfo {
     uint32_t num_registers;
     uint32_t num_gpr_registers;
     uint32_t num_fpr_registers;
     uint32_t num_avx_registers;
-
+    uint32_t num_mpx_registers;
     uint32_t last_gpr;
     uint32_t first_fpr;
     uint32_t last_fpr;
-
     uint32_t first_st;
     uint32_t last_st;
     uint32_t first_mm;
     uint32_t last_mm;
     uint32_t first_xmm;
     uint32_t last_xmm;
     uint32_t first_ymm;
     uint32_t last_ymm;
-
+    uint32_t first_mpxr;
+    uint32_t last_mpxr;
+    uint32_t first_mpxc;
+    uint32_t last_mpxc;
     uint32_t first_dr;
     uint32_t gpr_flags;
   };
 
   // Private member variables.
   mutable FPRType m_fpr_type;
   FPR m_fpr;
   IOVEC m_iovec;
   YMM m_ymm_set;
+  MPX m_mpx_set;
   RegInfo m_reg_info;
   uint64_t m_gpr_x86_64[k_num_gpr_registers_x86_64];
   uint32_t m_fctrl_offset_in_userarea;
 
   // Private member methods.
   bool IsRegisterSetAvailable(uint32_t set_index) const;
 
   bool IsGPR(uint32_t reg_index) const;
 
   FPRType GetFPRType() const;
 
   bool IsFPR(uint32_t reg_index) const;
 
   bool IsFPR(uint32_t reg_index, FPRType fpr_type) const;
 
   bool CopyXSTATEtoYMM(uint32_t reg_index, lldb::ByteOrder byte_order);
 
   bool CopyYMMtoXSTATE(uint32_t reg, lldb::ByteOrder byte_order);
 
   bool IsAVX(uint32_t reg_index) const;
+
+  bool CopyXSTATEtoMPX(uint32_t reg);
+
+  bool CopyMPXtoXSTATE(uint32_t reg);
+
+  bool IsMPX(uint32_t reg_index) const;
 };
 
 } // namespace process_linux
 } // namespace lldb_private
 
 #endif // #ifndef lldb_NativeRegisterContextLinux_x86_64_h
 
 #endif // defined(__i386__) || defined(__x86_64__)

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_x86_64.cpp

const uint32_t g_avx_regnums_i386[] = {
     lldb_ymm4_i386,     lldb_ymm5_i386, lldb_ymm6_i386, lldb_ymm7_i386,
     LLDB_INVALID_REGNUM // register sets need to end with this flag
 };
 static_assert((sizeof(g_avx_regnums_i386) / sizeof(g_avx_regnums_i386[0])) -
                       1 ==
                   k_num_avx_registers_i386,
               " g_avx_regnums_i386 has wrong number of register infos");
 
+// x64 32-bit MPX registers.
+static const uint32_t g_mpx_regnums_i386[] = {
+    lldb_bnd0_i386,     lldb_bnd1_i386, lldb_bnd2_i386, lldb_bnd3_i386,
+    lldb_bndcfgu_i386,  lldb_bndstatus_i386,
+    LLDB_INVALID_REGNUM // register sets need to end with this flag
+};
+static_assert((sizeof(g_mpx_regnums_i386) / sizeof(g_mpx_regnums_i386[0])) -
+                      1 ==
+                  k_num_mpx_registers_i386,
+              "g_mpx_regnums_x86_64 has wrong number of register infos");
+
 // x86 64-bit general purpose registers.
 static const uint32_t g_gpr_regnums_x86_64[] = {
     lldb_rax_x86_64,    lldb_rbx_x86_64,    lldb_rcx_x86_64, lldb_rdx_x86_64,
     lldb_rdi_x86_64,    lldb_rsi_x86_64,    lldb_rbp_x86_64, lldb_rsp_x86_64,
     lldb_r8_x86_64,     lldb_r9_x86_64,     lldb_r10_x86_64, lldb_r11_x86_64,
     lldb_r12_x86_64,    lldb_r13_x86_64,    lldb_r14_x86_64, lldb_r15_x86_64,
     lldb_rip_x86_64,    lldb_rflags_x86_64, lldb_cs_x86_64,  lldb_fs_x86_64,
     lldb_gs_x86_64,     lldb_ss_x86_64,     lldb_ds_x86_64,  lldb_es_x86_64,
static const uint32_t g_avx_regnums_x86_64[] = {
     lldb_ymm12_x86_64,  lldb_ymm13_x86_64, lldb_ymm14_x86_64, lldb_ymm15_x86_64,
     LLDB_INVALID_REGNUM // register sets need to end with this flag
 };
 static_assert((sizeof(g_avx_regnums_x86_64) / sizeof(g_avx_regnums_x86_64[0])) -
                       1 ==
                   k_num_avx_registers_x86_64,
               "g_avx_regnums_x86_64 has wrong number of register infos");
 
+// x86 64-bit MPX registers.
+static const uint32_t g_mpx_regnums_x86_64[] = {
+    lldb_bnd0_x86_64,    lldb_bnd1_x86_64,    lldb_bnd2_x86_64,
+    lldb_bnd3_x86_64,    lldb_bndcfgu_x86_64, lldb_bndstatus_x86_64,
+    LLDB_INVALID_REGNUM // register sets need to end with this flag
+};
+static_assert((sizeof(g_mpx_regnums_x86_64) / sizeof(g_mpx_regnums_x86_64[0])) -
+                      1 ==
+                  k_num_mpx_registers_x86_64,
+              "g_mpx_regnums_x86_64 has wrong number of register infos");
+
 // Number of register sets provided by this context.
-enum { k_num_extended_register_sets = 1, k_num_register_sets = 3 };
+enum { k_num_extended_register_sets = 2, k_num_register_sets = 4 };
 
 // Register sets for x86 32-bit.
 static const RegisterSet g_reg_sets_i386[k_num_register_sets] = {
     {"General Purpose Registers", "gpr", k_num_gpr_registers_i386,
      g_gpr_regnums_i386},
     {"Floating Point Registers", "fpu", k_num_fpr_registers_i386,
      g_fpu_regnums_i386},
     {"Advanced Vector Extensions", "avx", k_num_avx_registers_i386,
-     g_avx_regnums_i386}};
+     g_avx_regnums_i386},
+    { "Memory Protection Extensions", "mpx", k_num_mpx_registers_i386,
+     g_mpx_regnums_i386}};
 
 // Register sets for x86 64-bit.
 static const RegisterSet g_reg_sets_x86_64[k_num_register_sets] = {
     {"General Purpose Registers", "gpr", k_num_gpr_registers_x86_64,
      g_gpr_regnums_x86_64},
     {"Floating Point Registers", "fpu", k_num_fpr_registers_x86_64,
      g_fpu_regnums_x86_64},
     {"Advanced Vector Extensions", "avx", k_num_avx_registers_x86_64,
-     g_avx_regnums_x86_64}};
+     g_avx_regnums_x86_64},
+    { "Memory Protection Extensions", "mpx", k_num_mpx_registers_x86_64,
+     g_mpx_regnums_x86_64}};
 }
 
 #define REG_CONTEXT_SIZE (GetRegisterInfoInterface().GetGPRSize() + sizeof(FPR))
 
 // ----------------------------------------------------------------------------
 // Required ptrace defines.
 // ----------------------------------------------------------------------------
 

 }
 
 NativeRegisterContextLinux_x86_64::NativeRegisterContextLinux_x86_64(
     const ArchSpec &target_arch, NativeThreadProtocol &native_thread,
     uint32_t concrete_frame_idx)
     : NativeRegisterContextLinux(native_thread, concrete_frame_idx,
                                  CreateRegisterInfoInterface(target_arch)),
       m_fpr_type(eFPRTypeNotValid), m_fpr(), m_iovec(), m_ymm_set(),
-      m_reg_info(), m_gpr_x86_64() {
+      m_mpx_set(), m_reg_info(), m_gpr_x86_64() {
   // Set up data about ranges of valid registers.
   switch (target_arch.GetMachine()) {
   case llvm::Triple::x86:
     m_reg_info.num_registers = k_num_registers_i386;
     m_reg_info.num_gpr_registers = k_num_gpr_registers_i386;
     m_reg_info.num_fpr_registers = k_num_fpr_registers_i386;
     m_reg_info.num_avx_registers = k_num_avx_registers_i386;
+    m_reg_info.num_mpx_registers = k_num_mpx_registers_i386;
     m_reg_info.last_gpr = k_last_gpr_i386;
     m_reg_info.first_fpr = k_first_fpr_i386;
     m_reg_info.last_fpr = k_last_fpr_i386;
     m_reg_info.first_st = lldb_st0_i386;
     m_reg_info.last_st = lldb_st7_i386;
     m_reg_info.first_mm = lldb_mm0_i386;
     m_reg_info.last_mm = lldb_mm7_i386;
     m_reg_info.first_xmm = lldb_xmm0_i386;
     m_reg_info.last_xmm = lldb_xmm7_i386;
     m_reg_info.first_ymm = lldb_ymm0_i386;
     m_reg_info.last_ymm = lldb_ymm7_i386;
+    m_reg_info.first_mpxr = lldb_bnd0_i386;
+    m_reg_info.last_mpxr = lldb_bnd3_i386;
+    m_reg_info.first_mpxc = lldb_bndcfgu_i386;
+    m_reg_info.last_mpxc = lldb_bndstatus_i386;
     m_reg_info.first_dr = lldb_dr0_i386;
     m_reg_info.gpr_flags = lldb_eflags_i386;
     break;
   case llvm::Triple::x86_64:
     m_reg_info.num_registers = k_num_registers_x86_64;
     m_reg_info.num_gpr_registers = k_num_gpr_registers_x86_64;
     m_reg_info.num_fpr_registers = k_num_fpr_registers_x86_64;
     m_reg_info.num_avx_registers = k_num_avx_registers_x86_64;
+    m_reg_info.num_mpx_registers = k_num_mpx_registers_x86_64;
     m_reg_info.last_gpr = k_last_gpr_x86_64;
     m_reg_info.first_fpr = k_first_fpr_x86_64;
     m_reg_info.last_fpr = k_last_fpr_x86_64;
     m_reg_info.first_st = lldb_st0_x86_64;
     m_reg_info.last_st = lldb_st7_x86_64;
     m_reg_info.first_mm = lldb_mm0_x86_64;
     m_reg_info.last_mm = lldb_mm7_x86_64;
     m_reg_info.first_xmm = lldb_xmm0_x86_64;
     m_reg_info.last_xmm = lldb_xmm15_x86_64;
     m_reg_info.first_ymm = lldb_ymm0_x86_64;
     m_reg_info.last_ymm = lldb_ymm15_x86_64;
+    m_reg_info.first_mpxr = lldb_bnd0_x86_64;
+    m_reg_info.last_mpxr = lldb_bnd3_x86_64;
+    m_reg_info.first_mpxc = lldb_bndcfgu_x86_64;
+    m_reg_info.last_mpxc = lldb_bndstatus_x86_64;
     m_reg_info.first_dr = lldb_dr0_x86_64;
     m_reg_info.gpr_flags = lldb_rflags_x86_64;
     break;
   default:
     assert(false && "Unhandled target architecture.");
     break;
   }
 
if (byte_order != lldb::eByteOrderInvalid) {
         if (GetFPRType() == eFPRTypeXSAVE && CopyXSTATEtoYMM(reg, byte_order))
           reg_value.SetBytes(m_ymm_set.ymm[reg - m_reg_info.first_ymm].bytes,
                              reg_info->byte_size, byte_order);
         else {
           error.SetErrorString("failed to copy ymm register value");
           return error;
         }
       }
+      if (reg >= m_reg_info.first_mpxr && reg <= m_reg_info.last_mpxr) {
+        if (GetFPRType() == eFPRTypeXSAVE && CopyXSTATEtoMPX(reg))
+          reg_value.SetBytes(m_mpx_set.mpxr[reg - m_reg_info.first_mpxr].bytes,
+                             reg_info->byte_size, byte_order);
+        else {
+          error.SetErrorString("failed to copy mpx register value");
+          return error;
+        }
+      }
+      if (reg >= m_reg_info.first_mpxc && reg <= m_reg_info.last_mpxc) {
+        if (GetFPRType() == eFPRTypeXSAVE && CopyXSTATEtoMPX(reg))
+          reg_value.SetBytes(m_mpx_set.mpxc[reg - m_reg_info.first_mpxc].bytes,
+                             reg_info->byte_size, byte_order);
+        else {
+          error.SetErrorString("failed to copy mpx register value");
+          return error;
+        }
+      }
 
       if (reg_value.GetType() != RegisterValue::eTypeBytes)
         error.SetErrorString(
             "write failed - type was expected to be RegisterValue::eTypeBytes");
 
       return error;
     }
 
if (reg_info->encoding == lldb::eEncodingVector) {
 
         // Store ymm register content, and split into the register halves in
         // xmm.bytes and ymmh.bytes
         ::memcpy(m_ymm_set.ymm[reg_index - m_reg_info.first_ymm].bytes,
                  reg_value.GetBytes(), reg_value.GetByteSize());
         if (!CopyYMMtoXSTATE(reg_index, GetByteOrder()))
           return Error("CopyYMMtoXSTATE() failed");
       }
+
+      if (reg_index >= m_reg_info.first_mpxr &&
+          reg_index <= m_reg_info.last_mpxr) {
+        if (GetFPRType() != eFPRTypeXSAVE)
+          return Error("target processor does not support MPX");
+
+        ::memcpy(m_mpx_set.mpxr[reg_index - m_reg_info.first_mpxr].bytes,
+                 reg_value.GetBytes(), reg_value.GetByteSize());
+        if (!CopyMPXtoXSTATE(reg_index))
+          return Error("CopyMPXtoXSTATE() failed");
+      }
+
+      if (reg_index >= m_reg_info.first_mpxc &&
+          reg_index <= m_reg_info.last_mpxc) {
+        if (GetFPRType() != eFPRTypeXSAVE)
+          return Error("target processor does not support MPX");
+
+        ::memcpy(m_mpx_set.mpxc[reg_index - m_reg_info.first_mpxc].bytes,
+                 reg_value.GetBytes(), reg_value.GetByteSize());
+        if (!CopyMPXtoXSTATE(reg_index))
+          return Error("CopyMPXtoXSTATE() failed");
+      }
     } else {
       // Get pointer to m_fpr.xstate.fxsave variable and set the data to it.
 
       // Byte offsets of all registers are calculated wrt 'UserArea' structure.
       // However, WriteFPR() takes m_fpr (of type FPR structure) and writes only
       // fpu
       // registers using ptrace(PTRACE_SETFPREGS,..) API. Hence fpu registers
       // should
if (IsFPR(reg_index, GetFPRType())) {
     Error error = WriteFPR();
     if (error.Fail())
       return error;
 
     if (IsAVX(reg_index)) {
       if (!CopyYMMtoXSTATE(reg_index, GetByteOrder()))
         return Error("CopyYMMtoXSTATE() failed");
     }
+
+    if (IsMPX(reg_index)) {
+      if (!CopyMPXtoXSTATE(reg_index))
+        return Error("CopyMPXtoXSTATE() failed");
+    }
     return Error();
   }
   return Error("failed - register wasn't recognized to be a GPR or an FPR, "
                "write strategy unknown");
 }
 
 Error NativeRegisterContextLinux_x86_64::ReadAllRegisterValues(
     lldb::DataBufferSP &data_sp) {
for (uint32_t reg = m_reg_info.first_ymm; reg <= m_reg_info.last_ymm;
         error.SetErrorStringWithFormat("NativeRegisterContextLinux_x86_64::%s "
                                        "CopyXSTATEtoYMM() failed for reg num "
                                        "%" PRIu32,
                                        __FUNCTION__, reg);
         return error;
       }
     }
 
+    for (uint32_t reg = m_reg_info.first_mpxr; reg <= m_reg_info.last_mpxc;
+         ++reg) {
+      if (!CopyXSTATEtoMPX(reg)) {
+        error.SetErrorStringWithFormat("NativeRegisterContextLinux_x86_64::%s "
+                                       "CopyXSTATEtoMPX() failed for reg num "
+                                       "%" PRIu32,
+                                       __FUNCTION__, reg);
+        return error;
+      }
+    }
     // Copy the extended register state including the assembled ymm registers.
     ::memcpy(dst, &m_fpr, sizeof(m_fpr));
   } else {
     assert(false && "how do we save the floating point registers?");
     error.SetErrorString("unsure how to save the floating point registers");
   }
   /** The following code is specific to Linux x86 based architectures,
    *  where the register orig_eax (32 bit)/orig_rax (64 bit) is set to
for (uint32_t reg = m_reg_info.first_ymm; reg <= m_reg_info.last_ymm;
       if (!CopyYMMtoXSTATE(reg, byte_order)) {
         error.SetErrorStringWithFormat("NativeRegisterContextLinux_x86_64::%s "
                                        "CopyYMMtoXSTATE() failed for reg num "
                                        "%" PRIu32,
                                        __FUNCTION__, reg);
         return error;
       }
     }
+
+    for (uint32_t reg = m_reg_info.first_mpxr; reg <= m_reg_info.last_mpxc;
+         ++reg) {
+      if (!CopyMPXtoXSTATE(reg)) {
+        error.SetErrorStringWithFormat("NativeRegisterContextLinux_x86_64::%s "
+                                         "CopyMPXtoXSTATE() failed for reg num "
+                                         "%" PRIu32,
+                                         __FUNCTION__, reg);
+        return error;
+      }
+    }
   }
 
   return error;
 }
 
 bool NativeRegisterContextLinux_x86_64::IsRegisterSetAvailable(
     uint32_t set_index) const {
   // Note: Extended register sets are assumed to be at the end of g_reg_sets.
   uint32_t num_sets = k_num_register_sets - k_num_extended_register_sets;
 
   if (GetFPRType() == eFPRTypeXSAVE) {
     // AVX is the first extended register set.
-    ++num_sets;
+    num_sets += 2;
   }
   return (set_index < num_sets);
 }
 
 bool NativeRegisterContextLinux_x86_64::IsGPR(uint32_t reg_index) const {
   // GPRs come first.
   return reg_index <= m_reg_info.last_gpr;
 }
return (m_reg_info.first_fpr <= reg_index &&
           reg_index <= m_reg_info.last_fpr);
 }
 
 bool NativeRegisterContextLinux_x86_64::IsFPR(uint32_t reg_index,
                                               FPRType fpr_type) const {
   bool generic_fpr = IsFPR(reg_index);
 
   if (fpr_type == eFPRTypeXSAVE)
-    return generic_fpr || IsAVX(reg_index);
+    return generic_fpr || IsAVX(reg_index) || IsMPX(reg_index);
   return generic_fpr;
 }
 
 Error NativeRegisterContextLinux_x86_64::WriteFPR() {
   const FPRType fpr_type = GetFPRType();
   const lldb_private::ArchSpec &target_arch =
       GetRegisterInfoInterface().GetTargetArchitecture();
   switch (fpr_type) {
case FPRType::eFPRTypeFXSAVE:
     }
   case FPRType::eFPRTypeXSAVE:
     return ReadRegisterSet(&m_iovec, sizeof(m_fpr.xstate.xsave), NT_X86_XSTATE);
   default:
     return Error("Unrecognized FPR type");
   }
 }
 
+bool NativeRegisterContextLinux_x86_64::IsMPX(uint32_t reg_index) const {
+    return (m_reg_info.first_mpxr <= reg_index &&
+            reg_index <= m_reg_info.last_mpxc);
+}
+
+bool NativeRegisterContextLinux_x86_64::CopyXSTATEtoMPX(uint32_t reg) {
+  if (!IsMPX(reg))
+    return false;
+
+  if (reg >= m_reg_info.first_mpxr && reg <= m_reg_info.last_mpxr) {
+    ::memcpy(m_mpx_set.mpxr[reg - m_reg_info.first_mpxr].bytes,
+             m_fpr.xstate.xsave.mpxr[reg - m_reg_info.first_mpxr].bytes,
+             sizeof(MPXReg));
+  } else {
+    ::memcpy(m_mpx_set.mpxc[reg - m_reg_info.first_mpxc].bytes,
+             m_fpr.xstate.xsave.mpxc[reg - m_reg_info.first_mpxc].bytes,
+             sizeof(MPXCsr));
+  }
+  return true;
+}
+
+bool NativeRegisterContextLinux_x86_64::CopyMPXtoXSTATE(uint32_t reg) {
+  if (!IsMPX(reg))
+    return false;
+
+  if (reg >= m_reg_info.first_mpxr && reg <= m_reg_info.last_mpxr) {
+    ::memcpy(m_fpr.xstate.xsave.mpxr[reg - m_reg_info.first_mpxr].bytes,
+             m_mpx_set.mpxr[reg - m_reg_info.first_mpxr].bytes, sizeof(MPXReg));
+  } else {
+    ::memcpy(m_fpr.xstate.xsave.mpxc[reg - m_reg_info.first_mpxc].bytes,
+             m_mpx_set.mpxc[reg - m_reg_info.first_mpxc].bytes, sizeof(MPXCsr));
+  }
+  return true;
+}
+
 Error NativeRegisterContextLinux_x86_64::IsWatchpointHit(uint32_t wp_index,
                                                          bool &is_hit) {
   if (wp_index >= NumSupportedHardwareWatchpoints())
     return Error("Watchpoint index out of range");
 
   RegisterValue reg_value;
   Error error = ReadRegisterRaw(m_reg_info.first_dr + 6, reg_value);
   if (error.Fail()) {

lldb/trunk/source/Plugins/Process/Utility/RegisterContext_x86.h

enum {
   dwarf_fctrl_i386 = 37, // x87 control word
   dwarf_fstat_i386 = 38, // x87 status word
   dwarf_mxcsr_i386 = 39,
   dwarf_es_i386 = 40,
   dwarf_cs_i386 = 41,
   dwarf_ss_i386 = 42,
   dwarf_ds_i386 = 43,
   dwarf_fs_i386 = 44,
-  dwarf_gs_i386 = 45
+  dwarf_gs_i386 = 45,
 
   // I believe the ymm registers use the dwarf_xmm%_i386 register numbers and
   //  then differentiate based on size of the register.
+  dwarf_bnd0_i386 = 101,
+  dwarf_bnd1_i386,
+  dwarf_bnd2_i386,
+  dwarf_bnd3_i386,
 };
 
 //---------------------------------------------------------------------------
 // AMD x86_64, AMD64, Intel EM64T, or Intel 64 ehframe, dwarf regnums
 //---------------------------------------------------------------------------
 
 // EHFrame and DWARF Register numbers (eRegisterKindEHFrame &
 // eRegisterKindDWARF)
enum {
   dwarf_ymm8h_x86_64,
   dwarf_ymm9h_x86_64,
   dwarf_ymm10h_x86_64,
   dwarf_ymm11h_x86_64,
   dwarf_ymm12h_x86_64,
   dwarf_ymm13h_x86_64,
   dwarf_ymm14h_x86_64,
   dwarf_ymm15h_x86_64,
+  // MPX registers
+  dwarf_bnd0_x86_64 = 126,
+  dwarf_bnd1_x86_64,
+  dwarf_bnd2_x86_64,
+  dwarf_bnd3_x86_64,
   // AVX2 Vector Mask Registers
   // dwarf_k0_x86_64 = 118,
   // dwarf_k1_x86_64,
   // dwarf_k2_x86_64,
   // dwarf_k3_x86_64,
   // dwarf_k4_x86_64,
   // dwarf_k5_x86_64,
   // dwarf_k6_x86_64,

 struct YMMReg {
   uint8_t bytes[32]; // 16 * 16 bits for each YMM register
 };
 
 struct YMM {
   YMMReg ymm[16]; // assembled from ymmh and xmm registers
 };
 
+struct MPXReg {
+  uint8_t bytes[16]; // MPX 128 bit bound registers
+};
+
+struct MPXCsr {
+  uint8_t bytes[8]; // MPX 64 bit bndcfgu and bndstatus registers (collectively
+                    // BNDCSR state)
+};
+
+struct MPX {
+  MPXReg mpxr[4];
+  MPXCsr mpxc[2];
+};
+
 LLVM_PACKED_START
 struct XSAVE_HDR {
   uint64_t xstate_bv; // OS enabled xstate mask to determine the extended states
                       // supported by the processor
-  uint64_t reserved1[2];
+  uint64_t xcomp_bv;  // Mask to indicate the format of the XSAVE area and of
+                      // the XRSTOR instruction
+  uint64_t reserved1[1];
   uint64_t reserved2[5];
 };
 LLVM_PACKED_END
 
-// x86 extensions to FXSAVE (i.e. for AVX processors)
+// x86 extensions to FXSAVE (i.e. for AVX and MPX processors)
 LLVM_PACKED_START
 struct LLVM_ALIGNAS(64) XSAVE {
   FXSAVE i387;      // floating point registers typical in i387_fxsave_struct
   XSAVE_HDR header; // The xsave_hdr_struct can be used to determine if the
                     // following extensions are usable
   YMMHReg ymmh[16]; // High 16 bytes of each of 16 YMM registers (the low bytes
                     // are in FXSAVE.xmm for compatibility with SSE)
-                    // Slot any extensions to the register file here
+  uint64_t reserved3[16];
+  MPXReg mpxr[4];   // MPX BNDREG state, containing 128-bit bound registers
+  MPXCsr mpxc[2];   // MPX BNDCSR state, containing 64-bit BNDCFGU and
+                    // BNDSTATUS registers
 };
 LLVM_PACKED_END
 
 // Floating-point registers
 struct FPR {
   // Thread state for the floating-point unit of the processor read by ptrace.
   union XSTATE {
     FXSAVE fxsave; // Generic floating-point registers.

lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_i386.h

 // Computes the offset of the YMM register assembled from register halves.
 // Based on DNBArchImplI386.cpp from debugserver
 #define YMM_OFFSET(reg_index)                                                  \
   (LLVM_EXTENSION offsetof(UserArea, i387) +                                   \
    LLVM_EXTENSION offsetof(FPR, xstate) +                                      \
    LLVM_EXTENSION offsetof(FXSAVE, xmm[7]) + sizeof(XMMReg) +                  \
    (32 * reg_index))
 
+#define BNDR_OFFSET(reg_index) \
+    (LLVM_EXTENSION offsetof(UserArea, i387) + \
+     LLVM_EXTENSION offsetof(FPR, xstate) + \
+     LLVM_EXTENSION offsetof(XSAVE, mpxr[reg_index]))
+
+#define BNDC_OFFSET(reg_index) \
+    (LLVM_EXTENSION offsetof(UserArea, i387) + \
+     LLVM_EXTENSION offsetof(FPR, xstate) + \
+     LLVM_EXTENSION offsetof(XSAVE, mpxc[reg_index]))
+
 // Number of bytes needed to represent a FPR.
 #if !defined(FPR_SIZE)
 #define FPR_SIZE(reg) sizeof(((FXSAVE *)NULL)->reg)
 #endif
 
 // Number of bytes needed to represent the i'th FP register.
 #define FP_SIZE sizeof(((MMSReg *)NULL)->bytes)
 
 // Number of bytes needed to represent an XMM register.
 #define XMM_SIZE sizeof(XMMReg)
 
 // Number of bytes needed to represent a YMM register.
 #define YMM_SIZE sizeof(YMMReg)
 
+// Number of bytes needed to represent MPX registers.
+#define BNDR_SIZE sizeof(MPXReg)
+#define BNDC_SIZE sizeof(MPXCsr)
+
 // Note that the size and offset will be updated by platform-specific classes.
 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4)                       \
   {                                                                            \
     #reg, alt, sizeof(((GPR *) NULL)->reg),                                    \
                       GPR_OFFSET(reg), eEncodingUint, eFormatHex,              \
                                  {kind1, kind2, kind3, kind4,                  \
                                   lldb_##reg##_i386 },                         \
                                   NULL, NULL, NULL, 0                          \
#define DEFINE_YMM(reg, i)                                                     \
     #reg #i, NULL, YMM_SIZE,                                                   \
         LLVM_EXTENSION YMM_OFFSET(i), eEncodingVector, eFormatVectorOfUInt8,   \
                                   {LLDB_INVALID_REGNUM, dwarf_xmm##i##_i386,   \
                                    LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,   \
                                    lldb_##reg##i##_i386 },                     \
                                    NULL, NULL, NULL, 0                         \
   }
 
+#define DEFINE_BNDR(reg, i)                                                    \
+  {                                                                            \
+    #reg #i, NULL, BNDR_SIZE,                                                  \
+        LLVM_EXTENSION BNDR_OFFSET(i), eEncodingVector, eFormatVectorOfUInt64, \
+        {dwarf_##reg##i##_i386, dwarf_##reg##i##_i386, LLDB_INVALID_REGNUM,    \
+         LLDB_INVALID_REGNUM, lldb_##reg##i##_i386 },                          \
+         NULL, NULL                                                            \
+  }
+
+#define DEFINE_BNDC(name, i)                                                   \
+  {                                                                            \
+    #name, NULL, BNDC_SIZE,                                                    \
+           LLVM_EXTENSION BNDC_OFFSET(i), eEncodingVector,                     \
+           eFormatVectorOfUInt8,                                               \
+           {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,     \
+            LLDB_INVALID_REGNUM, lldb_##name##_i386 },                         \
+            NULL, NULL                                                         \
+  }
+
 #define DEFINE_DR(reg, i)                                                      \
   {                                                                            \
     #reg #i, NULL, DR_SIZE,                                                    \
         DR_OFFSET(i), eEncodingUint, eFormatHex,                               \
                   {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,                   \
                    LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,                   \
                    LLDB_INVALID_REGNUM },                                      \
                    NULL, NULL, NULL, 0                                         \
static RegisterInfo g_register_infos_i386[] = {
     DEFINE_XMM(xmm, 3), DEFINE_XMM(xmm, 4), DEFINE_XMM(xmm, 5),
     DEFINE_XMM(xmm, 6), DEFINE_XMM(xmm, 7),
 
     // Copy of YMM registers assembled from xmm and ymmh
     DEFINE_YMM(ymm, 0), DEFINE_YMM(ymm, 1), DEFINE_YMM(ymm, 2),
     DEFINE_YMM(ymm, 3), DEFINE_YMM(ymm, 4), DEFINE_YMM(ymm, 5),
     DEFINE_YMM(ymm, 6), DEFINE_YMM(ymm, 7),
 
+    // MPX registers
+    DEFINE_BNDR(bnd, 0),
+    DEFINE_BNDR(bnd, 1),
+    DEFINE_BNDR(bnd, 2),
+    DEFINE_BNDR(bnd, 3),
+
+    DEFINE_BNDC(bndcfgu, 0),
+    DEFINE_BNDC(bndstatus, 1),
+
     // Debug registers for lldb internal use
     DEFINE_DR(dr, 0), DEFINE_DR(dr, 1), DEFINE_DR(dr, 2), DEFINE_DR(dr, 3),
     DEFINE_DR(dr, 4), DEFINE_DR(dr, 5), DEFINE_DR(dr, 6), DEFINE_DR(dr, 7)};
 
 static_assert((sizeof(g_register_infos_i386) /
                sizeof(g_register_infos_i386[0])) == k_num_registers_i386,
               "g_register_infos_x86_64 has wrong number of register infos");
 
 #undef GPR_OFFSET
 #undef FPR_OFFSET
 #undef YMM_OFFSET
 #undef FPR_SIZE
 #undef FP_SIZE
 #undef XMM_SIZE
 #undef YMM_SIZE
 #undef DEFINE_GPR
 #undef DEFINE_FPR
 #undef DEFINE_FP
 #undef DEFINE_XMM
 #undef DEFINE_YMM
+#undef DEFINE_BNDR
+#undef DEFINE_BNDC
 #undef DEFINE_DR
 #undef DEFINE_GPR_PSEUDO_16
 #undef DEFINE_GPR_PSEUDO_8H
 #undef DEFINE_GPR_PSEUDO_8L
 
 #endif // DECLARE_REGISTER_INFOS_I386_STRUCT

lldb/trunk/source/Plugins/Process/Utility/RegisterInfos_x86_64.h

 
 // Computes the offset of the YMM register assembled from register halves.
 // Based on DNBArchImplX86_64.cpp from debugserver
 #define YMM_OFFSET(reg_index)                                                  \
   (LLVM_EXTENSION offsetof(UserArea, fpr) +                                    \
    LLVM_EXTENSION offsetof(FPR, xstate) +                                      \
    LLVM_EXTENSION offsetof(XSAVE, ymmh[0]) + (32 * reg_index))
 
+#define BNDR_OFFSET(reg_index) \
+    (LLVM_EXTENSION offsetof(UserArea, fpr) + \
+     LLVM_EXTENSION offsetof(FPR, xstate) + \
+     LLVM_EXTENSION offsetof(XSAVE, mpxr[reg_index]))
+
+#define BNDC_OFFSET(reg_index) \
+    (LLVM_EXTENSION offsetof(UserArea, fpr) + \
+     LLVM_EXTENSION offsetof(FPR, xstate) + \
+     LLVM_EXTENSION offsetof(XSAVE, mpxc[reg_index]))
+
 #ifdef DECLARE_REGISTER_INFOS_X86_64_STRUCT
 
 // Number of bytes needed to represent a FPR.
 #define FPR_SIZE(reg) sizeof(((FXSAVE *)NULL)->reg)
 
 // Number of bytes needed to represent the i'th FP register.
 #define FP_SIZE sizeof(((MMSReg *)NULL)->bytes)
 
 // Number of bytes needed to represent an XMM register.
 #define XMM_SIZE sizeof(XMMReg)
 
 // Number of bytes needed to represent a YMM register.
 #define YMM_SIZE sizeof(YMMReg)
 
+// Number of bytes needed to represent MPX registers.
+#define BNDR_SIZE sizeof(MPXReg)
+#define BNDC_SIZE sizeof(MPXCsr)
+
 #define DR_SIZE sizeof(((DBG *)NULL)->dr[0])
 
 // RegisterKind: EHFrame, DWARF, Generic, Process Plugin, LLDB
 
 // Note that the size and offset will be updated by platform-specific classes.
 #define DEFINE_GPR(reg, alt, kind1, kind2, kind3, kind4)                       \
   {                                                                            \
     #reg, alt, sizeof(((GPR *) NULL)->reg),                                    \
#reg #i, NULL, YMM_SIZE,                                                   \
         LLVM_EXTENSION YMM_OFFSET(i), eEncodingVector, eFormatVectorOfUInt8,   \
                                   {dwarf_##reg##i##h_x86_64,                   \
                                    dwarf_##reg##i##h_x86_64,                   \
                                    LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,   \
                                    lldb_##reg##i##_x86_64 },                   \
                                    NULL, NULL, NULL, 0                         \
   }
 
+#define DEFINE_BNDR(reg, i)                                                    \
+  {                                                                            \
+    #reg #i, NULL, BNDR_SIZE,                                                  \
+        LLVM_EXTENSION BNDR_OFFSET(i), eEncodingVector, eFormatVectorOfUInt64, \
+                                   {dwarf_##reg##i##_x86_64,                   \
+                                    dwarf_##reg##i##_x86_64,                   \
+                                    LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,  \
+                                    lldb_##reg##i##_x86_64 },                  \
+                                    NULL, NULL                                 \
+  }
+
+#define DEFINE_BNDC(name, i)                                                   \
+  {                                                                            \
+    #name, NULL, BNDC_SIZE,                                                    \
+        LLVM_EXTENSION BNDC_OFFSET(i), eEncodingVector, eFormatVectorOfUInt8,  \
+        {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,        \
+         LLDB_INVALID_REGNUM, lldb_##name##_x86_64 },                          \
+         NULL, NULL                                                            \
+  }
+
 #define DEFINE_DR(reg, i)                                                      \
   {                                                                            \
     #reg #i, NULL, DR_SIZE,                                                    \
         DR_OFFSET(i), eEncodingUint, eFormatHex,                               \
                   {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,                   \
                    LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM,                   \
                    LLDB_INVALID_REGNUM },                                      \
                    NULL, NULL, NULL, 0                                         \
static RegisterInfo g_register_infos_x86_64[] = {
     // Copy of YMM registers assembled from xmm and ymmh
     DEFINE_YMM(ymm, 0), DEFINE_YMM(ymm, 1), DEFINE_YMM(ymm, 2),
     DEFINE_YMM(ymm, 3), DEFINE_YMM(ymm, 4), DEFINE_YMM(ymm, 5),
     DEFINE_YMM(ymm, 6), DEFINE_YMM(ymm, 7), DEFINE_YMM(ymm, 8),
     DEFINE_YMM(ymm, 9), DEFINE_YMM(ymm, 10), DEFINE_YMM(ymm, 11),
     DEFINE_YMM(ymm, 12), DEFINE_YMM(ymm, 13), DEFINE_YMM(ymm, 14),
     DEFINE_YMM(ymm, 15),
 
+    // MPX registers
+    DEFINE_BNDR(bnd, 0),
+    DEFINE_BNDR(bnd, 1),
+    DEFINE_BNDR(bnd, 2),
+    DEFINE_BNDR(bnd, 3),
+
+    DEFINE_BNDC(bndcfgu, 0),
+    DEFINE_BNDC(bndstatus, 1),
+
     // Debug registers for lldb internal use
     DEFINE_DR(dr, 0), DEFINE_DR(dr, 1), DEFINE_DR(dr, 2), DEFINE_DR(dr, 3),
     DEFINE_DR(dr, 4), DEFINE_DR(dr, 5), DEFINE_DR(dr, 6), DEFINE_DR(dr, 7)};
 
 static_assert((sizeof(g_register_infos_x86_64) /
                sizeof(g_register_infos_x86_64[0])) == k_num_registers_x86_64,
               "g_register_infos_x86_64 has wrong number of register infos");
 
 #undef FPR_SIZE
 #undef FP_SIZE
 #undef XMM_SIZE
 #undef YMM_SIZE
 #undef DEFINE_GPR
 #undef DEFINE_FPR
 #undef DEFINE_FP
 #undef DEFINE_XMM
 #undef DEFINE_YMM
+#undef DEFINE_BNDR
+#undef DEFINE_BNDC
 #undef DEFINE_DR
 #undef DEFINE_GPR_PSEUDO_32
 #undef DEFINE_GPR_PSEUDO_16
 #undef DEFINE_GPR_PSEUDO_8H
 #undef DEFINE_GPR_PSEUDO_8L
 
 #endif // DECLARE_REGISTER_INFOS_X86_64_STRUCT
 

lldb/trunk/source/Plugins/Process/Utility/lldb-x86-register-enums.h

enum {
   lldb_ymm2_i386,
   lldb_ymm3_i386,
   lldb_ymm4_i386,
   lldb_ymm5_i386,
   lldb_ymm6_i386,
   lldb_ymm7_i386,
   k_last_avx_i386 = lldb_ymm7_i386,
 
+  k_first_mpxr_i386,
+  lldb_bnd0_i386 = k_first_mpxr_i386,
+  lldb_bnd1_i386,
+  lldb_bnd2_i386,
+  lldb_bnd3_i386,
+  k_last_mpxr = lldb_bnd3_i386,
+
+  k_first_mpxc_i386,
+  lldb_bndcfgu_i386 = k_first_mpxc_i386,
+  lldb_bndstatus_i386,
+  k_last_mpxc_i386 = lldb_bndstatus_i386,
+
   lldb_dr0_i386,
   lldb_dr1_i386,
   lldb_dr2_i386,
   lldb_dr3_i386,
   lldb_dr4_i386,
   lldb_dr5_i386,
   lldb_dr6_i386,
   lldb_dr7_i386,
 
   k_num_registers_i386,
   k_num_gpr_registers_i386 = k_last_gpr_i386 - k_first_gpr_i386 + 1,
   k_num_fpr_registers_i386 = k_last_fpr_i386 - k_first_fpr_i386 + 1,
   k_num_avx_registers_i386 = k_last_avx_i386 - k_first_avx_i386 + 1,
+  k_num_mpx_registers_i386 = k_last_mpxc_i386 - k_first_mpxr_i386 + 1,
   k_num_user_registers_i386 = k_num_gpr_registers_i386 +
                               k_num_fpr_registers_i386 +
-                              k_num_avx_registers_i386,
+                              k_num_avx_registers_i386 +
+                              k_num_mpx_registers_i386,
 };
 
 //---------------------------------------------------------------------------
 // Internal codes for all x86_64 registers.
 //---------------------------------------------------------------------------
 enum {
   k_first_gpr_x86_64,
   lldb_rax_x86_64 = k_first_gpr_x86_64,
enum {
   lldb_ymm10_x86_64,
   lldb_ymm11_x86_64,
   lldb_ymm12_x86_64,
   lldb_ymm13_x86_64,
   lldb_ymm14_x86_64,
   lldb_ymm15_x86_64,
   k_last_avx_x86_64 = lldb_ymm15_x86_64,
 
+  k_first_mpxr_x86_64,
+  lldb_bnd0_x86_64 = k_first_mpxr_x86_64,
+  lldb_bnd1_x86_64,
+  lldb_bnd2_x86_64,
+  lldb_bnd3_x86_64,
+  k_last_mpxr_x86_64 = lldb_bnd3_x86_64,
+
+  k_first_mpxc_x86_64,
+  lldb_bndcfgu_x86_64 = k_first_mpxc_x86_64,
+  lldb_bndstatus_x86_64,
+  k_last_mpxc_x86_64 = lldb_bndstatus_x86_64,
+
   lldb_dr0_x86_64,
   lldb_dr1_x86_64,
   lldb_dr2_x86_64,
   lldb_dr3_x86_64,
   lldb_dr4_x86_64,
   lldb_dr5_x86_64,
   lldb_dr6_x86_64,
   lldb_dr7_x86_64,
 
   k_num_registers_x86_64,
   k_num_gpr_registers_x86_64 = k_last_gpr_x86_64 - k_first_gpr_x86_64 + 1,
   k_num_fpr_registers_x86_64 = k_last_fpr_x86_64 - k_first_fpr_x86_64 + 1,
   k_num_avx_registers_x86_64 = k_last_avx_x86_64 - k_first_avx_x86_64 + 1,
+  k_num_mpx_registers_x86_64 = k_last_mpxc_x86_64 - k_first_mpxr_x86_64 + 1,
   k_num_user_registers_x86_64 = k_num_gpr_registers_x86_64 +
                                 k_num_fpr_registers_x86_64 +
-                                k_num_avx_registers_x86_64,
+                                k_num_avx_registers_x86_64 +
+                                k_num_mpx_registers_x86_64,
 };
 }
 
 #endif // #ifndef lldb_x86_register_enums_h

lldb/trunk/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationServerLLGS.cpp

case eFormatVectorOfSInt32:
     response.PutCString("format:vector-sint32;");
     break;
   case eFormatVectorOfUInt32:
     response.PutCString("format:vector-uint32;");
     break;
   case eFormatVectorOfFloat32:
     response.PutCString("format:vector-float32;");
     break;
+  case eFormatVectorOfUInt64:
+    response.PutCString("format:vector-uint64;");
+    break;
   case eFormatVectorOfUInt128:
     response.PutCString("format:vector-uint128;");
     break;
   default:
     break;
   };
 
   const char *const register_set_name =

lldb/trunk/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp

if (m_gdb_comm.SendPacketAndWaitForResponse(packet, packet_len, response,
                       .Case("float", eFormatFloat)
                       .Case("vector-sint8", eFormatVectorOfSInt8)
                       .Case("vector-uint8", eFormatVectorOfUInt8)
                       .Case("vector-sint16", eFormatVectorOfSInt16)
                       .Case("vector-uint16", eFormatVectorOfUInt16)
                       .Case("vector-sint32", eFormatVectorOfSInt32)
                       .Case("vector-uint32", eFormatVectorOfUInt32)
                       .Case("vector-float32", eFormatVectorOfFloat32)
+                      .Case("vector-uint64", eFormatVectorOfUInt64)
                       .Case("vector-uint128", eFormatVectorOfUInt128)
                       .Default(eFormatInvalid);
             }
           } else if (name.equals("set")) {
             set_name.SetString(value);
           } else if (name.equals("gcc") || name.equals("ehframe")) {
             if (value.getAsInteger(0, reg_info.kinds[eRegisterKindEHFrame]))
               reg_info.kinds[eRegisterKindEHFrame] = LLDB_INVALID_REGNUM;
feature_node.ForEachChildElementWithName(
             else if (value == "vector-uint16")
               reg_info.format = eFormatVectorOfUInt16;
             else if (value == "vector-sint32")
               reg_info.format = eFormatVectorOfSInt32;
             else if (value == "vector-uint32")
               reg_info.format = eFormatVectorOfUInt32;
             else if (value == "vector-float32")
               reg_info.format = eFormatVectorOfFloat32;
+            else if (value == "vector-uint64")
+              reg_info.format = eFormatVectorOfUInt64;
             else if (value == "vector-uint128")
               reg_info.format = eFormatVectorOfUInt128;
           } else if (name == "group_id") {
             const uint32_t set_id =
                 StringConvert::ToUInt32(value.data(), UINT32_MAX, 0);
             RegisterSetMap::const_iterator pos =
                 target_info.reg_set_map.find(set_id);
             if (pos != target_info.reg_set_map.end())