[PowerPC] Don't generate ST_VSR_SCAL_INT if power8-vector is disabled, fix PR45297

[lkail]

Summary

In https://bugs.llvm.org/show_bug.cgi?id=45297, it fails selecting instructions for PPCISD::ST_VSR_SCAL_INT. The reason it generate the PPCISD::ST_VSR_SCAL_INT with -power8-vector in IR is PPC's combiner checks hasP8Altivec rather than hasP8Vector. This patch should resolve PR45297.

[jhibbits]

Can you fix the title of this? "Fix PR45297" is not very descriptive unless someone also reviews the PR.

[steven.zhang]

LGTM. Please hold on for some days in case someone else has concern.

[sfertile]

A couple minor suggestions. If you agree with them, feel free to land them as an NFC update to the test before commiting this patch.

llvm/test/CodeGen/PowerPC/pr45297.ll

1–6

Pre-commiting the test to show the intended change in behaviour is a really good idea. I think it would be more effective if we check for the error we are tying to fix though:

; RUN: not --crash llc -verify-machineinstrs \
; RUN:   -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec \
; RUN:   -mattr=-power8-vector -mattr=-vsx < %s 2>&1 | FileCheck %s

; CHECK: LLVM ERROR: Cannot select: t{{[0-9]+}}: ch = PPCISD::ST_VSR_SCAL_INT<(store 4 into @Global)>

11

Nit: can we store to something other then undef? Maybe changing the IR to:

@Global = dso_local global i32 55, align 4

define dso_local void @test(float %0) local_unnamed_addr {
entry:
  %1 = fptosi float %0 to i32
  store i32 %1, i32* @Global, align 4
  ret void
}

[lkail]

Address @sfertile 's comment.

[sfertile]

Thank you for the updates. One minor comment, but patch LGTM.

llvm/test/CodeGen/PowerPC/pr45297.ll

2

Do we want to use -ppc-asm-full-reg-names to make the assembly easier to read?

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

SDValue PPCTargetLowering::combineStoreFPToInt(SDNode *N,
   if (ResVT.getScalarSizeInBits() < 32)
     return SDValue();
 
   // Only perform combine for conversion to i64/i32 or power9 i16/i8.
   bool ValidTypeForStoreFltAsInt =
         (Op1VT == MVT::i32 || Op1VT == MVT::i64 ||
          (Subtarget.hasP9Vector() && (Op1VT == MVT::i16 || Op1VT == MVT::i8)));
 
-  if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Altivec() ||
+  if (ResVT == MVT::ppcf128 || !Subtarget.hasP8Vector() ||
       cast<StoreSDNode>(N)->isTruncatingStore() || !ValidTypeForStoreFltAsInt)
     return SDValue();
 
   // Extend f32 values to f64
   if (ResVT.getScalarSizeInBits() == 32) {
     Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
     DCI.AddToWorklist(Val.getNode());
   }

llvm/test/CodeGen/PowerPC/pr45297.ll

-; RUN: not --crash llc -verify-machineinstrs \
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names \
 ; RUN:   -mtriple=powerpc64le-unknown-linux-gnu -mattr=+altivec \
 ; RUN:   -mattr=-power8-vector -mattr=-vsx < %s 2>&1 | FileCheck %s
-; CHECK: LLVM ERROR: Cannot select: {{.*}}: ch = PPCISD::ST_VSR_SCAL_INT<(store 4 into @Global)>
 
 @Global = dso_local global i32 55, align 4
 
 define dso_local void @test(float %0) local_unnamed_addr {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fctiwz f0, f1
+; CHECK-NEXT:    addi r3, r1, -4
+; CHECK-NEXT:    addis r4, r2, Global@toc@ha
+; CHECK-NEXT:    stfiwx f0, 0, r3
+; CHECK-NEXT:    lwz r3, -4(r1)
+; CHECK-NEXT:    stw r3, Global@toc@l(r4)
+; CHECK-NEXT:    blr
 entry:
   %1 = fptosi float %0 to i32
   store i32 %1, i32* @Global, align 4
   ret void
 }