[ARM] Move ConstantIsland and LowOverheadLoops Passes.

[yroux]

Summary

Move ARM ConstantIsland and LowOverheadLopps passes later in thepipeline such that they will be run after the upcoming Machine Outlining pass.

This is a follow-up of ARM Machine Outliner support RFC D57054

[samparker]

LGTM

llvm/lib/Target/ARM/ARMTargetMachine.cpp

public:
   bool addInstSelector() override;
   bool addIRTranslator() override;
   bool addLegalizeMachineIR() override;
   bool addRegBankSelect() override;
   bool addGlobalInstructionSelect() override;
   void addPreRegAlloc() override;
   void addPreSched2() override;
   void addPreEmitPass() override;
+  void addPreEmitPass2() override;
 
   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
 };
 
 class ARMExecutionDomainFix : public ExecutionDomainFix {
 public:
   static char ID;
   ARMExecutionDomainFix() : ExecutionDomainFix(ID, ARM::DPRRegClass) {}
void ARMPassConfig::addPreEmitPass() {
   // Constant island pass work on unbundled instructions.
   addPass(createUnpackMachineBundles([](const MachineFunction &MF) {
     return MF.getSubtarget<ARMSubtarget>().isThumb2();
   }));
 
   // Don't optimize barriers at -O0.
   if (getOptLevel() != CodeGenOpt::None)
     addPass(createARMOptimizeBarriersPass());
+}
 
+void ARMPassConfig::addPreEmitPass2() {
   addPass(createARMConstantIslandPass());
   addPass(createARMLowOverheadLoopsPass());
 
   // Identify valid longjmp targets for Windows Control Flow Guard.
   if (TM->getTargetTriple().isOSWindows())
     addPass(createCFGuardLongjmpPass());
 }

llvm/test/CodeGen/ARM/O3-pipeline.ll

 ; CHECK-NEXT:      MachinePostDominator Tree Construction
 ; CHECK-NEXT:      Branch Probability Basic Block Placement
 ; CHECK-NEXT:      Insert fentry calls
 ; CHECK-NEXT:      Insert XRay ops
 ; CHECK-NEXT:      Implement the 'patchable-function' attribute
 ; CHECK-NEXT:      Thumb2 instruction size reduce pass
 ; CHECK-NEXT:      Unpack machine instruction bundles
 ; CHECK-NEXT:      optimise barriers pass
+; CHECK-NEXT:      Contiguously Lay Out Funclets
+; CHECK-NEXT:      StackMap Liveness Analysis
+; CHECK-NEXT:      Live DEBUG_VALUE analysis
 ; CHECK-NEXT:      MachineDominator Tree Construction
 ; CHECK-NEXT:      ARM constant island placement and branch shortening pass
 ; CHECK-NEXT:      MachineDominator Tree Construction
 ; CHECK-NEXT:      Machine Natural Loop Construction
 ; CHECK-NEXT:      ReachingDefAnalysis
 ; CHECK-NEXT:      ARM Low Overhead Loops pass
-; CHECK-NEXT:      Contiguously Lay Out Funclets
-; CHECK-NEXT:      StackMap Liveness Analysis
-; CHECK-NEXT:      Live DEBUG_VALUE analysis
 ; CHECK-NEXT:      Lazy Machine Block Frequency Analysis
 ; CHECK-NEXT:      Machine Optimization Remark Emitter
 ; CHECK-NEXT:      ARM Assembly Printer
 ; CHECK-NEXT:      Free MachineFunction

llvm/test/DebugInfo/ARM/cfi-eof-prologue.mir

--- |
   !44 = !DILocation(line: 0, scope: !31, inlinedAt: !45)
   !45 = !DILocation(line: 9, scope: !40)
   !46 = !DILocation(line: 9, scope: !31, inlinedAt: !45)
 
 ...
 ---
 name:            _ZN1BC2Ev
 alignment:       2
+tracksRegLiveness: true
 liveins:         
   - { reg: '$r0' }
 frameInfo:       
   stackSize:       8
   maxAlignment:    4
   adjustsStack:    true
   hasCalls:        true
   maxCallFrameSize: 0
 stack:           
   - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default,
       callee-saved-register: '$lr', callee-saved-restored: false }
   - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, stack-id: default,
       callee-saved-register: '$r4' }
 body:             |
   bb.0.entry:
+    liveins: $r0, $r4, $lr
+
     frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r4, -8
     DBG_VALUE debug-use $r0, debug-use $noreg, !33, !DIExpression(), debug-location !35
     $r4 = tMOVr $r0, 14, $noreg
     DBG_VALUE debug-use $r4, debug-use $noreg, !33, !DIExpression(), debug-location !35
     tBL 14, $noreg, @_ZN1AC2Ev, csr_ios, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def dead $r0, debug-location !36
     $r0 = t2MOVi16_ga_pcrel target-flags(arm-lo16, arm-nonlazy) @_ZTV1B, 0, debug-location !36
     $r0 = t2MOVTi16_ga_pcrel killed $r0, target-flags(arm-hi16, arm-nonlazy) @_ZTV1B, 0, debug-location !36
     $r0 = tPICADD killed $r0, 0, debug-location !36
     renamable $r0 = tLDRi killed renamable $r0, 0, 14, $noreg, debug-location !36 :: (load 4 from got)
     renamable $r0, dead $cpsr = nuw tADDi8 killed renamable $r0, 8, 14, $noreg, debug-location !36
     tSTRi killed renamable $r0, renamable $r4, 0, 14, $noreg, debug-location !36 :: (store 4 into %ir.1, !tbaa !37)
     $r0 = tMOVr killed $r4, 14, $noreg, debug-location !36
     tPOP_RET 14, $noreg, def $r4, def $pc, implicit killed $r0, debug-location !36
 
 ...
 ---
 name:            _ZN1BC1Ev
 alignment:       2
+tracksRegLiveness: true
 liveins:         
   - { reg: '$r0' }
 frameInfo:       
   stackSize:       8
   maxAlignment:    4
   adjustsStack:    true
   hasCalls:        true
   maxCallFrameSize: 0
 stack:           
   - { id: 0, type: spill-slot, offset: -4, size: 4, alignment: 4, stack-id: default,
       callee-saved-register: '$lr', callee-saved-restored: false }
   - { id: 1, type: spill-slot, offset: -8, size: 4, alignment: 4, stack-id: default,
       callee-saved-register: '$r4' }
 body:             |
   bb.0.entry:
+    liveins: $r0, $r4, $lr
+
     frame-setup tPUSH 14, $noreg, killed $r4, killed $lr, implicit-def $sp, implicit $sp
     frame-setup CFI_INSTRUCTION def_cfa_offset 8
     frame-setup CFI_INSTRUCTION offset $lr, -4
     frame-setup CFI_INSTRUCTION offset $r4, -8
     DBG_VALUE debug-use $r0, debug-use $noreg, !42, !DIExpression(), debug-location !43
     DBG_VALUE debug-use $r0, debug-use $noreg, !33, !DIExpression(), debug-location !44
     $r4 = tMOVr $r0, 14, $noreg
     DBG_VALUE debug-use $r4, debug-use $noreg, !33, !DIExpression(), debug-location !44

llvm/test/DebugInfo/MIR/ARM/larger-subregister.mir

--- |
   !4 = !{}
   !5 = distinct !DISubprogram(name: "f", scope: !3, file: !3, line: 388, type: !9, scopeLine: 388, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !2, retainedNodes: !4)
   !9 = !DISubroutineType(types: !4)
   !10 = !DILocation(line: 0, scope: !5)
   !12 = !DILocalVariable(name: "boundingRect", arg: 1, scope: !5, file: !3, line: 388, type: !13)
   !13 = !DIDerivedType(tag: DW_TAG_const_type, baseType: !14)
   !14 = !DICompositeType(tag: DW_TAG_structure_type, name: "CGRect", scope: !5, file: !3, line: 46, size: 128, elements: !4, runtimeLang: DW_LANG_Swift, identifier: "$sSo6CGRectVD")
 name:            'f'
+tracksRegLiveness: true
 body:             |
   bb.0:
+    liveins: $r6
+
     DBG_VALUE $s31, $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !10
     DBG_VALUE $q8, $noreg, !12, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !10
     renamable $r0 = t2ADDri $r6, 144, 14, $noreg, $noreg, debug-location !10

llvm/test/DebugInfo/MIR/ARM/param-reg-const-mix.mir

--- |
   !16 = !{!17}
   !17 = !DILocalVariable(name: "p1", arg: 1, scope: !7, file: !1, line: 3, type: !11)
   !18 = !DILocation(line: 3, scope: !7)
   !19 = !DILocation(line: 4, scope: !7)
 
 ...
 ---
 name:            fn1
-tracksRegLiveness: false
+tracksRegLiveness: true
 body:             |
   bb.0.entry:
+    liveins: $r0, $r1, $r4, $lr
+
     $sp = frame-setup STMDB_UPD $sp, 14, $noreg, killed $r4, killed $lr
     $r4 = MOVr $r0, 14, $noreg, $noreg
     DBG_VALUE $r1, $noreg, !17, !DIExpression(DW_OP_LLVM_fragment, 32, 32), debug-location !18
     DBG_VALUE $noreg, $noreg, !17, !DIExpression(DW_OP_LLVM_fragment, 64, 32), debug-location !18
     DBG_VALUE $r4, $noreg, !17, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !18
     $r0 = MOVr killed $r1, 14, $noreg, $noreg, debug-location !19
     BL @fn2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def $r0, debug-location !19
     renamable $r1 = MOVi 0, 14, $noreg, $noreg

llvm/test/DebugInfo/MIR/ARM/subregister-full-piece.mir

--- |
   !4 = !DIFile(filename: "t.cpp", directory: "/")
   !5 = distinct !DISubprogram(name: "f",scope: !4, file: !4, line: 1, type: !6, scopeLine: 1, unit: !3)
   !6 = !DISubroutineType(types: !{})
   !7 = distinct !DICompositeType(tag: DW_TAG_structure_type, name: "uint8x8x2_t", file: !4, line: 113, size: 128, flags: DIFlagTypePassByValue, elements: !{})
   !8 = !DILocalVariable(name: "q8", scope: !5, file: !4, line: 1, type: !7)
   !9 = !DILocalVariable(name: "q9", scope: !5, file: !4, line: 1, type: !7)
   !20 = !DILocation(line: 0, scope: !5)
 name:            f
+tracksRegLiveness: true
 body:             |
   bb.2.for.body:
+    liveins: $r2
+
+    t2CMPri killed renamable $r2, 5, 14, $noreg, implicit-def $cpsr
     t2Bcc %bb.2.for.body, 0, killed $cpsr, debug-location !20
     DBG_VALUE $q8, $noreg, !8, !DIExpression(DW_OP_LLVM_fragment, 0, 64), debug-location !20
     DBG_VALUE $q9, $noreg, !9, !DIExpression(DW_OP_LLVM_fragment, 0, 56), debug-location !20
     tB %bb.2.for.body, 14, $noreg