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Differential D74838

[ARM,MVE] Fix predicate types of some intrinsics
ClosedPublic

Authored by miyuki on Feb 19 2020, 7:54 AM.

Details

Reviewers
simon_tatham
dmgreen
ostannard
MarkMurrayARM
Commits
rG461fd94f004c: [ARM,MVE] Fix predicate types of some intrinsics
Summary

Some predicated MVE intrinsics return a vector with element size
different from the input vector element size. In this case the
predicate must type correspond to the output vector type.

The following intrinsics use the incorrect predicate type:

  • llvm.arm.mve.mull.int.predicated
  • llvm.arm.mve.mull.poly.predicated
  • llvm.arm.mve.vshll.imm.predicated

This patch fixes the issue.

Diff Detail

Event Timeline

miyuki created this revision.Feb 19 2020, 7:54 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptFeb 19 2020, 7:54 AM
Herald added subscribers: llvm-commits, cfe-commits, hiraditya, kristof.beyls. · View Herald Transcript
MarkMurrayARM added a comment.Feb 19 2020, 8:05 AM

Nice catch!

MarkMurrayARM accepted this revision.Feb 19 2020, 8:05 AM
This revision is now accepted and ready to land.Feb 19 2020, 8:05 AM
Harbormaster failed remote builds in B46811: Diff 245407!Feb 19 2020, 8:17 AM
miyuki added a comment.Feb 19 2020, 8:22 AM

The test failure is unrelated

Closed by commit rG461fd94f004c: [ARM,MVE] Fix predicate types of some intrinsics (authored by miyuki). · Explain WhyFeb 19 2020, 8:26 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
clang/
include/
clang/
Basic/
8 lines
2 lines
test/
CodeGen/
arm-mve-intrinsics/
64 lines
24 lines
24 lines
llvm/
lib/
Target/
ARM/
52 lines
test/
CodeGen/
Thumb2/
mve-intrinsics/
132 lines
41 lines
36 lines

Diff 245414

clang/include/clang/Basic/arm_mve.td

Show First 20 Lines • Show All 326 Lines • ▼ Show 20 Lineslet params = T.Usual in {
defm : VectorScalarArithmetic<"add_predicated", "vaddq">; defm : VectorScalarArithmetic<"add_predicated", "vaddq">;
defm : VectorScalarArithmetic<"sub_predicated", "vsubq">; defm : VectorScalarArithmetic<"sub_predicated", "vsubq">;
defm : VectorScalarArithmetic<"mul_predicated", "vmulq">; defm : VectorScalarArithmetic<"mul_predicated", "vmulq">;
} }
multiclass DblVectorVectorArithmetic<string operation, dag extraArgs = (?)> { multiclass DblVectorVectorArithmetic<string operation, dag extraArgs = (?)> {
defm "" : IntrinsicMX< defm "" : IntrinsicMX<
DblVector, (args Vector:$a, Vector:$b, Predicate:$pred), DblVector, (args Vector:$a, Vector:$b, DblPredicate:$pred),
!con((IRInt<operation, [DblVector, Vector, Predicate]> $a, $b), !con((IRInt<operation, [DblVector, Vector, DblPredicate]> $a, $b),
extraArgs, (? $pred, $inactive))>; extraArgs, (? $pred, $inactive))>;
} }
// Predicated intrinsics - Int types only // Predicated intrinsics - Int types only
let params = T.Int in { let params = T.Int in {
defm vminq : VectorVectorArithmetic<"min_predicated", (? (unsignedflag Scalar))>; defm vminq : VectorVectorArithmetic<"min_predicated", (? (unsignedflag Scalar))>;
defm vmaxq : VectorVectorArithmetic<"max_predicated", (? (unsignedflag Scalar))>; defm vmaxq : VectorVectorArithmetic<"max_predicated", (? (unsignedflag Scalar))>;
defm vmulhq : VectorVectorArithmetic<"mulh_predicated", (? (unsignedflag Scalar))>; defm vmulhq : VectorVectorArithmetic<"mulh_predicated", (? (unsignedflag Scalar))>;
▲ Show 20 Lines • Show All 531 Lines • ▼ Show 20 Lines
} }
multiclass vshll_imm<int top> { multiclass vshll_imm<int top> {
let params = !listconcat(T.Int8, T.Int16), pnt = PNT_NType in { let params = !listconcat(T.Int8, T.Int16), pnt = PNT_NType in {
def _n: Intrinsic<DblVector, (args Vector:$v, imm_1toN:$sh), def _n: Intrinsic<DblVector, (args Vector:$v, imm_1toN:$sh),
(IRInt<"vshll_imm", [DblVector, Vector]> (IRInt<"vshll_imm", [DblVector, Vector]>
$v, $sh, (unsignedflag Scalar), top)>; $v, $sh, (unsignedflag Scalar), top)>;
defm "": IntrinsicMX<DblVector, (args Vector:$v, imm_1toN:$sh, defm "": IntrinsicMX<DblVector, (args Vector:$v, imm_1toN:$sh,
Predicate:$pred), DblPredicate:$pred),
(IRInt<"vshll_imm_predicated", [DblVector, Vector, Predicate]> (IRInt<"vshll_imm_predicated", [DblVector, Vector, DblPredicate]>
$v, $sh, (unsignedflag Scalar), top, $pred, $inactive), 1, "_n">; $v, $sh, (unsignedflag Scalar), top, $pred, $inactive), 1, "_n">;
} }
} }
defm vshllbq : vshll_imm<0>; defm vshllbq : vshll_imm<0>;
defm vshlltq : vshll_imm<1>; defm vshlltq : vshll_imm<1>;
multiclass DyadicImmShift<Type outtype, Immediate imm, string intname = NAME, multiclass DyadicImmShift<Type outtype, Immediate imm, string intname = NAME,
dag extraargs = (?)> { dag extraargs = (?)> {
▲ Show 20 Lines • Show All 395 Lines • Show Last 20 Lines

clang/include/clang/Basic/arm_mve_defs.td

Show First 20 Lines • Show All 312 Lines • ▼ Show 20 Lines
// UScalar and UVector expand to the unsigned-integer versions of // UScalar and UVector expand to the unsigned-integer versions of
// Scalar and Vector. SScalar and SVector are signed-integer versions. // Scalar and Vector. SScalar and SVector are signed-integer versions.
def UScalar: Unsigned<Scalar>; def UScalar: Unsigned<Scalar>;
def UVector: VecOf<UScalar>; def UVector: VecOf<UScalar>;
def SScalar: Signed<Scalar>; def SScalar: Signed<Scalar>;
def SVector: VecOf<SScalar>; def SVector: VecOf<SScalar>;
// DblVector expands to a vector of scalars of size twice the size of Scalar. // DblVector expands to a vector of scalars of size twice the size of Scalar.
// DblPredicate expands to a predicate corresponding to DblVector
// HalfVector, similarly, expands to a vector of half-sized scalars. And // HalfVector, similarly, expands to a vector of half-sized scalars. And
// UHalfVector is a vector of half-sized _unsigned integers_. // UHalfVector is a vector of half-sized _unsigned integers_.
def DblVector: VecOf<DoubleSize<Scalar>>; def DblVector: VecOf<DoubleSize<Scalar>>;
def DblPredicate: PredOf<DoubleSize<Scalar>>;
def HalfVector: VecOf<HalfSize<Scalar>>; def HalfVector: VecOf<HalfSize<Scalar>>;
def UHalfVector: VecOf<Unsigned<HalfSize<Scalar>>>; def UHalfVector: VecOf<Unsigned<HalfSize<Scalar>>>;
// Expands to the 32-bit integer of the same signedness as Scalar. // Expands to the 32-bit integer of the same signedness as Scalar.
def Scalar32: CopyKind<u32, Scalar>; def Scalar32: CopyKind<u32, Scalar>;
// Expands to the 64-bit integer of the same signedness as Scalar. // Expands to the 64-bit integer of the same signedness as Scalar.
def Scalar64: CopyKind<u64, Scalar>; def Scalar64: CopyKind<u64, Scalar>;
▲ Show 20 Lines • Show All 246 Lines • Show Last 20 Lines

clang/test/CodeGen/arm-mve-intrinsics/vector-shift-imm.c

Show First 20 Lines • Show All 1,376 Lines • ▼ Show 20 Lines
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshlltq_n_u16(a, 14); return vshlltq_n_u16(a, 14);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vshllbq_m_n_s8( // CHECK-LABEL: @test_vshllbq_m_n_s8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 6, i32 0, i32 0, <16 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> [[A:%.*]], i32 6, i32 0, i32 0, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
int16x8_t test_vshllbq_m_n_s8(int16x8_t inactive, int8x16_t a, mve_pred16_t p) int16x8_t test_vshllbq_m_n_s8(int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vshllbq_m(inactive, a, 6, p); return vshllbq_m(inactive, a, 6, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshllbq_m_n_s8(inactive, a, 6, p); return vshllbq_m_n_s8(inactive, a, 6, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vshllbq_m_n_s16( // CHECK-LABEL: @test_vshllbq_m_n_s16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 10, i32 0, i32 0, <8 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> [[A:%.*]], i32 10, i32 0, i32 0, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
int32x4_t test_vshllbq_m_n_s16(int32x4_t inactive, int16x8_t a, mve_pred16_t p) int32x4_t test_vshllbq_m_n_s16(int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vshllbq_m(inactive, a, 10, p); return vshllbq_m(inactive, a, 10, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshllbq_m_n_s16(inactive, a, 10, p); return vshllbq_m_n_s16(inactive, a, 10, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vshllbq_m_n_u8( // CHECK-LABEL: @test_vshllbq_m_n_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 3, i32 1, i32 0, <16 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> [[A:%.*]], i32 3, i32 1, i32 0, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
uint16x8_t test_vshllbq_m_n_u8(uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) uint16x8_t test_vshllbq_m_n_u8(uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vshllbq_m(inactive, a, 3, p); return vshllbq_m(inactive, a, 3, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshllbq_m_n_u8(inactive, a, 3, p); return vshllbq_m_n_u8(inactive, a, 3, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vshllbq_m_n_u16( // CHECK-LABEL: @test_vshllbq_m_n_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 14, i32 1, i32 0, <8 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> [[A:%.*]], i32 14, i32 1, i32 0, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
uint32x4_t test_vshllbq_m_n_u16(uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) uint32x4_t test_vshllbq_m_n_u16(uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vshllbq_m(inactive, a, 14, p); return vshllbq_m(inactive, a, 14, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshllbq_m_n_u16(inactive, a, 14, p); return vshllbq_m_n_u16(inactive, a, 14, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vshlltq_m_n_s8( // CHECK-LABEL: @test_vshlltq_m_n_s8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 4, i32 0, i32 1, <16 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> [[A:%.*]], i32 4, i32 0, i32 1, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
int16x8_t test_vshlltq_m_n_s8(int16x8_t inactive, int8x16_t a, mve_pred16_t p) int16x8_t test_vshlltq_m_n_s8(int16x8_t inactive, int8x16_t a, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vshlltq_m(inactive, a, 4, p); return vshlltq_m(inactive, a, 4, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshlltq_m_n_s8(inactive, a, 4, p); return vshlltq_m_n_s8(inactive, a, 4, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vshlltq_m_n_s16( // CHECK-LABEL: @test_vshlltq_m_n_s16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 12, i32 0, i32 1, <8 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> [[A:%.*]], i32 12, i32 0, i32 1, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
int32x4_t test_vshlltq_m_n_s16(int32x4_t inactive, int16x8_t a, mve_pred16_t p) int32x4_t test_vshlltq_m_n_s16(int32x4_t inactive, int16x8_t a, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vshlltq_m(inactive, a, 12, p); return vshlltq_m(inactive, a, 12, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshlltq_m_n_s16(inactive, a, 12, p); return vshlltq_m_n_s16(inactive, a, 12, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vshlltq_m_n_u8( // CHECK-LABEL: @test_vshlltq_m_n_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 2, i32 1, i32 1, <16 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> [[A:%.*]], i32 2, i32 1, i32 1, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
uint16x8_t test_vshlltq_m_n_u8(uint16x8_t inactive, uint8x16_t a, mve_pred16_t p) uint16x8_t test_vshlltq_m_n_u8(uint16x8_t inactive, uint8x16_t a, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vshlltq_m(inactive, a, 2, p); return vshlltq_m(inactive, a, 2, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshlltq_m_n_u8(inactive, a, 2, p); return vshlltq_m_n_u8(inactive, a, 2, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vshlltq_m_n_u16( // CHECK-LABEL: @test_vshlltq_m_n_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 9, i32 1, i32 1, <8 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> [[A:%.*]], i32 9, i32 1, i32 1, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
uint32x4_t test_vshlltq_m_n_u16(uint32x4_t inactive, uint16x8_t a, mve_pred16_t p) uint32x4_t test_vshlltq_m_n_u16(uint32x4_t inactive, uint16x8_t a, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vshlltq_m(inactive, a, 9, p); return vshlltq_m(inactive, a, 9, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshlltq_m_n_u16(inactive, a, 9, p); return vshlltq_m_n_u16(inactive, a, 9, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vshllbq_x_n_s8( // CHECK-LABEL: @test_vshllbq_x_n_s8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 1, i32 0, i32 0, <16 x i1> [[TMP1]], <8 x i16> undef) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> [[A:%.*]], i32 1, i32 0, i32 0, <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
int16x8_t test_vshllbq_x_n_s8(int8x16_t a, mve_pred16_t p) int16x8_t test_vshllbq_x_n_s8(int8x16_t a, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vshllbq_x(a, 1, p); return vshllbq_x(a, 1, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshllbq_x_n_s8(a, 1, p); return vshllbq_x_n_s8(a, 1, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vshllbq_x_n_s16( // CHECK-LABEL: @test_vshllbq_x_n_s16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 10, i32 0, i32 0, <8 x i1> [[TMP1]], <4 x i32> undef) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> [[A:%.*]], i32 10, i32 0, i32 0, <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
int32x4_t test_vshllbq_x_n_s16(int16x8_t a, mve_pred16_t p) int32x4_t test_vshllbq_x_n_s16(int16x8_t a, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vshllbq_x(a, 10, p); return vshllbq_x(a, 10, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshllbq_x_n_s16(a, 10, p); return vshllbq_x_n_s16(a, 10, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vshllbq_x_n_u8( // CHECK-LABEL: @test_vshllbq_x_n_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 6, i32 1, i32 0, <16 x i1> [[TMP1]], <8 x i16> undef) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> [[A:%.*]], i32 6, i32 1, i32 0, <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
uint16x8_t test_vshllbq_x_n_u8(uint8x16_t a, mve_pred16_t p) uint16x8_t test_vshllbq_x_n_u8(uint8x16_t a, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vshllbq_x(a, 6, p); return vshllbq_x(a, 6, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshllbq_x_n_u8(a, 6, p); return vshllbq_x_n_u8(a, 6, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vshllbq_x_n_u16( // CHECK-LABEL: @test_vshllbq_x_n_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 10, i32 1, i32 0, <8 x i1> [[TMP1]], <4 x i32> undef) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> [[A:%.*]], i32 10, i32 1, i32 0, <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
uint32x4_t test_vshllbq_x_n_u16(uint16x8_t a, mve_pred16_t p) uint32x4_t test_vshllbq_x_n_u16(uint16x8_t a, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vshllbq_x(a, 10, p); return vshllbq_x(a, 10, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshllbq_x_n_u16(a, 10, p); return vshllbq_x_n_u16(a, 10, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vshlltq_x_n_s8( // CHECK-LABEL: @test_vshlltq_x_n_s8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 2, i32 0, i32 1, <16 x i1> [[TMP1]], <8 x i16> undef) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> [[A:%.*]], i32 2, i32 0, i32 1, <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
int16x8_t test_vshlltq_x_n_s8(int8x16_t a, mve_pred16_t p) int16x8_t test_vshlltq_x_n_s8(int8x16_t a, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vshlltq_x(a, 2, p); return vshlltq_x(a, 2, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshlltq_x_n_s8(a, 2, p); return vshlltq_x_n_s8(a, 2, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vshlltq_x_n_s16( // CHECK-LABEL: @test_vshlltq_x_n_s16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 6, i32 0, i32 1, <8 x i1> [[TMP1]], <4 x i32> undef) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> [[A:%.*]], i32 6, i32 0, i32 1, <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
int32x4_t test_vshlltq_x_n_s16(int16x8_t a, mve_pred16_t p) int32x4_t test_vshlltq_x_n_s16(int16x8_t a, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vshlltq_x(a, 6, p); return vshlltq_x(a, 6, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshlltq_x_n_s16(a, 6, p); return vshlltq_x_n_s16(a, 6, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vshlltq_x_n_u8( // CHECK-LABEL: @test_vshlltq_x_n_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], i32 5, i32 1, i32 1, <16 x i1> [[TMP1]], <8 x i16> undef) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> [[A:%.*]], i32 5, i32 1, i32 1, <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
uint16x8_t test_vshlltq_x_n_u8(uint8x16_t a, mve_pred16_t p) uint16x8_t test_vshlltq_x_n_u8(uint8x16_t a, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vshlltq_x(a, 5, p); return vshlltq_x(a, 5, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshlltq_x_n_u8(a, 5, p); return vshlltq_x_n_u8(a, 5, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vshlltq_x_n_u16( // CHECK-LABEL: @test_vshlltq_x_n_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], i32 3, i32 1, i32 1, <8 x i1> [[TMP1]], <4 x i32> undef) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> [[A:%.*]], i32 3, i32 1, i32 1, <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
uint32x4_t test_vshlltq_x_n_u16(uint16x8_t a, mve_pred16_t p) uint32x4_t test_vshlltq_x_n_u16(uint16x8_t a, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vshlltq_x(a, 3, p); return vshlltq_x(a, 3, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vshlltq_x_n_u16(a, 3, p); return vshlltq_x_n_u16(a, 3, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }

clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmullbq_poly_p16(a, b); return vmullbq_poly_p16(a, b);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmullbq_int_m_s8( // CHECK-LABEL: @test_vmullbq_int_m_s8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 0, <16 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 0, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
int16x8_t test_vmullbq_int_m_s8(int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) int16x8_t test_vmullbq_int_m_s8(int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmullbq_int_m(inactive, a, b, p); return vmullbq_int_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmullbq_int_m_s8(inactive, a, b, p); return vmullbq_int_m_s8(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmullbq_int_m_u16( // CHECK-LABEL: @test_vmullbq_int_m_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 0, <8 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 0, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
uint32x4_t test_vmullbq_int_m_u16(uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) uint32x4_t test_vmullbq_int_m_u16(uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmullbq_int_m(inactive, a, b, p); return vmullbq_int_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmullbq_int_m_u16(inactive, a, b, p); return vmullbq_int_m_u16(inactive, a, b, p);
Show All 14 Lines
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmullbq_int_m_s32(inactive, a, b, p); return vmullbq_int_m_s32(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmullbq_poly_m_p8( // CHECK-LABEL: @test_vmullbq_poly_m_p8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, <16 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
uint16x8_t test_vmullbq_poly_m_p8(uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) uint16x8_t test_vmullbq_poly_m_p8(uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmullbq_poly_m(inactive, a, b, p); return vmullbq_poly_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmullbq_poly_m_p8(inactive, a, b, p); return vmullbq_poly_m_p8(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmullbq_int_x_u8( // CHECK-LABEL: @test_vmullbq_int_x_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 0, <16 x i1> [[TMP1]], <8 x i16> undef) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 0, <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
uint16x8_t test_vmullbq_int_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p) uint16x8_t test_vmullbq_int_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmullbq_int_x(a, b, p); return vmullbq_int_x(a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmullbq_int_x_u8(a, b, p); return vmullbq_int_x_u8(a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmullbq_int_x_s16( // CHECK-LABEL: @test_vmullbq_int_x_s16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 0, <8 x i1> [[TMP1]], <4 x i32> undef) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 0, <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
int32x4_t test_vmullbq_int_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p) int32x4_t test_vmullbq_int_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmullbq_int_x(a, b, p); return vmullbq_int_x(a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmullbq_int_x_s16(a, b, p); return vmullbq_int_x_s16(a, b, p);
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#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmullbq_int_x_u32(a, b, p); return vmullbq_int_x_u32(a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmullbq_poly_x_p16( // CHECK-LABEL: @test_vmullbq_poly_x_p16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.poly.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, <8 x i1> [[TMP1]], <4 x i32> undef) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.poly.predicated.v4i32.v8i16.v4i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
uint32x4_t test_vmullbq_poly_x_p16(uint16x8_t a, uint16x8_t b, mve_pred16_t p) uint32x4_t test_vmullbq_poly_x_p16(uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmullbq_poly_x(a, b, p); return vmullbq_poly_x(a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmullbq_poly_x_p16(a, b, p); return vmullbq_poly_x_p16(a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }

clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmulltq_poly_p16(a, b); return vmulltq_poly_p16(a, b);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmulltq_int_m_s8( // CHECK-LABEL: @test_vmulltq_int_m_s8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 1, <16 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, i32 1, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
int16x8_t test_vmulltq_int_m_s8(int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) int16x8_t test_vmulltq_int_m_s8(int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmulltq_int_m(inactive, a, b, p); return vmulltq_int_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmulltq_int_m_s8(inactive, a, b, p); return vmulltq_int_m_s8(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmulltq_int_m_u16( // CHECK-LABEL: @test_vmulltq_int_m_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 1, <8 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, i32 1, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
uint32x4_t test_vmulltq_int_m_u16(uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) uint32x4_t test_vmulltq_int_m_u16(uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmulltq_int_m(inactive, a, b, p); return vmulltq_int_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmulltq_int_m_u16(inactive, a, b, p); return vmulltq_int_m_u16(inactive, a, b, p);
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#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmulltq_int_m_s32(inactive, a, b, p); return vmulltq_int_m_s32(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmulltq_poly_m_p8( // CHECK-LABEL: @test_vmulltq_poly_m_p8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, <16 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
uint16x8_t test_vmulltq_poly_m_p8(uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) uint16x8_t test_vmulltq_poly_m_p8(uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmulltq_poly_m(inactive, a, b, p); return vmulltq_poly_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmulltq_poly_m_p8(inactive, a, b, p); return vmulltq_poly_m_p8(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmulltq_int_x_u8( // CHECK-LABEL: @test_vmulltq_int_x_u8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 1, <16 x i1> [[TMP1]], <8 x i16> undef) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, i32 1, <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
uint16x8_t test_vmulltq_int_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p) uint16x8_t test_vmulltq_int_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmulltq_int_x(a, b, p); return vmulltq_int_x(a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmulltq_int_x_u8(a, b, p); return vmulltq_int_x_u8(a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmulltq_int_x_s16( // CHECK-LABEL: @test_vmulltq_int_x_s16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 1, <8 x i1> [[TMP1]], <4 x i32> undef) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, i32 1, <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
int32x4_t test_vmulltq_int_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p) int32x4_t test_vmulltq_int_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmulltq_int_x(a, b, p); return vmulltq_int_x(a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmulltq_int_x_s16(a, b, p); return vmulltq_int_x_s16(a, b, p);
Show All 14 Lines
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmulltq_int_x_u32(a, b, p); return vmulltq_int_x_u32(a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmulltq_poly_x_p8( // CHECK-LABEL: @test_vmulltq_poly_x_p8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, <16 x i1> [[TMP1]], <8 x i16> undef) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
uint16x8_t test_vmulltq_poly_x_p8(uint8x16_t a, uint8x16_t b, mve_pred16_t p) uint16x8_t test_vmulltq_poly_x_p8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmulltq_poly_x(a, b, p); return vmulltq_poly_x(a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmulltq_poly_x_p8(a, b, p); return vmulltq_poly_x_p8(a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }

llvm/lib/Target/ARM/ARMInstrMVE.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 233 Lines • ▼ Show 20 Linesclass mve_addr_q_shift<int shift> : MemOperand {
let ParserMatchClass = let ParserMatchClass =
!cast<AsmOperandClass>("MemRegQS"#shift#"OffsetAsmOperand"); !cast<AsmOperandClass>("MemRegQS"#shift#"OffsetAsmOperand");
let DecoderMethod = "DecodeMveAddrModeQ<"#shift#">"; let DecoderMethod = "DecodeMveAddrModeQ<"#shift#">";
let MIOperandInfo = (ops MQPR:$base, i32imm:$imm); let MIOperandInfo = (ops MQPR:$base, i32imm:$imm);
} }
// A family of classes wrapping up information about the vector types // A family of classes wrapping up information about the vector types
// used by MVE. // used by MVE.
class MVEVectorVTInfo<ValueType vec, ValueType dblvec, ValueType pred, class MVEVectorVTInfo<ValueType vec, ValueType dblvec,
ValueType pred, ValueType dblpred,
bits<2> size, string suffixletter, bit unsigned> { bits<2> size, string suffixletter, bit unsigned> {
// The LLVM ValueType representing the vector, so we can use it in // The LLVM ValueType representing the vector, so we can use it in
// ISel patterns. // ISel patterns.
ValueType Vec = vec; ValueType Vec = vec;
// The LLVM ValueType representing a vector with elements double the size // The LLVM ValueType representing a vector with elements double the size
// of those in Vec, so we can use it in ISel patterns. It is up to the // of those in Vec, so we can use it in ISel patterns. It is up to the
// invoker of this class to ensure that this is a correct choice. // invoker of this class to ensure that this is a correct choice.
ValueType DblVec = dblvec; ValueType DblVec = dblvec;
// An LLVM ValueType representing a corresponding vector of // An LLVM ValueType representing a corresponding vector of
// predicate bits, for use in ISel patterns that handle an IR // predicate bits, for use in ISel patterns that handle an IR
// intrinsic describing the predicated form of the instruction. // intrinsic describing the predicated form of the instruction.
// //
// Usually, for a vector of N things, this will be vNi1. But for // Usually, for a vector of N things, this will be vNi1. But for
// vectors of 2 values, we make an exception, and use v4i1 instead // vectors of 2 values, we make an exception, and use v4i1 instead
// of v2i1. Rationale: MVE codegen doesn't support doing all the // of v2i1. Rationale: MVE codegen doesn't support doing all the
// auxiliary operations on v2i1 (vector shuffles etc), and also, // auxiliary operations on v2i1 (vector shuffles etc), and also,
// there's no MVE compare instruction that will _generate_ v2i1 // there's no MVE compare instruction that will _generate_ v2i1
// directly. // directly.
ValueType Pred = pred; ValueType Pred = pred;
// Same as Pred but for DblVec rather than Vec.
ValueType DblPred = dblpred;
// The most common representation of the vector element size in MVE // The most common representation of the vector element size in MVE
// instruction encodings: a 2-bit value V representing an (8<<V)-bit // instruction encodings: a 2-bit value V representing an (8<<V)-bit
// vector element. // vector element.
bits<2> Size = size; bits<2> Size = size;
// For vectors explicitly mentioning a signedness of integers: 0 for // For vectors explicitly mentioning a signedness of integers: 0 for
// signed and 1 for unsigned. For anything else, undefined. // signed and 1 for unsigned. For anything else, undefined.
bit Unsigned = unsigned; bit Unsigned = unsigned;
Show All 10 Linesclass MVEVectorVTInfo<ValueType vec, ValueType dblvec,
// The suffix used on an instruction that mentions the whole type. // The suffix used on an instruction that mentions the whole type.
string Suffix = suffixletter ## BitsSuffix; string Suffix = suffixletter ## BitsSuffix;
// The letter part of the suffix only. // The letter part of the suffix only.
string SuffixLetter = suffixletter; string SuffixLetter = suffixletter;
} }
// Integer vector types that don't treat signed and unsigned differently. // Integer vector types that don't treat signed and unsigned differently.
def MVE_v16i8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, 0b00, "i", ?>; def MVE_v16i8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "i", ?>;
def MVE_v8i16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, 0b01, "i", ?>; def MVE_v8i16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "i", ?>;
def MVE_v4i32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, 0b10, "i", ?>; def MVE_v4i32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, v4i1, 0b10, "i", ?>;
def MVE_v2i64 : MVEVectorVTInfo<v2i64, ?, v4i1, 0b11, "i", ?>; def MVE_v2i64 : MVEVectorVTInfo<v2i64, ?, v4i1, ?, 0b11, "i", ?>;
// Explicitly signed and unsigned integer vectors. They map to the // Explicitly signed and unsigned integer vectors. They map to the
// same set of LLVM ValueTypes as above, but are represented // same set of LLVM ValueTypes as above, but are represented
// differently in assembly and instruction encodings. // differently in assembly and instruction encodings.
def MVE_v16s8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, 0b00, "s", 0b0>; def MVE_v16s8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "s", 0b0>;
def MVE_v8s16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, 0b01, "s", 0b0>; def MVE_v8s16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "s", 0b0>;
def MVE_v4s32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, 0b10, "s", 0b0>; def MVE_v4s32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, v4i1, 0b10, "s", 0b0>;
def MVE_v2s64 : MVEVectorVTInfo<v2i64, ?, v4i1, 0b11, "s", 0b0>; def MVE_v2s64 : MVEVectorVTInfo<v2i64, ?, v4i1, ?, 0b11, "s", 0b0>;
def MVE_v16u8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, 0b00, "u", 0b1>; def MVE_v16u8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b00, "u", 0b1>;
def MVE_v8u16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, 0b01, "u", 0b1>; def MVE_v8u16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b01, "u", 0b1>;
def MVE_v4u32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, 0b10, "u", 0b1>; def MVE_v4u32 : MVEVectorVTInfo<v4i32, v2i64, v4i1, v4i1, 0b10, "u", 0b1>;
def MVE_v2u64 : MVEVectorVTInfo<v2i64, ?, v4i1, 0b11, "u", 0b1>; def MVE_v2u64 : MVEVectorVTInfo<v2i64, ?, v4i1, ?, 0b11, "u", 0b1>;
// FP vector types. // FP vector types.
def MVE_v8f16 : MVEVectorVTInfo<v8f16, v4f32, v8i1, 0b01, "f", ?>; def MVE_v8f16 : MVEVectorVTInfo<v8f16, v4f32, v8i1, v4i1, 0b01, "f", ?>;
def MVE_v4f32 : MVEVectorVTInfo<v4f32, v2f64, v4i1, 0b10, "f", ?>; def MVE_v4f32 : MVEVectorVTInfo<v4f32, v2f64, v4i1, v4i1, 0b10, "f", ?>;
def MVE_v2f64 : MVEVectorVTInfo<v2f64, ?, v4i1, 0b11, "f", ?>; def MVE_v2f64 : MVEVectorVTInfo<v2f64, ?, v4i1, ?, 0b11, "f", ?>;
// Polynomial vector types. // Polynomial vector types.
def MVE_v16p8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, 0b11, "p", 0b0>; def MVE_v16p8 : MVEVectorVTInfo<v16i8, v8i16, v16i1, v8i1, 0b11, "p", 0b0>;
def MVE_v8p16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, 0b11, "p", 0b1>; def MVE_v8p16 : MVEVectorVTInfo<v8i16, v4i32, v8i1, v4i1, 0b11, "p", 0b1>;
// --------- Start of base classes for the instructions themselves // --------- Start of base classes for the instructions themselves
class MVE_MI<dag oops, dag iops, InstrItinClass itin, string asm, class MVE_MI<dag oops, dag iops, InstrItinClass itin, string asm,
string ops, string cstr, list<dag> pattern> string ops, string cstr, list<dag> pattern>
: Thumb2XI<oops, iops, AddrModeNone, 4, itin, !strconcat(asm, "\t", ops), cstr, : Thumb2XI<oops, iops, AddrModeNone, 4, itin, !strconcat(asm, "\t", ops), cstr,
pattern>, pattern>,
Requires<[HasMVEInt]> { Requires<[HasMVEInt]> {
▲ Show 20 Lines • Show All 2,285 Lines • ▼ Show 20 Lines def : Pat<(VTI.DblVec (unpred_int (VTI.Vec MQPR:$src), imm:$imm,
(i32 VTI.Unsigned), (i32 top))), (i32 VTI.Unsigned), (i32 top))),
(VTI.DblVec (inst_imm (VTI.Vec MQPR:$src), imm:$imm))>; (VTI.DblVec (inst_imm (VTI.Vec MQPR:$src), imm:$imm))>;
def : Pat<(VTI.DblVec (unpred_int (VTI.Vec MQPR:$src), (i32 VTI.LaneBits), def : Pat<(VTI.DblVec (unpred_int (VTI.Vec MQPR:$src), (i32 VTI.LaneBits),
(i32 VTI.Unsigned), (i32 top))), (i32 VTI.Unsigned), (i32 top))),
(VTI.DblVec (inst_lw (VTI.Vec MQPR:$src)))>; (VTI.DblVec (inst_lw (VTI.Vec MQPR:$src)))>;
def : Pat<(VTI.DblVec (pred_int (VTI.Vec MQPR:$src), imm:$imm, def : Pat<(VTI.DblVec (pred_int (VTI.Vec MQPR:$src), imm:$imm,
(i32 VTI.Unsigned), (i32 top), (i32 VTI.Unsigned), (i32 top),
(VTI.Pred VCCR:$mask), (VTI.DblPred VCCR:$mask),
(VTI.DblVec MQPR:$inactive))), (VTI.DblVec MQPR:$inactive))),
(VTI.DblVec (inst_imm (VTI.Vec MQPR:$src), imm:$imm, (VTI.DblVec (inst_imm (VTI.Vec MQPR:$src), imm:$imm,
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.DblPred VCCR:$mask),
(VTI.DblVec MQPR:$inactive)))>; (VTI.DblVec MQPR:$inactive)))>;
def : Pat<(VTI.DblVec (pred_int (VTI.Vec MQPR:$src), (i32 VTI.LaneBits), def : Pat<(VTI.DblVec (pred_int (VTI.Vec MQPR:$src), (i32 VTI.LaneBits),
(i32 VTI.Unsigned), (i32 top), (i32 VTI.Unsigned), (i32 top),
(VTI.Pred VCCR:$mask), (VTI.DblPred VCCR:$mask),
(VTI.DblVec MQPR:$inactive))), (VTI.DblVec MQPR:$inactive))),
(VTI.DblVec (inst_lw (VTI.Vec MQPR:$src), ARMVCCThen, (VTI.DblVec (inst_lw (VTI.Vec MQPR:$src), ARMVCCThen,
(VTI.Pred VCCR:$mask), (VTI.DblPred VCCR:$mask),
(VTI.DblVec MQPR:$inactive)))>; (VTI.DblVec MQPR:$inactive)))>;
} }
foreach VTI = [MVE_v16s8, MVE_v8s16, MVE_v16u8, MVE_v8u16] in foreach VTI = [MVE_v16s8, MVE_v8s16, MVE_v16u8, MVE_v8u16] in
foreach top = [0, 1] in foreach top = [0, 1] in
defm : MVE_VSHLL_patterns<VTI, top>; defm : MVE_VSHLL_patterns<VTI, top>;
class MVE_shift_imm_partial<Operand imm, string iname, string suffix> class MVE_shift_imm_partial<Operand imm, string iname, string suffix>
▲ Show 20 Lines • Show All 1,641 Lines • ▼ Show 20 Lines let Predicates = [HasMVEInt] in {
def : Pat<(VTI.DblVec !con((unpred_op (VTI.Vec MQPR:$Qm), def : Pat<(VTI.DblVec !con((unpred_op (VTI.Vec MQPR:$Qm),
(VTI.Vec MQPR:$Qn)), (VTI.Vec MQPR:$Qn)),
uflag, (? (i32 Top)))), uflag, (? (i32 Top)))),
(VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>; (VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
// Predicated multiply // Predicated multiply
def : Pat<(VTI.DblVec !con((pred_int (VTI.Vec MQPR:$Qm), def : Pat<(VTI.DblVec !con((pred_int (VTI.Vec MQPR:$Qm),
(VTI.Vec MQPR:$Qn)), (VTI.Vec MQPR:$Qn)),
uflag, (? (i32 Top), (VTI.Pred VCCR:$mask), uflag, (? (i32 Top), (VTI.DblPred VCCR:$mask),
(VTI.DblVec MQPR:$inactive)))), (VTI.DblVec MQPR:$inactive)))),
(VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.DblVec (Inst (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.DblPred VCCR:$mask),
(VTI.DblVec MQPR:$inactive)))>; (VTI.DblVec MQPR:$inactive)))>;
} }
} }
// For polynomial multiplies, the size bits take the unused value 0b11, and // For polynomial multiplies, the size bits take the unused value 0b11, and
// the unsigned bit switches to encoding the size. // the unsigned bit switches to encoding the size.
defm MVE_VMULLBs8 : MVE_VMULL_m<MVE_v16s8, int_arm_mve_vmull, defm MVE_VMULLBs8 : MVE_VMULL_m<MVE_v16s8, int_arm_mve_vmull,
▲ Show 20 Lines • Show All 2,466 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-intrinsics/vector-shift-imm.ll

Show First 20 Lines • Show All 992 Lines • ▼ Show 20 Lines
; CHECK-LABEL: test_vshllbq_m_n_s8: ; CHECK-LABEL: test_vshllbq_m_n_s8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshllbt.s8 q0, q1, #6 ; CHECK-NEXT: vshllbt.s8 q0, q1, #6
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, i32 6, i32 0, i32 0, <16 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 6, i32 0, i32 0, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_m_n_s8_lanewidth(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_m_n_s8_lanewidth(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshllbq_m_n_s8_lanewidth: ; CHECK-LABEL: test_vshllbq_m_n_s8_lanewidth:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshllbt.s8 q0, q1, #8 ; CHECK-NEXT: vshllbt.s8 q0, q1, #8
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, i32 8, i32 0, i32 0, <16 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 8, i32 0, i32 0, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_m_n_s16(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_m_n_s16(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshllbq_m_n_s16: ; CHECK-LABEL: test_vshllbq_m_n_s16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshllbt.s16 q0, q1, #10 ; CHECK-NEXT: vshllbt.s16 q0, q1, #10
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, i32 10, i32 0, i32 0, <8 x i1> %1, <4 x i32> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 10, i32 0, i32 0, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_m_n_s16_lanewidth(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_m_n_s16_lanewidth(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshllbq_m_n_s16_lanewidth: ; CHECK-LABEL: test_vshllbq_m_n_s16_lanewidth:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshllbt.s16 q0, q1, #16 ; CHECK-NEXT: vshllbt.s16 q0, q1, #16
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, i32 16, i32 0, i32 0, <8 x i1> %1, <4 x i32> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 16, i32 0, i32 0, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_m_n_u8(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_m_n_u8(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshllbq_m_n_u8: ; CHECK-LABEL: test_vshllbq_m_n_u8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshllbt.u8 q0, q1, #3 ; CHECK-NEXT: vshllbt.u8 q0, q1, #3
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, i32 3, i32 1, i32 0, <16 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 3, i32 1, i32 0, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_m_n_u8_lanewidth(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_m_n_u8_lanewidth(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshllbq_m_n_u8_lanewidth: ; CHECK-LABEL: test_vshllbq_m_n_u8_lanewidth:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshllbt.u8 q0, q1, #8 ; CHECK-NEXT: vshllbt.u8 q0, q1, #8
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, i32 8, i32 1, i32 0, <16 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 8, i32 1, i32 0, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_m_n_u16(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_m_n_u16(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshllbq_m_n_u16: ; CHECK-LABEL: test_vshllbq_m_n_u16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshllbt.u16 q0, q1, #14 ; CHECK-NEXT: vshllbt.u16 q0, q1, #14
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, i32 14, i32 1, i32 0, <8 x i1> %1, <4 x i32> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 14, i32 1, i32 0, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_m_n_u16_lanewidth(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_m_n_u16_lanewidth(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshllbq_m_n_u16_lanewidth: ; CHECK-LABEL: test_vshllbq_m_n_u16_lanewidth:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshllbt.u16 q0, q1, #16 ; CHECK-NEXT: vshllbt.u16 q0, q1, #16
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, i32 16, i32 1, i32 0, <8 x i1> %1, <4 x i32> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 16, i32 1, i32 0, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_m_n_s8(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_m_n_s8(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshlltq_m_n_s8: ; CHECK-LABEL: test_vshlltq_m_n_s8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshlltt.s8 q0, q1, #4 ; CHECK-NEXT: vshlltt.s8 q0, q1, #4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, i32 4, i32 0, i32 1, <16 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 4, i32 0, i32 1, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_m_n_s8_lanewidth(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_m_n_s8_lanewidth(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshlltq_m_n_s8_lanewidth: ; CHECK-LABEL: test_vshlltq_m_n_s8_lanewidth:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshlltt.s8 q0, q1, #8 ; CHECK-NEXT: vshlltt.s8 q0, q1, #8
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, i32 8, i32 0, i32 1, <16 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 8, i32 0, i32 1, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_m_n_s16(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_m_n_s16(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshlltq_m_n_s16: ; CHECK-LABEL: test_vshlltq_m_n_s16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshlltt.s16 q0, q1, #12 ; CHECK-NEXT: vshlltt.s16 q0, q1, #12
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, i32 12, i32 0, i32 1, <8 x i1> %1, <4 x i32> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 12, i32 0, i32 1, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_m_n_s16_lanewidth(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_m_n_s16_lanewidth(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshlltq_m_n_s16_lanewidth: ; CHECK-LABEL: test_vshlltq_m_n_s16_lanewidth:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshlltt.s16 q0, q1, #16 ; CHECK-NEXT: vshlltt.s16 q0, q1, #16
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, i32 16, i32 0, i32 1, <8 x i1> %1, <4 x i32> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 16, i32 0, i32 1, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_m_n_u8(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_m_n_u8(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshlltq_m_n_u8: ; CHECK-LABEL: test_vshlltq_m_n_u8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshlltt.u8 q0, q1, #2 ; CHECK-NEXT: vshlltt.u8 q0, q1, #2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, i32 2, i32 1, i32 1, <16 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 2, i32 1, i32 1, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_m_n_u8_lanewidth(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_m_n_u8_lanewidth(<8 x i16> %inactive, <16 x i8> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshlltq_m_n_u8_lanewidth: ; CHECK-LABEL: test_vshlltq_m_n_u8_lanewidth:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshlltt.u8 q0, q1, #8 ; CHECK-NEXT: vshlltt.u8 q0, q1, #8
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, i32 8, i32 1, i32 1, <16 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 8, i32 1, i32 1, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_m_n_u16(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_m_n_u16(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshlltq_m_n_u16: ; CHECK-LABEL: test_vshlltq_m_n_u16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshlltt.u16 q0, q1, #9 ; CHECK-NEXT: vshlltt.u16 q0, q1, #9
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, i32 9, i32 1, i32 1, <8 x i1> %1, <4 x i32> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 9, i32 1, i32 1, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_m_n_u16_lanewidth(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_m_n_u16_lanewidth(<4 x i32> %inactive, <8 x i16> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshlltq_m_n_u16_lanewidth: ; CHECK-LABEL: test_vshlltq_m_n_u16_lanewidth:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshlltt.u16 q0, q1, #16 ; CHECK-NEXT: vshlltt.u16 q0, q1, #16
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, i32 16, i32 1, i32 1, <8 x i1> %1, <4 x i32> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 16, i32 1, i32 1, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_x_n_s8(<16 x i8> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_x_n_s8(<16 x i8> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshllbq_x_n_s8: ; CHECK-LABEL: test_vshllbq_x_n_s8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshllbt.s8 q0, q0, #1 ; CHECK-NEXT: vshllbt.s8 q0, q0, #1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, i32 1, i32 0, i32 0, <16 x i1> %1, <8 x i16> undef) %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 1, i32 0, i32 0, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_x_n_s8_lanewidth(<16 x i8> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_x_n_s8_lanewidth(<16 x i8> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshllbq_x_n_s8_lanewidth: ; CHECK-LABEL: test_vshllbq_x_n_s8_lanewidth:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshllbt.s8 q0, q0, #8 ; CHECK-NEXT: vshllbt.s8 q0, q0, #8
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, i32 8, i32 0, i32 0, <16 x i1> %1, <8 x i16> undef) %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 8, i32 0, i32 0, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_x_n_s16(<8 x i16> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_x_n_s16(<8 x i16> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshllbq_x_n_s16: ; CHECK-LABEL: test_vshllbq_x_n_s16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshllbt.s16 q0, q0, #10 ; CHECK-NEXT: vshllbt.s16 q0, q0, #10
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, i32 10, i32 0, i32 0, <8 x i1> %1, <4 x i32> undef) %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 10, i32 0, i32 0, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_x_n_s16_lanewidth(<8 x i16> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_x_n_s16_lanewidth(<8 x i16> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshllbq_x_n_s16_lanewidth: ; CHECK-LABEL: test_vshllbq_x_n_s16_lanewidth:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshllbt.s16 q0, q0, #16 ; CHECK-NEXT: vshllbt.s16 q0, q0, #16
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, i32 16, i32 0, i32 0, <8 x i1> %1, <4 x i32> undef) %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 16, i32 0, i32 0, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_x_n_u8(<16 x i8> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_x_n_u8(<16 x i8> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshllbq_x_n_u8: ; CHECK-LABEL: test_vshllbq_x_n_u8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshllbt.u8 q0, q0, #6 ; CHECK-NEXT: vshllbt.u8 q0, q0, #6
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, i32 6, i32 1, i32 0, <16 x i1> %1, <8 x i16> undef) %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 6, i32 1, i32 0, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_x_n_u8_lanewidth(<16 x i8> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vshllbq_x_n_u8_lanewidth(<16 x i8> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshllbq_x_n_u8_lanewidth: ; CHECK-LABEL: test_vshllbq_x_n_u8_lanewidth:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshllbt.u8 q0, q0, #8 ; CHECK-NEXT: vshllbt.u8 q0, q0, #8
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, i32 8, i32 1, i32 0, <16 x i1> %1, <8 x i16> undef) %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 8, i32 1, i32 0, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_x_n_u16(<8 x i16> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_x_n_u16(<8 x i16> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshllbq_x_n_u16: ; CHECK-LABEL: test_vshllbq_x_n_u16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshllbt.u16 q0, q0, #10 ; CHECK-NEXT: vshllbt.u16 q0, q0, #10
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, i32 10, i32 1, i32 0, <8 x i1> %1, <4 x i32> undef) %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 10, i32 1, i32 0, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_x_n_u16_lanewidth(<8 x i16> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vshllbq_x_n_u16_lanewidth(<8 x i16> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshllbq_x_n_u16_lanewidth: ; CHECK-LABEL: test_vshllbq_x_n_u16_lanewidth:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshllbt.u16 q0, q0, #16 ; CHECK-NEXT: vshllbt.u16 q0, q0, #16
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, i32 16, i32 1, i32 0, <8 x i1> %1, <4 x i32> undef) %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 16, i32 1, i32 0, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_x_n_s8(<16 x i8> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_x_n_s8(<16 x i8> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshlltq_x_n_s8: ; CHECK-LABEL: test_vshlltq_x_n_s8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshlltt.s8 q0, q0, #2 ; CHECK-NEXT: vshlltt.s8 q0, q0, #2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, i32 2, i32 0, i32 1, <16 x i1> %1, <8 x i16> undef) %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 2, i32 0, i32 1, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_x_n_s8_lanewidth(<16 x i8> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_x_n_s8_lanewidth(<16 x i8> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshlltq_x_n_s8_lanewidth: ; CHECK-LABEL: test_vshlltq_x_n_s8_lanewidth:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshlltt.s8 q0, q0, #8 ; CHECK-NEXT: vshlltt.s8 q0, q0, #8
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, i32 8, i32 0, i32 1, <16 x i1> %1, <8 x i16> undef) %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 8, i32 0, i32 1, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_x_n_s16(<8 x i16> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_x_n_s16(<8 x i16> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshlltq_x_n_s16: ; CHECK-LABEL: test_vshlltq_x_n_s16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshlltt.s16 q0, q0, #6 ; CHECK-NEXT: vshlltt.s16 q0, q0, #6
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, i32 6, i32 0, i32 1, <8 x i1> %1, <4 x i32> undef) %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 6, i32 0, i32 1, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_x_n_s16_lanewidth(<8 x i16> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_x_n_s16_lanewidth(<8 x i16> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshlltq_x_n_s16_lanewidth: ; CHECK-LABEL: test_vshlltq_x_n_s16_lanewidth:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshlltt.s16 q0, q0, #16 ; CHECK-NEXT: vshlltt.s16 q0, q0, #16
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, i32 16, i32 0, i32 1, <8 x i1> %1, <4 x i32> undef) %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 16, i32 0, i32 1, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_x_n_u8(<16 x i8> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_x_n_u8(<16 x i8> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshlltq_x_n_u8: ; CHECK-LABEL: test_vshlltq_x_n_u8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshlltt.u8 q0, q0, #5 ; CHECK-NEXT: vshlltt.u8 q0, q0, #5
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, i32 5, i32 1, i32 1, <16 x i1> %1, <8 x i16> undef) %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 5, i32 1, i32 1, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_x_n_u8_lanewidth(<16 x i8> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vshlltq_x_n_u8_lanewidth(<16 x i8> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshlltq_x_n_u8_lanewidth: ; CHECK-LABEL: test_vshlltq_x_n_u8_lanewidth:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshlltt.u8 q0, q0, #8 ; CHECK-NEXT: vshlltt.u8 q0, q0, #8
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, i32 8, i32 1, i32 1, <16 x i1> %1, <8 x i16> undef) %2 = tail call <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, i32 8, i32 1, i32 1, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_x_n_u16(<8 x i16> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_x_n_u16(<8 x i16> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshlltq_x_n_u16: ; CHECK-LABEL: test_vshlltq_x_n_u16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshlltt.u16 q0, q0, #3 ; CHECK-NEXT: vshlltt.u16 q0, q0, #3
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, i32 3, i32 1, i32 1, <8 x i1> %1, <4 x i32> undef) %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 3, i32 1, i32 1, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_x_n_u16_lanewidth(<8 x i16> %a, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vshlltq_x_n_u16_lanewidth(<8 x i16> %a, i16 zeroext %p) {
; CHECK-LABEL: test_vshlltq_x_n_u16_lanewidth: ; CHECK-LABEL: test_vshlltq_x_n_u16_lanewidth:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vshlltt.u16 q0, q0, #16 ; CHECK-NEXT: vshlltt.u16 q0, q0, #16
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, i32 16, i32 1, i32 1, <8 x i1> %1, <4 x i32> undef) %2 = tail call <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, i32 16, i32 1, i32 1, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2 ret <4 x i32> %2
} }
declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
declare <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>) declare <16 x i8> @llvm.arm.mve.shl.imm.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>)
Show All 22 Lines
declare <8 x i16> @llvm.arm.mve.vrshr.imm.v8i16(<8 x i16>, i32, i32) declare <8 x i16> @llvm.arm.mve.vrshr.imm.v8i16(<8 x i16>, i32, i32)
declare <4 x i32> @llvm.arm.mve.vrshr.imm.v4i32(<4 x i32>, i32, i32) declare <4 x i32> @llvm.arm.mve.vrshr.imm.v4i32(<4 x i32>, i32, i32)
declare <16 x i8> @llvm.arm.mve.vrshr.imm.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>, <16 x i8>) declare <16 x i8> @llvm.arm.mve.vrshr.imm.predicated.v16i8.v16i1(<16 x i8>, i32, i32, <16 x i1>, <16 x i8>)
declare <8 x i16> @llvm.arm.mve.vrshr.imm.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>, <8 x i16>) declare <8 x i16> @llvm.arm.mve.vrshr.imm.predicated.v8i16.v8i1(<8 x i16>, i32, i32, <8 x i1>, <8 x i16>)
declare <4 x i32> @llvm.arm.mve.vrshr.imm.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>, <4 x i32>) declare <4 x i32> @llvm.arm.mve.vrshr.imm.predicated.v4i32.v4i1(<4 x i32>, i32, i32, <4 x i1>, <4 x i32>)
declare <8 x i16> @llvm.arm.mve.vshll.imm.v8i16.v16i8(<16 x i8>, i32, i32, i32) declare <8 x i16> @llvm.arm.mve.vshll.imm.v8i16.v16i8(<16 x i8>, i32, i32, i32)
declare <4 x i32> @llvm.arm.mve.vshll.imm.v4i32.v8i16(<8 x i16>, i32, i32, i32) declare <4 x i32> @llvm.arm.mve.vshll.imm.v4i32.v8i16(<8 x i16>, i32, i32, i32)
declare <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v16i1(<16 x i8>, i32, i32, i32, <16 x i1>, <8 x i16>) declare <8 x i16> @llvm.arm.mve.vshll.imm.predicated.v8i16.v16i8.v8i1(<16 x i8>, i32, i32, i32, <8 x i1>, <8 x i16>)
declare <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v8i1(<8 x i16>, i32, i32, i32, <8 x i1>, <4 x i32>) declare <4 x i32> @llvm.arm.mve.vshll.imm.predicated.v4i32.v8i16.v4i1(<8 x i16>, i32, i32, i32, <4 x i1>, <4 x i32>)

llvm/test/CodeGen/Thumb2/mve-intrinsics/vmullbq.ll

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
; CHECK-LABEL: test_vmullbq_int_m_s8: ; CHECK-LABEL: test_vmullbq_int_m_s8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmullbt.s8 q0, q1, q2 ; CHECK-NEXT: vmullbt.s8 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 0, <16 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 0, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, i32, <16 x i1>, <8 x i16>) #1 declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_m_u16(<4 x i32> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_m_u16(<4 x i32> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) #0 {
; CHECK-LABEL: test_vmullbq_int_m_u16: ; CHECK-LABEL: test_vmullbq_int_m_u16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmullbt.u16 q0, q1, q2 ; CHECK-NEXT: vmullbt.u16 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, i32 0, <8 x i1> %1, <4 x i32> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 1, i32 0, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, i32, <8 x i1>, <4 x i32>) #1 declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
define arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_m_s32(<2 x i64> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_m_s32(<2 x i64> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmullbq_int_m_s32: ; CHECK-LABEL: test_vmullbq_int_m_s32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmullbt.s32 q0, q1, q2 ; CHECK-NEXT: vmullbt.s32 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 0, <4 x i1> %1, <2 x i64> %inactive) %2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 0, <4 x i1> %1, <2 x i64> %inactive)
ret <2 x i64> %2 ret <2 x i64> %2
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, i32, <4 x i1>, <2 x i64>) #1 declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, i32, <4 x i1>, <2 x i64>) #1
define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_poly_m_p8(<8 x i16> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_poly_m_p8(<8 x i16> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmullbq_poly_m_p8: ; CHECK-LABEL: test_vmullbq_poly_m_p8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmullbt.p8 q0, q1, q2 ; CHECK-NEXT: vmullbt.p8 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, <16 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 0, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <8 x i16>) #1 declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1
define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmullbq_int_x_u8: ; CHECK-LABEL: test_vmullbq_int_x_u8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmullbt.u8 q0, q0, q1 ; CHECK-NEXT: vmullbt.u8 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, i32 0, <16 x i1> %1, <8 x i16> undef) %2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 1, i32 0, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmullbq_int_x_s16: ; CHECK-LABEL: test_vmullbq_int_x_s16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmullbt.s16 q0, q0, q1 ; CHECK-NEXT: vmullbt.s16 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0, <8 x i1> %1, <4 x i32> undef) %2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 0, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmullbq_int_x_u32: ; CHECK-LABEL: test_vmullbq_int_x_u32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
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; CHECK-LABEL: test_vmullbq_poly_x_p16: ; CHECK-LABEL: test_vmullbq_poly_x_p16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmullbt.p16 q0, q0, q1 ; CHECK-NEXT: vmullbt.p16 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.mull.poly.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, <8 x i1> %1, <4 x i32> undef) %2 = tail call <4 x i32> @llvm.arm.mve.mull.poly.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 0, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2 ret <4 x i32> %2
} }
declare <4 x i32> @llvm.arm.mve.mull.poly.predicated.v4i32.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <4 x i32>) #1 declare <4 x i32> @llvm.arm.mve.mull.poly.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, <4 x i1>, <4 x i32>) #1

llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulltq.ll

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; CHECK-LABEL: test_vmulltq_int_m_s8: ; CHECK-LABEL: test_vmulltq_int_m_s8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmulltt.s8 q0, q1, q2 ; CHECK-NEXT: vmulltt.s8 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, <16 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 0, i32 1, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, i32, <16 x i1>, <8 x i16>) #1 declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, i32, <8 x i1>, <8 x i16>) #1
define arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_m_u16(<4 x i32> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_m_u16(<4 x i32> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulltq_int_m_u16: ; CHECK-LABEL: test_vmulltq_int_m_u16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmulltt.u16 q0, q1, q2 ; CHECK-NEXT: vmulltt.u16 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, i32 1, <8 x i1> %1, <4 x i32> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 1, i32 1, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, i32, <8 x i1>, <4 x i32>) #1 declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16>, <8 x i16>, i32, i32, <4 x i1>, <4 x i32>) #1
define arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_m_s32(<2 x i64> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_m_s32(<2 x i64> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulltq_int_m_s32: ; CHECK-LABEL: test_vmulltq_int_m_s32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmulltt.s32 q0, q1, q2 ; CHECK-NEXT: vmulltt.s32 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 1, <4 x i1> %1, <2 x i64> %inactive) %2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, i32 1, <4 x i1> %1, <2 x i64> %inactive)
ret <2 x i64> %2 ret <2 x i64> %2
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, i32, <4 x i1>, <2 x i64>) #1 declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, i32, <4 x i1>, <2 x i64>) #1
define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_m_p8(<8 x i16> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_m_p8(<8 x i16> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulltq_poly_m_p8: ; CHECK-LABEL: test_vmulltq_poly_m_p8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmulltt.p8 q0, q1, q2 ; CHECK-NEXT: vmulltt.p8 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, <16 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 1, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <8 x i16>) #1 declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8>, <16 x i8>, i32, <8 x i1>, <8 x i16>) #1
define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulltq_int_x_u8: ; CHECK-LABEL: test_vmulltq_int_x_u8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmulltt.u8 q0, q0, q1 ; CHECK-NEXT: vmulltt.u8 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, i32 1, <16 x i1> %1, <8 x i16> undef) %2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 1, i32 1, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2 ret <8 x i16> %2
} }
define arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulltq_int_x_s16: ; CHECK-LABEL: test_vmulltq_int_x_s16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmulltt.s16 q0, q0, q1 ; CHECK-NEXT: vmulltt.s16 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 1, <8 x i1> %1, <4 x i32> undef) %2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v4i1(<8 x i16> %a, <8 x i16> %b, i32 0, i32 1, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2 ret <4 x i32> %2
} }
define arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulltq_int_x_u32: ; CHECK-LABEL: test_vmulltq_int_x_u32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
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; CHECK-LABEL: test_vmulltq_poly_x_p8: ; CHECK-LABEL: test_vmulltq_poly_x_p8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmulltt.p8 q0, q0, q1 ; CHECK-NEXT: vmulltt.p8 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, <16 x i1> %1, <8 x i16> undef) %2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v8i1(<16 x i8> %a, <16 x i8> %b, i32 1, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2 ret <8 x i16> %2
} }