AMDGPU/GlobalISel: Support llvm.trap intrinsic

[hsmhsm]

Summary

Translate llvm.trap intrinsic to AMDGPU machine instruction(s).

[arsenm]

Should also handle debug trap, but that may be a separate patch

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

1114–1131

I would factor all of this into a helper function. This is also basically identical to AMDGPULegalizerInfo::loadInputValue, so you could just move this handling into the legalizer

1117

s/unsigned/Regisster

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-trap.ll

1

This isn't an irtranslator, so it shouldn't have it in the name. I would also expect it to be possible to share the test with the DAG tests

39–40

Remove the dead code

42

Should also have a test where this is used inside a non-entry block, and in a case that uses the stack.

[hsmhsm]

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

1114–1131

I think, there is no straightforward way to use Legalizer within IRTranslator?

I can do STI.getLegalizerInfo(), but it won't help to call AMDGPULegalizerInfo::loadInputValue() as it is not a general virtually callable API, but, it is a kind of helper function specific to AMDGPU.

I again need to explicitly cast STI.getLegalizerInfo() into AMDGPULegalizerInfo*, in order to loadInputValue(). I am not sure, if it is something worth doing it here.

[arsenm]

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

1114–1131

The IRTranslator isn't involved. The decision to put this in the legalizer or in selection is somewhat arbitrary. We handle the other intrinsics in the legalizer now, so you might as well put this there as well.

[hsmhsm]

Based on the review comments by arsenm, I have moved handling of trap and debugtrap intrinsics to Legazizer, and submitted a new Phabricator review request - https://reviews.llvm.org/D74688. Hence closing this review request.

[arsenm]

In D74527#1878103, @hsmhsm wrote:

Based on the review comments by arsenm, I have moved handling of trap and debugtrap intrinsics to Legazizer, and submitted a new Phabricator review request - https://reviews.llvm.org/D74688. Hence closing this review request.

You could also have just updated this one with a new diff, instead of creating a separate review. Splitting the review usually makes it harder to track

[hsmhsm]

In D74527#1878248, @arsenm wrote:

In D74527#1878103, @hsmhsm wrote:

Based on the review comments by arsenm, I have moved handling of trap and debugtrap intrinsics to Legazizer, and submitted a new Phabricator review request - https://reviews.llvm.org/D74688. Hence closing this review request.

You could also have just updated this one with a new diff, instead of creating a separate review. Splitting the review usually makes it harder to track

Yes, I definitely agree. That is the right way to make any review changes. I initially thought of doing the same. But, later created new review because I thought of handling both trap and debug-trap intrinsics together. I will avoid it in next time on-wards.

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h

private:
 
   /// tblgen-erated 'select' implementation.
   bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
 
   MachineOperand getSubOperand64(MachineOperand &MO,
                                  const TargetRegisterClass &SubRC,
                                  unsigned SubIdx) const;
 
+  Register getLiveInRegister(Register SrcReg) const;
+
   bool constrainCopyLikeIntrin(MachineInstr &MI, unsigned NewOpc) const;
   bool selectCOPY(MachineInstr &I) const;
   bool selectPHI(MachineInstr &I) const;
   bool selectG_TRUNC(MachineInstr &I) const;
   bool selectG_SZA_EXT(MachineInstr &I) const;
   bool selectG_CONSTANT(MachineInstr &I) const;
   bool selectG_FNEG(MachineInstr &I) const;
   bool selectG_AND_OR_XOR(MachineInstr &I) const;
   bool selectG_ADD_SUB(MachineInstr &I) const;
   bool selectG_UADDO_USUBO_UADDE_USUBE(MachineInstr &I) const;
   bool selectG_EXTRACT(MachineInstr &I) const;
   bool selectG_MERGE_VALUES(MachineInstr &I) const;
   bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
   bool selectG_PTR_ADD(MachineInstr &I) const;
   bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
   bool selectG_INSERT(MachineInstr &I) const;
 
   bool selectInterpP1F16(MachineInstr &MI) const;
   bool selectG_INTRINSIC(MachineInstr &I) const;
 
   bool selectEndCfIntrinsic(MachineInstr &MI) const;
   bool selectDSOrderedIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
   bool selectDSGWSIntrinsic(MachineInstr &MI, Intrinsic::ID IID) const;
   bool selectDSAppendConsume(MachineInstr &MI, bool IsAppend) const;
+  bool selectTrapIntrinsic(MachineInstr &MI) const;
 
   bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I) const;
   int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
   bool selectG_ICMP(MachineInstr &I) const;
   bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
   void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
                        SmallVectorImpl<GEPInfo> &AddrInfo) const;
   bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;

llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

default:
     llvm_unreachable("do not know to split immediate with this sub index.");
   case AMDGPU::sub0:
     return MachineOperand::CreateImm(Imm.getLoBits(32).getSExtValue());
   case AMDGPU::sub1:
     return MachineOperand::CreateImm(Imm.getHiBits(32).getSExtValue());
   }
 }
 
+Register AMDGPUInstructionSelector::getLiveInRegister(Register SrcReg) const {
+  Register LiveIn = MRI->getLiveInVirtReg(SrcReg);
+  if (!LiveIn) {
+    LiveIn = MRI->createGenericVirtualRegister(MRI->getType(SrcReg));
+    MRI->addLiveIn(SrcReg, LiveIn);
+  }
+  return LiveIn;
+}
+
 static unsigned getLogicalBitOpcode(unsigned Opc, bool Is64) {
   switch (Opc) {
   case AMDGPU::G_AND:
     return Is64 ? AMDGPU::S_AND_B64 : AMDGPU::S_AND_B32;
   case AMDGPU::G_OR:
     return Is64 ? AMDGPU::S_OR_B64 : AMDGPU::S_OR_B32;
   case AMDGPU::G_XOR:
     return Is64 ? AMDGPU::S_XOR_B64 : AMDGPU::S_XOR_B32;
BuildMI(*MBB, &MI, DL, TII.get(Opc), MI.getOperand(0).getReg())
     .addImm(Offset)
     .addImm(IsGDS ? -1 : 0)
     .cloneMemRefs(MI);
 
   MI.eraseFromParent();
   return true;
 }
 
+bool AMDGPUInstructionSelector::selectTrapIntrinsic(MachineInstr &MI) const {
+  MachineBasicBlock *MBB = MI.getParent();
+  MachineFunction *MF = MBB->getParent();
+  const DebugLoc &DL = MI.getDebugLoc();
+
+  // Is non-HSA path or trap-handler disabled? then, insert s_endpgm instruction
+  if (STI.getTrapHandlerAbi() != GCNSubtarget::TrapHandlerAbiHsa ||
+      !STI.isTrapHandlerEnabled()) {
+    BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::S_ENDPGM)).addImm(0);
+  } else {
+    // Pass queue pointer to trap handler as input
+    // Reference: https://llvm.org/docs/AMDGPUUsage.html#trap-handler-abi
+    unsigned RegNo =
+        MF->getInfo<SIMachineFunctionInfo>()->getQueuePtrUserSGPR();
+    assert(RegNo != AMDGPU::NoRegister);
+    Register SrcReg = Register(RegNo);
+    Register LiveIn = getLiveInRegister(SrcReg);
+    Register DstReg(AMDGPU::SGPR0_SGPR1);
+    BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::COPY), DstReg).addReg(LiveIn);
+
+    if (!MRI->getVRegDef(LiveIn)) {
+      MachineBasicBlock &EntryMBB = MF->front();
+      EntryMBB.addLiveIn(SrcReg);
+      BuildMI(EntryMBB, EntryMBB.begin(), DebugLoc(), TII.get(AMDGPU::COPY),
+              LiveIn)
+          .addReg(SrcReg);
+    }
+
+    // Insert trap instruction
+    BuildMI(*MBB, &MI, DL, TII.get(AMDGPU::S_TRAP))
+        .addImm(GCNSubtarget::TrapIDLLVMTrap)
+        .addReg(DstReg, RegState::Implicit);
+  }
+
+  MI.eraseFromParent();
+  return true;
+}
+
 bool AMDGPUInstructionSelector::selectG_INTRINSIC_W_SIDE_EFFECTS(
     MachineInstr &I) const {
   unsigned IntrinsicID = I.getIntrinsicID();
   switch (IntrinsicID) {
   case Intrinsic::amdgcn_end_cf:
     return selectEndCfIntrinsic(I);
   case Intrinsic::amdgcn_ds_ordered_add:
   case Intrinsic::amdgcn_ds_ordered_swap:
     return selectDSOrderedIntrinsic(I, IntrinsicID);
   case Intrinsic::amdgcn_ds_gws_init:
   case Intrinsic::amdgcn_ds_gws_barrier:
   case Intrinsic::amdgcn_ds_gws_sema_v:
   case Intrinsic::amdgcn_ds_gws_sema_br:
   case Intrinsic::amdgcn_ds_gws_sema_p:
   case Intrinsic::amdgcn_ds_gws_sema_release_all:
     return selectDSGWSIntrinsic(I, IntrinsicID);
   case Intrinsic::amdgcn_ds_append:
     return selectDSAppendConsume(I, true);
   case Intrinsic::amdgcn_ds_consume:
     return selectDSAppendConsume(I, false);
+  case Intrinsic::trap:
+    return selectTrapIntrinsic(I);
   default:
     return selectImpl(I, *CoverageInfo);
   }
 }
 
 bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const {
   if (selectImpl(I, *CoverageInfo))
     return true;

llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-trap.ll

+; hsa: trap handler enabled
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=LABLE-HSA-TRAP -check-prefix=HSA-TRAP %s
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -mattr=+trap-handler < %s | FileCheck -check-prefix=LABLE-HSA-TRAP -check-prefix=HSA-TRAP %s
+
+; hsa: trap handler disabled
+; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -mattr=-trap-handler < %s | FileCheck -check-prefix=LABLE-HSA-TRAP -check-prefix=NO-HSA-TRAP %s
+
+; mesa: trap handler enabled
+; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -verify-machineinstrs -mattr=+trap-handler < %s | FileCheck -check-prefix=LABLE-HSA-TRAP -check-prefix=MESA-TRAP %s
+
+; mesa: trap handler disabled
+; RUN: llc -global-isel -mtriple=amdgcn-unknown-mesa3d -verify-machineinstrs -mattr=-trap-handler < %s | FileCheck -check-prefix=LABLE-HSA-TRAP -check-prefix=NO-MESA-TRAP %s
+
+declare void @llvm.trap() #0
+
+; LABLE-HSA-TRAP: {{^}}hsa_trap:
+
+; HSA-TRAP: enable_trap_handler = 0
+; HSA-TRAP: s_mov_b64 s[0:1], s[4:5]
+; HSA-TRAP: s_trap 2
+; HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
+
+; NO-HSA-TRAP: enable_trap_handler = 0
+; NO-HSA-TRAP: s_endpgm
+; NO-HSA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
+
+; MESA-TRAP: enable_trap_handler = 1
+; MESA-TRAP: s_endpgm
+; MESA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 1
+
+; NO-MESA-TRAP: enable_trap_handler = 0
+; NO-MESA-TRAP: s_endpgm
+; NO-MESA-TRAP: COMPUTE_PGM_RSRC2:TRAP_HANDLER: 0
+
+define amdgpu_kernel void @hsa_trap(i32 addrspace(1)* nocapture readonly %arg0) {
+  store volatile i32 1, i32 addrspace(1)* %arg0
+  call void @llvm.trap()
+  unreachable
+  store volatile i32 2, i32 addrspace(1)* %arg0
+  ret void
+}
+
+attributes #0 = { nounwind noreturn }