[llvm-exegesis][mips] Add support for memory instructions

[mstojanovic]

Summary

Implementing functions used to enable testing of memory instructions.

[atanasyan]

LGTM

llvm/tools/llvm-exegesis/lib/Mips/Target.cpp

 //===-- Target.cpp ----------------------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 #include "../Target.h"
 #include "../Latency.h"
+#include "MCTargetDesc/MipsBaseInfo.h"
 #include "Mips.h"
 #include "MipsRegisterInfo.h"
 
 namespace llvm {
 namespace exegesis {
 
+// Returns an error if we cannot handle the memory references in this
+// instruction.
+static Error isInvalidMemoryInstr(const Instruction &Instr) {
+  switch (Instr.Description.TSFlags & MipsII::FormMask) {
+  default:
+    return Error::success();
+    llvm_unreachable("Unknown FormMask value");
+  // These have no memory access.
+  case MipsII::Pseudo:
+  case MipsII::FrmR:
+  case MipsII::FrmJ:
+  case MipsII::FrmFR:
+    return Error::success();
+  // These access memory and are handled.
+  case MipsII::FrmI:
+    return Error::success();
+  // These access memory and are not handled yet.
+  case MipsII::FrmFI:
+  case MipsII::FrmOther:
+    return make_error<Failure>("unsupported opcode: non uniform memory access");
+  }
+}
+
+// Helper to fill a memory operand with a value.
+static void setMemOp(InstructionTemplate &IT, int OpIdx,
+                     const MCOperand &OpVal) {
+  const auto Op = IT.getInstr().Operands[OpIdx];
+  assert(Op.isExplicit() && "invalid memory pattern");
+  IT.getValueFor(Op) = OpVal;
+}
+
 #include "MipsGenExegesis.inc"
 
 namespace {
 class ExegesisMipsTarget : public ExegesisTarget {
 public:
   ExegesisMipsTarget() : ExegesisTarget(MipsCpuPfmCounters) {}
 
 private:
+  unsigned getScratchMemoryRegister(const llvm::Triple &TT) const override;
+  unsigned getMaxMemoryAccessSize() const override { return 64; }
+  void fillMemoryOperands(InstructionTemplate &IT, unsigned Reg,
+                          unsigned Offset) const override;
+
   std::vector<MCInst> setRegTo(const MCSubtargetInfo &STI, unsigned Reg,
                                const APInt &Value) const override;
   bool matchesArch(Triple::ArchType Arch) const override {
     return Arch == Triple::mips || Arch == Triple::mipsel ||
            Arch == Triple::mips64 || Arch == Triple::mips64el;
   }
 };
 } // end anonymous namespace
if (Value.isIntN(32)) {
     }
 
     return Instructions;
   }
 
   llvm_unreachable("Not implemented for values wider than 32 bits");
 }
 
+unsigned ExegesisMipsTarget::getScratchMemoryRegister(const Triple &TT) const {
+  return TT.isArch64Bit() ? Mips::A0_64 : Mips::A0;
+}
+
+void ExegesisMipsTarget::fillMemoryOperands(InstructionTemplate &IT,
+                                            unsigned Reg,
+                                            unsigned Offset) const {
+  assert(!isInvalidMemoryInstr(IT.getInstr()) &&
+         "fillMemoryOperands requires a valid memory instruction");
+  setMemOp(IT, 0, MCOperand::createReg(0));      // IndexReg
+  setMemOp(IT, 1, MCOperand::createReg(Reg));    // BaseReg
+  setMemOp(IT, 2, MCOperand::createImm(Offset)); // Disp
+}
+
 std::vector<MCInst> ExegesisMipsTarget::setRegTo(const MCSubtargetInfo &STI,
                                                  unsigned Reg,
                                                  const APInt &Value) const {
   if (Mips::GPR32RegClass.contains(Reg))
     return loadImmediate(Reg, true, Value);
   if (Mips::GPR64RegClass.contains(Reg))
     return loadImmediate(Reg, false, Value);
   errs() << "setRegTo is not implemented, results will be unreliable\n";

llvm/unittests/tools/llvm-exegesis/Mips/SnippetGeneratorTest.cpp

 //===-- SnippetGeneratorTest.cpp --------------------------------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "../Common/AssemblerUtils.h"
 #include "Latency.h"
 #include "LlvmState.h"
 #include "MCInstrDescView.h"
 #include "MipsInstrInfo.h"
 #include "RegisterAliasing.h"
 #include "TestBase.h"
+#include "Uops.h"
 
 #include <unordered_set>
 
 namespace llvm {
 namespace exegesis {
 namespace {
 
 using testing::AnyOf;
 using testing::ElementsAre;
+using testing::HasSubstr;
 using testing::SizeIs;
 
 MATCHER(IsInvalid, "") { return !arg.isValid(); }
 MATCHER(IsReg, "") { return arg.isReg(); }
 
 class MipsSnippetGeneratorTest : public MipsTestBase {};
 
 template <typename SnippetGeneratorT>
protected:
   }
 
   SnippetGeneratorT Generator;
 };
 
 using LatencySnippetGeneratorTest =
     SnippetGeneratorTest<LatencySnippetGenerator>;
 
+using UopsSnippetGeneratorTest = SnippetGeneratorTest<UopsSnippetGenerator>;
+
 TEST_F(LatencySnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
   // - ADD
   // - Op0 Explicit Def RegClass(GPR32)
   // - Op1 Explicit Use RegClass(GPR32)
   // - Op2 Explicit Use RegClass(GPR32)
   // - Var0 [Op0]
   // - Var1 [Op1]
   // - Var2 [Op2]
+  // - hasAliasingRegisters
   const unsigned Opcode = Mips::ADD;
   const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
   ASSERT_THAT(CodeTemplates, SizeIs(1));
   const auto &CT = CodeTemplates[0];
   EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
   ASSERT_THAT(CT.Instructions, SizeIs(1));
   const InstructionTemplate &IT = CT.Instructions[0];
   EXPECT_THAT(IT.getOpcode(), Opcode);
   ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
   EXPECT_THAT(IT.getVariableValues(),
               AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
                     ElementsAre(IsReg(), IsReg(), IsInvalid())))
       << "Op0 is either set to Op1 or to Op2";
 }
 
 TEST_F(LatencySnippetGeneratorTest,
  ImplicitSelfDependencyThroughExplicitRegsForbidAll) {
   // - XOR
   // - Op0 Explicit Def RegClass(GPR32)
   // - Op1 Explicit Use RegClass(GPR32)
   // - Op2 Explicit Use RegClass(GPR32)
   // - Var0 [Op0]
   // - Var1 [Op1]
   // - Var2 [Op2]
+  // - hasAliasingRegisters
   randomGenerator().seed(0); // Initialize seed.
   const Instruction &Instr = State.getIC().getInstr(Mips::XOR);
   auto AllRegisters = State.getRATC().emptyRegisters();
   AllRegisters.flip();
   auto Error = Generator.generateCodeTemplates(Instr, AllRegisters).takeError();
   EXPECT_TRUE((bool)Error);
   consumeError(std::move(Error));
 }
 
+TEST_F(UopsSnippetGeneratorTest, MemoryUse) {
+  // LB reads from memory.
+  // - LB
+  // - Op0 Explicit Def RegClass(GPR32)
+  // - Op1 Explicit Use Memory RegClass(MSA128F16)
+  // - Op2 Explicit Use Memory
+  // - Var0 [Op0]
+  // - Var1 [Op1]
+  // - Var2 [Op2]
+  // - hasMemoryOperands
+  const unsigned Opcode = Mips::LB;
+  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
+  ASSERT_THAT(CodeTemplates, SizeIs(1));
+  const auto &CT = CodeTemplates[0];
+  EXPECT_THAT(CT.Info, HasSubstr("instruction is parallel, repeating a random one."));
+  EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
+  ASSERT_THAT(CT.Instructions,
+              SizeIs(UopsSnippetGenerator::kMinNumDifferentAddresses));
+  const InstructionTemplate &IT = CT.Instructions[0];
+  EXPECT_THAT(IT.getOpcode(), Opcode);
+  ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
+  EXPECT_EQ(IT.getVariableValues()[0].getReg(), 0u);
+  EXPECT_EQ(IT.getVariableValues()[2].getImm(), 0);
+}
+
 } // namespace
 } // namespace exegesis
 } // namespace llvm