[MachineScheduler] Don't swap when we can't cluster

[jsji]

Summary

https://reviews.llvm.org/D72706 tried to reduce reordering due to mem op
clustering. This patch avoid doing the swap when we can't cluster.

[rampitec]

LGTM.

[merge_guards_bot]

Unit tests: pass. 61905 tests passed, 0 failed and 782 were skipped.

clang-tidy: unknown.

clang-format: pass.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[jsji]

Thanks for review and accepting.

However, after further investigation, looks like our downstream additional reordering is NOT only due to this.
I will commit this as a NFC patch first.

[foad]

This patch would only change behaviour if the target's shouldClusterMemOps(SUa, SUb) might return a different answer from shouldClusterMemOps(SUb, SUa).

[jsji]

In D72800#1823492, @foad wrote:

This patch would only change behaviour if the target's shouldClusterMemOps(SUa, SUb) might return a different answer from shouldClusterMemOps(SUb, SUa).

Yes, agree. Thanks.

llvm/lib/CodeGen/MachineScheduler.cpp

void BaseMemOpClusterMutation::clusterNeighboringMemOps(
   if (MemOpRecords.size() < 2)
     return;
 
   llvm::sort(MemOpRecords);
   unsigned ClusterLength = 1;
   for (unsigned Idx = 0, End = MemOpRecords.size(); Idx < (End - 1); ++Idx) {
     SUnit *SUa = MemOpRecords[Idx].SU;
     SUnit *SUb = MemOpRecords[Idx+1].SU;
-    if (SUa->NodeNum > SUb->NodeNum)
-      std::swap(SUa, SUb);
     if (TII->shouldClusterMemOps(*MemOpRecords[Idx].BaseOp,
                                  *MemOpRecords[Idx + 1].BaseOp,
-                                 ClusterLength) &&
-        DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
+                                 ClusterLength)) {
+      if (SUa->NodeNum > SUb->NodeNum)
+        std::swap(SUa, SUb);
+      if (DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
         LLVM_DEBUG(dbgs() << "Cluster ld/st SU(" << SUa->NodeNum << ") - SU("
                           << SUb->NodeNum << ")\n");
         // Copy successor edges from SUa to SUb. Interleaving computation
         // dependent on SUa can prevent load combining due to register reuse.
-      // Predecessor edges do not need to be copied from SUb to SUa since nearby
-      // loads should have effectively the same inputs.
+        // Predecessor edges do not need to be copied from SUb to SUa since
+        // nearby loads should have effectively the same inputs.
         for (const SDep &Succ : SUa->Succs) {
           if (Succ.getSUnit() == SUb)
             continue;
-        LLVM_DEBUG(dbgs() << "  Copy Succ SU(" << Succ.getSUnit()->NodeNum
-                          << ")\n");
+          LLVM_DEBUG(dbgs()
+                     << "  Copy Succ SU(" << Succ.getSUnit()->NodeNum << ")\n");
           DAG->addEdge(Succ.getSUnit(), SDep(SUb, SDep::Artificial));
         }
         ++ClusterLength;
       } else
         ClusterLength = 1;
+    } else
+      ClusterLength = 1;
   }
 }
 
 /// Callback from DAG postProcessing to create cluster edges for loads.
 void BaseMemOpClusterMutation::apply(ScheduleDAGInstrs *DAG) {
   // Map DAG NodeNum to a set of dependent MemOps in store chain.
   DenseMap<unsigned, SmallVector<SUnit *, 4>> StoreChains;
   for (SUnit &SU : DAG->SUnits) {