[PowerPC] Add exception constraint to FP sqrt, fma, min/max

[qiucf]

Summary

The concept of strict floating point nodes was added into LLVM in https://reviews.llvm.org/D55506.
This is the third follow-up patch to add constraint fp support about exception part for PowerPC target.

[merge_guards_bot]

Unit tests: pass. 61907 tests passed, 0 failed and 781 were skipped.

clang-tidy: unknown.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

[amyk]

Please adjust the RUN lines so they do not exceed 80 characters.

llvm/test/CodeGen/PowerPC/fp-strict-fma-f128.ll

1

Exceeding 80 characters.

[kpn]

Most of this is in TableGen files, and I have so little experience there that I can't review. I'm sorry.

The test cases have large changes in the generated assembly, but I can't read PowerPC assembly so I don't know what's going on there.

Is there a PowerPC person who can review meaningfully?

llvm/test/CodeGen/PowerPC/fp-strict-fma-f128.ll

1

I don't think we care about test cases exceeding 80 characters. A quick check shows thousands with just RUN: lines longer than 80.

[hfinkel]

LGTM.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
   setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
 
   // Handle constrained floating-point operations of scalar.
   // TODO: Handle SPE specific operation.
   setOperationAction(ISD::STRICT_FADD, MVT::f32, Legal);
   setOperationAction(ISD::STRICT_FSUB, MVT::f32, Legal);
   setOperationAction(ISD::STRICT_FMUL, MVT::f32, Legal);
   setOperationAction(ISD::STRICT_FDIV, MVT::f32, Legal);
+  setOperationAction(ISD::STRICT_FMA, MVT::f32, Legal);
+  if (Subtarget.hasFSQRT())
+    setOperationAction(ISD::STRICT_FSQRT, MVT::f32, Legal);
   setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
   if (Subtarget.hasFPRND()) {
     setOperationAction(ISD::STRICT_FFLOOR, MVT::f32, Legal);
     setOperationAction(ISD::STRICT_FCEIL,  MVT::f32, Legal);
     setOperationAction(ISD::STRICT_FTRUNC, MVT::f32, Legal);
     setOperationAction(ISD::STRICT_FROUND, MVT::f32, Legal);
   }
 
   setOperationAction(ISD::STRICT_FADD, MVT::f64, Legal);
   setOperationAction(ISD::STRICT_FSUB, MVT::f64, Legal);
   setOperationAction(ISD::STRICT_FMUL, MVT::f64, Legal);
   setOperationAction(ISD::STRICT_FDIV, MVT::f64, Legal);
+  setOperationAction(ISD::STRICT_FMA, MVT::f64, Legal);
+  if (Subtarget.hasFSQRT())
+    setOperationAction(ISD::STRICT_FSQRT, MVT::f64, Legal);
   if (Subtarget.hasVSX())
     setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f64, Legal);
   if (Subtarget.hasFPRND()) {
     setOperationAction(ISD::STRICT_FFLOOR, MVT::f64, Legal);
     setOperationAction(ISD::STRICT_FCEIL,  MVT::f64, Legal);
     setOperationAction(ISD::STRICT_FTRUNC, MVT::f64, Legal);
     setOperationAction(ISD::STRICT_FROUND, MVT::f64, Legal);
   }
 
   // We don't support sin/cos/sqrt/fmod/pow
   setOperationAction(ISD::FSIN , MVT::f64, Expand);
   setOperationAction(ISD::FCOS , MVT::f64, Expand);
   setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
if (Subtarget.hasVSX()) {
 
       // Handle constrained floating-point operations of vector.
       // The predictor is `hasVSX` because altivec instruction has
       // no exception but VSX vector instruction has.
       setOperationAction(ISD::STRICT_FADD, MVT::v4f32, Legal);
       setOperationAction(ISD::STRICT_FSUB, MVT::v4f32, Legal);
       setOperationAction(ISD::STRICT_FMUL, MVT::v4f32, Legal);
       setOperationAction(ISD::STRICT_FDIV, MVT::v4f32, Legal);
+      setOperationAction(ISD::STRICT_FMA, MVT::v4f32, Legal);
+      setOperationAction(ISD::STRICT_FSQRT, MVT::v4f32, Legal);
       setOperationAction(ISD::STRICT_FNEARBYINT, MVT::v4f32, Legal);
       setOperationAction(ISD::STRICT_FFLOOR, MVT::v4f32, Legal);
       setOperationAction(ISD::STRICT_FCEIL,  MVT::v4f32, Legal);
       setOperationAction(ISD::STRICT_FTRUNC, MVT::v4f32, Legal);
       setOperationAction(ISD::STRICT_FROUND, MVT::v4f32, Legal);
+      setOperationAction(ISD::STRICT_FMAXNUM, MVT::v4f32, Legal);
+      setOperationAction(ISD::STRICT_FMINNUM, MVT::v4f32, Legal);
 
       setOperationAction(ISD::STRICT_FADD, MVT::v2f64, Legal);
       setOperationAction(ISD::STRICT_FSUB, MVT::v2f64, Legal);
       setOperationAction(ISD::STRICT_FMUL, MVT::v2f64, Legal);
       setOperationAction(ISD::STRICT_FDIV, MVT::v2f64, Legal);
+      setOperationAction(ISD::STRICT_FMA, MVT::v2f64, Legal);
+      setOperationAction(ISD::STRICT_FSQRT, MVT::v2f64, Legal);
       setOperationAction(ISD::STRICT_FNEARBYINT, MVT::v2f64, Legal);
       setOperationAction(ISD::STRICT_FFLOOR, MVT::v2f64, Legal);
       setOperationAction(ISD::STRICT_FCEIL,  MVT::v2f64, Legal);
       setOperationAction(ISD::STRICT_FTRUNC, MVT::v2f64, Legal);
       setOperationAction(ISD::STRICT_FROUND, MVT::v2f64, Legal);
+      setOperationAction(ISD::STRICT_FMAXNUM, MVT::v2f64, Legal);
+      setOperationAction(ISD::STRICT_FMINNUM, MVT::v2f64, Legal);
 
       addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
     }
 
     if (Subtarget.hasP8Altivec()) {
       addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
       addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
     }
if (Subtarget.hasP9Vector()) {
         setOperationAction(ISD::FPOWI, MVT::f128, Expand);
         setOperationAction(ISD::FREM, MVT::f128, Expand);
 
         // Handle constrained floating-point operations of fp128
         setOperationAction(ISD::STRICT_FADD, MVT::f128, Legal);
         setOperationAction(ISD::STRICT_FSUB, MVT::f128, Legal);
         setOperationAction(ISD::STRICT_FMUL, MVT::f128, Legal);
         setOperationAction(ISD::STRICT_FDIV, MVT::f128, Legal);
+        setOperationAction(ISD::STRICT_FMA, MVT::f128, Legal);
+        setOperationAction(ISD::STRICT_FSQRT, MVT::f128, Legal);
         setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f128, Legal);
         setOperationAction(ISD::STRICT_FP_ROUND, MVT::f64, Legal);
         setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
         setOperationAction(ISD::STRICT_FRINT, MVT::f128, Legal);
         setOperationAction(ISD::STRICT_FNEARBYINT, MVT::f128, Legal);
         setOperationAction(ISD::STRICT_FFLOOR, MVT::f128, Legal);
         setOperationAction(ISD::STRICT_FCEIL,  MVT::f128, Legal);
         setOperationAction(ISD::STRICT_FTRUNC, MVT::f128, Legal);
         setOperationAction(ISD::STRICT_FROUND, MVT::f128, Legal);
       }
       setOperationAction(ISD::FP_EXTEND, MVT::v2f32, Custom);
       setOperationAction(ISD::BSWAP, MVT::v8i16, Legal);
       setOperationAction(ISD::BSWAP, MVT::v4i32, Legal);
       setOperationAction(ISD::BSWAP, MVT::v2i64, Legal);
       setOperationAction(ISD::BSWAP, MVT::v1i128, Legal);

llvm/lib/Target/PowerPC/PPCInstrInfo.td

defm FRIMD  : XForm_26r<63, 488, (outs f8rc:$frD), (ins f8rc:$frB),
                           "frim", "$frD, $frB", IIC_FPGeneral,
                           [(set f64:$frD, (any_ffloor f64:$frB))]>;
   defm FRIMS  : XForm_26r<63, 488, (outs f4rc:$frD), (ins f4rc:$frB),
                           "frim", "$frD, $frB", IIC_FPGeneral,
                           [(set f32:$frD, (any_ffloor f32:$frB))]>;
 
   defm FSQRT  : XForm_26r<63, 22, (outs f8rc:$frD), (ins f8rc:$frB),
                           "fsqrt", "$frD, $frB", IIC_FPSqrtD,
-                          [(set f64:$frD, (fsqrt f64:$frB))]>;
+                          [(set f64:$frD, (any_fsqrt f64:$frB))]>;
   defm FSQRTS : XForm_26r<59, 22, (outs f4rc:$frD), (ins f4rc:$frB),
                           "fsqrts", "$frD, $frB", IIC_FPSqrtS,
-                          [(set f32:$frD, (fsqrt f32:$frB))]>;
+                          [(set f32:$frD, (any_fsqrt f32:$frB))]>;
   }
   }
 }
 
 /// Note that FMR is defined as pseudo-ops on the PPC970 because they are
 /// often coalesced away and we don't want the dispatch group builder to think
 /// that they will fill slots (which could cause the load of a LSU reject to
 /// sneak into a d-group with a store).

 // this type.
 //
 let PPC970_Unit = 3, hasSideEffects = 0, Predicates = [HasFPU] in {  // FPU Operations.
 let Uses = [RM] in {
 let isCommutable = 1 in {
   defm FMADD : AForm_1r<63, 29, 
                       (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
                       "fmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
-                      [(set f64:$FRT, (fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
+                      [(set f64:$FRT, (any_fma f64:$FRA, f64:$FRC, f64:$FRB))]>;
   defm FMADDS : AForm_1r<59, 29,
                       (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
                       "fmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
-                      [(set f32:$FRT, (fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
+                      [(set f32:$FRT, (any_fma f32:$FRA, f32:$FRC, f32:$FRB))]>;
   defm FMSUB : AForm_1r<63, 28,
                       (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
                       "fmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                       [(set f64:$FRT,
-                            (fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
+                            (any_fma f64:$FRA, f64:$FRC, (fneg f64:$FRB)))]>;
   defm FMSUBS : AForm_1r<59, 28,
                       (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
                       "fmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
                       [(set f32:$FRT,
-                            (fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
+                            (any_fma f32:$FRA, f32:$FRC, (fneg f32:$FRB)))]>;
   defm FNMADD : AForm_1r<63, 31,
                       (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
                       "fnmadd", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                       [(set f64:$FRT,
-                            (fneg (fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
+                            (fneg (any_fma f64:$FRA, f64:$FRC, f64:$FRB)))]>;
   defm FNMADDS : AForm_1r<59, 31,
                       (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
                       "fnmadds", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
                       [(set f32:$FRT,
-                            (fneg (fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
+                            (fneg (any_fma f32:$FRA, f32:$FRC, f32:$FRB)))]>;
   defm FNMSUB : AForm_1r<63, 30,
                       (outs f8rc:$FRT), (ins f8rc:$FRA, f8rc:$FRC, f8rc:$FRB),
                       "fnmsub", "$FRT, $FRA, $FRC, $FRB", IIC_FPFused,
-                      [(set f64:$FRT, (fneg (fma f64:$FRA, f64:$FRC,
+                      [(set f64:$FRT, (fneg (any_fma f64:$FRA, f64:$FRC,
                                                  (fneg f64:$FRB))))]>;
   defm FNMSUBS : AForm_1r<59, 30,
                       (outs f4rc:$FRT), (ins f4rc:$FRA, f4rc:$FRC, f4rc:$FRB),
                       "fnmsubs", "$FRT, $FRA, $FRC, $FRB", IIC_FPGeneral,
-                      [(set f32:$FRT, (fneg (fma f32:$FRA, f32:$FRC,
+                      [(set f32:$FRT, (fneg (any_fma f32:$FRA, f32:$FRC,
                                                  (fneg f32:$FRB))))]>;
 } // isCommutable
 }
 // FSEL is artificially split into 4 and 8-byte forms for the result.  To avoid
 // having 4 of these, force the comparison to always be an 8-byte double (code
 // should use an FMRSD if the input comparison value really wants to be a float)
 // and 4/8 byte forms for the result and operand type..
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in

 // versions of Power.
 def : Pat<(atomic_fence (i64 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>;
 def : Pat<(atomic_fence (i32 7), (timm)), (SYNC 0)>, Requires<[HasSYNC]>;
 def : Pat<(atomic_fence (timm), (timm)), (SYNC 1)>, Requires<[HasSYNC]>;
 def : Pat<(atomic_fence (timm), (timm)), (MSYNC)>, Requires<[HasOnlyMSYNC]>;
 
 let Predicates = [HasFPU] in {
 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
-def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
+def : Pat<(any_fma (fneg f64:$A), f64:$C, f64:$B),
           (FNMSUB $A, $C, $B)>;
-def : Pat<(fma f64:$A, (fneg f64:$C), f64:$B),
+def : Pat<(any_fma f64:$A, (fneg f64:$C), f64:$B),
           (FNMSUB $A, $C, $B)>;
-def : Pat<(fma (fneg f32:$A), f32:$C, f32:$B),
+def : Pat<(any_fma (fneg f32:$A), f32:$C, f32:$B),
           (FNMSUBS $A, $C, $B)>;
-def : Pat<(fma f32:$A, (fneg f32:$C), f32:$B),
+def : Pat<(any_fma f32:$A, (fneg f32:$C), f32:$B),
           (FNMSUBS $A, $C, $B)>;
 
 // FCOPYSIGN's operand types need not agree.
 def : Pat<(fcopysign f64:$frB, f32:$frA),
           (FCPSGND (COPY_TO_REGCLASS $frA, F8RC), $frB)>;
 def : Pat<(fcopysign f32:$frB, f64:$frA),
           (FCPSGNS (COPY_TO_REGCLASS $frA, F4RC), $frB)>;
 }

llvm/lib/Target/PowerPC/PPCInstrVSX.td

def XVSUBSP : XX3Form<60, 72,
                         [(set v4f32:$XT, (any_fsub v4f32:$XA, v4f32:$XB))]>;
 
   // FMA Instructions
   let BaseName = "XSMADDADP" in {
   let isCommutable = 1 in
   def XSMADDADP : XX3Form<60, 33,
                           (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
                           "xsmaddadp $XT, $XA, $XB", IIC_VecFP,
-                          [(set f64:$XT, (fma f64:$XA, f64:$XB, f64:$XTi))]>,
+                          [(set f64:$XT, (any_fma f64:$XA, f64:$XB, f64:$XTi))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XSMADDMDP : XX3Form<60, 41,
                           (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
                           "xsmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   let BaseName = "XSMSUBADP" in {
   let isCommutable = 1 in
   def XSMSUBADP : XX3Form<60, 49,
                           (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
                           "xsmsubadp $XT, $XA, $XB", IIC_VecFP,
-                          [(set f64:$XT, (fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>,
+                          [(set f64:$XT, (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi)))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XSMSUBMDP : XX3Form<60, 57,
                           (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
                           "xsmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   let BaseName = "XSNMADDADP" in {
   let isCommutable = 1 in
   def XSNMADDADP : XX3Form<60, 161,
                           (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
                           "xsnmaddadp $XT, $XA, $XB", IIC_VecFP,
-                          [(set f64:$XT, (fneg (fma f64:$XA, f64:$XB, f64:$XTi)))]>,
+                          [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, f64:$XTi)))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XSNMADDMDP : XX3Form<60, 169,
                           (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
                           "xsnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   let BaseName = "XSNMSUBADP" in {
   let isCommutable = 1 in
   def XSNMSUBADP : XX3Form<60, 177,
                           (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
                           "xsnmsubadp $XT, $XA, $XB", IIC_VecFP,
-                          [(set f64:$XT, (fneg (fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>,
+                          [(set f64:$XT, (fneg (any_fma f64:$XA, f64:$XB, (fneg f64:$XTi))))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XSNMSUBMDP : XX3Form<60, 185,
                           (outs vsfrc:$XT), (ins vsfrc:$XTi, vsfrc:$XA, vsfrc:$XB),
                           "xsnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   let BaseName = "XVMADDADP" in {
   let isCommutable = 1 in
   def XVMADDADP : XX3Form<60, 97,
                           (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
                           "xvmaddadp $XT, $XA, $XB", IIC_VecFP,
-                          [(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>,
+                          [(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XVMADDMDP : XX3Form<60, 105,
                           (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
                           "xvmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   let BaseName = "XVMADDASP" in {
   let isCommutable = 1 in
   def XVMADDASP : XX3Form<60, 65,
                           (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
                           "xvmaddasp $XT, $XA, $XB", IIC_VecFP,
-                          [(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>,
+                          [(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, v4f32:$XTi))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XVMADDMSP : XX3Form<60, 73,
                           (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
                           "xvmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   let BaseName = "XVMSUBADP" in {
   let isCommutable = 1 in
   def XVMSUBADP : XX3Form<60, 113,
                           (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
                           "xvmsubadp $XT, $XA, $XB", IIC_VecFP,
-                          [(set v2f64:$XT, (fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>,
+                          [(set v2f64:$XT, (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi)))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XVMSUBMDP : XX3Form<60, 121,
                           (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
                           "xvmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   let BaseName = "XVMSUBASP" in {
   let isCommutable = 1 in
   def XVMSUBASP : XX3Form<60, 81,
                           (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
                           "xvmsubasp $XT, $XA, $XB", IIC_VecFP,
-                          [(set v4f32:$XT, (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>,
+                          [(set v4f32:$XT, (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi)))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XVMSUBMSP : XX3Form<60, 89,
                           (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
                           "xvmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   let BaseName = "XVNMADDADP" in {
   let isCommutable = 1 in
   def XVNMADDADP : XX3Form<60, 225,
                           (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
                           "xvnmaddadp $XT, $XA, $XB", IIC_VecFP,
-                          [(set v2f64:$XT, (fneg (fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>,
+                          [(set v2f64:$XT, (fneg (any_fma v2f64:$XA, v2f64:$XB, v2f64:$XTi)))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XVNMADDMDP : XX3Form<60, 233,
                           (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
                           "xvnmaddmdp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   let BaseName = "XVNMADDASP" in {
   let isCommutable = 1 in
   def XVNMADDASP : XX3Form<60, 193,
                           (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
                           "xvnmaddasp $XT, $XA, $XB", IIC_VecFP,
-                          [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>,
+                          [(set v4f32:$XT, (fneg (any_fma v4f32:$XA, v4f32:$XB, v4f32:$XTi)))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XVNMADDMSP : XX3Form<60, 201,
                           (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
                           "xvnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   let BaseName = "XVNMSUBADP" in {
   let isCommutable = 1 in
   def XVNMSUBADP : XX3Form<60, 241,
                           (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
                           "xvnmsubadp $XT, $XA, $XB", IIC_VecFP,
-                          [(set v2f64:$XT, (fneg (fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi))))]>,
+                          [(set v2f64:$XT, (fneg (any_fma v2f64:$XA, v2f64:$XB, (fneg v2f64:$XTi))))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XVNMSUBMDP : XX3Form<60, 249,
                           (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
                           "xvnmsubmdp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   let BaseName = "XVNMSUBASP" in {
   let isCommutable = 1 in
   def XVNMSUBASP : XX3Form<60, 209,
                           (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
                           "xvnmsubasp $XT, $XA, $XB", IIC_VecFP,
-                          [(set v4f32:$XT, (fneg (fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>,
+                          [(set v4f32:$XT, (fneg (any_fma v4f32:$XA, v4f32:$XB, (fneg v4f32:$XTi))))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XVNMSUBMSP : XX3Form<60, 217,
                           (outs vsrc:$XT), (ins vsrc:$XTi, vsrc:$XA, vsrc:$XB),
                           "xvnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   // Division Instructions
   def XSDIVDP : XX3Form<60, 56,
                         (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB),
                         "xsdivdp $XT, $XA, $XB", IIC_FPDivD,
                         [(set f64:$XT, (any_fdiv f64:$XA, f64:$XB))]>;
   def XSSQRTDP : XX2Form<60, 75,
                         (outs vsfrc:$XT), (ins vsfrc:$XB),
                         "xssqrtdp $XT, $XB", IIC_FPSqrtD,
-                        [(set f64:$XT, (fsqrt f64:$XB))]>;
+                        [(set f64:$XT, (any_fsqrt f64:$XB))]>;
 
   def XSREDP : XX2Form<60, 90,
                         (outs vsfrc:$XT), (ins vsfrc:$XB),
                         "xsredp $XT, $XB", IIC_VecFP,
                         [(set f64:$XT, (PPCfre f64:$XB))]>;
   def XSRSQRTEDP : XX2Form<60, 74,
                            (outs vsfrc:$XT), (ins vsfrc:$XB),
                            "xsrsqrtedp $XT, $XB", IIC_VecFP,
let hasSideEffects = 0 in { // VSX instructions don't have side effects.
   def XVDIVSP : XX3Form<60, 88,
                         (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
                         "xvdivsp $XT, $XA, $XB", IIC_FPDivS,
                         [(set v4f32:$XT, (any_fdiv v4f32:$XA, v4f32:$XB))]>;
 
   def XVSQRTDP : XX2Form<60, 203,
                         (outs vsrc:$XT), (ins vsrc:$XB),
                         "xvsqrtdp $XT, $XB", IIC_FPSqrtD,
-                        [(set v2f64:$XT, (fsqrt v2f64:$XB))]>;
+                        [(set v2f64:$XT, (any_fsqrt v2f64:$XB))]>;
   def XVSQRTSP : XX2Form<60, 139,
                         (outs vsrc:$XT), (ins vsrc:$XB),
                         "xvsqrtsp $XT, $XB", IIC_FPSqrtS,
-                        [(set v4f32:$XT, (fsqrt v4f32:$XB))]>;
+                        [(set v4f32:$XT, (any_fsqrt v4f32:$XB))]>;
 
   def XVTDIVDP : XX3Form_1<60, 125,
                          (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
                          "xvtdivdp $crD, $XA, $XB", IIC_FPCompare, []>;
   def XVTDIVSP : XX3Form_1<60, 93,
                          (outs crrc:$crD), (ins vsrc:$XA, vsrc:$XB),
                          "xvtdivsp $crD, $XA, $XB", IIC_FPCompare, []>;
 

 
 def : Pat<(f64 (extractelt v2f64:$S, 0)),
           (f64 (EXTRACT_SUBREG (XXPERMDI $S, $S, 2), sub_64))>;
 def : Pat<(f64 (extractelt v2f64:$S, 1)),
           (f64 (EXTRACT_SUBREG $S, sub_64))>;
 }
 
 // Additional fnmsub patterns: -a*b + c == -(a*b - c)
-def : Pat<(fma (fneg f64:$A), f64:$B, f64:$C),
+def : Pat<(any_fma (fneg f64:$A), f64:$B, f64:$C),
           (XSNMSUBADP $C, $A, $B)>;
-def : Pat<(fma f64:$A, (fneg f64:$B), f64:$C),
+def : Pat<(any_fma f64:$A, (fneg f64:$B), f64:$C),
           (XSNMSUBADP $C, $A, $B)>;
 
-def : Pat<(fma (fneg v2f64:$A), v2f64:$B, v2f64:$C),
+def : Pat<(any_fma (fneg v2f64:$A), v2f64:$B, v2f64:$C),
           (XVNMSUBADP $C, $A, $B)>;
-def : Pat<(fma v2f64:$A, (fneg v2f64:$B), v2f64:$C),
+def : Pat<(any_fma v2f64:$A, (fneg v2f64:$B), v2f64:$C),
           (XVNMSUBADP $C, $A, $B)>;
 
-def : Pat<(fma (fneg v4f32:$A), v4f32:$B, v4f32:$C),
+def : Pat<(any_fma (fneg v4f32:$A), v4f32:$B, v4f32:$C),
           (XVNMSUBASP $C, $A, $B)>;
-def : Pat<(fma v4f32:$A, (fneg v4f32:$B), v4f32:$C),
+def : Pat<(any_fma v4f32:$A, (fneg v4f32:$B), v4f32:$C),
           (XVNMSUBASP $C, $A, $B)>;
 
 def : Pat<(v2f64 (bitconvert v4f32:$A)),
           (COPY_TO_REGCLASS $A, VSRC)>;
 def : Pat<(v2f64 (bitconvert v4i32:$A)),
           (COPY_TO_REGCLASS $A, VSRC)>;
 def : Pat<(v2f64 (bitconvert v8i16:$A)),
           (COPY_TO_REGCLASS $A, VSRC)>;
def : Pat<(vselect v4i32:$vA, v4i32:$vB, v4i32:$vC),
           (XXSEL $vC, $vB, $vA)>;
 def : Pat<(vselect v2i64:$vA, v2i64:$vB, v2i64:$vC),
           (XXSEL $vC, $vB, $vA)>;
 def : Pat<(vselect v4i32:$vA, v4f32:$vB, v4f32:$vC),
           (XXSEL $vC, $vB, $vA)>;
 def : Pat<(vselect v2i64:$vA, v2f64:$vB, v2f64:$vC),
           (XXSEL $vC, $vB, $vA)>;
 
-def : Pat<(v4f32 (fmaxnum v4f32:$src1, v4f32:$src2)),
+def : Pat<(v4f32 (any_fmaxnum v4f32:$src1, v4f32:$src2)),
           (v4f32 (XVMAXSP $src1, $src2))>;
-def : Pat<(v4f32 (fminnum v4f32:$src1, v4f32:$src2)),
+def : Pat<(v4f32 (any_fminnum v4f32:$src1, v4f32:$src2)),
           (v4f32 (XVMINSP $src1, $src2))>;
-def : Pat<(v2f64 (fmaxnum v2f64:$src1, v2f64:$src2)),
+def : Pat<(v2f64 (any_fmaxnum v2f64:$src1, v2f64:$src2)),
           (v2f64 (XVMAXDP $src1, $src2))>;
-def : Pat<(v2f64 (fminnum v2f64:$src1, v2f64:$src2)),
+def : Pat<(v2f64 (any_fminnum v2f64:$src1, v2f64:$src2)),
           (v2f64 (XVMINDP $src1, $src2))>;
 
 let Predicates = [IsLittleEndian] in {
 def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
           (f64 (XSCVSXDDP (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSFRC)))>;
 def : Pat<(f64 (PPCfcfid (PPCmtvsra (i64 (vector_extract v2i64:$S, 1))))),
           (f64 (XSCVSXDDP (COPY_TO_REGCLASS (f64 (COPY_TO_REGCLASS $S, VSRC)), VSFRC)))>;
 def : Pat<(f64 (PPCfcfidu (PPCmtvsra (i64 (vector_extract v2i64:$S, 0))))),
let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
   def XSRESP : XX2Form<60, 26,
                         (outs vssrc:$XT), (ins vssrc:$XB),
                         "xsresp $XT, $XB", IIC_VecFP,
                         [(set f32:$XT, (PPCfre f32:$XB))]>;
   def XSRSP : XX2Form<60, 281,
                         (outs vssrc:$XT), (ins vsfrc:$XB),
                         "xsrsp $XT, $XB", IIC_VecFP,
                         [(set f32:$XT, (any_fpround f64:$XB))]>;
-  } // mayRaiseFPException
   def XSSQRTSP : XX2Form<60, 11,
                         (outs vssrc:$XT), (ins vssrc:$XB),
                         "xssqrtsp $XT, $XB", IIC_FPSqrtS,
-                        [(set f32:$XT, (fsqrt f32:$XB))]>;
+                        [(set f32:$XT, (any_fsqrt f32:$XB))]>;
   def XSRSQRTESP : XX2Form<60, 10,
                            (outs vssrc:$XT), (ins vssrc:$XB),
                            "xsrsqrtesp $XT, $XB", IIC_VecFP,
                            [(set f32:$XT, (PPCfrsqrte f32:$XB))]>;
 
   // FMA Instructions
   let BaseName = "XSMADDASP" in {
   let isCommutable = 1 in
   def XSMADDASP : XX3Form<60, 1,
                           (outs vssrc:$XT),
                           (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
                           "xsmaddasp $XT, $XA, $XB", IIC_VecFP,
-                          [(set f32:$XT, (fma f32:$XA, f32:$XB, f32:$XTi))]>,
+                          [(set f32:$XT, (any_fma f32:$XA, f32:$XB, f32:$XTi))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XSMADDMSP : XX3Form<60, 9,
                           (outs vssrc:$XT),
                           (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
                           "xsmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   let BaseName = "XSMSUBASP" in {
   let isCommutable = 1 in
   def XSMSUBASP : XX3Form<60, 17,
                           (outs vssrc:$XT),
                           (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
                           "xsmsubasp $XT, $XA, $XB", IIC_VecFP,
-                          [(set f32:$XT, (fma f32:$XA, f32:$XB,
+                          [(set f32:$XT, (any_fma f32:$XA, f32:$XB,
                                               (fneg f32:$XTi)))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XSMSUBMSP : XX3Form<60, 25,
                           (outs vssrc:$XT),
                           (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
                           "xsmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   let BaseName = "XSNMADDASP" in {
   let isCommutable = 1 in
   def XSNMADDASP : XX3Form<60, 129,
                           (outs vssrc:$XT),
                           (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
                           "xsnmaddasp $XT, $XA, $XB", IIC_VecFP,
-                          [(set f32:$XT, (fneg (fma f32:$XA, f32:$XB,
+                          [(set f32:$XT, (fneg (any_fma f32:$XA, f32:$XB,
                                                     f32:$XTi)))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XSNMADDMSP : XX3Form<60, 137,
                           (outs vssrc:$XT),
                           (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
                           "xsnmaddmsp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
   let BaseName = "XSNMSUBASP" in {
   let isCommutable = 1 in
   def XSNMSUBASP : XX3Form<60, 145,
                           (outs vssrc:$XT),
                           (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
                           "xsnmsubasp $XT, $XA, $XB", IIC_VecFP,
-                          [(set f32:$XT, (fneg (fma f32:$XA, f32:$XB,
+                          [(set f32:$XT, (fneg (any_fma f32:$XA, f32:$XB,
                                                     (fneg f32:$XTi))))]>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   let IsVSXFMAAlt = 1 in
   def XSNMSUBMSP : XX3Form<60, 153,
                           (outs vssrc:$XT),
                           (ins vssrc:$XTi, vssrc:$XA, vssrc:$XB),
                           "xsnmsubmsp $XT, $XA, $XB", IIC_VecFP, []>,
                           RegConstraint<"$XTi = $XT">, NoEncode<"$XTi">,
                           AltVSXFMARel;
   }
 
-  // Additional xsnmsubasp patterns: -a*b + c == -(a*b - c)
-  def : Pat<(fma (fneg f32:$A), f32:$B, f32:$C),
-            (XSNMSUBASP $C, $A, $B)>;
-  def : Pat<(fma f32:$A, (fneg f32:$B), f32:$C),
-            (XSNMSUBASP $C, $A, $B)>;
-
   // Single Precision Conversions (FP <-> INT)
   def XSCVSXDSP : XX2Form<60, 312,
                       (outs vssrc:$XT), (ins vsfrc:$XB),
                       "xscvsxdsp $XT, $XB", IIC_VecFP,
                       [(set f32:$XT, (PPCfcfids f64:$XB))]>;
   def XSCVUXDSP : XX2Form<60, 296,
                       (outs vssrc:$XT), (ins vsfrc:$XB),
                       "xscvuxdsp $XT, $XB", IIC_VecFP,
                       [(set f32:$XT, (PPCfcfidus f64:$XB))]>;
 
   // Conversions between vector and scalar single precision
   def XSCVDPSPN : XX2Form<60, 267, (outs vsrc:$XT), (ins vssrc:$XB),
                           "xscvdpspn $XT, $XB", IIC_VecFP, []>;
   def XSCVSPDPN : XX2Form<60, 331, (outs vssrc:$XT), (ins vsrc:$XB),
                           "xscvspdpn $XT, $XB", IIC_VecFP, []>;
+  } // mayRaiseFPException
+
+  // Additional xsnmsubasp patterns: -a*b + c == -(a*b - c)
+  def : Pat<(fma (fneg f32:$A), f32:$B, f32:$C),
+            (XSNMSUBASP $C, $A, $B)>;
+  def : Pat<(fma f32:$A, (fneg f32:$B), f32:$C),
+            (XSNMSUBASP $C, $A, $B)>;
+
 
   let Predicates = [IsLittleEndian] in {
   def : Pat<DWToSPExtractConv.El0SS1,
             (f32 (XSCVSXDSP (COPY_TO_REGCLASS (XXPERMDI $S1, $S1, 2), VSFRC)))>;
   def : Pat<DWToSPExtractConv.El1SS1,
             (f32 (XSCVSXDSP (COPY_TO_REGCLASS
                               (f64 (COPY_TO_REGCLASS $S1, VSRC)), VSFRC)))>;
   def : Pat<DWToSPExtractConv.El0US1,
def XSADDQP   : X_VT5_VA5_VB5   <63,   4, "xsaddqp",
                                    [(set f128:$vT, (any_fadd f128:$vA, f128:$vB))]>;
   def XSMULQP   : X_VT5_VA5_VB5   <63,  36, "xsmulqp",
                                    [(set f128:$vT, (any_fmul f128:$vA, f128:$vB))]>;
   }
   def XSSUBQP   : X_VT5_VA5_VB5   <63, 516, "xssubqp" ,
                                    [(set f128:$vT, (any_fsub f128:$vA, f128:$vB))]>;
   def XSDIVQP   : X_VT5_VA5_VB5   <63, 548, "xsdivqp",
                                    [(set f128:$vT, (any_fdiv f128:$vA, f128:$vB))]>;
-  } // mayRaiseFPException
   // Square-Root
   def XSSQRTQP  : X_VT5_XO5_VB5   <63, 27, 804, "xssqrtqp",
-                                   [(set f128:$vT, (fsqrt f128:$vB))]>;
+                                   [(set f128:$vT, (any_fsqrt f128:$vB))]>;
   // (Negative) Multiply-{Add/Subtract}
   def XSMADDQP : X_VT5_VA5_VB5_FMA <63, 388, "xsmaddqp",
                                     [(set f128:$vT,
-                                          (fma f128:$vA, f128:$vB,
+                                          (any_fma f128:$vA, f128:$vB,
                                                f128:$vTi))]>;
   def XSMSUBQP  : X_VT5_VA5_VB5_FMA   <63, 420, "xsmsubqp"  ,
                                        [(set f128:$vT,
-                                             (fma f128:$vA, f128:$vB,
+                                             (any_fma f128:$vA, f128:$vB,
                                                   (fneg f128:$vTi)))]>;
   def XSNMADDQP : X_VT5_VA5_VB5_FMA <63, 452, "xsnmaddqp",
                                      [(set f128:$vT,
-                                           (fneg (fma f128:$vA, f128:$vB,
+                                           (fneg (any_fma f128:$vA, f128:$vB,
                                                       f128:$vTi)))]>;
   def XSNMSUBQP : X_VT5_VA5_VB5_FMA <63, 484, "xsnmsubqp",
                                      [(set f128:$vT,
-                                           (fneg (fma f128:$vA, f128:$vB,
+                                           (fneg (any_fma f128:$vA, f128:$vB,
                                                       (fneg f128:$vTi))))]>;
 
   let isCommutable = 1 in {
   def XSADDQPO : X_VT5_VA5_VB5_Ro<63, 4, "xsaddqpo",
                                   [(set f128:$vT,
                                   (int_ppc_addf128_round_to_odd
                                   f128:$vA, f128:$vB))]>;
   def XSMULQPO : X_VT5_VA5_VB5_Ro<63, 36, "xsmulqpo",
let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   def XSNMADDQPO: X_VT5_VA5_VB5_FMA_Ro<63, 452, "xsnmaddqpo",
                                       [(set f128:$vT,
                                       (fneg (int_ppc_fmaf128_round_to_odd
                                       f128:$vA, f128:$vB, f128:$vTi)))]>;
   def XSNMSUBQPO: X_VT5_VA5_VB5_FMA_Ro<63, 484, "xsnmsubqpo",
                                       [(set f128:$vT,
                                       (fneg (int_ppc_fmaf128_round_to_odd
                                       f128:$vA, f128:$vB, (fneg f128:$vTi))))]>;
+  } // mayRaiseFPException
 
   // Additional fnmsub patterns: -a*b + c == -(a*b - c)
-  def : Pat<(fma (fneg f128:$A), f128:$B, f128:$C), (XSNMSUBQP $C, $A, $B)>;
-  def : Pat<(fma f128:$A, (fneg f128:$B), f128:$C), (XSNMSUBQP $C, $A, $B)>;
+  def : Pat<(any_fma (fneg f128:$A), f128:$B, f128:$C), (XSNMSUBQP $C, $A, $B)>;
+  def : Pat<(any_fma f128:$A, (fneg f128:$B), f128:$C), (XSNMSUBQP $C, $A, $B)>;
 
   //===--------------------------------------------------------------------===//
   // Quad/Double-Precision Compare Instructions:
 
   // [PO BF // VRA VRB XO /]
   class X_BF3_VA5_VB5<bits<6> opcode, bits<10> xo, string opc,
                       list<dag> pattern>
     : XForm_17<opcode, xo, (outs crrc:$crD), (ins vrrc:$VA, vrrc:$VB),

llvm/test/CodeGen/PowerPC/fp-strict-fma-f128.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 -enable-ppc-quad-precision=true | FileCheck %s
+
+declare fp128 @llvm.experimental.constrained.fma.f128(fp128, fp128, fp128, metadata, metadata)
+
+define fp128 @f4(fp128 %f0, fp128 %f1, fp128 %f2) {
+; CHECK-LABEL: f4:
+; CHECK: xsmaddqp v4, v2, v3
+; CHECK-NEXT: vmr v2, v4
+; CHECK-NEXT: blr
+  %res = call fp128 @llvm.experimental.constrained.fma.f128(
+                        fp128 %f0, fp128 %f1, fp128 %f2,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret fp128 %res;
+}
+
+
+define fp128 @f4_1(fp128 %f0, fp128 %f1, fp128 %f2) {
+; CHECK-LABEL: f4_1:
+; CHECK: xsmsubqp v4, v2, v3
+; CHECK-NEXT: vmr v2, v4
+; CHECK-NEXT: blr
+  %f2_1 = fneg fp128 %f2
+  %res = call fp128 @llvm.experimental.constrained.fma.f128(
+                        fp128 %f0, fp128 %f1, fp128 %f2_1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret fp128 %res;
+}
+
+define fp128 @f4_2(fp128 %f0, fp128 %f1, fp128 %f2) {
+; CHECK-LABEL: f4_2:
+; CHECK: xsnmaddqp v4, v2, v3
+; CHECK-NEXT: vmr v2, v4
+; CHECK-NEXT: blr
+  %f3 = call fp128 @llvm.experimental.constrained.fma.f128(
+                        fp128 %f0, fp128 %f1, fp128 %f2,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  %f4 = fneg fp128 %f3
+  ret fp128 %f4;
+}
+
+define fp128 @f4_3(fp128 %f0, fp128 %f1, fp128 %f2) {
+; CHECK-LABEL: f4_3:
+; CHECK: xsnmsubqp v4, v2, v3
+; CHECK-NEXT: vmr v2, v4
+; CHECK-NEXT: blr
+  %f2_1 = fneg fp128 %f2
+  %f3 = call fp128 @llvm.experimental.constrained.fma.f128(
+                        fp128 %f0, fp128 %f1, fp128 %f2_1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  %f4 = fneg fp128 %f3
+  ret fp128 %f4;
+}

llvm/test/CodeGen/PowerPC/fp-strict-fma.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=NOVSX
+
+declare float @llvm.experimental.constrained.fma.f32(float, float, float, metadata, metadata)
+declare double @llvm.experimental.constrained.fma.f64(double, double, double, metadata, metadata)
+declare <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float>, <4 x float>, <4 x float>, metadata, metadata)
+declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata)
+
+define float @f1(float %f0, float %f1, float %f2) {
+; CHECK-LABEL: f1:
+; CHECK: xsmaddasp f3, f1, f2
+; CHECK-NEXT: fmr f1, f3
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f1:
+; NOVSX: fmadds f1, f1, f2, f3
+; NOVSX-NEXT: blr
+  %res = call float @llvm.experimental.constrained.fma.f32(
+                        float %f0, float %f1, float %f2,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret float %res;
+}
+
+define double @f2(double %f0, double %f1, double %f2) {
+; CHECK-LABEL: f2:
+; CHECK: xsmaddadp f3, f1, f2
+; CHECK-NEXT: fmr f1, f3
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f2:
+; NOVSX: fmadd f1, f1, f2, f3
+; NOVSX-NEXT: blr
+  %res = call double @llvm.experimental.constrained.fma.f64(
+                        double %f0, double %f1, double %f2,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret double %res;
+}
+
+define <4 x float> @f3(<4 x float> %vf0, <4 x float> %vf1, <4 x float> %vf2) {
+; CHECK-LABEL: f3:
+; CHECK: xvmaddasp v4, v2, v3
+; CHECK-NEXT: vmr v2, v4
+; CHECK-NEXT: blr
+  %res = call <4 x float> @llvm.experimental.constrained.fma.v4f32(
+                        <4 x float> %vf0, <4 x float> %vf1, <4 x float> %vf2,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret <4 x float> %res;
+}
+
+define <2 x double> @f4(<2 x double> %vf0, <2 x double> %vf1, <2 x double> %vf2) {
+; CHECK-LABEL: f4:
+; CHECK: xvmaddadp v4, v2, v3
+; CHECK-NEXT: vmr v2, v4
+; CHECK-NEXT: blr
+  %res = call <2 x double> @llvm.experimental.constrained.fma.v2f64(
+                        <2 x double> %vf0, <2 x double> %vf1, <2 x double> %vf2,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret <2 x double> %res;
+}
+
+define float @f1_1(float %f0, float %f1, float %f2) {
+; CHECK-LABEL: f1_1:
+; CHECK: xsmsubasp f3, f1, f2
+; CHECK-NEXT: fmr f1, f3
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f1_1:
+; NOVSX: fmsubs f1, f1, f2, f3
+; NOVSX-NEXT: blr
+  %f2_1 = fneg float %f2
+  %res = call float @llvm.experimental.constrained.fma.f32(
+                        float %f0, float %f1, float %f2_1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret float %res;
+}
+
+define double @f2_1(double %f0, double %f1, double %f2) {
+; CHECK-LABEL: f2_1:
+; CHECK: xsmsubadp f3, f1, f2
+; CHECK-NEXT: fmr f1, f3
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f2_1:
+; NOVSX: fmsub f1, f1, f2, f3
+; NOVSX-NEXT: blr
+  %f2_1 = fneg double %f2
+  %res = call double @llvm.experimental.constrained.fma.f64(
+                        double %f0, double %f1, double %f2_1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret double %res;
+}
+
+define <4 x float> @f3_1(<4 x float> %vf0, <4 x float> %vf1, <4 x float> %vf2) {
+; CHECK-LABEL: f3_1:
+; CHECK: xvmsubasp v4, v2, v3
+; CHECK-NEXT: vmr v2, v4
+; CHECK-NEXT: blr
+  %vf2_1 = fneg <4 x float> %vf2
+  %res = call <4 x float> @llvm.experimental.constrained.fma.v4f32(
+                        <4 x float> %vf0, <4 x float> %vf1, <4 x float> %vf2_1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret <4 x float> %res;
+}
+
+define <2 x double> @f4_1(<2 x double> %vf0, <2 x double> %vf1, <2 x double> %vf2) {
+; CHECK-LABEL: f4_1:
+; CHECK: xvmsubadp v4, v2, v3
+; CHECK-NEXT: vmr v2, v4
+; CHECK-NEXT: blr
+  %vf2_1 = fneg <2 x double> %vf2
+  %res = call <2 x double> @llvm.experimental.constrained.fma.v2f64(
+                        <2 x double> %vf0, <2 x double> %vf1, <2 x double> %vf2_1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret <2 x double> %res;
+}
+
+define float @f1_2(float %f0, float %f1, float %f2) {
+; CHECK-LABEL: f1_2:
+; CHECK: xsnmaddasp f3, f1, f2
+; CHECK-NEXT: fmr f1, f3
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f1_2:
+; NOVSX: fnmadds f1, f1, f2, f3
+; NOVSX-NEXT: blr
+  %f3 = call float @llvm.experimental.constrained.fma.f32(
+                        float %f0, float %f1, float %f2,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  %f4 = fneg float %f3
+  ret float %f4
+}
+
+define double @f2_2(double %f0, double %f1, double %f2) {
+; CHECK-LABEL: f2_2:
+; CHECK: xsnmaddadp f3, f1, f2
+; CHECK-NEXT: fmr f1, f3
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f2_2:
+; NOVSX: fnmadd f1, f1, f2, f3
+; NOVSX-NEXT: blr
+  %f3 = call double @llvm.experimental.constrained.fma.f64(
+                        double %f0, double %f1, double %f2,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  %f4 = fneg double %f3
+  ret double %f4;
+}
+
+define <4 x float> @f3_2(<4 x float> %vf0, <4 x float> %vf1, <4 x float> %vf2) {
+; CHECK-LABEL: f3_2:
+; CHECK: xvnmaddasp v4, v2, v3
+; CHECK-NEXT: vmr v2, v4
+; CHECK-NEXT: blr
+  %vf3 = call <4 x float> @llvm.experimental.constrained.fma.v4f32(
+                        <4 x float> %vf0, <4 x float> %vf1, <4 x float> %vf2,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  %vf4 = fneg <4 x float> %vf3
+  ret <4 x float> %vf4;
+}
+
+define <2 x double> @f4_2(<2 x double> %vf0, <2 x double> %vf1, <2 x double> %vf2) {
+; CHECK-LABEL: f4_2:
+; CHECK: xvnmaddadp v4, v2, v3
+; CHECK-NEXT: vmr v2, v4
+; CHECK-NEXT: blr
+  %vf3 = call <2 x double> @llvm.experimental.constrained.fma.v2f64(
+                        <2 x double> %vf0, <2 x double> %vf1, <2 x double> %vf2,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  %vf4 = fneg <2 x double> %vf3
+  ret <2 x double> %vf4;
+}
+
+define float @f1_3(float %f0, float %f1, float %f2) {
+; CHECK-LABEL: f1_3:
+; CHECK: xsnmsubasp f3, f1, f2
+; CHECK-NEXT: fmr f1, f3
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f1_3:
+; NOVSX: fnmsubs f1, f1, f2, f3
+; NOVSX-NEXT: blr
+  %f2_1 = fneg float %f2
+  %f3 = call float @llvm.experimental.constrained.fma.f32(
+                        float %f0, float %f1, float %f2_1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  %f4 = fneg float %f3
+  ret float %f4
+}
+
+define double @f2_3(double %f0, double %f1, double %f2) {
+; CHECK-LABEL: f2_3:
+; CHECK: xsnmsubadp f3, f1, f2
+; CHECK-NEXT: fmr f1, f3
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f2_3:
+; NOVSX: fnmsub f1, f1, f2, f3
+; NOVSX-NEXT: blr
+  %f2_1 = fneg double %f2
+  %f3 = call double @llvm.experimental.constrained.fma.f64(
+                        double %f0, double %f1, double %f2_1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  %f4 = fneg double %f3
+  ret double %f4;
+}
+
+define <4 x float> @f3_3(<4 x float> %vf0, <4 x float> %vf1, <4 x float> %vf2) {
+; CHECK-LABEL: f3_3:
+; CHECK: xvnmsubasp v4, v2, v3
+; CHECK-NEXT: vmr v2, v4
+; CHECK-NEXT: blr
+  %vf2_1 = fneg <4 x float> %vf2
+  %vf3 = call <4 x float> @llvm.experimental.constrained.fma.v4f32(
+                        <4 x float> %vf0, <4 x float> %vf1, <4 x float> %vf2_1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  %vf4 = fneg <4 x float> %vf3
+  ret <4 x float> %vf4;
+}
+
+define <2 x double> @f4_3(<2 x double> %vf0, <2 x double> %vf1, <2 x double> %vf2) {
+; CHECK-LABEL: f4_3:
+; CHECK: xvnmsubadp v4, v2, v3
+; CHECK-NEXT: vmr v2, v4
+; CHECK-NEXT: blr
+  %vf2_1 = fneg <2 x double> %vf2
+  %vf3 = call <2 x double> @llvm.experimental.constrained.fma.v2f64(
+                        <2 x double> %vf0, <2 x double> %vf1, <2 x double> %vf2_1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  %vf4 = fneg <2 x double> %vf3
+  ret <2 x double> %vf4;
+}

llvm/test/CodeGen/PowerPC/fp-strict-fmaxnum.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s
+
+declare <4 x float> @llvm.experimental.constrained.maxnum.v4f32(<4 x float>, <4 x float>, metadata)
+declare <2 x double> @llvm.experimental.constrained.maxnum.v2f64(<2 x double>, <2 x double>, metadata)
+
+define <4 x float> @f3(<4 x float> %vf0, <4 x float> %vf1) {
+; CHECK-LABEL: f3:
+; CHECK: xvmaxsp v2, v2, v3
+; CHECK-NEXT: blr
+  %res = call <4 x float> @llvm.experimental.constrained.maxnum.v4f32(
+                        <4 x float> %vf0, <4 x float> %vf1,
+                        metadata !"fpexcept.strict")
+  ret <4 x float> %res;
+}
+
+define <2 x double> @f4(<2 x double> %vf0, <2 x double> %vf1) {
+; CHECK-LABEL: f4:
+; CHECK: xvmaxdp v2, v2, v3
+; CHECK-NEXT: blr
+  %res = call <2 x double> @llvm.experimental.constrained.maxnum.v2f64(
+                        <2 x double> %vf0, <2 x double> %vf1,
+                        metadata !"fpexcept.strict")
+  ret <2 x double> %res;
+}

llvm/test/CodeGen/PowerPC/fp-strict-fminnum.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s
+
+declare <4 x float> @llvm.experimental.constrained.minnum.v4f32(<4 x float>, <4 x float>, metadata)
+declare <2 x double> @llvm.experimental.constrained.minnum.v2f64(<2 x double>, <2 x double>, metadata)
+
+define <4 x float> @f3(<4 x float> %vf0, <4 x float> %vf1) {
+; CHECK-LABEL: f3:
+; CHECK: xvminsp v2, v2, v3
+; CHECK-NEXT: blr
+  %res = call <4 x float> @llvm.experimental.constrained.minnum.v4f32(
+                        <4 x float> %vf0, <4 x float> %vf1,
+                        metadata !"fpexcept.strict")
+  ret <4 x float> %res;
+}
+
+define <2 x double> @f4(<2 x double> %vf0, <2 x double> %vf1) {
+; CHECK-LABEL: f4:
+; CHECK: xvmindp v2, v2, v3
+; CHECK-NEXT: blr
+  %res = call <2 x double> @llvm.experimental.constrained.minnum.v2f64(
+                        <2 x double> %vf0, <2 x double> %vf1,
+                        metadata !"fpexcept.strict")
+  ret <2 x double> %res;
+}

llvm/test/CodeGen/PowerPC/fp-strict-sqrt-f128.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 -enable-ppc-quad-precision=true | FileCheck %s
+
+declare fp128 @llvm.experimental.constrained.sqrt.f128(fp128, metadata, metadata)
+
+define fp128 @f1(fp128 %f1) {
+; CHECK-LABEL: f1:
+; CHECK: xssqrtqp v2, v2
+; CHECK-NEXT: blr
+  %res = call fp128 @llvm.experimental.constrained.sqrt.f128(
+                        fp128 %f1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret fp128 %res;
+}

llvm/test/CodeGen/PowerPC/fp-strict-sqrt.ll

+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64-unknown-linux -mcpu=pwr8 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr9 | FileCheck %s
+; RUN: llc -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s -mtriple=powerpc64le-unknown-linux -mcpu=pwr8 -mattr=-vsx | FileCheck %s -check-prefix=NOVSX
+
+declare float @llvm.experimental.constrained.sqrt.f32(float, metadata, metadata)
+declare double @llvm.experimental.constrained.sqrt.f64(double, metadata, metadata)
+declare <4 x float> @llvm.experimental.constrained.sqrt.v4f32(<4 x float>, metadata, metadata)
+declare <2 x double> @llvm.experimental.constrained.sqrt.v2f64(<2 x double>, metadata, metadata)
+
+define float @f1(float %f1) {
+; CHECK-LABEL: f1:
+; CHECK: xssqrtsp f1, f1
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f1:
+; NOVSX: fsqrts f1, f1
+; NOVSX-NEXT: blr
+  %res = call float @llvm.experimental.constrained.sqrt.f32(
+                        float %f1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret float %res;
+}
+
+define double @f2(double %f1) {
+; CHECK-LABEL: f2:
+; CHECK: xssqrtdp f1, f1
+; CHECK-NEXT: blr
+
+; NOVSX-LABEL: f2:
+; NOVSX: fsqrt f1, f1
+; NOVSX-NEXT: blr
+  %res = call double @llvm.experimental.constrained.sqrt.f64(
+                        double %f1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret double %res;
+}
+
+define <4 x float> @f3(<4 x float> %vf1) {
+; CHECK-LABEL: f3:
+; CHECK: xvsqrtsp v2, v2
+; CHECK-NEXT: blr
+  %res = call <4 x float> @llvm.experimental.constrained.sqrt.v4f32(
+                        <4 x float> %vf1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret <4 x float> %res;
+}
+
+define <2 x double> @f4(<2 x double> %vf1) {
+; CHECK-LABEL: f4:
+; CHECK: xvsqrtdp v2, v2
+; CHECK-NEXT: blr
+  %res = call <2 x double> @llvm.experimental.constrained.sqrt.v2f64(
+                        <2 x double> %vf1,
+                        metadata !"round.dynamic",
+                        metadata !"fpexcept.strict")
+  ret <2 x double> %res;
+}

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

 ; PC64LE-NEXT:    addis 3, 2, .LCPI29_0@toc@ha
 ; PC64LE-NEXT:    addis 4, 2, .LCPI29_1@toc@ha
 ; PC64LE-NEXT:    addi 3, 3, .LCPI29_0@toc@l
 ; PC64LE-NEXT:    addi 4, 4, .LCPI29_1@toc@l
 ; PC64LE-NEXT:    lxvd2x 0, 0, 3
 ; PC64LE-NEXT:    lxvd2x 1, 0, 4
 ; PC64LE-NEXT:    xxswapd 0, 0
 ; PC64LE-NEXT:    xxswapd 1, 1
-; PC64LE-NEXT:    xvsqrtdp 34, 0
-; PC64LE-NEXT:    xvsqrtdp 35, 1
+; PC64LE-NEXT:    xvsqrtdp 35, 0
+; PC64LE-NEXT:    xvsqrtdp 34, 1
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_sqrt_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI29_0@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI29_0@toc@l
 ; PC64LE9-NEXT:    lxvx 0, 0, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI29_1@toc@ha
 ; PC64LE9-NEXT:    addi 3, 3, .LCPI29_1@toc@l
-; PC64LE9-NEXT:    xvsqrtdp 34, 0
-; PC64LE9-NEXT:    lxvx 0, 0, 3
 ; PC64LE9-NEXT:    xvsqrtdp 35, 0
+; PC64LE9-NEXT:    lxvx 0, 0, 3
+; PC64LE9-NEXT:    xvsqrtdp 34, 0
 ; PC64LE9-NEXT:    blr
  entry:
   %sqrt = call <4 x double> @llvm.experimental.constrained.sqrt.v4f64(
                               <4 x double> <double 42.0, double 42.1,
                                             double 42.2, double 42.3>,
                               metadata !"round.dynamic",
                               metadata !"fpexcept.strict") #1
   ret <4 x double> %sqrt
%max = call <1 x float> @llvm.experimental.constrained.maxnum.v1f32(
                                <1 x float> <float 42.0>, <1 x float> <float 41.0>,
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %max
 }
 
 define <2 x double> @constrained_vector_maxnum_v2f64() #0 {
 ; PC64LE-LABEL: constrained_vector_maxnum_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mflr 0
-; PC64LE-NEXT:    std 0, 16(1)
-; PC64LE-NEXT:    stdu 1, -64(1)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI86_0@toc@ha
 ; PC64LE-NEXT:    addis 4, 2, .LCPI86_1@toc@ha
-; PC64LE-NEXT:    lfs 1, .LCPI86_0@toc@l(3)
-; PC64LE-NEXT:    lfs 2, .LCPI86_1@toc@l(4)
-; PC64LE-NEXT:    bl fmax
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    addis 4, 2, .LCPI86_3@toc@ha
-; PC64LE-NEXT:    stxvd2x 1, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    addis 3, 2, .LCPI86_2@toc@ha
-; PC64LE-NEXT:    lfs 2, .LCPI86_3@toc@l(4)
-; PC64LE-NEXT:    lfs 1, .LCPI86_2@toc@l(3)
-; PC64LE-NEXT:    bl fmax
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    lxvd2x 0, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    xxmrghd 34, 1, 0
-; PC64LE-NEXT:    addi 1, 1, 64
-; PC64LE-NEXT:    ld 0, 16(1)
-; PC64LE-NEXT:    mtlr 0
+; PC64LE-NEXT:    addi 3, 3, .LCPI86_0@toc@l
+; PC64LE-NEXT:    addi 4, 4, .LCPI86_1@toc@l
+; PC64LE-NEXT:    lxvd2x 0, 0, 3
+; PC64LE-NEXT:    lxvd2x 1, 0, 4
+; PC64LE-NEXT:    xxswapd 0, 0
+; PC64LE-NEXT:    xxswapd 1, 1
+; PC64LE-NEXT:    xvmaxdp 34, 1, 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_maxnum_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mflr 0
-; PC64LE9-NEXT:    std 0, 16(1)
-; PC64LE9-NEXT:    stdu 1, -48(1)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI86_0@toc@ha
-; PC64LE9-NEXT:    lfs 1, .LCPI86_0@toc@l(3)
+; PC64LE9-NEXT:    addi 3, 3, .LCPI86_0@toc@l
+; PC64LE9-NEXT:    lxvx 0, 0, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI86_1@toc@ha
-; PC64LE9-NEXT:    lfs 2, .LCPI86_1@toc@l(3)
-; PC64LE9-NEXT:    bl fmax
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    addis 3, 2, .LCPI86_2@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    stxv 1, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    lfs 1, .LCPI86_2@toc@l(3)
-; PC64LE9-NEXT:    addis 3, 2, .LCPI86_3@toc@ha
-; PC64LE9-NEXT:    lfs 2, .LCPI86_3@toc@l(3)
-; PC64LE9-NEXT:    bl fmax
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    lxv 0, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 34, 1, 0
-; PC64LE9-NEXT:    addi 1, 1, 48
-; PC64LE9-NEXT:    ld 0, 16(1)
-; PC64LE9-NEXT:    mtlr 0
+; PC64LE9-NEXT:    addi 3, 3, .LCPI86_1@toc@l
+; PC64LE9-NEXT:    lxvx 1, 0, 3
+; PC64LE9-NEXT:    xvmaxdp 34, 1, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %max = call <2 x double> @llvm.experimental.constrained.maxnum.v2f64(
                                 <2 x double> <double 43.0, double 42.0>,
                                 <2 x double> <double 41.0, double 40.0>,
                                 metadata !"fpexcept.strict") #1
   ret <2 x double> %max
 }
entry:
   ret <3 x float> %max
 }
 
 define <3 x double> @constrained_vector_max_v3f64() #0 {
 ; PC64LE-LABEL: constrained_vector_max_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
-; PC64LE-NEXT:    stdu 1, -80(1)
-; PC64LE-NEXT:    li 3, 64
-; PC64LE-NEXT:    addis 4, 2, .LCPI88_1@toc@ha
-; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    stdu 1, -32(1)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI88_0@toc@ha
-; PC64LE-NEXT:    lfs 2, .LCPI88_1@toc@l(4)
+; PC64LE-NEXT:    addis 4, 2, .LCPI88_1@toc@ha
 ; PC64LE-NEXT:    lfs 1, .LCPI88_0@toc@l(3)
+; PC64LE-NEXT:    lfs 2, .LCPI88_1@toc@l(4)
 ; PC64LE-NEXT:    bl fmax
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    addis 4, 2, .LCPI88_3@toc@ha
-; PC64LE-NEXT:    stxvd2x 1, 1, 3 # 16-byte Folded Spill
 ; PC64LE-NEXT:    addis 3, 2, .LCPI88_2@toc@ha
-; PC64LE-NEXT:    lfs 2, .LCPI88_3@toc@l(4)
-; PC64LE-NEXT:    lfs 1, .LCPI88_2@toc@l(3)
-; PC64LE-NEXT:    bl fmax
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    addis 4, 2, .LCPI88_5@toc@ha
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    lxvd2x 0, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    addis 3, 2, .LCPI88_4@toc@ha
-; PC64LE-NEXT:    lfs 2, .LCPI88_5@toc@l(4)
-; PC64LE-NEXT:    xxmrghd 63, 1, 0
-; PC64LE-NEXT:    lfs 1, .LCPI88_4@toc@l(3)
-; PC64LE-NEXT:    bl fmax
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
-; PC64LE-NEXT:    li 3, 64
-; PC64LE-NEXT:    xxlor 2, 63, 63
-; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    addis 4, 2, .LCPI88_3@toc@ha
 ; PC64LE-NEXT:    fmr 3, 1
+; PC64LE-NEXT:    addi 3, 3, .LCPI88_2@toc@l
+; PC64LE-NEXT:    addi 4, 4, .LCPI88_3@toc@l
+; PC64LE-NEXT:    lxvd2x 0, 0, 3
+; PC64LE-NEXT:    lxvd2x 2, 0, 4
+; PC64LE-NEXT:    xxswapd 0, 0
+; PC64LE-NEXT:    xxswapd 2, 2
+; PC64LE-NEXT:    xvmaxdp 2, 2, 0
+; PC64LE-NEXT:    xxswapd 0, 2
+; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    fmr 1, 0
-; PC64LE-NEXT:    addi 1, 1, 80
+; PC64LE-NEXT:    addi 1, 1, 32
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_max_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
-; PC64LE9-NEXT:    stdu 1, -64(1)
+; PC64LE9-NEXT:    stdu 1, -32(1)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI88_0@toc@ha
 ; PC64LE9-NEXT:    lfs 1, .LCPI88_0@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI88_1@toc@ha
 ; PC64LE9-NEXT:    lfs 2, .LCPI88_1@toc@l(3)
-; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
 ; PC64LE9-NEXT:    bl fmax
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI88_2@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    stxv 1, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    lfs 1, .LCPI88_2@toc@l(3)
+; PC64LE9-NEXT:    addi 3, 3, .LCPI88_2@toc@l
+; PC64LE9-NEXT:    lxvx 0, 0, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI88_3@toc@ha
-; PC64LE9-NEXT:    lfs 2, .LCPI88_3@toc@l(3)
-; PC64LE9-NEXT:    bl fmax
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    lxv 0, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    addis 3, 2, .LCPI88_4@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 1, 0
-; PC64LE9-NEXT:    lfs 1, .LCPI88_4@toc@l(3)
-; PC64LE9-NEXT:    addis 3, 2, .LCPI88_5@toc@ha
-; PC64LE9-NEXT:    lfs 2, .LCPI88_5@toc@l(3)
-; PC64LE9-NEXT:    bl fmax
-; PC64LE9-NEXT:    nop
+; PC64LE9-NEXT:    addi 3, 3, .LCPI88_3@toc@l
 ; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
-; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    lxvx 1, 0, 3
+; PC64LE9-NEXT:    xvmaxdp 2, 1, 0
+; PC64LE9-NEXT:    xxswapd 1, 2
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
-; PC64LE9-NEXT:    addi 1, 1, 64
+; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
+; PC64LE9-NEXT:    addi 1, 1, 32
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
   %max = call <3 x double> @llvm.experimental.constrained.maxnum.v3f64(
                           <3 x double> <double 43.0, double 44.0, double 45.0>,
                           <3 x double> <double 40.0, double 41.0, double 42.0>,
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %max
 }
 
 define <4 x double> @constrained_vector_maxnum_v4f64() #0 {
 ; PC64LE-LABEL: constrained_vector_maxnum_v4f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mflr 0
-; PC64LE-NEXT:    std 0, 16(1)
-; PC64LE-NEXT:    stdu 1, -80(1)
-; PC64LE-NEXT:    li 3, 64
-; PC64LE-NEXT:    addis 4, 2, .LCPI89_1@toc@ha
-; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
 ; PC64LE-NEXT:    addis 3, 2, .LCPI89_0@toc@ha
-; PC64LE-NEXT:    lfs 2, .LCPI89_1@toc@l(4)
-; PC64LE-NEXT:    lfs 1, .LCPI89_0@toc@l(3)
-; PC64LE-NEXT:    bl fmax
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    addis 4, 2, .LCPI89_3@toc@ha
-; PC64LE-NEXT:    stxvd2x 1, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    addis 3, 2, .LCPI89_2@toc@ha
-; PC64LE-NEXT:    lfs 2, .LCPI89_3@toc@l(4)
-; PC64LE-NEXT:    lfs 1, .LCPI89_2@toc@l(3)
-; PC64LE-NEXT:    bl fmax
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    addis 4, 2, .LCPI89_5@toc@ha
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    lxvd2x 0, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    addis 3, 2, .LCPI89_4@toc@ha
-; PC64LE-NEXT:    lfs 2, .LCPI89_5@toc@l(4)
-; PC64LE-NEXT:    xxmrghd 63, 1, 0
-; PC64LE-NEXT:    lfs 1, .LCPI89_4@toc@l(3)
-; PC64LE-NEXT:    bl fmax
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    addis 4, 2, .LCPI89_7@toc@ha
-; PC64LE-NEXT:    stxvd2x 1, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    addis 3, 2, .LCPI89_6@toc@ha
-; PC64LE-NEXT:    lfs 2, .LCPI89_7@toc@l(4)
-; PC64LE-NEXT:    lfs 1, .LCPI89_6@toc@l(3)
-; PC64LE-NEXT:    bl fmax
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    vmr 2, 31
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    lxvd2x 0, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    li 3, 64
-; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    xxmrghd 35, 1, 0
-; PC64LE-NEXT:    addi 1, 1, 80
-; PC64LE-NEXT:    ld 0, 16(1)
-; PC64LE-NEXT:    mtlr 0
+; PC64LE-NEXT:    addis 4, 2, .LCPI89_1@toc@ha
+; PC64LE-NEXT:    addis 5, 2, .LCPI89_2@toc@ha
+; PC64LE-NEXT:    addis 6, 2, .LCPI89_3@toc@ha
+; PC64LE-NEXT:    addi 3, 3, .LCPI89_0@toc@l
+; PC64LE-NEXT:    addi 4, 4, .LCPI89_1@toc@l
+; PC64LE-NEXT:    lxvd2x 0, 0, 3
+; PC64LE-NEXT:    lxvd2x 1, 0, 4
+; PC64LE-NEXT:    addi 3, 5, .LCPI89_2@toc@l
+; PC64LE-NEXT:    addi 4, 6, .LCPI89_3@toc@l
+; PC64LE-NEXT:    lxvd2x 2, 0, 3
+; PC64LE-NEXT:    lxvd2x 3, 0, 4
+; PC64LE-NEXT:    xxswapd 0, 0
+; PC64LE-NEXT:    xxswapd 1, 1
+; PC64LE-NEXT:    xxswapd 2, 2
+; PC64LE-NEXT:    xxswapd 3, 3
+; PC64LE-NEXT:    xvmaxdp 34, 1, 0
+; PC64LE-NEXT:    xvmaxdp 35, 3, 2
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_maxnum_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mflr 0
-; PC64LE9-NEXT:    std 0, 16(1)
-; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI89_0@toc@ha
-; PC64LE9-NEXT:    lfs 1, .LCPI89_0@toc@l(3)
+; PC64LE9-NEXT:    addi 3, 3, .LCPI89_0@toc@l
+; PC64LE9-NEXT:    lxvx 0, 0, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI89_1@toc@ha
-; PC64LE9-NEXT:    lfs 2, .LCPI89_1@toc@l(3)
-; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    bl fmax
-; PC64LE9-NEXT:    nop
+; PC64LE9-NEXT:    addi 3, 3, .LCPI89_1@toc@l
+; PC64LE9-NEXT:    lxvx 1, 0, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI89_2@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    stxv 1, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    lfs 1, .LCPI89_2@toc@l(3)
+; PC64LE9-NEXT:    addi 3, 3, .LCPI89_2@toc@l
+; PC64LE9-NEXT:    xvmaxdp 34, 1, 0
+; PC64LE9-NEXT:    lxvx 0, 0, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI89_3@toc@ha
-; PC64LE9-NEXT:    lfs 2, .LCPI89_3@toc@l(3)
-; PC64LE9-NEXT:    bl fmax
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    lxv 0, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    addis 3, 2, .LCPI89_4@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 1, 0
-; PC64LE9-NEXT:    lfs 1, .LCPI89_4@toc@l(3)
-; PC64LE9-NEXT:    addis 3, 2, .LCPI89_5@toc@ha
-; PC64LE9-NEXT:    lfs 2, .LCPI89_5@toc@l(3)
-; PC64LE9-NEXT:    bl fmax
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    addis 3, 2, .LCPI89_6@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    stxv 1, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    lfs 1, .LCPI89_6@toc@l(3)
-; PC64LE9-NEXT:    addis 3, 2, .LCPI89_7@toc@ha
-; PC64LE9-NEXT:    lfs 2, .LCPI89_7@toc@l(3)
-; PC64LE9-NEXT:    bl fmax
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    lxv 0, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    vmr 2, 31
-; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 35, 1, 0
-; PC64LE9-NEXT:    addi 1, 1, 64
-; PC64LE9-NEXT:    ld 0, 16(1)
-; PC64LE9-NEXT:    mtlr 0
+; PC64LE9-NEXT:    addi 3, 3, .LCPI89_3@toc@l
+; PC64LE9-NEXT:    lxvx 1, 0, 3
+; PC64LE9-NEXT:    xvmaxdp 35, 1, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %max = call <4 x double> @llvm.experimental.constrained.maxnum.v4f64(
                                 <4 x double> <double 44.0, double 45.0,
                                               double 46.0, double 47.0>,
                                 <4 x double> <double 40.0, double 41.0,
                                               double 42.0, double 43.0>,
                                 metadata !"fpexcept.strict") #1
%min = call <1 x float> @llvm.experimental.constrained.minnum.v1f32(
                                <1 x float> <float 42.0>, <1 x float> <float 41.0>,
                                metadata !"fpexcept.strict") #1
   ret <1 x float> %min
 }
 
 define <2 x double> @constrained_vector_minnum_v2f64() #0 {
 ; PC64LE-LABEL: constrained_vector_minnum_v2f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mflr 0
-; PC64LE-NEXT:    std 0, 16(1)
-; PC64LE-NEXT:    stdu 1, -64(1)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI91_0@toc@ha
 ; PC64LE-NEXT:    addis 4, 2, .LCPI91_1@toc@ha
-; PC64LE-NEXT:    lfs 1, .LCPI91_0@toc@l(3)
-; PC64LE-NEXT:    lfs 2, .LCPI91_1@toc@l(4)
-; PC64LE-NEXT:    bl fmin
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    addis 4, 2, .LCPI91_3@toc@ha
-; PC64LE-NEXT:    stxvd2x 1, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    addis 3, 2, .LCPI91_2@toc@ha
-; PC64LE-NEXT:    lfs 2, .LCPI91_3@toc@l(4)
-; PC64LE-NEXT:    lfs 1, .LCPI91_2@toc@l(3)
-; PC64LE-NEXT:    bl fmin
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    lxvd2x 0, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    xxmrghd 34, 1, 0
-; PC64LE-NEXT:    addi 1, 1, 64
-; PC64LE-NEXT:    ld 0, 16(1)
-; PC64LE-NEXT:    mtlr 0
+; PC64LE-NEXT:    addi 3, 3, .LCPI91_0@toc@l
+; PC64LE-NEXT:    addi 4, 4, .LCPI91_1@toc@l
+; PC64LE-NEXT:    lxvd2x 0, 0, 3
+; PC64LE-NEXT:    lxvd2x 1, 0, 4
+; PC64LE-NEXT:    xxswapd 0, 0
+; PC64LE-NEXT:    xxswapd 1, 1
+; PC64LE-NEXT:    xvmindp 34, 1, 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_minnum_v2f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mflr 0
-; PC64LE9-NEXT:    std 0, 16(1)
-; PC64LE9-NEXT:    stdu 1, -48(1)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI91_0@toc@ha
-; PC64LE9-NEXT:    lfs 1, .LCPI91_0@toc@l(3)
+; PC64LE9-NEXT:    addi 3, 3, .LCPI91_0@toc@l
+; PC64LE9-NEXT:    lxvx 0, 0, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI91_1@toc@ha
-; PC64LE9-NEXT:    lfs 2, .LCPI91_1@toc@l(3)
-; PC64LE9-NEXT:    bl fmin
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    addis 3, 2, .LCPI91_2@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    stxv 1, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    lfs 1, .LCPI91_2@toc@l(3)
-; PC64LE9-NEXT:    addis 3, 2, .LCPI91_3@toc@ha
-; PC64LE9-NEXT:    lfs 2, .LCPI91_3@toc@l(3)
-; PC64LE9-NEXT:    bl fmin
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    lxv 0, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 34, 1, 0
-; PC64LE9-NEXT:    addi 1, 1, 48
-; PC64LE9-NEXT:    ld 0, 16(1)
-; PC64LE9-NEXT:    mtlr 0
+; PC64LE9-NEXT:    addi 3, 3, .LCPI91_1@toc@l
+; PC64LE9-NEXT:    lxvx 1, 0, 3
+; PC64LE9-NEXT:    xvmindp 34, 1, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %min = call <2 x double> @llvm.experimental.constrained.minnum.v2f64(
                                 <2 x double> <double 43.0, double 42.0>,
                                 <2 x double> <double 41.0, double 40.0>,
                                 metadata !"fpexcept.strict") #1
   ret <2 x double> %min
 }
entry:
   ret <3 x float> %min
 }
 
 define <3 x double> @constrained_vector_min_v3f64() #0 {
 ; PC64LE-LABEL: constrained_vector_min_v3f64:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    mflr 0
 ; PC64LE-NEXT:    std 0, 16(1)
-; PC64LE-NEXT:    stdu 1, -80(1)
-; PC64LE-NEXT:    li 3, 64
-; PC64LE-NEXT:    addis 4, 2, .LCPI93_1@toc@ha
-; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
+; PC64LE-NEXT:    stdu 1, -32(1)
 ; PC64LE-NEXT:    addis 3, 2, .LCPI93_0@toc@ha
-; PC64LE-NEXT:    lfs 2, .LCPI93_1@toc@l(4)
+; PC64LE-NEXT:    addis 4, 2, .LCPI93_1@toc@ha
 ; PC64LE-NEXT:    lfs 1, .LCPI93_0@toc@l(3)
+; PC64LE-NEXT:    lfs 2, .LCPI93_1@toc@l(4)
 ; PC64LE-NEXT:    bl fmin
 ; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    addis 4, 2, .LCPI93_3@toc@ha
-; PC64LE-NEXT:    stxvd2x 1, 1, 3 # 16-byte Folded Spill
 ; PC64LE-NEXT:    addis 3, 2, .LCPI93_2@toc@ha
-; PC64LE-NEXT:    lfs 2, .LCPI93_3@toc@l(4)
-; PC64LE-NEXT:    lfs 1, .LCPI93_2@toc@l(3)
-; PC64LE-NEXT:    bl fmin
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    addis 4, 2, .LCPI93_5@toc@ha
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    lxvd2x 0, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    addis 3, 2, .LCPI93_4@toc@ha
-; PC64LE-NEXT:    lfs 2, .LCPI93_5@toc@l(4)
-; PC64LE-NEXT:    xxmrghd 63, 1, 0
-; PC64LE-NEXT:    lfs 1, .LCPI93_4@toc@l(3)
-; PC64LE-NEXT:    bl fmin
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    xxswapd 0, 63
-; PC64LE-NEXT:    li 3, 64
-; PC64LE-NEXT:    xxlor 2, 63, 63
-; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
+; PC64LE-NEXT:    addis 4, 2, .LCPI93_3@toc@ha
 ; PC64LE-NEXT:    fmr 3, 1
+; PC64LE-NEXT:    addi 3, 3, .LCPI93_2@toc@l
+; PC64LE-NEXT:    addi 4, 4, .LCPI93_3@toc@l
+; PC64LE-NEXT:    lxvd2x 0, 0, 3
+; PC64LE-NEXT:    lxvd2x 2, 0, 4
+; PC64LE-NEXT:    xxswapd 0, 0
+; PC64LE-NEXT:    xxswapd 2, 2
+; PC64LE-NEXT:    xvmindp 2, 2, 0
+; PC64LE-NEXT:    xxswapd 0, 2
+; PC64LE-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
 ; PC64LE-NEXT:    fmr 1, 0
-; PC64LE-NEXT:    addi 1, 1, 80
+; PC64LE-NEXT:    addi 1, 1, 32
 ; PC64LE-NEXT:    ld 0, 16(1)
 ; PC64LE-NEXT:    mtlr 0
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_min_v3f64:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    mflr 0
 ; PC64LE9-NEXT:    std 0, 16(1)
-; PC64LE9-NEXT:    stdu 1, -64(1)
+; PC64LE9-NEXT:    stdu 1, -32(1)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI93_0@toc@ha
 ; PC64LE9-NEXT:    lfs 1, .LCPI93_0@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI93_1@toc@ha
 ; PC64LE9-NEXT:    lfs 2, .LCPI93_1@toc@l(3)
-; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
 ; PC64LE9-NEXT:    bl fmin
 ; PC64LE9-NEXT:    nop
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI93_2@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    stxv 1, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    lfs 1, .LCPI93_2@toc@l(3)
+; PC64LE9-NEXT:    addi 3, 3, .LCPI93_2@toc@l
+; PC64LE9-NEXT:    lxvx 0, 0, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI93_3@toc@ha
-; PC64LE9-NEXT:    lfs 2, .LCPI93_3@toc@l(3)
-; PC64LE9-NEXT:    bl fmin
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    lxv 0, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    addis 3, 2, .LCPI93_4@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 1, 0
-; PC64LE9-NEXT:    lfs 1, .LCPI93_4@toc@l(3)
-; PC64LE9-NEXT:    addis 3, 2, .LCPI93_5@toc@ha
-; PC64LE9-NEXT:    lfs 2, .LCPI93_5@toc@l(3)
-; PC64LE9-NEXT:    bl fmin
-; PC64LE9-NEXT:    nop
+; PC64LE9-NEXT:    addi 3, 3, .LCPI93_3@toc@l
 ; PC64LE9-NEXT:    fmr 3, 1
-; PC64LE9-NEXT:    xxswapd 1, 63
-; PC64LE9-NEXT:    xscpsgndp 2, 63, 63
-; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
+; PC64LE9-NEXT:    lxvx 1, 0, 3
+; PC64LE9-NEXT:    xvmindp 2, 1, 0
+; PC64LE9-NEXT:    xxswapd 1, 2
 ; PC64LE9-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
-; PC64LE9-NEXT:    addi 1, 1, 64
+; PC64LE9-NEXT:    # kill: def $f2 killed $f2 killed $vsl2
+; PC64LE9-NEXT:    addi 1, 1, 32
 ; PC64LE9-NEXT:    ld 0, 16(1)
 ; PC64LE9-NEXT:    mtlr 0
 ; PC64LE9-NEXT:    blr
 entry:
  %min = call <3 x double> @llvm.experimental.constrained.minnum.v3f64(
                           <3 x double> <double 43.0, double 44.0, double 45.0>,
                           <3 x double> <double 40.0, double 41.0, double 42.0>,
                           metadata !"fpexcept.strict") #1
   ret <3 x double> %min
 }
 
 define <4 x double> @constrained_vector_minnum_v4f64() #0 {
 ; PC64LE-LABEL: constrained_vector_minnum_v4f64:
 ; PC64LE:       # %bb.0: # %entry
-; PC64LE-NEXT:    mflr 0
-; PC64LE-NEXT:    std 0, 16(1)
-; PC64LE-NEXT:    stdu 1, -80(1)
-; PC64LE-NEXT:    li 3, 64
-; PC64LE-NEXT:    addis 4, 2, .LCPI94_1@toc@ha
-; PC64LE-NEXT:    stxvd2x 63, 1, 3 # 16-byte Folded Spill
 ; PC64LE-NEXT:    addis 3, 2, .LCPI94_0@toc@ha
-; PC64LE-NEXT:    lfs 2, .LCPI94_1@toc@l(4)
-; PC64LE-NEXT:    lfs 1, .LCPI94_0@toc@l(3)
-; PC64LE-NEXT:    bl fmin
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    addis 4, 2, .LCPI94_3@toc@ha
-; PC64LE-NEXT:    stxvd2x 1, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    addis 3, 2, .LCPI94_2@toc@ha
-; PC64LE-NEXT:    lfs 2, .LCPI94_3@toc@l(4)
-; PC64LE-NEXT:    lfs 1, .LCPI94_2@toc@l(3)
-; PC64LE-NEXT:    bl fmin
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    addis 4, 2, .LCPI94_5@toc@ha
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    lxvd2x 0, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    addis 3, 2, .LCPI94_4@toc@ha
-; PC64LE-NEXT:    lfs 2, .LCPI94_5@toc@l(4)
-; PC64LE-NEXT:    xxmrghd 63, 1, 0
-; PC64LE-NEXT:    lfs 1, .LCPI94_4@toc@l(3)
-; PC64LE-NEXT:    bl fmin
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    addis 4, 2, .LCPI94_7@toc@ha
-; PC64LE-NEXT:    stxvd2x 1, 1, 3 # 16-byte Folded Spill
-; PC64LE-NEXT:    addis 3, 2, .LCPI94_6@toc@ha
-; PC64LE-NEXT:    lfs 2, .LCPI94_7@toc@l(4)
-; PC64LE-NEXT:    lfs 1, .LCPI94_6@toc@l(3)
-; PC64LE-NEXT:    bl fmin
-; PC64LE-NEXT:    nop
-; PC64LE-NEXT:    li 3, 48
-; PC64LE-NEXT:    vmr 2, 31
-; PC64LE-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE-NEXT:    lxvd2x 0, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    li 3, 64
-; PC64LE-NEXT:    lxvd2x 63, 1, 3 # 16-byte Folded Reload
-; PC64LE-NEXT:    xxmrghd 35, 1, 0
-; PC64LE-NEXT:    addi 1, 1, 80
-; PC64LE-NEXT:    ld 0, 16(1)
-; PC64LE-NEXT:    mtlr 0
+; PC64LE-NEXT:    addis 4, 2, .LCPI94_1@toc@ha
+; PC64LE-NEXT:    addis 5, 2, .LCPI94_2@toc@ha
+; PC64LE-NEXT:    addis 6, 2, .LCPI94_3@toc@ha
+; PC64LE-NEXT:    addi 3, 3, .LCPI94_0@toc@l
+; PC64LE-NEXT:    addi 4, 4, .LCPI94_1@toc@l
+; PC64LE-NEXT:    lxvd2x 0, 0, 3
+; PC64LE-NEXT:    lxvd2x 1, 0, 4
+; PC64LE-NEXT:    addi 3, 5, .LCPI94_2@toc@l
+; PC64LE-NEXT:    addi 4, 6, .LCPI94_3@toc@l
+; PC64LE-NEXT:    lxvd2x 2, 0, 3
+; PC64LE-NEXT:    lxvd2x 3, 0, 4
+; PC64LE-NEXT:    xxswapd 0, 0
+; PC64LE-NEXT:    xxswapd 1, 1
+; PC64LE-NEXT:    xxswapd 2, 2
+; PC64LE-NEXT:    xxswapd 3, 3
+; PC64LE-NEXT:    xvmindp 34, 1, 0
+; PC64LE-NEXT:    xvmindp 35, 3, 2
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_minnum_v4f64:
 ; PC64LE9:       # %bb.0: # %entry
-; PC64LE9-NEXT:    mflr 0
-; PC64LE9-NEXT:    std 0, 16(1)
-; PC64LE9-NEXT:    stdu 1, -64(1)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI94_0@toc@ha
-; PC64LE9-NEXT:    lfs 1, .LCPI94_0@toc@l(3)
+; PC64LE9-NEXT:    addi 3, 3, .LCPI94_0@toc@l
+; PC64LE9-NEXT:    lxvx 0, 0, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI94_1@toc@ha
-; PC64LE9-NEXT:    lfs 2, .LCPI94_1@toc@l(3)
-; PC64LE9-NEXT:    stxv 63, 48(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    bl fmin
-; PC64LE9-NEXT:    nop
+; PC64LE9-NEXT:    addi 3, 3, .LCPI94_1@toc@l
+; PC64LE9-NEXT:    lxvx 1, 0, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI94_2@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    stxv 1, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    lfs 1, .LCPI94_2@toc@l(3)
+; PC64LE9-NEXT:    addi 3, 3, .LCPI94_2@toc@l
+; PC64LE9-NEXT:    xvmindp 34, 1, 0
+; PC64LE9-NEXT:    lxvx 0, 0, 3
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI94_3@toc@ha
-; PC64LE9-NEXT:    lfs 2, .LCPI94_3@toc@l(3)
-; PC64LE9-NEXT:    bl fmin
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    lxv 0, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    addis 3, 2, .LCPI94_4@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 63, 1, 0
-; PC64LE9-NEXT:    lfs 1, .LCPI94_4@toc@l(3)
-; PC64LE9-NEXT:    addis 3, 2, .LCPI94_5@toc@ha
-; PC64LE9-NEXT:    lfs 2, .LCPI94_5@toc@l(3)
-; PC64LE9-NEXT:    bl fmin
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    addis 3, 2, .LCPI94_6@toc@ha
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    stxv 1, 32(1) # 16-byte Folded Spill
-; PC64LE9-NEXT:    lfs 1, .LCPI94_6@toc@l(3)
-; PC64LE9-NEXT:    addis 3, 2, .LCPI94_7@toc@ha
-; PC64LE9-NEXT:    lfs 2, .LCPI94_7@toc@l(3)
-; PC64LE9-NEXT:    bl fmin
-; PC64LE9-NEXT:    nop
-; PC64LE9-NEXT:    lxv 0, 32(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    vmr 2, 31
-; PC64LE9-NEXT:    lxv 63, 48(1) # 16-byte Folded Reload
-; PC64LE9-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; PC64LE9-NEXT:    xxmrghd 35, 1, 0
-; PC64LE9-NEXT:    addi 1, 1, 64
-; PC64LE9-NEXT:    ld 0, 16(1)
-; PC64LE9-NEXT:    mtlr 0
+; PC64LE9-NEXT:    addi 3, 3, .LCPI94_3@toc@l
+; PC64LE9-NEXT:    lxvx 1, 0, 3
+; PC64LE9-NEXT:    xvmindp 35, 1, 0
 ; PC64LE9-NEXT:    blr
 entry:
   %min = call <4 x double> @llvm.experimental.constrained.minnum.v4f64(
                                 <4 x double> <double 44.0, double 45.0,
                                               double 46.0, double 47.0>,
                                 <4 x double> <double 40.0, double 41.0,
                                               double 42.0, double 43.0>,
                                 metadata !"fpexcept.strict") #1