[mlir] NFC: Fix trivial typos

[kiszk]

Summary

Fix trivial typos

[antiagainst]

Nice, thanks for the fix!

[kiszk]

I do not have commit rights to the repository yet. Could someone commit this change?
Kazuaki Ishizaki <[e-mail]>

mlir/include/mlir/Dialect/SPIRV/SPIRVAvailability.td

 //===- SPIRVAvailability.td - Op Availability Base file ----*- tablegen -*-===//
 //
 // Part of the MLIR Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef SPIRV_AVAILABILITY
 #define SPIRV_AVAILABILITY
 
 include "mlir/IR/OpBase.td"
 
 //===----------------------------------------------------------------------===//
-// Op availaility definitions
+// Op availability definitions
 //===----------------------------------------------------------------------===//
 
 // The base class for defining op availability dimensions.
 class Availability {
   // The following are fields for controlling the generated C++ OpInterface.
 
   // The name for the generated C++ OpInterface subclass.
   string interfaceName = ?;

mlir/include/mlir/Dialect/SPIRV/SPIRVBase.td

def SPV_Dialect : Dialect {
   let description = [{
     SPIR-V is a binary intermediate language for representing graphical-shader
     stages and compute kernels for multiple Khronos APIs, including OpenCL,
     OpenGL, and Vulkan.
     See https://www.khronos.org/registry/spir-v for more details regarding
     SPIR-V itself.
 
     The SPIR-V dialect aims to be a proper compiler intermediate representation
-    to faciliate transformations. Ops in this dialect stay at the same semantic
+    to facilitate transformations. Ops in this dialect stay at the same semantic
     level as the SPIR-V specification and try to have one-to-one mapping to the
     corresponding SPIR-V instructions; but they may deviate representationally
     to utilize MLIR mechanisms if it results in better representation and thus
     benefits transformations. The dialect also aims to maintain straightforward
     serialization into and deserialization from the SPIR-V binary format.
     See https://mlir.llvm.org/docs/Dialects/SPIR-V/ for more details regarding
     high-level designs and implementation structures of the SPIR-V dialect.
   }];

mlir/include/mlir/Dialect/SPIRV/SPIRVTypes.h

 #define MLIR_DIALECT_SPIRV_SPIRVTYPES_H_
 
 #include "mlir/IR/StandardTypes.h"
 #include "mlir/IR/TypeSupport.h"
 #include "mlir/IR/Types.h"
 
 // Forward declare enum classes related to op availability. Their definitions
 // are in the TableGen'erated SPIRVEnums.h.inc and can be referenced by other
-// dclarations in SPIRVEnums.h.inc.
+// declarations in SPIRVEnums.h.inc.
 namespace mlir {
 namespace spirv {
 enum class Version : uint32_t;
 enum class Extension;
 enum class Capability : uint32_t;
 } // namespace spirv
 } // namespace mlir
 

mlir/include/mlir/Dialect/VectorOps/VectorOps.td

let description = [{
     according to the given mask. The legality rules are:
     * the two operands must have the same element type as the result
     * the two operands and the result must have the same rank and trailing
       dimension sizes, viz. given two k-D operands
               v1 : <s_1 x s_2 x .. x s_k x type> and
               v2 : <t_1 x t_2 x .. x t_k x type>
       we have s_i = t_i for all 1 < i <= k
     * the mask length equals the leading dimension size of the result
-    * numbering the input vector indices left to right accross the operands, all
+    * numbering the input vector indices left to right across the operands, all
       mask values must be within range, viz. given two k-D operands v1 and v2
       above, all mask values are in the range [0,s_1+t_1)
 
     Examples:
     ```
     %0 = vector.shuffle %a, %b[0, 3]
                : vector<2xf32>, vector<2xf32>       ; yields vector<2xf32>
     %1 = vector.shuffle %c, %b[0, 1, 2]

mlir/lib/Dialect/GPU/Transforms/MemoryPromotion.cpp

if (rank < GPUDialect::getNumWorkgroupDimensions()) {
     unsigned extraLoops = GPUDialect::getNumWorkgroupDimensions() - rank;
     edsc::ValueHandle zero = edsc::intrinsics::constant_index(0);
     edsc::ValueHandle one = edsc::intrinsics::constant_index(1);
     lbs.resize(extraLoops, zero);
     ubs.resize(extraLoops, one);
     steps.resize(extraLoops, one);
   }
 
-  // Add existing bonuds.
+  // Add existing bounds.
   lbs.append(bounds.getLbs().begin(), bounds.getLbs().end());
   ubs.append(bounds.getUbs().begin(), bounds.getUbs().end());
 
   // Emit constant operations for steps.
   steps.reserve(lbs.size());
   llvm::transform(
       bounds.getSteps(), std::back_inserter(steps),
       [](int64_t step) { return edsc::intrinsics::constant_index(step); });

mlir/lib/Dialect/SPIRV/SPIRVOps.cpp

private:
   // "Before version 1.4, Result Type must be a pointer, scalar, or vector.
   // Starting with version 1.4, Result Type can additionally be a composite type
   // other than a vector."
   bool isValidType(Type type) const {
     return spirv::SPIRVDialect::isValidScalarType(type) ||
            type.isa<VectorType>();
   }
 
-  // Returns a soruce value for the given block.
+  // Returns a source value for the given block.
   Value getSrcValue(Block *block) const {
     auto storeOp = cast<spirv::StoreOp>(block->front());
     return storeOp.value();
   }
 
   // Returns a destination value for the given block.
   Value getDstPtr(Block *block) const {
     auto storeOp = cast<spirv::StoreOp>(block->front());

mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp

 //===----------------------------------------------------------------------===//
 
 static void emitAvailabilityQueryForIntEnum(const Record &enumDef,
                                             raw_ostream &os) {
   EnumAttr enumAttr(enumDef);
   StringRef enumName = enumAttr.getEnumClassName();
   std::vector<EnumAttrCase> enumerants = enumAttr.getAllCases();
 
-  // Mapping from availability class name to (enumerant, availablity
+  // Mapping from availability class name to (enumerant, availability
   // specification) pairs.
   llvm::StringMap<llvm::SmallVector<std::pair<EnumAttrCase, Availability>, 1>>
       classCaseMap;
 
-  // Place all availablity specifications to their corresponding
-  // availablility classes.
+  // Place all availability specifications to their corresponding
+  // availability classes.
   for (const EnumAttrCase &enumerant : enumerants)
     for (const Availability &avail : getAvailabilities(enumerant.getDef()))
       classCaseMap[avail.getClass()].push_back({enumerant, avail});
 
   for (const auto &classCasePair : classCaseMap) {
     Availability avail = classCasePair.getValue().front().second;
 
     os << formatv("llvm::Optional<{0}> {1}({2} value) {{\n",

 
 static void emitAvailabilityQueryForBitEnum(const Record &enumDef,
                                             raw_ostream &os) {
   EnumAttr enumAttr(enumDef);
   StringRef enumName = enumAttr.getEnumClassName();
   std::string underlyingType = enumAttr.getUnderlyingType();
   std::vector<EnumAttrCase> enumerants = enumAttr.getAllCases();
 
-  // Mapping from availability class name to (enumerant, availablity
+  // Mapping from availability class name to (enumerant, availability
   // specification) pairs.
   llvm::StringMap<llvm::SmallVector<std::pair<EnumAttrCase, Availability>, 1>>
       classCaseMap;
 
-  // Place all availablity specifications to their corresponding
-  // availablility classes.
+  // Place all availability specifications to their corresponding
+  // availability classes.
   for (const EnumAttrCase &enumerant : enumerants)
     for (const Availability &avail : getAvailabilities(enumerant.getDef()))
       classCaseMap[avail.getClass()].push_back({enumerant, avail});
 
   for (const auto &classCasePair : classCaseMap) {
     Availability avail = classCasePair.getValue().front().second;
 
     os << formatv("llvm::Optional<{0}> {1}({2} value) {{\n",
static void emitEnumDecl(const Record &enumDef, raw_ostream &os) {
   llvm::SmallVector<StringRef, 2> namespaces;
   llvm::SplitString(cppNamespace, namespaces, "::");
 
   for (auto ns : namespaces)
     os << "namespace " << ns << " {\n";
 
   llvm::StringSet<> handledClasses;
 
-  // Place all availablity specifications to their corresponding
-  // availablility classes.
+  // Place all availability specifications to their corresponding
+  // availability classes.
   for (const EnumAttrCase &enumerant : enumerants)
     for (const Availability &avail : getAvailabilities(enumerant.getDef())) {
       StringRef className = avail.getClass();
       if (handledClasses.count(className))
         continue;
       os << formatv("llvm::Optional<{0}> {1}({2} value);\n",
                     avail.getMergeInstanceType(), avail.getQueryFnName(),
                     enumName);

 
 static void emitAvailabilityImpl(const Operator &srcOp, raw_ostream &os) {
   mlir::tblgen::FmtContext fctx;
   fctx.addSubst("overall", "overall");
 
   std::vector<Availability> opAvailabilities =
       getAvailabilities(srcOp.getDef());
 
-  // First collect all availablity classes this op should implement.
-  // All availablity instances keep information for the generated interface and
+  // First collect all availability classes this op should implement.
+  // All availability instances keep information for the generated interface and
   // the instance's specific requirement. Here we remember a random instance so
   // we can get the information regarding the generated interface.
   llvm::StringMap<Availability> availClasses;
   for (const Availability &avail : opAvailabilities)
     availClasses.try_emplace(avail.getClass(), avail);
   for (const NamedAttribute &namedAttr : srcOp.getAttributes()) {
     const auto *enumAttr = llvm::dyn_cast<EnumAttr>(&namedAttr.attr);
     if (!enumAttr)
for (const Availability &avail : opAvailabilities)
       }
 
     // Update with enum attributes' specific availability spec.
     for (const NamedAttribute &namedAttr : srcOp.getAttributes()) {
       const auto *enumAttr = llvm::dyn_cast<EnumAttr>(&namedAttr.attr);
       if (!enumAttr)
         continue;
 
-      // (enumerant, availablity specification) pairs for this availability
+      // (enumerant, availability specification) pairs for this availability
       // class.
       SmallVector<std::pair<EnumAttrCase, Availability>, 1> caseSpecs;
 
       // Collect all cases' availability specs.
       for (const EnumAttrCase &enumerant : enumAttr->getAllCases())
         for (const Availability &caseAvail :
              getAvailabilities(enumerant.getDef()))
           if (availClassName == caseAvail.getClass())
             caseSpecs.push_back({enumerant, caseAvail});
 
-      // If this attribute kind does not have any availablity spec from any of
+      // If this attribute kind does not have any availability spec from any of
       // its cases, no more work to do.
       if (caseSpecs.empty())
         continue;
 
       if (enumAttr->isBitEnum()) {
         // For BitEnumAttr, we need to iterate over each bit to query its
         // availability spec.
         os << formatv("  for (unsigned i = 0; "

mlir/utils/spirv/define_inst.sh

 
 # <filename> is required, which is the file name of MLIR SPIR-V op definitions
 # spec.
 # <baseclass> is required. It will be the direct base class the newly defined
 # op will drive from.
 # If <opname> is missing, this script updates existing ones in <filename>.
 
 # For example:
-# ./define_inst.sh SPIRVArithmeticOps.td ArithmeticBianryOp OpIAdd
+# ./define_inst.sh SPIRVArithmeticOps.td ArithmeticBinaryOp OpIAdd
 # ./define_inst.sh SPIRVLogicalOps.td LogicalOp OpFOrdEqual
 set -e
 
 file_name=$1
 baseclass=$2
 
 case $baseclass in
   Op | ArithmeticBinaryOp | ArithmeticUnaryOp | LogicalBinaryOp | LogicalUnaryOp | CastOp | ControlFlowOp | StructureOp | AtomicUpdateOp | AtomicUpdateWithValueOp)