Page MenuHomePhabricator

[MTE] Pin the tagged base pointer to one of the stack slots.
ClosedPublic

Authored by eugenis on Jan 7 2020, 3:02 PM.

Details

Summary

Pin the tagged base pointer to one of the stack slots, and (if
necessary) rewrite tag offsets so that an object that occupies that
slot has both address and tag offsets of 0. This allows ADDG
instructions for that object to be eliminated and their uses replaced
with the tagged base pointer itself.

This optimization must be done in machine instructions and not in the IR
instrumentation pass, because referring to a stack slot through an IRG
pointer would confuse the stack coloring pass.

The optimization makes a (pretty naive) attempt to find the slot that
would benefit the most by counting the uses of stack slots in the
function.

Diff Detail

Event Timeline

eugenis created this revision.Jan 7 2020, 3:02 PM
Herald added a project: Restricted Project. · View Herald TranscriptJan 7 2020, 3:02 PM
Herald added a subscriber: hiraditya. · View Herald Transcript

Unit tests: pass. 61305 tests passed, 0 failed and 736 were skipped.

clang-tidy: pass.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

Unit tests: pass. 62114 tests passed, 0 failed and 808 were skipped.

clang-tidy: pass.

clang-format: fail. Please format your changes with clang-format by running git-clang-format HEAD^ or applying this patch.

Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml

rankov added inline comments.Apr 24 2020, 9:53 AM
llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
256

Size of the slot might be important because of the range of addg. It can only reach 2^6 tag granules (64 * 16B) from base register. If you select a large slot it will reduce the number of slots that can be reached with addg and will result in additional add instructions.

Also, it might be beneficial to sort smaller slots near the SP.

llvm/test/CodeGen/AArch64/irg_sp_tagp.ll
53

There is no addg anymore.

61

Why not check that there is no more addg?

70

No more addg.

74–78

This might not be guaranteed to be x1

79

Check that addg is not there?

97–101

Might not be x1 here.

98

Check that there is no addg.

eugenis marked an inline comment as done.Apr 27 2020, 1:53 PM
eugenis added inline comments.
llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp
256

I've tried sorting by size and/or access density (size / number of references) in D72366, but could not show any significant improvement. There are conflicting requirements there between minimizing the average ld/st immediate offset, maximizing the number of references to the object with tag 0 & offset 0, and keeping the objects that are untagged at the same time together (for STG merging).

I may return to this problem at some later time.

eugenis updated this revision to Diff 261566.May 1 2020, 3:57 PM
eugenis marked 3 inline comments as done.

address comments

eugenis marked 4 inline comments as done.May 1 2020, 3:57 PM
danielkiss accepted this revision.Mon, Oct 12, 6:49 AM

LGTM, just please fix the lint issues in the llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h

This revision is now accepted and ready to land.Mon, Oct 12, 6:49 AM

Sorry, I don't see any lint issues. Could you be more specific?

Those are gone from the view, so ignore what I said.

This revision was landed with ongoing or failed builds.Thu, Oct 15, 1:06 PM
This revision was automatically updated to reflect the committed changes.