This is an archive of the discontinued LLVM Phabricator instance.

Differential D71421

[ARM][MVE][Intrinsics] Add *_x() variants of my *_m() intrinsics.
ClosedPublic

Authored by MarkMurrayARM on Dec 12 2019, 8:28 AM.

Details

Reviewers
dmgreen
miyuki
ostannard
simon_tatham
Commits
rG228c74076d51: [ARM][MVE][Intrinsics] Add *_x() variants of my *_m() intrinsics.
Summary

Better use of multiclass is used, and this helped find some existing bugs
in the predicated VMULL* intrinsics, which are now fixed.

The refactored VMULL[TB]Q_(INT|POLY)_M() intrinsics were discovered
to have an argument ("inactive") with incorrect type, and this required
a fix that is included in this whole patch. The argument "inactive"
should have been the same width (per vector element) as the return
type of the intrinsic, but was not in the case where the return type
was double the element width of the input types.

To assist in testing the multiclassing , and to thwart further gremlins,
the unit tests are improved in scope.

The *.ll tests are all generated by a small bit of throw-away scripting
from the corresponding *.c tests, and as such the diffs are large and
nasty. Look at the file rather than the diff.

Diff Detail

Event Timeline

MarkMurrayARM created this revision.Dec 12 2019, 8:28 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptDec 12 2019, 8:28 AM
Herald added subscribers: llvm-commits, cfe-commits, hiraditya, kristof.beyls. · View Herald Transcript
Harbormaster completed remote builds in B42395: Diff 233626.Dec 12 2019, 8:32 AM
MarkMurrayARM updated this revision to Diff 233647.Dec 12 2019, 9:34 AM

Reformat commit message.

Harbormaster completed remote builds in B42407: Diff 233647.Dec 12 2019, 9:37 AM
MarkMurrayARM updated this revision to Diff 233764.Dec 13 2019, 3:17 AM

Shorten title/subject line.

MarkMurrayARM retitled this revision from [ARM][MVE][Intrinsics] Add *_x_*() variants of all the *_m_*() intrinsics added by me to this point. Better use of multiclass is used, and this helped find some existing bugs in the predicated VMULL* intrinsics, which are now fixed. to [ARM][MVE][Intrinsics] Add *_x() variants of my *_m() intrinsics. .Dec 13 2019, 3:19 AM
MarkMurrayARM edited the summary of this revision. (Show Details)
Harbormaster completed remote builds in B42453: Diff 233764.Dec 13 2019, 3:22 AM
simon_tatham accepted this revision.Dec 13 2019, 3:23 AM

LGTM. I must admit that I probably didn't manage to take in every single detail of the revised test collection, but the shape of it looks generally nice, and everything I spot-checked looked spot-on. And the diffs in actual source files are definitely an improvement :-)

This revision is now accepted and ready to land.Dec 13 2019, 3:23 AM
Closed by commit rG228c74076d51: [ARM][MVE][Intrinsics] Add *_x() variants of my *_m() intrinsics. (authored by MarkMurrayARM). · Explain WhyDec 13 2019, 3:59 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
clang/
include/
clang/
Basic/
123 lines
test/
CodeGen/
arm-mve-intrinsics/
48 lines
52 lines
127 lines
129 lines
127 lines
48 lines
32 lines
48 lines
32 lines
48 lines
48 lines
80 lines
80 lines
64 lines
129 lines
127 lines
48 lines
48 lines
vsubq.c
vaddq.c
52 lines
llvm/
include/
llvm/
IR/
4 lines
lib/
Target/
ARM/
4 lines
test/
CodeGen/
Thumb2/
mve-intrinsics/
111 lines
83 lines
109 lines
113 lines
109 lines
43 lines
38 lines
97 lines
37 lines
55 lines
43 lines
84 lines
82 lines
133 lines
113 lines
109 lines
43 lines
43 lines
93 lines

Diff 233647

clang/include/clang/Basic/arm_mve.td

Show First 20 Lines • Show All 129 Lines • ▼ Show 20 Lines
} }
// Plain intrinsics // Plain intrinsics
let params = T.Usual in { let params = T.Usual in {
def vabdq: Intrinsic<Vector, (args Vector:$a, Vector:$b), def vabdq: Intrinsic<Vector, (args Vector:$a, Vector:$b),
(IRInt<"vabd", [Vector]> $a, $b)>; (IRInt<"vabd", [Vector]> $a, $b)>;
} }
multiclass VectorVectorArithmetic<string operation> {
defm "" : IntrinsicMX<Vector, (args Vector:$a, Vector:$b,
Predicate:$pred),
(IRInt<operation, [Vector, Predicate]> $a, $b,
$pred, $inactive)>;
}
multiclass VectorVectorArithmeticBitcast<string operation> {
defm "" : IntrinsicMX<Vector, (args Vector:$a, Vector:$b,
Predicate:$pred),
(bitcast (IRInt<operation, [UVector, Predicate]>
(bitcast $a, UVector),
(bitcast $b, UVector),
$pred,
(bitcast $inactive, UVector)), Vector)>;
}
// Predicated intrinsics // Predicated intrinsics
let params = T.Usual in { let params = T.Usual in {
def vabdq_m: Intrinsic< defm vabdq : VectorVectorArithmetic<"abd_predicated">;
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred), defm vaddq : VectorVectorArithmetic<"add_predicated">;
(IRInt<"abd_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>; defm vsubq : VectorVectorArithmetic<"sub_predicated">;
def vaddq_m: Intrinsic< defm vmulq : VectorVectorArithmetic<"mul_predicated">;
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred), defm vandq : VectorVectorArithmeticBitcast<"and_predicated">;
(IRInt<"add_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>; defm vbicq : VectorVectorArithmeticBitcast<"bic_predicated">;
def vsubq_m: Intrinsic< defm veorq : VectorVectorArithmeticBitcast<"eor_predicated">;
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred), defm vornq : VectorVectorArithmeticBitcast<"orn_predicated">;
(IRInt<"sub_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>; defm vorrq : VectorVectorArithmeticBitcast<"orr_predicated">;
def vmulq_m: Intrinsic< }
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
(IRInt<"mul_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>; multiclass DblVectorVectorArithmetic<string operation, dag top> {
defm vandq_m: predicated_bit_op_fp<"and_predicated">; defm "" : IntrinsicMX<DblVector, (args Vector:$a, Vector:$b,
defm vbicq_m: predicated_bit_op_fp<"bic_predicated">; Predicate:$pred),
defm veorq_m: predicated_bit_op_fp<"eor_predicated">; (IRInt<operation,
defm vornq_m: predicated_bit_op_fp<"orn_predicated">; [DblVector, Vector, Predicate]>
defm vorrq_m: predicated_bit_op_fp<"orr_predicated">; $a, $b, top, $pred, $inactive)>;
} }
// Predicated intrinsics - Int types only // Predicated intrinsics - Int types only
let params = T.Int in { let params = T.Int in {
def vminq_m: Intrinsic< defm vminq : VectorVectorArithmetic<"min_predicated">;
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred), defm vmaxq : VectorVectorArithmetic<"max_predicated">;
(IRInt<"min_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>; defm vmulhq : VectorVectorArithmetic<"mulh_predicated">;
def vmaxq_m: Intrinsic< defm vrmulhq : VectorVectorArithmetic<"rmulh_predicated">;
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred), defm vqdmulhq : VectorVectorArithmetic<"qdmulh_predicated">;
(IRInt<"max_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>; defm vqrdmulhq : VectorVectorArithmetic<"qrdmulh_predicated">;
def vmulhq_m: Intrinsic< defm vqaddq : VectorVectorArithmetic<"qadd_predicated">;
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred), defm vhaddq : VectorVectorArithmetic<"hadd_predicated">;
(IRInt<"mulh_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>; defm vrhaddq : VectorVectorArithmetic<"rhadd_predicated">;
def vrmulhq_m: Intrinsic< defm vqsubq : VectorVectorArithmetic<"qsub_predicated">;
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred), defm vhsubq : VectorVectorArithmetic<"hsub_predicated">;
(IRInt<"rmulh_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>; defm vmullbq_int : DblVectorVectorArithmetic<"mull_int_predicated", (u32 0)>;
def vqdmulhq_m: Intrinsic< defm vmulltq_int : DblVectorVectorArithmetic<"mull_int_predicated", (u32 1)>;
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
(IRInt<"qdmulh_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
def vqrdmulhq_m: Intrinsic<
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
(IRInt<"qrdmulh_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
def vmullbq_int_m: Intrinsic<
DblVector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
(IRInt<"mull_int_predicated", [DblVector, Vector, Predicate]> $a, $b, 0,
$pred, $inactive)>;
def vmulltq_int_m: Intrinsic<
DblVector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
(IRInt<"mull_int_predicated", [DblVector, Vector, Predicate]> $a, $b, 1,
$pred, $inactive)>;
def vqaddq_m: Intrinsic<
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
(IRInt<"qadd_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
def vhaddq_m: Intrinsic<
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
(IRInt<"hadd_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
def vrhaddq_m: Intrinsic<
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
(IRInt<"rhadd_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
def vqsubq_m: Intrinsic<
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
(IRInt<"qsub_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
def vhsubq_m: Intrinsic<
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
(IRInt<"hsub_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
} }
let params = T.Poly, overrideKindLetter = "p" in { let params = T.Poly, overrideKindLetter = "p" in {
def vmullbq_poly_m: Intrinsic< defm vmullbq_poly : DblVectorVectorArithmetic<"mull_poly_predicated", (u32 0)>;
DblVector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred), defm vmulltq_poly : DblVectorVectorArithmetic<"mull_poly_predicated", (u32 1)>;
(IRInt<"mull_poly_predicated", [DblVector, Vector, Predicate]> $a, $b, 0,
$pred, $inactive)>;
def vmulltq_poly_m: Intrinsic<
DblVector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
(IRInt<"mull_poly_predicated", [DblVector, Vector, Predicate]> $a, $b, 1,
$pred, $inactive)>;
} }
// Predicated intrinsics - Float types only // Predicated intrinsics - Float types only
let params = T.Float in { let params = T.Float in {
def vminnmq_m: Intrinsic< defm vminnmq : VectorVectorArithmetic<"min_predicated">;
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred), defm vmaxnmq : VectorVectorArithmetic<"max_predicated">;
(IRInt<"min_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
def vmaxnmq_m: Intrinsic<
Vector, (args Vector:$inactive, Vector:$a, Vector:$b, Predicate:$pred),
(IRInt<"max_predicated", [Vector, Predicate]> $a, $b, $pred, $inactive)>;
} }
let params = T.Int in { let params = T.Int in {
def vminvq: Intrinsic<Scalar, (args Scalar:$prev, Vector:$vec), def vminvq: Intrinsic<Scalar, (args Scalar:$prev, Vector:$vec),
(Scalar (IRInt<"minv", [Vector], 1> $prev, $vec))>; (Scalar (IRInt<"minv", [Vector], 1> $prev, $vec))>;
def vmaxvq: Intrinsic<Scalar, (args Scalar:$prev, Vector:$vec), def vmaxvq: Intrinsic<Scalar, (args Scalar:$prev, Vector:$vec),
(Scalar (IRInt<"maxv", [Vector], 1> $prev, $vec))>; (Scalar (IRInt<"maxv", [Vector], 1> $prev, $vec))>;
} }
▲ Show 20 Lines • Show All 572 Lines • Show Last 20 Lines

clang/test/CodeGen/arm-mve-intrinsics/vabdq.c

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
float32x4_t test_vabdq_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) float32x4_t test_vabdq_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vabdq_m(inactive, a, b, p); return vabdq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vabdq_m_f32(inactive, a, b, p); return vabdq_m_f32(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vabdq_x_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
uint16x8_t test_vabdq_x_u16(uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vabdq_x(a, b, p);
#else /* POLYMORPHIC */
return vabdq_x_u16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vabdq_x_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_vabdq_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vabdq_x(a, b, p);
#else /* POLYMORPHIC */
return vabdq_x_u32(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vabdq_x_f16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]], <8 x half> undef)
// CHECK-NEXT: ret <8 x half> [[TMP2]]
//
float16x8_t test_vabdq_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vabdq_x(a, b, p);
#else /* POLYMORPHIC */
return vabdq_x_f16(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/vaddq.c

  • This file was copied to clang/test/CodeGen/arm-mve-intrinsics/vsubq.c.
Show All 12 Lines
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vaddq(a, b); return vaddq(a, b);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vaddq_u32(a, b); return vaddq_u32(a, b);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vsubq_f16( // CHECK-LABEL: @test_vaddq_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = fsub <8 x half> [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[TMP0:%.*]] = fadd <8 x half> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <8 x half> [[TMP0]] // CHECK-NEXT: ret <8 x half> [[TMP0]]
// //
float16x8_t test_vsubq_f16(float16x8_t a, float16x8_t b) float16x8_t test_vaddq_f16(float16x8_t a, float16x8_t b)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vsubq(a, b); return vaddq(a, b);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vsubq_f16(a, b); return vaddq_f16(a, b);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vaddq_m_s8( // CHECK-LABEL: @test_vaddq_m_s8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <16 x i8> [[TMP2]] // CHECK-NEXT: ret <16 x i8> [[TMP2]]
// //
int8x16_t test_vaddq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) int8x16_t test_vaddq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vaddq_m(inactive, a, b, p); return vaddq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vaddq_m_s8(inactive, a, b, p); return vaddq_m_s8(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vsubq_m_f32( // CHECK-LABEL: @test_vaddq_m_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]], <4 x float> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]], <4 x float> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x float> [[TMP2]] // CHECK-NEXT: ret <4 x float> [[TMP2]]
// //
float32x4_t test_vsubq_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) float32x4_t test_vaddq_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vaddq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vaddq_m_f32(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vaddq_x_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
uint16x8_t test_vaddq_x_u16(uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vaddq_x(a, b, p);
#else /* POLYMORPHIC */
return vaddq_x_u16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vaddq_x_f16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]], <8 x half> undef)
// CHECK-NEXT: ret <8 x half> [[TMP2]]
//
float16x8_t test_vaddq_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vsubq_m(inactive, a, b, p); return vaddq_x(a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vsubq_m_f32(inactive, a, b, p); return vaddq_x_f16(a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }

clang/test/CodeGen/arm-mve-intrinsics/vandq.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
#include <arm_mve.h> #include <arm_mve.h>
// CHECK-LABEL: @test_vandq_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = and <16 x i8> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <16 x i8> [[TMP0]]
//
uint8x16_t test_vandq_u8(uint8x16_t a, uint8x16_t b)
{
#ifdef POLYMORPHIC
return vandq(a, b);
#else /* POLYMORPHIC */
return vandq_u8(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vandq_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = and <8 x i16> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
int16x8_t test_vandq_s16(int16x8_t a, int16x8_t b)
{
#ifdef POLYMORPHIC
return vandq(a, b);
#else /* POLYMORPHIC */
return vandq_s16(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vandq_u32( // CHECK-LABEL: @test_vandq_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = and <4 x i32> [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[TMP0:%.*]] = and <4 x i32> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
uint32x4_t test_vandq_u32(uint32x4_t a, uint32x4_t b) uint32x4_t test_vandq_u32(uint32x4_t a, uint32x4_t b)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
Show All 31 Lines
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vandq_m(inactive, a, b, p); return vandq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vandq_m_s8(inactive, a, b, p); return vandq_m_s8(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vandq_m_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
uint16x8_t test_vandq_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vandq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vandq_m_u16(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vandq_m_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
int32x4_t test_vandq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vandq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vandq_m_s32(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vandq_m_f16( // CHECK-LABEL: @test_vandq_m_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP3:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP2]]) // CHECK-NEXT: [[TMP3:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP2]])
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x half> [[INACTIVE:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x half> [[INACTIVE:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP5:%.*]] = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> [[TMP0]], <8 x i16> [[TMP1]], <8 x i1> [[TMP3]], <8 x i16> [[TMP4]]) // CHECK-NEXT: [[TMP5:%.*]] = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> [[TMP0]], <8 x i16> [[TMP1]], <8 x i1> [[TMP3]], <8 x i16> [[TMP4]])
// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP5]] to <8 x half> // CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP5]] to <8 x half>
// CHECK-NEXT: ret <8 x half> [[TMP6]] // CHECK-NEXT: ret <8 x half> [[TMP6]]
// //
float16x8_t test_vandq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) float16x8_t test_vandq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vandq_m(inactive, a, b, p); return vandq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vandq_m_f16(inactive, a, b, p); return vandq_m_f16(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vandq_x_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> undef)
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
uint8x16_t test_vandq_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vandq_x(a, b, p);
#else /* POLYMORPHIC */
return vandq_x_u8(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vandq_x_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
int16x8_t test_vandq_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vandq_x(a, b, p);
#else /* POLYMORPHIC */
return vandq_x_s16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vandq_x_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_vandq_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vandq_x(a, b, p);
#else /* POLYMORPHIC */
return vandq_x_u32(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vandq_m_f32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A:%.*]] to <4 x i32>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B:%.*]] to <4 x i32>
// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP2]])
// CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> [[TMP0]], <4 x i32> [[TMP1]], <4 x i1> [[TMP3]], <4 x i32> undef)
// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[TMP5]]
//
float32x4_t test_vandq_m_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vandq_x(a, b, p);
#else /* POLYMORPHIC */
return vandq_x_f32(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/vbicq.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
#include <arm_mve.h> #include <arm_mve.h>
// CHECK-LABEL: @test_vbicq_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <16 x i8> [[B:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[TMP1:%.*]] = and <16 x i8> [[A:%.*]], [[TMP0]]
// CHECK-NEXT: ret <16 x i8> [[TMP1]]
//
uint8x16_t test_vbicq_u8(uint8x16_t a, uint8x16_t b)
{
#ifdef POLYMORPHIC
return vbicq(a, b);
#else /* POLYMORPHIC */
return vbicq_u8(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vbicq_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <8 x i16> [[B:%.*]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK-NEXT: [[TMP1:%.*]] = and <8 x i16> [[A:%.*]], [[TMP0]]
// CHECK-NEXT: ret <8 x i16> [[TMP1]]
//
int16x8_t test_vbicq_s16(int16x8_t a, int16x8_t b)
{
#ifdef POLYMORPHIC
return vbicq(a, b);
#else /* POLYMORPHIC */
return vbicq_s16(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vbicq_u32( // CHECK-LABEL: @test_vbicq_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <4 x i32> [[B:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1> // CHECK-NEXT: [[TMP0:%.*]] = xor <4 x i32> [[B:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], [[TMP0]] // CHECK-NEXT: [[TMP1:%.*]] = and <4 x i32> [[A:%.*]], [[TMP0]]
// CHECK-NEXT: ret <4 x i32> [[TMP1]] // CHECK-NEXT: ret <4 x i32> [[TMP1]]
// //
uint32x4_t test_vbicq_u32(uint32x4_t a, uint32x4_t b) uint32x4_t test_vbicq_u32(uint32x4_t a, uint32x4_t b)
{ {
Show All 33 Lines
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vbicq_m(inactive, a, b, p); return vbicq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vbicq_m_s8(inactive, a, b, p); return vbicq_m_s8(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vbicq_m_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
uint16x8_t test_vbicq_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vbicq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vbicq_m_u16(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vbicq_m_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
int32x4_t test_vbicq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vbicq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vbicq_m_s32(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vbicq_m_f16( // CHECK-LABEL: @test_vbicq_m_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP3:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP2]]) // CHECK-NEXT: [[TMP3:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP2]])
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x half> [[INACTIVE:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x half> [[INACTIVE:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP5:%.*]] = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> [[TMP0]], <8 x i16> [[TMP1]], <8 x i1> [[TMP3]], <8 x i16> [[TMP4]]) // CHECK-NEXT: [[TMP5:%.*]] = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> [[TMP0]], <8 x i16> [[TMP1]], <8 x i1> [[TMP3]], <8 x i16> [[TMP4]])
// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP5]] to <8 x half> // CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP5]] to <8 x half>
// CHECK-NEXT: ret <8 x half> [[TMP6]] // CHECK-NEXT: ret <8 x half> [[TMP6]]
// //
float16x8_t test_vbicq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) float16x8_t test_vbicq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vbicq_m(inactive, a, b, p); return vbicq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vbicq_m_f16(inactive, a, b, p); return vbicq_m_f16(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vbicq_x_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> undef)
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
uint8x16_t test_vbicq_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vbicq_x(a, b, p);
#else /* POLYMORPHIC */
return vbicq_x_u8(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vbicq_x_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
int16x8_t test_vbicq_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vbicq_x(a, b, p);
#else /* POLYMORPHIC */
return vbicq_x_s16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vbicq_x_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_vbicq_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vbicq_x(a, b, p);
#else /* POLYMORPHIC */
return vbicq_x_u32(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vbicq_m_f32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A:%.*]] to <4 x i32>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B:%.*]] to <4 x i32>
// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP2]])
// CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> [[TMP0]], <4 x i32> [[TMP1]], <4 x i1> [[TMP3]], <4 x i32> undef)
// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[TMP5]]
//
float32x4_t test_vbicq_m_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vbicq_x(a, b, p);
#else /* POLYMORPHIC */
return vbicq_x_f32(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/veorq.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
#include <arm_mve.h> #include <arm_mve.h>
// CHECK-LABEL: @test_veorq_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <16 x i8> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <16 x i8> [[TMP0]]
//
uint8x16_t test_veorq_u8(uint8x16_t a, uint8x16_t b)
{
#ifdef POLYMORPHIC
return veorq(a, b);
#else /* POLYMORPHIC */
return veorq_u8(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_veorq_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <8 x i16> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
int16x8_t test_veorq_s16(int16x8_t a, int16x8_t b)
{
#ifdef POLYMORPHIC
return veorq(a, b);
#else /* POLYMORPHIC */
return veorq_s16(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_veorq_u32( // CHECK-LABEL: @test_veorq_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <4 x i32> [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[TMP0:%.*]] = xor <4 x i32> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
uint32x4_t test_veorq_u32(uint32x4_t a, uint32x4_t b) uint32x4_t test_veorq_u32(uint32x4_t a, uint32x4_t b)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
Show All 31 Lines
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return veorq_m(inactive, a, b, p); return veorq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return veorq_m_s8(inactive, a, b, p); return veorq_m_s8(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_veorq_m_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
uint16x8_t test_veorq_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return veorq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return veorq_m_u16(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_veorq_m_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
int32x4_t test_veorq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return veorq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return veorq_m_s32(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_veorq_m_f16( // CHECK-LABEL: @test_veorq_m_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP3:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP2]]) // CHECK-NEXT: [[TMP3:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP2]])
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x half> [[INACTIVE:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x half> [[INACTIVE:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP5:%.*]] = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> [[TMP0]], <8 x i16> [[TMP1]], <8 x i1> [[TMP3]], <8 x i16> [[TMP4]]) // CHECK-NEXT: [[TMP5:%.*]] = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> [[TMP0]], <8 x i16> [[TMP1]], <8 x i1> [[TMP3]], <8 x i16> [[TMP4]])
// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP5]] to <8 x half> // CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP5]] to <8 x half>
// CHECK-NEXT: ret <8 x half> [[TMP6]] // CHECK-NEXT: ret <8 x half> [[TMP6]]
// //
float16x8_t test_veorq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) float16x8_t test_veorq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return veorq_m(inactive, a, b, p); return veorq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return veorq_m_f16(inactive, a, b, p); return veorq_m_f16(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_veorq_x_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> undef)
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
uint8x16_t test_veorq_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return veorq_x(a, b, p);
#else /* POLYMORPHIC */
return veorq_x_u8(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_veorq_x_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
int16x8_t test_veorq_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return veorq_x(a, b, p);
#else /* POLYMORPHIC */
return veorq_x_s16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_veorq_x_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_veorq_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return veorq_x(a, b, p);
#else /* POLYMORPHIC */
return veorq_x_u32(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_veorq_m_f32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A:%.*]] to <4 x i32>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B:%.*]] to <4 x i32>
// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP2]])
// CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> [[TMP0]], <4 x i32> [[TMP1]], <4 x i1> [[TMP3]], <4 x i32> undef)
// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[TMP5]]
//
float32x4_t test_veorq_m_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return veorq_x(a, b, p);
#else /* POLYMORPHIC */
return veorq_x_f32(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/vhaddq.c

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
int32x4_t test_vhaddq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) int32x4_t test_vhaddq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vhaddq_m(inactive, a, b, p); return vhaddq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vhaddq_m_s32(inactive, a, b, p); return vhaddq_m_s32(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vhaddq_x_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> undef)
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
uint8x16_t test_vhaddq_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vhaddq_x(a, b, p);
#else /* POLYMORPHIC */
return vhaddq_x_u8(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vhaddq_x_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
int16x8_t test_vhaddq_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vhaddq_x(a, b, p);
#else /* POLYMORPHIC */
return vhaddq_x_s16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vhaddq_x_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_vhaddq_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vhaddq_x(a, b, p);
#else /* POLYMORPHIC */
return vhaddq_x_u32(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/vmaxnmq.c

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
float32x4_t test_vmaxnmq_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) float32x4_t test_vmaxnmq_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmaxnmq_m(inactive, a, b, p); return vmaxnmq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmaxnmq_m_f32(inactive, a, b, p); return vmaxnmq_m_f32(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmaxnmq_x_f16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = tail call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]], <8 x half> undef)
// CHECK-NEXT: ret <8 x half> [[TMP2]]
//
float16x8_t test_vmaxnmq_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmaxnmq_x(a, b, p);
#else /* POLYMORPHIC */
return vmaxnmq_x_f16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmaxnmq_x_f32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]], <4 x float> undef)
// CHECK-NEXT: ret <4 x float> [[TMP2]]
//
float32x4_t test_vmaxnmq_x_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmaxnmq_x(a, b, p);
#else /* POLYMORPHIC */
return vmaxnmq_x_f32(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/vmaxq.c

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
uint32x4_t test_vmaxq_m_u32(uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) uint32x4_t test_vmaxq_m_u32(uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmaxq_m(inactive, a, b, p); return vmaxq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmaxq_m_u32(inactive, a, b, p); return vmaxq_m_u32(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmaxq_x_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = tail call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> undef)
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
int8x16_t test_vmaxq_x_u8(int8x16_t a, int8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmaxq_x(a, b, p);
#else /* POLYMORPHIC */
return vmaxq_x_s8(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmaxq_x_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = tail call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
uint16x8_t test_vmaxq_x_u16(uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmaxq_x(a, b, p);
#else /* POLYMORPHIC */
return vmaxq_x_u16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmaxq_x_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
int32x4_t test_vmaxq_x_s32(int32x4_t a, int32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmaxq_x(a, b, p);
#else /* POLYMORPHIC */
return vmaxq_x_u32(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/vminnmq.c

Show First 20 Lines • Show All 57 Lines • ▼ Show 20 Lines
float32x4_t test_vminnmq_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) float32x4_t test_vminnmq_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vminnmq_m(inactive, a, b, p); return vminnmq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vminnmq_m_f32(inactive, a, b, p); return vminnmq_m_f32(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vminnmq_x_f16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = tail call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]], <8 x half> undef)
// CHECK-NEXT: ret <8 x half> [[TMP2]]
//
float16x8_t test_vminnmq_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vminnmq_x(a, b, p);
#else /* POLYMORPHIC */
return vminnmq_x_f16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vminnmq_x_f32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]], <4 x float> undef)
// CHECK-NEXT: ret <4 x float> [[TMP2]]
//
float32x4_t test_vminnmq_x_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vminnmq_x(a, b, p);
#else /* POLYMORPHIC */
return vminnmq_x_f32(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/vminq.c

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines
int32x4_t test_vminq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) int32x4_t test_vminq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vminq_m(inactive, a, b, p); return vminq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vminq_m_s32(inactive, a, b, p); return vminq_m_s32(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vminq_x_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = tail call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> undef)
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
uint8x16_t test_vminq_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vminq_x(a, b, p);
#else /* POLYMORPHIC */
return vminq_x_u8(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vminq_x_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = tail call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
int16x8_t test_vminq_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vminq_x(a, b, p);
#else /* POLYMORPHIC */
return vminq_x_u16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vminq_x_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_vminq_x_s32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vminq_x(a, b, p);
#else /* POLYMORPHIC */
return vminq_x_u32(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/vmulhq.c

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
int32x4_t test_vmulhq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) int32x4_t test_vmulhq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmulhq_m(inactive, a, b, p); return vmulhq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmulhq_m_s32(inactive, a, b, p); return vmulhq_m_s32(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmulhq_x_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> undef)
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
uint8x16_t test_vmulhq_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulhq_x(a, b, p);
#else /* POLYMORPHIC */
return vmulhq_x_u8(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulhq_x_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
int16x8_t test_vmulhq_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulhq_x(a, b, p);
#else /* POLYMORPHIC */
return vmulhq_x_s16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulhq_x_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_vmulhq_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulhq_x(a, b, p);
#else /* POLYMORPHIC */
return vmulhq_x_u32(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/vmullbq.c

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines#else /* POLYMORPHIC */
return vmullbq_poly_p16(a, b); return vmullbq_poly_p16(a, b);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmullbq_int_m_s8( // CHECK-LABEL: @test_vmullbq_int_m_s8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, <16 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
int16x8_t test_vmullbq_int_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) int16x8_t test_vmullbq_int_m_s8(int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmullbq_int_m(inactive, a, b, p); return vmullbq_int_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmullbq_int_m_s8(inactive, a, b, p); return vmullbq_int_m_s8(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmullbq_int_m_u16( // CHECK-LABEL: @test_vmullbq_int_m_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, <8 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
uint32x4_t test_vmullbq_int_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) uint32x4_t test_vmullbq_int_m_u16(uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmullbq_int_m(inactive, a, b, p); return vmullbq_int_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmullbq_int_m_u16(inactive, a, b, p); return vmullbq_int_m_u16(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmullbq_int_m_s32( // CHECK-LABEL: @test_vmullbq_int_m_s32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, <4 x i1> [[TMP1]], <2 x i64> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <2 x i64> [[TMP2]] // CHECK-NEXT: ret <2 x i64> [[TMP2]]
// //
int64x2_t test_vmullbq_int_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) int64x2_t test_vmullbq_int_m_s32(int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmullbq_int_m(inactive, a, b, p); return vmullbq_int_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmullbq_int_m_s32(inactive, a, b, p); return vmullbq_int_m_s32(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmullbq_poly_m_p8( // CHECK-LABEL: @test_vmullbq_poly_m_p8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, <16 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
uint16x8_t test_vmullbq_poly_m_p8(uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) uint16x8_t test_vmullbq_poly_m_p8(uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmullbq_poly_m(inactive, a, b, p); return vmullbq_poly_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmullbq_poly_m_p8(inactive, a, b, p); return vmullbq_poly_m_p8(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmullbq_int_x_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 0, <16 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
uint16x8_t test_vmullbq_int_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmullbq_int_x(a, b, p);
#else /* POLYMORPHIC */
return vmullbq_int_x_s8(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmullbq_int_x_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, <8 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
int32x4_t test_vmullbq_int_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmullbq_int_x(a, b, p);
#else /* POLYMORPHIC */
return vmullbq_int_x_u16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmullbq_int_x_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 0, <4 x i1> [[TMP1]], <2 x i64> undef)
// CHECK-NEXT: ret <2 x i64> [[TMP2]]
//
uint64x2_t test_vmullbq_int_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmullbq_int_x(a, b, p);
#else /* POLYMORPHIC */
return vmullbq_int_x_s32(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmullbq_poly_x_p16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.poly.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 0, <8 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_vmullbq_poly_x_p16(uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmullbq_poly_x(a, b, p);
#else /* POLYMORPHIC */
return vmullbq_poly_x_p16(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/vmulltq.c

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines#else /* POLYMORPHIC */
return vmulltq_poly_p16(a, b); return vmulltq_poly_p16(a, b);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmulltq_int_m_s8( // CHECK-LABEL: @test_vmulltq_int_m_s8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, <16 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
int16x8_t test_vmulltq_int_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) int16x8_t test_vmulltq_int_m_s8(int16x8_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmulltq_int_m(inactive, a, b, p); return vmulltq_int_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmulltq_int_m_s8(inactive, a, b, p); return vmulltq_int_m_s8(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmulltq_int_m_u16( // CHECK-LABEL: @test_vmulltq_int_m_u16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, <8 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x i32> [[TMP2]] // CHECK-NEXT: ret <4 x i32> [[TMP2]]
// //
uint32x4_t test_vmulltq_int_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) uint32x4_t test_vmulltq_int_m_u16(uint32x4_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmulltq_int_m(inactive, a, b, p); return vmulltq_int_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmulltq_int_m_u16(inactive, a, b, p); return vmulltq_int_m_u16(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmulltq_int_m_s32( // CHECK-LABEL: @test_vmulltq_int_m_s32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, <4 x i1> [[TMP1]], <2 x i64> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <2 x i64> [[TMP2]] // CHECK-NEXT: ret <2 x i64> [[TMP2]]
// //
int64x2_t test_vmulltq_int_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) int64x2_t test_vmulltq_int_m_s32(int64x2_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmulltq_int_m(inactive, a, b, p); return vmulltq_int_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmulltq_int_m_s32(inactive, a, b, p); return vmulltq_int_m_s32(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmulltq_poly_m_p8( // CHECK-LABEL: @test_vmulltq_poly_m_p8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, <16 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]] // CHECK-NEXT: ret <8 x i16> [[TMP2]]
// //
uint16x8_t test_vmulltq_poly_m_p8(uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) uint16x8_t test_vmulltq_poly_m_p8(uint16x8_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmulltq_poly_m(inactive, a, b, p); return vmulltq_poly_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmulltq_poly_m_p8(inactive, a, b, p); return vmulltq_poly_m_p8(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmulltq_int_x_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, <16 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
uint16x8_t test_vmulltq_int_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulltq_int_x(a, b, p);
#else /* POLYMORPHIC */
return vmulltq_int_x_u8(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulltq_int_x_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], i32 1, <8 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
int32x4_t test_vmulltq_int_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulltq_int_x(a, b, p);
#else /* POLYMORPHIC */
return vmulltq_int_x_s16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulltq_int_x_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], i32 1, <4 x i1> [[TMP1]], <2 x i64> undef)
// CHECK-NEXT: ret <2 x i64> [[TMP2]]
//
uint64x2_t test_vmulltq_int_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulltq_int_x(a, b, p);
#else /* POLYMORPHIC */
return vmulltq_int_x_u32(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulltq_poly_x_p8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], i32 1, <16 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
uint16x8_t test_vmulltq_poly_x_p8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulltq_poly_x(a, b, p);
#else /* POLYMORPHIC */
return vmulltq_poly_x_p8(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/vmulq.c

Show First 20 Lines • Show All 117 Lines • ▼ Show 20 Lines
float16x8_t test_vmulq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) float16x8_t test_vmulq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vmulq_m(inactive, a, b, p); return vmulq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vmulq_m_f16(inactive, a, b, p); return vmulq_m_f16(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vmulq_x_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> undef)
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
uint8x16_t test_vmulq_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_x(a, b, p);
#else /* POLYMORPHIC */
return vmulq_x_u8(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_x_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
int16x8_t test_vmulq_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_x(a, b, p);
#else /* POLYMORPHIC */
return vmulq_x_s16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_x_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_vmulq_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_x(a, b, p);
#else /* POLYMORPHIC */
return vmulq_x_u32(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vmulq_m_f32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]], <4 x float> undef)
// CHECK-NEXT: ret <4 x float> [[TMP2]]
//
float32x4_t test_vmulq_m_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vmulq_x(a, b, p);
#else /* POLYMORPHIC */
return vmulq_x_f32(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/vornq.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
#include <arm_mve.h> #include <arm_mve.h>
// CHECK-LABEL: @test_vornq_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <16 x i8> [[B:%.*]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK-NEXT: [[TMP1:%.*]] = or <16 x i8> [[A:%.*]], [[TMP0]]
// CHECK-NEXT: ret <16 x i8> [[TMP1]]
//
uint8x16_t test_vornq_u8(uint8x16_t a, uint8x16_t b)
{
#ifdef POLYMORPHIC
return vornq(a, b);
#else /* POLYMORPHIC */
return vornq_u8(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vornq_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <8 x i16> [[B:%.*]], <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
// CHECK-NEXT: [[TMP1:%.*]] = or <8 x i16> [[A:%.*]], [[TMP0]]
// CHECK-NEXT: ret <8 x i16> [[TMP1]]
//
int16x8_t test_vornq_s16(int16x8_t a, int16x8_t b)
{
#ifdef POLYMORPHIC
return vornq(a, b);
#else /* POLYMORPHIC */
return vornq_s16(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vornq_u32( // CHECK-LABEL: @test_vornq_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = xor <4 x i32> [[B:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1> // CHECK-NEXT: [[TMP0:%.*]] = xor <4 x i32> [[B:%.*]], <i32 -1, i32 -1, i32 -1, i32 -1>
// CHECK-NEXT: [[TMP1:%.*]] = or <4 x i32> [[A:%.*]], [[TMP0]] // CHECK-NEXT: [[TMP1:%.*]] = or <4 x i32> [[A:%.*]], [[TMP0]]
// CHECK-NEXT: ret <4 x i32> [[TMP1]] // CHECK-NEXT: ret <4 x i32> [[TMP1]]
// //
uint32x4_t test_vornq_u32(uint32x4_t a, uint32x4_t b) uint32x4_t test_vornq_u32(uint32x4_t a, uint32x4_t b)
{ {
Show All 33 Lines
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vornq_m(inactive, a, b, p); return vornq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vornq_m_s8(inactive, a, b, p); return vornq_m_s8(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vornq_m_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
uint16x8_t test_vornq_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vornq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vornq_m_u16(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vornq_m_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
int32x4_t test_vornq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vornq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vornq_m_s32(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vornq_m_f16( // CHECK-LABEL: @test_vornq_m_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP3:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP2]]) // CHECK-NEXT: [[TMP3:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP2]])
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x half> [[INACTIVE:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x half> [[INACTIVE:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP5:%.*]] = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> [[TMP0]], <8 x i16> [[TMP1]], <8 x i1> [[TMP3]], <8 x i16> [[TMP4]]) // CHECK-NEXT: [[TMP5:%.*]] = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> [[TMP0]], <8 x i16> [[TMP1]], <8 x i1> [[TMP3]], <8 x i16> [[TMP4]])
// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP5]] to <8 x half> // CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP5]] to <8 x half>
// CHECK-NEXT: ret <8 x half> [[TMP6]] // CHECK-NEXT: ret <8 x half> [[TMP6]]
// //
float16x8_t test_vornq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) float16x8_t test_vornq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vornq_m(inactive, a, b, p); return vornq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vornq_m_f16(inactive, a, b, p); return vornq_m_f16(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vornq_x_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> undef)
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
uint8x16_t test_vornq_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vornq_x(a, b, p);
#else /* POLYMORPHIC */
return vornq_x_u8(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vornq_x_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
int16x8_t test_vornq_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vornq_x(a, b, p);
#else /* POLYMORPHIC */
return vornq_x_s16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vornq_x_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_vornq_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vornq_x(a, b, p);
#else /* POLYMORPHIC */
return vornq_x_u32(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vornq_m_f32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A:%.*]] to <4 x i32>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B:%.*]] to <4 x i32>
// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP2]])
// CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> [[TMP0]], <4 x i32> [[TMP1]], <4 x i1> [[TMP3]], <4 x i32> undef)
// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[TMP5]]
//
float32x4_t test_vornq_m_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vornq_x(a, b, p);
#else /* POLYMORPHIC */
return vornq_x_f32(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/vorrq.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
#include <arm_mve.h> #include <arm_mve.h>
// CHECK-LABEL: @test_vorrq_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = or <16 x i8> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <16 x i8> [[TMP0]]
//
uint8x16_t test_vorrq_u8(uint8x16_t a, uint8x16_t b)
{
#ifdef POLYMORPHIC
return vorrq(a, b);
#else /* POLYMORPHIC */
return vorrq_u8(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vorrq_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = or <8 x i16> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <8 x i16> [[TMP0]]
//
int16x8_t test_vorrq_s16(int16x8_t a, int16x8_t b)
{
#ifdef POLYMORPHIC
return vorrq(a, b);
#else /* POLYMORPHIC */
return vorrq_s16(a, b);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vorrq_u32( // CHECK-LABEL: @test_vorrq_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = or <4 x i32> [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[TMP0:%.*]] = or <4 x i32> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
uint32x4_t test_vorrq_u32(uint32x4_t a, uint32x4_t b) uint32x4_t test_vorrq_u32(uint32x4_t a, uint32x4_t b)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
Show All 31 Lines
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vorrq_m(inactive, a, b, p); return vorrq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vorrq_m_s8(inactive, a, b, p); return vorrq_m_s8(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vorrq_m_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
uint16x8_t test_vorrq_m_u16(uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vorrq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vorrq_m_u16(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vorrq_m_s32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
int32x4_t test_vorrq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vorrq_m(inactive, a, b, p);
#else /* POLYMORPHIC */
return vorrq_m_s32(inactive, a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vorrq_m_f16( // CHECK-LABEL: @test_vorrq_m_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x half> [[A:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x half> [[B:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP3:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP2]]) // CHECK-NEXT: [[TMP3:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP2]])
// CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x half> [[INACTIVE:%.*]] to <8 x i16> // CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x half> [[INACTIVE:%.*]] to <8 x i16>
// CHECK-NEXT: [[TMP5:%.*]] = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> [[TMP0]], <8 x i16> [[TMP1]], <8 x i1> [[TMP3]], <8 x i16> [[TMP4]]) // CHECK-NEXT: [[TMP5:%.*]] = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> [[TMP0]], <8 x i16> [[TMP1]], <8 x i1> [[TMP3]], <8 x i16> [[TMP4]])
// CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP5]] to <8 x half> // CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP5]] to <8 x half>
// CHECK-NEXT: ret <8 x half> [[TMP6]] // CHECK-NEXT: ret <8 x half> [[TMP6]]
// //
float16x8_t test_vorrq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) float16x8_t test_vorrq_m_f16(float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vorrq_m(inactive, a, b, p); return vorrq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vorrq_m_f16(inactive, a, b, p); return vorrq_m_f16(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vorrq_x_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> undef)
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
uint8x16_t test_vorrq_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vorrq_x(a, b, p);
#else /* POLYMORPHIC */
return vorrq_x_u8(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vorrq_x_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
int16x8_t test_vorrq_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vorrq_x(a, b, p);
#else /* POLYMORPHIC */
return vorrq_x_s16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vorrq_x_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_vorrq_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vorrq_x(a, b, p);
#else /* POLYMORPHIC */
return vorrq_x_u32(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vorrq_m_f32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x float> [[A:%.*]] to <4 x i32>
// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x float> [[B:%.*]] to <4 x i32>
// CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP3:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP2]])
// CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> [[TMP0]], <4 x i32> [[TMP1]], <4 x i1> [[TMP3]], <4 x i32> undef)
// CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP4]] to <4 x float>
// CHECK-NEXT: ret <4 x float> [[TMP5]]
//
float32x4_t test_vorrq_m_f32(float32x4_t a, float32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vorrq_x(a, b, p);
#else /* POLYMORPHIC */
return vorrq_x_f32(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/vrhaddq.c

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
int32x4_t test_vrhaddq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) int32x4_t test_vrhaddq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vrhaddq_m(inactive, a, b, p); return vrhaddq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vrhaddq_m_s32(inactive, a, b, p); return vrhaddq_m_s32(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vrhaddq_x_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> undef)
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
uint8x16_t test_vrhaddq_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vrhaddq_x(a, b, p);
#else /* POLYMORPHIC */
return vrhaddq_x_u8(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vrhaddq_x_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
int16x8_t test_vrhaddq_x_u16(int16x8_t a, int16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vrhaddq_x(a, b, p);
#else /* POLYMORPHIC */
return vrhaddq_x_u16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vrhaddq_x_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_vrhaddq_x_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vrhaddq_x(a, b, p);
#else /* POLYMORPHIC */
return vrhaddq_x_u32(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/vrmulhq.c

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
int32x4_t test_vrmulhq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) int32x4_t test_vrmulhq_m_s32(int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vrmulhq_m(inactive, a, b, p); return vrmulhq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vrmulhq_m_s32(inactive, a, b, p); return vrmulhq_m_s32(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vrmulhq_x_u8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> undef)
// CHECK-NEXT: ret <16 x i8> [[TMP2]]
//
uint8x16_t test_vrmulhq_x_u8(uint8x16_t a, uint8x16_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vrmulhq_x(a, b, p);
#else /* POLYMORPHIC */
return vrmulhq_x_u8(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vrmulhq_x_s16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
int16x8_t test_vrmulhq_x_s16(int16x8_t a, int16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vrmulhq_x(a, b, p);
#else /* POLYMORPHIC */
return vrmulhq_x_s16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vrmulhq_m_u32(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i1> [[TMP1]], <4 x i32> undef)
// CHECK-NEXT: ret <4 x i32> [[TMP2]]
//
uint32x4_t test_vrmulhq_m_u32(uint32x4_t a, uint32x4_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vrmulhq_x(a, b, p);
#else /* POLYMORPHIC */
return vrmulhq_x_u32(a, b, p);
#endif /* POLYMORPHIC */
}

clang/test/CodeGen/arm-mve-intrinsics/vsubq.c

  • This file was copied from clang/test/CodeGen/arm-mve-intrinsics/vaddq.c.
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
// RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s // RUN: %clang_cc1 -triple thumbv8.1m.main-arm-none-eabi -target-feature +mve.fp -mfloat-abi hard -fallow-half-arguments-and-returns -O0 -disable-O0-optnone -DPOLYMORPHIC -S -emit-llvm -o - %s | opt -S -mem2reg | FileCheck %s
#include <arm_mve.h> #include <arm_mve.h>
// CHECK-LABEL: @test_vaddq_u32( // CHECK-LABEL: @test_vsubq_u32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = add <4 x i32> [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[TMP0:%.*]] = sub <4 x i32> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <4 x i32> [[TMP0]] // CHECK-NEXT: ret <4 x i32> [[TMP0]]
// //
uint32x4_t test_vaddq_u32(uint32x4_t a, uint32x4_t b) uint32x4_t test_vsubq_u32(uint32x4_t a, uint32x4_t b)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vaddq(a, b); return vsubq(a, b);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vaddq_u32(a, b); return vsubq_u32(a, b);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vsubq_f16( // CHECK-LABEL: @test_vsubq_f16(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = fsub <8 x half> [[A:%.*]], [[B:%.*]] // CHECK-NEXT: [[TMP0:%.*]] = fsub <8 x half> [[A:%.*]], [[B:%.*]]
// CHECK-NEXT: ret <8 x half> [[TMP0]] // CHECK-NEXT: ret <8 x half> [[TMP0]]
// //
float16x8_t test_vsubq_f16(float16x8_t a, float16x8_t b) float16x8_t test_vsubq_f16(float16x8_t a, float16x8_t b)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vsubq(a, b); return vsubq(a, b);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vsubq_f16(a, b); return vsubq_f16(a, b);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vaddq_m_s8( // CHECK-LABEL: @test_vsubq_m_s8(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i1> [[TMP1]], <16 x i8> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <16 x i8> [[TMP2]] // CHECK-NEXT: ret <16 x i8> [[TMP2]]
// //
int8x16_t test_vaddq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) int8x16_t test_vsubq_m_s8(int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vaddq_m(inactive, a, b, p); return vsubq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vaddq_m_s8(inactive, a, b, p); return vsubq_m_s8(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vsubq_m_f32( // CHECK-LABEL: @test_vsubq_m_f32(
// CHECK-NEXT: entry: // CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32 // CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]]) // CHECK-NEXT: [[TMP1:%.*]] = call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]], <4 x float> [[INACTIVE:%.*]]) // CHECK-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x i1> [[TMP1]], <4 x float> [[INACTIVE:%.*]])
// CHECK-NEXT: ret <4 x float> [[TMP2]] // CHECK-NEXT: ret <4 x float> [[TMP2]]
// //
float32x4_t test_vsubq_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) float32x4_t test_vsubq_m_f32(float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p)
{ {
#ifdef POLYMORPHIC #ifdef POLYMORPHIC
return vsubq_m(inactive, a, b, p); return vsubq_m(inactive, a, b, p);
#else /* POLYMORPHIC */ #else /* POLYMORPHIC */
return vsubq_m_f32(inactive, a, b, p); return vsubq_m_f32(inactive, a, b, p);
#endif /* POLYMORPHIC */ #endif /* POLYMORPHIC */
} }
// CHECK-LABEL: @test_vsubq_x_u16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i1> [[TMP1]], <8 x i16> undef)
// CHECK-NEXT: ret <8 x i16> [[TMP2]]
//
uint16x8_t test_vsubq_x_u16(uint16x8_t a, uint16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vsubq_x(a, b, p);
#else /* POLYMORPHIC */
return vsubq_x_u16(a, b, p);
#endif /* POLYMORPHIC */
}
// CHECK-LABEL: @test_vsubq_x_f16(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = zext i16 [[P:%.*]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 [[TMP0]])
// CHECK-NEXT: [[TMP2:%.*]] = call <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half> [[A:%.*]], <8 x half> [[B:%.*]], <8 x i1> [[TMP1]], <8 x half> undef)
// CHECK-NEXT: ret <8 x half> [[TMP2]]
//
float16x8_t test_vsubq_x_f16(float16x8_t a, float16x8_t b, mve_pred16_t p)
{
#ifdef POLYMORPHIC
return vsubq_x(a, b, p);
#else /* POLYMORPHIC */
return vsubq_x_f16(a, b, p);
#endif /* POLYMORPHIC */
}

llvm/include/llvm/IR/IntrinsicsARM.td

Show First 20 Lines • Show All 842 Lines • ▼ Show 20 Lines
def int_arm_mve_rmulh_predicated: Intrinsic<[llvm_anyvector_ty], def int_arm_mve_rmulh_predicated: Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
[IntrNoMem]>; [IntrNoMem]>;
def int_arm_mve_qrdmulh_predicated: Intrinsic<[llvm_anyvector_ty], def int_arm_mve_qrdmulh_predicated: Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
[IntrNoMem]>; [IntrNoMem]>;
def int_arm_mve_mull_int_predicated: Intrinsic<[llvm_anyvector_ty], def int_arm_mve_mull_int_predicated: Intrinsic<[llvm_anyvector_ty],
[llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty, llvm_anyvector_ty, [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty, llvm_anyvector_ty,
LLVMMatchType<1>], LLVMMatchType<0>],
[IntrNoMem]>; [IntrNoMem]>;
def int_arm_mve_mull_poly_predicated: Intrinsic<[llvm_anyvector_ty], def int_arm_mve_mull_poly_predicated: Intrinsic<[llvm_anyvector_ty],
[llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty, llvm_anyvector_ty, [llvm_anyvector_ty, LLVMMatchType<1>, llvm_i32_ty, llvm_anyvector_ty,
LLVMMatchType<1>], LLVMMatchType<0>],
[IntrNoMem]>; [IntrNoMem]>;
def int_arm_mve_qadd_predicated: Intrinsic<[llvm_anyvector_ty], def int_arm_mve_qadd_predicated: Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
[IntrNoMem]>; [IntrNoMem]>;
def int_arm_mve_hadd_predicated: Intrinsic<[llvm_anyvector_ty], def int_arm_mve_hadd_predicated: Intrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>], [LLVMMatchType<0>, LLVMMatchType<0>, llvm_anyvector_ty, LLVMMatchType<0>],
[IntrNoMem]>; [IntrNoMem]>;
def int_arm_mve_rhadd_predicated: Intrinsic<[llvm_anyvector_ty], def int_arm_mve_rhadd_predicated: Intrinsic<[llvm_anyvector_ty],
▲ Show 20 Lines • Show All 167 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMInstrMVE.td

Show First 20 Lines • Show All 3,825 Lines • ▼ Show 20 Lines let Predicates = [HasMVEInt] in {
def : Pat<(VTI.DblVec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), def : Pat<(VTI.DblVec (unpred_op (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
(i32 Top))), (i32 Top))),
(VTI.DblVec (!cast<Instruction>(NAME) (VTI.DblVec (!cast<Instruction>(NAME)
(VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>; (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn)))>;
// Predicated multiply // Predicated multiply
def : Pat<(VTI.DblVec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), def : Pat<(VTI.DblVec (pred_int (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
(i32 Top), (i32 Top),
(VTI.Pred VCCR:$mask), (VTI.Vec MQPR:$inactive))), (VTI.Pred VCCR:$mask), (VTI.DblVec MQPR:$inactive))),
(VTI.DblVec (!cast<Instruction>(NAME) (VTI.DblVec (!cast<Instruction>(NAME)
(VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn), (VTI.Vec MQPR:$Qm), (VTI.Vec MQPR:$Qn),
ARMVCCThen, (VTI.Pred VCCR:$mask), ARMVCCThen, (VTI.Pred VCCR:$mask),
(VTI.Vec MQPR:$inactive)))>; (VTI.DblVec MQPR:$inactive)))>;
} }
} }
// For polynomial multiplies, the size bits take the unused value 0b11, and // For polynomial multiplies, the size bits take the unused value 0b11, and
// the unsigned bit switches to encoding the size. // the unsigned bit switches to encoding the size.
defm MVE_VMULLBs8 : MVE_VMULL_m<MVE_v16s8, int_arm_mve_vmull, defm MVE_VMULLBs8 : MVE_VMULL_m<MVE_v16s8, int_arm_mve_vmull,
int_arm_mve_mull_int_predicated, 0b0>; int_arm_mve_mull_int_predicated, 0b0>;
▲ Show 20 Lines • Show All 2,274 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/mve-intrinsics/vabdq.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
define arm_aapcs_vfpcc <4 x i32> @test_vabdq_u32(<4 x i32> %a, <4 x i32> %b) { define arm_aapcs_vfpcc <16 x i8> @test_vabdq_s8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vabdq_s8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vabd.s8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = tail call <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8> %a, <16 x i8> %b)
ret <16 x i8> %0
}
declare <16 x i8> @llvm.arm.mve.vabd.v16i8(<16 x i8>, <16 x i8>) #1
define arm_aapcs_vfpcc <4 x i32> @test_vabdq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vabdq_u32: ; CHECK-LABEL: test_vabdq_u32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vabd.s32 q0, q0, q1 ; CHECK-NEXT: vabd.s32 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = tail call <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32>%a, <4 x i32>%b) %0 = tail call <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32> %a, <4 x i32> %b)
ret <4 x i32> %0 ret <4 x i32> %0
} }
declare <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32>, <4 x i32>) declare <4 x i32> @llvm.arm.mve.vabd.v4i32(<4 x i32>, <4 x i32>) #1
define arm_aapcs_vfpcc <4 x float> @test_vabdq_f32(<4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <8 x half> @test_vabdq_f32(<8 x half> %a, <8 x half> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vabdq_f32: ; CHECK-LABEL: test_vabdq_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vabd.f32 q0, q0, q1 ; CHECK-NEXT: vabd.f16 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = tail call <4 x float> @llvm.arm.mve.vabd.v4f32(<4 x float>%a, <4 x float>%b) %0 = tail call <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half> %a, <8 x half> %b)
ret <4 x float> %0 ret <8 x half> %0
} }
declare <4 x float> @llvm.arm.mve.vabd.v4f32(<4 x float>, <4 x float>) declare <8 x half> @llvm.arm.mve.vabd.v8f16(<8 x half>, <8 x half>) #1
define arm_aapcs_vfpcc <16 x i8> @test_vabdq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vabdq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vabdq_m_u16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vabdt.s16 q0, q1, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2
}
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
declare <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #1
define arm_aapcs_vfpcc <16 x i8> @test_vabdq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vabdq_m_s8: ; CHECK-LABEL: test_vabdq_m_s8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vabdt.s8 q0, q1, q2 ; CHECK-NEXT: vabdt.s8 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive) %2 = tail call <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive)
ret <16 x i8> %2 ret <16 x i8> %2
} }
declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
declare <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #1
define arm_aapcs_vfpcc <4 x float> @test_vabdq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vabdq_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vabdt.f32 q0, q1, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, <4 x i1> %1, <4 x float> %inactive)
ret <4 x float> %2
}
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
declare <4 x float> @llvm.arm.mve.abd.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #1
define arm_aapcs_vfpcc <8 x i16> @test_vabdq_x_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vabdq_x_u16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vabdt.s16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.abd.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vabdq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vabdq_x_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vabdt.s32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2
}
declare <16 x i8> @llvm.arm.mve.abd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) declare <4 x i32> @llvm.arm.mve.abd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
define arm_aapcs_vfpcc <8 x half> @test_vabdq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x half> @test_vabdq_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vabdq_m_f16: ; CHECK-LABEL: test_vabdq_x_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vabdt.f16 q0, q1, q2 ; CHECK-NEXT: vabdt.f16 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1, <8 x half> %inactive) %2 = tail call <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1, <8 x half> undef)
ret <8 x half> %2 ret <8 x half> %2
} }
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) declare <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #1
declare <8 x half> @llvm.arm.mve.abd.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>)

llvm/test/CodeGen/Thumb2/mve-intrinsics/vaddq.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
define arm_aapcs_vfpcc <4 x i32> @test_vaddq_u32(<4 x i32> %a, <4 x i32> %b) { define arm_aapcs_vfpcc <4 x i32> @test_vaddq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vaddq_u32: ; CHECK-LABEL: test_vaddq_u32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.i32 q0, q1, q0 ; CHECK-NEXT: vadd.i32 q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = add <4 x i32> %b, %a %0 = add <4 x i32> %b, %a
ret <4 x i32> %0 ret <4 x i32> %0
} }
define arm_aapcs_vfpcc <4 x float> @test_vaddq_f32(<4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <8 x half> @test_vaddq_f16(<8 x half> %a, <8 x half> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vaddq_f32: ; CHECK-LABEL: test_vaddq_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vadd.f32 q0, q1, q0 ; CHECK-NEXT: vadd.f16 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = fadd <4 x float> %b, %a %0 = fadd <8 x half> %a, %b
ret <4 x float> %0
}
define arm_aapcs_vfpcc <8 x half> @test_vsubq_f16(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: test_vsubq_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vsub.f16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = fsub <8 x half> %a, %b
ret <8 x half> %0 ret <8 x half> %0
} }
define arm_aapcs_vfpcc <8 x i16> @test_vsubq_s16(<8 x i16> %a, <8 x i16> %b) { define arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vsubq_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vsub.i16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = sub <8 x i16> %a, %b
ret <8 x i16> %0
}
define arm_aapcs_vfpcc <16 x i8> @test_vaddq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) {
; CHECK-LABEL: test_vaddq_m_s8: ; CHECK-LABEL: test_vaddq_m_s8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vaddt.i8 q0, q1, q2 ; CHECK-NEXT: vaddt.i8 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive) %2 = tail call <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive)
ret <16 x i8> %2 ret <16 x i8> %2
} }
declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
declare <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) declare <16 x i8> @llvm.arm.mve.add.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #2
define arm_aapcs_vfpcc <8 x half> @test_vaddq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x float> @test_vaddq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vaddq_m_f16: ; CHECK-LABEL: test_vaddq_m_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vaddt.f16 q0, q1, q2 ; CHECK-NEXT: vaddt.f32 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1, <8 x half> %inactive) %2 = tail call <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, <4 x i1> %1, <4 x float> %inactive)
ret <8 x half> %2 ret <4 x float> %2
} }
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) declare <4 x float> @llvm.arm.mve.add.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #2
define arm_aapcs_vfpcc <4 x float> @test_vsubq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x i16> @test_vaddq_x_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vsubq_m_f32: ; CHECK-LABEL: test_vaddq_x_u16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vsubt.f32 q0, q1, q2 ; CHECK-NEXT: vaddt.i16 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, <4 x i1> %1, <4 x float> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)
ret <4 x float> %2 ret <8 x i16> %2
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) declare <8 x i16> @llvm.arm.mve.add.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2
define arm_aapcs_vfpcc <4 x i32> @test_vsubq_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) { define arm_aapcs_vfpcc <8 x half> @test_vaddq_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vsubq_m_u32: ; CHECK-LABEL: test_vaddq_x_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vsubt.i32 q0, q1, q2 ; CHECK-NEXT: vaddt.f16 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.sub.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive) %2 = tail call <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1, <8 x half> undef)
ret <4 x i32> %2 ret <8 x half> %2
} }
declare <4 x i32> @llvm.arm.mve.sub.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) declare <8 x half> @llvm.arm.mve.add.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #2

llvm/test/CodeGen/Thumb2/mve-intrinsics/vandq.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
define arm_aapcs_vfpcc <16 x i8> @test_vandq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <16 x i8> @test_vandq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vandq_u8: ; CHECK-LABEL: test_vandq_u8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vand q0, q1, q0 ; CHECK-NEXT: vand q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = and <16 x i8> %b, %a %0 = and <16 x i8> %b, %a
ret <16 x i8> %0 ret <16 x i8> %0
} }
define arm_aapcs_vfpcc <4 x i32> @test_vandq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x i16> @test_vandq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vandq_u32: ; CHECK-LABEL: test_vandq_s16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vand q0, q1, q0 ; CHECK-NEXT: vand q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = and <4 x i32> %b, %a %0 = and <8 x i16> %b, %a
ret <4 x i32> %0 ret <8 x i16> %0
} }
define arm_aapcs_vfpcc <8 x i16> @test_vandq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x i32> @test_vandq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vandq_s16: ; CHECK-LABEL: test_vandq_u32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vand q0, q1, q0 ; CHECK-NEXT: vand q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = and <8 x i16> %b, %a %0 = and <4 x i32> %b, %a
ret <8 x i16> %0 ret <4 x i32> %0
} }
define arm_aapcs_vfpcc <4 x float> @test_vandq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x float> @test_vandq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vandq_f32: ; CHECK-LABEL: test_vandq_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vand q0, q1, q0 ; CHECK-NEXT: vand q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
Show All 35 Linesentry:
%2 = tail call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
declare <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2 declare <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2
; Function Attrs: nounwind readnone define arm_aapcs_vfpcc <4 x i32> @test_vandq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
define arm_aapcs_vfpcc <8 x half> @test_vandq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 { ; CHECK-LABEL: test_vandq_m_s32:
; CHECK-LABEL: test_vandq_m_f32: ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q0, q1, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2
}
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2
define arm_aapcs_vfpcc <8 x half> @test_vandq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vandq_m_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q0, q1, q2 ; CHECK-NEXT: vandt q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast <8 x half> %a to <8 x i16>
%1 = bitcast <8 x half> %b to <8 x i16>
%2 = zext i16 %p to i32
%3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
%4 = bitcast <8 x half> %inactive to <8 x i16>
%5 = tail call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %3, <8 x i16> %4)
%6 = bitcast <8 x i16> %5 to <8 x half>
ret <8 x half> %6
}
define arm_aapcs_vfpcc <16 x i8> @test_vandq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vandq_x_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.and.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vandq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vandq_x_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.and.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vandq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vandq_x_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vandq_m_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vandq_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vandt q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = bitcast <4 x float> %a to <4 x i32> %0 = bitcast <4 x float> %a to <4 x i32>
%1 = bitcast <4 x float> %b to <4 x i32> %1 = bitcast <4 x float> %b to <4 x i32>
%2 = zext i16 %p to i32 %2 = zext i16 %p to i32
%3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) %3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
%4 = bitcast <4 x float> %inactive to <4 x i32> %4 = tail call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %3, <4 x i32> undef)
%5 = tail call <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %3, <4 x i32> %4) %5 = bitcast <4 x i32> %4 to <4 x float>
%6 = bitcast <4 x i32> %5 to <8 x half> ret <4 x float> %5
ret <8 x half> %6
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <4 x i32> @llvm.arm.mve.and.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2

llvm/test/CodeGen/Thumb2/mve-intrinsics/vbicq.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
define arm_aapcs_vfpcc <16 x i8> @test_vbicq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <16 x i8> @test_vbicq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vbicq_u8: ; CHECK-LABEL: test_vbicq_u8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vbic q0, q0, q1 ; CHECK-NEXT: vbic q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> %0 = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%1 = and <16 x i8> %0, %a %1 = and <16 x i8> %0, %a
ret <16 x i8> %1 ret <16 x i8> %1
} }
define arm_aapcs_vfpcc <4 x i32> @test_vbicq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x i16> @test_vbicq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vbicq_u32: ; CHECK-LABEL: test_vbicq_s16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vbic q0, q0, q1 ; CHECK-NEXT: vbic q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1> %0 = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
%1 = and <4 x i32> %0, %a %1 = and <8 x i16> %0, %a
ret <4 x i32> %1 ret <8 x i16> %1
} }
define arm_aapcs_vfpcc <8 x i16> @test_vbicq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x i32> @test_vbicq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vbicq_s16: ; CHECK-LABEL: test_vbicq_u32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vbic q0, q0, q1 ; CHECK-NEXT: vbic q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> %0 = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
%1 = and <8 x i16> %0, %a %1 = and <4 x i32> %0, %a
ret <8 x i16> %1 ret <4 x i32> %1
} }
define arm_aapcs_vfpcc <4 x float> @test_vbicq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x float> @test_vbicq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vbicq_f32: ; CHECK-LABEL: test_vbicq_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vbic q0, q0, q1 ; CHECK-NEXT: vbic q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
Show All 36 Linesentry:
%2 = tail call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
declare <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2 declare <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2
; Function Attrs: nounwind readnone define arm_aapcs_vfpcc <4 x i32> @test_vbicq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
define arm_aapcs_vfpcc <8 x half> @test_vbicq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 { ; CHECK-LABEL: test_vbicq_m_s32:
; CHECK-LABEL: test_vbicq_m_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vbict q0, q1, q2 ; CHECK-NEXT: vbict q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2
}
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2
define arm_aapcs_vfpcc <8 x half> @test_vbicq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vbicq_m_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vbict q0, q1, q2
; CHECK-NEXT: bx lr
entry:
%0 = bitcast <8 x half> %a to <8 x i16>
%1 = bitcast <8 x half> %b to <8 x i16>
%2 = zext i16 %p to i32
%3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
%4 = bitcast <8 x half> %inactive to <8 x i16>
%5 = tail call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %3, <8 x i16> %4)
%6 = bitcast <8 x i16> %5 to <8 x half>
ret <8 x half> %6
}
define arm_aapcs_vfpcc <16 x i8> @test_vbicq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vbicq_x_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vbict q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.bic.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vbicq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vbicq_x_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vbict q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.bic.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vbicq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vbicq_x_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vbict q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vbicq_m_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vbicq_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vbict q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = bitcast <4 x float> %a to <4 x i32> %0 = bitcast <4 x float> %a to <4 x i32>
%1 = bitcast <4 x float> %b to <4 x i32> %1 = bitcast <4 x float> %b to <4 x i32>
%2 = zext i16 %p to i32 %2 = zext i16 %p to i32
%3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) %3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
%4 = bitcast <4 x float> %inactive to <4 x i32> %4 = tail call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %3, <4 x i32> undef)
%5 = tail call <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %3, <4 x i32> %4) %5 = bitcast <4 x i32> %4 to <4 x float>
%6 = bitcast <4 x i32> %5 to <8 x half> ret <4 x float> %5
ret <8 x half> %6
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <4 x i32> @llvm.arm.mve.bic.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2

llvm/test/CodeGen/Thumb2/mve-intrinsics/veorq.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
define arm_aapcs_vfpcc <16 x i8> @test_veorq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <16 x i8> @test_veorq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_veorq_u8: ; CHECK-LABEL: test_veorq_u8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: veor q0, q1, q0 ; CHECK-NEXT: veor q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = xor <16 x i8> %b, %a %0 = xor <16 x i8> %b, %a
ret <16 x i8> %0 ret <16 x i8> %0
} }
define arm_aapcs_vfpcc <4 x i32> @test_veorq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x i16> @test_veorq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_veorq_u32: ; CHECK-LABEL: test_veorq_s16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: veor q0, q1, q0 ; CHECK-NEXT: veor q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = xor <4 x i32> %b, %a %0 = xor <8 x i16> %b, %a
ret <4 x i32> %0 ret <8 x i16> %0
} }
define arm_aapcs_vfpcc <8 x i16> @test_veorq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x i32> @test_veorq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_veorq_s16: ; CHECK-LABEL: test_veorq_u32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: veor q0, q1, q0 ; CHECK-NEXT: veor q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = xor <8 x i16> %b, %a %0 = xor <4 x i32> %b, %a
ret <8 x i16> %0 ret <4 x i32> %0
} }
define arm_aapcs_vfpcc <4 x float> @test_veorq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x float> @test_veorq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_veorq_f32: ; CHECK-LABEL: test_veorq_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: veor q0, q1, q0 ; CHECK-NEXT: veor q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
Show All 35 Linesentry:
%2 = tail call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
declare <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2 declare <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2
; Function Attrs: nounwind readnone define arm_aapcs_vfpcc <4 x i32> @test_veorq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
define arm_aapcs_vfpcc <8 x half> @test_veorq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 { ; CHECK-LABEL: test_veorq_m_s32:
; CHECK-LABEL: test_veorq_m_f32: ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: veort q0, q1, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2
}
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2
define arm_aapcs_vfpcc <8 x half> @test_veorq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_veorq_m_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: veort q0, q1, q2 ; CHECK-NEXT: veort q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast <8 x half> %a to <8 x i16>
%1 = bitcast <8 x half> %b to <8 x i16>
%2 = zext i16 %p to i32
%3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
%4 = bitcast <8 x half> %inactive to <8 x i16>
%5 = tail call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %3, <8 x i16> %4)
%6 = bitcast <8 x i16> %5 to <8 x half>
ret <8 x half> %6
}
define arm_aapcs_vfpcc <16 x i8> @test_veorq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_veorq_x_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: veort q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_veorq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_veorq_x_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: veort q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.eor.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_veorq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_veorq_x_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: veort q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <4 x float> @test_veorq_m_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_veorq_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: veort q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = bitcast <4 x float> %a to <4 x i32> %0 = bitcast <4 x float> %a to <4 x i32>
%1 = bitcast <4 x float> %b to <4 x i32> %1 = bitcast <4 x float> %b to <4 x i32>
%2 = zext i16 %p to i32 %2 = zext i16 %p to i32
%3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) %3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
%4 = bitcast <4 x float> %inactive to <4 x i32> %4 = tail call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %3, <4 x i32> undef)
%5 = tail call <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %3, <4 x i32> %4) %5 = bitcast <4 x i32> %4 to <4 x float>
%6 = bitcast <4 x i32> %5 to <8 x half> ret <4 x float> %5
ret <8 x half> %6
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <4 x i32> @llvm.arm.mve.eor.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2

llvm/test/CodeGen/Thumb2/mve-intrinsics/vhaddq.ll

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Linesentry:
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
declare <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 declare <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
define arm_aapcs_vfpcc <16 x i8> @test_vhaddq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vhaddq_x_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vhaddt.s8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vhaddq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vhaddq_x_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vhaddt.s16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.hadd.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vhaddq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vhaddq_x_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vhaddt.s32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.hadd.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2
}

llvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxnmq.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_f16(<8 x half> %a, <8 x half> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_f16(<8 x half> %a, <8 x half> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmaxnmq_f16: ; CHECK-LABEL: test_vmaxnmq_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmaxnm.f16 q0, q0, q1 ; CHECK-NEXT: vmaxnm.f16 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = tail call <8 x half> @llvm.maxnum.v8f16(<8 x half> %a, <8 x half> %b) %0 = tail call <8 x half> @llvm.maxnum.v8f16(<8 x half> %a, <8 x half> %b)
ret <8 x half> %0 ret <8 x half> %0
} }
declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1 declare <8 x half> @llvm.maxnum.v8f16(<8 x half>, <8 x half>) #1
define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmaxnmq_f32: ; CHECK-LABEL: test_vmaxnmq_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmaxnm.f32 q0, q0, q1 ; CHECK-NEXT: vmaxnm.f32 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = tail call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b) %0 = tail call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b)
ret <4 x float> %0 ret <4 x float> %0
} }
declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1 declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1
define dso_local arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmaxnmq_m_f16: ; CHECK-LABEL: test_vmaxnmq_m_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmaxnmt.f32 q0, q1, q2 ; CHECK-NEXT: vmaxnmt.f32 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1, <8 x half> %inactive) %2 = tail call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1, <8 x half> %inactive)
ret <8 x half> %2 ret <8 x half> %2
} }
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
declare <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #2 declare <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #2
define dso_local arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmaxnmq_m_f32: ; CHECK-LABEL: test_vmaxnmq_m_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmaxnmt.f32 q0, q1, q2 ; CHECK-NEXT: vmaxnmt.f32 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, <4 x i1> %1, <4 x float> %inactive) %2 = tail call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, <4 x i1> %1, <4 x float> %inactive)
ret <4 x float> %2 ret <4 x float> %2
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #2 declare <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #2
define arm_aapcs_vfpcc <8 x half> @test_vmaxnmq_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmaxnmq_x_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmaxnmt.f32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x half> @llvm.arm.mve.max.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1, <8 x half> undef)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vmaxnmq_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmaxnmq_x_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmaxnmt.f32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x float> @llvm.arm.mve.max.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, <4 x i1> %1, <4 x float> undef)
ret <4 x float> %2
}

llvm/test/CodeGen/Thumb2/mve-intrinsics/vmaxq.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <16 x i8> @test_vmaxq_s8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmaxq_u8: ; CHECK-LABEL: test_vmaxq_s8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmin.u8 q0, q0, q1 ; CHECK-NEXT: vmax.s8 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = icmp ugt <16 x i8> %a, %b %0 = icmp slt <16 x i8> %a, %b
%1 = select <16 x i1> %0, <16 x i8> %b, <16 x i8> %a %1 = select <16 x i1> %0, <16 x i8> %b, <16 x i8> %a
ret <16 x i8> %1 ret <16 x i8> %1
} }
define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x i16> @test_vmaxq_u16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmaxq_s16: ; CHECK-LABEL: test_vmaxq_u16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmin.s16 q0, q0, q1 ; CHECK-NEXT: vmax.u16 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = icmp sgt <8 x i16> %a, %b %0 = icmp ult <8 x i16> %a, %b
%1 = select <8 x i1> %0, <8 x i16> %b, <8 x i16> %a %1 = select <8 x i1> %0, <8 x i16> %b, <8 x i16> %a
ret <8 x i16> %1 ret <8 x i16> %1
} }
define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x i32> @test_vmaxq_s32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmaxq_u32: ; CHECK-LABEL: test_vmaxq_s32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmin.u32 q0, q0, q1 ; CHECK-NEXT: vmax.s32 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = icmp ugt <4 x i32> %a, %b %0 = icmp slt <4 x i32> %a, %b
%1 = select <4 x i1> %0, <4 x i32> %b, <4 x i32> %a %1 = select <4 x i1> %0, <4 x i32> %b, <4 x i32> %a
ret <4 x i32> %1 ret <4 x i32> %1
} }
define dso_local arm_aapcs_vfpcc <16 x i8> @test_vmaxq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 { define arm_aapcs_vfpcc <16 x i8> @test_vmaxq_m_u8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vmaxq_m_s8: ; CHECK-LABEL: test_vmaxq_m_u8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmint.s8 q0, q1, q2 ; CHECK-NEXT: vmaxt.s8 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive) %2 = tail call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive)
ret <16 x i8> %2 ret <16 x i8> %2
} }
declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
declare <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #2 declare <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #2
define dso_local arm_aapcs_vfpcc <8 x i16> @test_vmaxq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 { define arm_aapcs_vfpcc <8 x i16> @test_vmaxq_m_s16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vmaxq_m_u16: ; CHECK-LABEL: test_vmaxq_m_s16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmint.s16 q0, q1, q2 ; CHECK-NEXT: vmaxt.s16 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
declare <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2 declare <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2
define dso_local arm_aapcs_vfpcc <4 x i32> @test_vmaxq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 { define arm_aapcs_vfpcc <4 x i32> @test_vmaxq_m_u32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vmaxq_m_s32: ; CHECK-LABEL: test_vmaxq_m_u32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmint.s32 q0, q1, q2 ; CHECK-NEXT: vmaxt.s32 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2 declare <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2
define arm_aapcs_vfpcc <16 x i8> @test_vmaxq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vmaxq_x_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmaxt.s8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vmaxq_x_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vmaxq_x_u16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmaxt.s16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.max.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vmaxq_x_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vmaxq_x_s32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmaxt.s32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.max.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2
}

llvm/test/CodeGen/Thumb2/mve-intrinsics/vminnmq.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_f16(<8 x half> %a, <8 x half> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x half> @test_vminnmq_f16(<8 x half> %a, <8 x half> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vminnmq_f16: ; CHECK-LABEL: test_vminnmq_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vminnm.f16 q0, q0, q1 ; CHECK-NEXT: vminnm.f16 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = tail call <8 x half> @llvm.minnum.v8f16(<8 x half> %a, <8 x half> %b) %0 = tail call <8 x half> @llvm.minnum.v8f16(<8 x half> %a, <8 x half> %b)
ret <8 x half> %0 ret <8 x half> %0
} }
declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1 declare <8 x half> @llvm.minnum.v8f16(<8 x half>, <8 x half>) #1
define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x float> @test_vminnmq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vminnmq_f32: ; CHECK-LABEL: test_vminnmq_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vminnm.f32 q0, q0, q1 ; CHECK-NEXT: vminnm.f32 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = tail call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b) %0 = tail call <4 x float> @llvm.minnum.v4f32(<4 x float> %a, <4 x float> %b)
ret <4 x float> %0 ret <4 x float> %0
} }
declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1 declare <4 x float> @llvm.minnum.v4f32(<4 x float>, <4 x float>) #1
define dso_local arm_aapcs_vfpcc <8 x half> @test_vminnmq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x half> @test_vminnmq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vminnmq_m_f16: ; CHECK-LABEL: test_vminnmq_m_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vminnmt.f32 q0, q1, q2 ; CHECK-NEXT: vminnmt.f32 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1, <8 x half> %inactive) %2 = tail call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1, <8 x half> %inactive)
ret <8 x half> %2 ret <8 x half> %2
} }
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
declare <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #2 declare <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #2
define dso_local arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x float> @test_vminnmq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vminnmq_m_f32: ; CHECK-LABEL: test_vminnmq_m_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vminnmt.f32 q0, q1, q2 ; CHECK-NEXT: vminnmt.f32 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, <4 x i1> %1, <4 x float> %inactive) %2 = tail call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, <4 x i1> %1, <4 x float> %inactive)
ret <4 x float> %2 ret <4 x float> %2
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #2 declare <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #2
define arm_aapcs_vfpcc <8 x half> @test_vminnmq_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vminnmq_x_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vminnmt.f32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x half> @llvm.arm.mve.min.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1, <8 x half> undef)
ret <8 x half> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vminnmq_x_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vminnmq_x_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vminnmt.f32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x float> @llvm.arm.mve.min.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, <4 x i1> %1, <4 x float> undef)
ret <4 x float> %2
}

llvm/test/CodeGen/Thumb2/mve-intrinsics/vminq.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <16 x i8> @test_vminq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vminq_u8: ; CHECK-LABEL: test_vminq_u8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmin.u8 q0, q0, q1 ; CHECK-NEXT: vmin.u8 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = icmp ugt <16 x i8> %a, %b %0 = icmp ugt <16 x i8> %a, %b
%1 = select <16 x i1> %0, <16 x i8> %b, <16 x i8> %a %1 = select <16 x i1> %0, <16 x i8> %b, <16 x i8> %a
ret <16 x i8> %1 ret <16 x i8> %1
} }
define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x i16> @test_vminq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vminq_s16: ; CHECK-LABEL: test_vminq_s16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmin.s16 q0, q0, q1 ; CHECK-NEXT: vmin.s16 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = icmp sgt <8 x i16> %a, %b %0 = icmp sgt <8 x i16> %a, %b
%1 = select <8 x i1> %0, <8 x i16> %b, <8 x i16> %a %1 = select <8 x i1> %0, <8 x i16> %b, <8 x i16> %a
ret <8 x i16> %1 ret <8 x i16> %1
} }
define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x i32> @test_vminq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vminq_u32: ; CHECK-LABEL: test_vminq_u32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmin.u32 q0, q0, q1 ; CHECK-NEXT: vmin.u32 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = icmp ugt <4 x i32> %a, %b %0 = icmp ugt <4 x i32> %a, %b
%1 = select <4 x i1> %0, <4 x i32> %b, <4 x i32> %a %1 = select <4 x i1> %0, <4 x i32> %b, <4 x i32> %a
ret <4 x i32> %1 ret <4 x i32> %1
} }
define dso_local arm_aapcs_vfpcc <16 x i8> @test_vminq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 { define arm_aapcs_vfpcc <16 x i8> @test_vminq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vminq_m_s8: ; CHECK-LABEL: test_vminq_m_s8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmint.s8 q0, q1, q2 ; CHECK-NEXT: vmint.s8 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive) %2 = tail call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive)
ret <16 x i8> %2 ret <16 x i8> %2
} }
declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
declare <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #2 declare <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #2
define dso_local arm_aapcs_vfpcc <8 x i16> @test_vminq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 { define arm_aapcs_vfpcc <8 x i16> @test_vminq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vminq_m_u16: ; CHECK-LABEL: test_vminq_m_u16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmint.s16 q0, q1, q2 ; CHECK-NEXT: vmint.s16 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
declare <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2 declare <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2
define dso_local arm_aapcs_vfpcc <4 x i32> @test_vminq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 { define arm_aapcs_vfpcc <4 x i32> @test_vminq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vminq_m_s32: ; CHECK-LABEL: test_vminq_m_s32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmint.s32 q0, q1, q2 ; CHECK-NEXT: vmint.s32 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2 declare <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2
define arm_aapcs_vfpcc <16 x i8> @test_vminq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vminq_x_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmint.s8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vminq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vminq_x_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmint.s16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.min.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vminq_x_s32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vminq_x_s32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmint.s32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.min.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2
}

llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulhq.ll

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Linesentry:
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
declare <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 declare <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
define arm_aapcs_vfpcc <16 x i8> @test_vmulhq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulhq_x_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmulht.s8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vmulhq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulhq_x_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmulht.s16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mulh.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vmulhq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulhq_x_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmulht.s32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.mulh.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2
}

llvm/test/CodeGen/Thumb2/mve-intrinsics/vmullbq.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = tail call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0) %0 = tail call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 0)
ret <4 x i32> %0 ret <4 x i32> %0
} }
declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_m_s8(<8 x i16> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmullbq_int_m_s8: ; CHECK-LABEL: test_vmullbq_int_m_s8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmullbt.s8 q0, q1, q2 ; CHECK-NEXT: vmullbt.s8 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, <16 x i1> %1, <16 x i8> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, <16 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <8 x i16>) #1
define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_m_u16(<4 x i32> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmullbq_int_m_u16: ; CHECK-LABEL: test_vmullbq_int_m_u16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmullbt.s16 q0, q1, q2 ; CHECK-NEXT: vmullbt.s16 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, <8 x i1> %1, <8 x i16> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, <8 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <4 x i32>) #1
define arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_m_s32(<2 x i64> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmullbq_int_m_s32: ; CHECK-LABEL: test_vmullbq_int_m_s32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmullbt.s32 q0, q1, q2 ; CHECK-NEXT: vmullbt.s32 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, <4 x i1> %1, <4 x i32> %inactive) %2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, <4 x i1> %1, <2 x i64> %inactive)
ret <2 x i64> %2 ret <2 x i64> %2
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <2 x i64>) #1
define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_poly_m_p8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_poly_m_p8(<8 x i16> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmullbq_poly_m_p8: ; CHECK-LABEL: test_vmullbq_poly_m_p8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmullbt.p8 q0, q1, q2 ; CHECK-NEXT: vmullbt.p8 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, <16 x i1> %1, <16 x i8> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, <16 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <8 x i16>) #1
define arm_aapcs_vfpcc <8 x i16> @test_vmullbq_int_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmullbq_int_x_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmullbt.s8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 0, <16 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_int_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmullbq_int_x_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmullbt.s16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, <8 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <2 x i64> @test_vmullbq_int_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmullbq_int_x_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmullbt.s32 q2, q0, q1
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 0, <4 x i1> %1, <2 x i64> undef)
ret <2 x i64> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vmullbq_poly_x_p16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmullbq_poly_x_p16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmullbt.p16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.mull.poly.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 0, <8 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2
}
declare <4 x i32> @llvm.arm.mve.mull.poly.predicated.v4i32.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <4 x i32>) #1

llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulltq.ll

Show First 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = tail call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 1) %0 = tail call <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16> %a, <8 x i16> %b, i32 1)
ret <4 x i32> %0 ret <4 x i32> %0
} }
declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1 declare <4 x i32> @llvm.arm.mve.vmull.poly.v4i32.v8i16(<8 x i16>, <8 x i16>, i32) #1
define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_m_s8(<8 x i16> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulltq_int_m_s8: ; CHECK-LABEL: test_vmulltq_int_m_s8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmulltt.s8 q0, q1, q2 ; CHECK-NEXT: vmulltt.s8 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, <16 x i1> %1, <16 x i8> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, <16 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1 declare <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <8 x i16>) #1
define arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_m_u16(<4 x i32> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulltq_int_m_u16: ; CHECK-LABEL: test_vmulltq_int_m_u16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmulltt.s16 q0, q1, q2 ; CHECK-NEXT: vmulltt.s16 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, <8 x i1> %1, <8 x i16> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, <8 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #1
declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <8 x i16>) #1 declare <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16>, <8 x i16>, i32, <8 x i1>, <4 x i32>) #1
define arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_m_s32(<2 x i64> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulltq_int_m_s32: ; CHECK-LABEL: test_vmulltq_int_m_s32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmulltt.s32 q0, q1, q2 ; CHECK-NEXT: vmulltt.s32 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, <4 x i1> %1, <4 x i32> %inactive) %2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, <4 x i1> %1, <2 x i64> %inactive)
ret <2 x i64> %2 ret <2 x i64> %2
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <4 x i32>) #1 declare <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32>, <4 x i32>, i32, <4 x i1>, <2 x i64>) #1
define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_m_p8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_m_p8(<8 x i16> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulltq_poly_m_p8: ; CHECK-LABEL: test_vmulltq_poly_m_p8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmulltt.p8 q0, q1, q2 ; CHECK-NEXT: vmulltt.p8 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, <16 x i1> %1, <16 x i8> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, <16 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2
}
declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <8 x i16>) #1
define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_int_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulltq_int_x_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmulltt.s8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mull.int.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, <16 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vmulltq_int_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulltq_int_x_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmulltt.s16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.mull.int.predicated.v4i32.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, i32 1, <8 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <2 x i64> @test_vmulltq_int_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulltq_int_x_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmulltt.s32 q2, q0, q1
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <2 x i64> @llvm.arm.mve.mull.int.predicated.v2i64.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, i32 1, <4 x i1> %1, <2 x i64> undef)
ret <2 x i64> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vmulltq_poly_x_p8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulltq_poly_x_p8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmulltt.p8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 1, <16 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2 ret <8 x i16> %2
} }
declare <8 x i16> @llvm.arm.mve.mull.poly.predicated.v8i16.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <16 x i8>) #1

llvm/test/CodeGen/Thumb2/mve-intrinsics/vmulq.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
define arm_aapcs_vfpcc <4 x i32> @test_vmulq_u32(<4 x i32> %a, <4 x i32> %b) { define arm_aapcs_vfpcc <16 x i8> @test_vmulq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulq_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmul.i8 q0, q1, q0
; CHECK-NEXT: bx lr
entry:
%0 = mul <16 x i8> %b, %a
ret <16 x i8> %0
}
define arm_aapcs_vfpcc <8 x i16> @test_vmulq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulq_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmul.i16 q0, q1, q0
; CHECK-NEXT: bx lr
entry:
%0 = mul <8 x i16> %b, %a
ret <8 x i16> %0
}
define arm_aapcs_vfpcc <4 x i32> @test_vmulq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulq_u32: ; CHECK-LABEL: test_vmulq_u32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmul.i32 q0, q1, q0 ; CHECK-NEXT: vmul.i32 q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = mul <4 x i32> %b, %a %0 = mul <4 x i32> %b, %a
ret <4 x i32> %0 ret <4 x i32> %0
} }
define arm_aapcs_vfpcc <4 x float> @test_vmulq_f32(<4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @test_vmulq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vmulq_f32: ; CHECK-LABEL: test_vmulq_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmul.f32 q0, q1, q0 ; CHECK-NEXT: vmul.f32 q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = fmul <4 x float> %b, %a %0 = fmul <4 x float> %a, %b
ret <4 x float> %0 ret <4 x float> %0
} }
define arm_aapcs_vfpcc <16 x i8> @test_vmulq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) { define arm_aapcs_vfpcc <16 x i8> @test_vmulq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vmulq_m_s8: ; CHECK-LABEL: test_vmulq_m_s8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.i8 q0, q1, q2 ; CHECK-NEXT: vmult.i8 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0) %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive) %2 = tail call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive)
ret <16 x i8> %2 ret <16 x i8> %2
} }
declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
declare <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #2
define arm_aapcs_vfpcc <8 x i16> @test_vmulq_m_u16(<8 x i16> %inactive, <8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vmulq_m_u16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.i16 q0, q1, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2
}
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
declare <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) declare <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2
define arm_aapcs_vfpcc <8 x half> @test_vmulq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) { define arm_aapcs_vfpcc <4 x i32> @test_vmulq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vmulq_m_s32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.i32 q0, q1, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2
}
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2
define arm_aapcs_vfpcc <8 x half> @test_vmulq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vmulq_m_f16: ; CHECK-LABEL: test_vmulq_m_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.f16 q0, q1, q2 ; CHECK-NEXT: vmult.f16 q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32 %0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0) %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1, <8 x half> %inactive) %2 = tail call <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1, <8 x half> %inactive)
ret <8 x half> %2 ret <8 x half> %2
} }
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) declare <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #2
define arm_aapcs_vfpcc <16 x i8> @test_vmulq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vmulq_x_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.i8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.mul.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vmulq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vmulq_x_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.i16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.mul.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vmulq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vmulq_x_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.i32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.mul.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vmulq_m_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vmulq_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vmult.f32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, <4 x i1> %1, <4 x float> undef)
ret <4 x float> %2
}
declare <4 x float> @llvm.arm.mve.mul.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #2
declare <8 x half> @llvm.arm.mve.mul.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>)

llvm/test/CodeGen/Thumb2/mve-intrinsics/vornq.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
define arm_aapcs_vfpcc <16 x i8> @test_vornq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <16 x i8> @test_vornq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vornq_u8: ; CHECK-LABEL: test_vornq_u8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vorn q0, q0, q1 ; CHECK-NEXT: vorn q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1> %0 = xor <16 x i8> %b, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
%1 = or <16 x i8> %0, %a %1 = or <16 x i8> %0, %a
ret <16 x i8> %1 ret <16 x i8> %1
} }
define arm_aapcs_vfpcc <4 x i32> @test_vornq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x i16> @test_vornq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vornq_u32: ; CHECK-LABEL: test_vornq_s16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vorn q0, q0, q1 ; CHECK-NEXT: vorn q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1> %0 = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
%1 = or <4 x i32> %0, %a %1 = or <8 x i16> %0, %a
ret <4 x i32> %1 ret <8 x i16> %1
} }
define arm_aapcs_vfpcc <8 x i16> @test_vornq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x i32> @test_vornq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vornq_s16: ; CHECK-LABEL: test_vornq_u32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vorn q0, q0, q1 ; CHECK-NEXT: vorn q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = xor <8 x i16> %b, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1> %0 = xor <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1>
%1 = or <8 x i16> %0, %a %1 = or <4 x i32> %0, %a
ret <8 x i16> %1 ret <4 x i32> %1
} }
define arm_aapcs_vfpcc <4 x float> @test_vornq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x float> @test_vornq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vornq_f32: ; CHECK-LABEL: test_vornq_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vorn q0, q0, q1 ; CHECK-NEXT: vorn q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
Show All 36 Linesentry:
%2 = tail call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
declare <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2 declare <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2
; Function Attrs: nounwind readnone define arm_aapcs_vfpcc <4 x i32> @test_vornq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
define arm_aapcs_vfpcc <8 x half> @test_vornq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 { ; CHECK-LABEL: test_vornq_m_s32:
; CHECK-LABEL: test_vornq_m_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vornt q0, q1, q2 ; CHECK-NEXT: vornt q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2
}
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2
define arm_aapcs_vfpcc <8 x half> @test_vornq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vornq_m_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vornt q0, q1, q2
; CHECK-NEXT: bx lr
entry:
%0 = bitcast <8 x half> %a to <8 x i16>
%1 = bitcast <8 x half> %b to <8 x i16>
%2 = zext i16 %p to i32
%3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
%4 = bitcast <8 x half> %inactive to <8 x i16>
%5 = tail call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %3, <8 x i16> %4)
%6 = bitcast <8 x i16> %5 to <8 x half>
ret <8 x half> %6
}
define arm_aapcs_vfpcc <16 x i8> @test_vornq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vornq_x_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vornt q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.orn.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vornq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vornq_x_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vornt q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.orn.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vornq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vornq_x_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vornt q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vornq_m_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vornq_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vornt q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = bitcast <4 x float> %a to <4 x i32> %0 = bitcast <4 x float> %a to <4 x i32>
%1 = bitcast <4 x float> %b to <4 x i32> %1 = bitcast <4 x float> %b to <4 x i32>
%2 = zext i16 %p to i32 %2 = zext i16 %p to i32
%3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) %3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
%4 = bitcast <4 x float> %inactive to <4 x i32> %4 = tail call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %3, <4 x i32> undef)
%5 = tail call <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %3, <4 x i32> %4) %5 = bitcast <4 x i32> %4 to <4 x float>
%6 = bitcast <4 x i32> %5 to <8 x half> ret <4 x float> %5
ret <8 x half> %6
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <4 x i32> @llvm.arm.mve.orn.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2

llvm/test/CodeGen/Thumb2/mve-intrinsics/vorrq.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
define arm_aapcs_vfpcc <16 x i8> @test_vorrq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <16 x i8> @test_vorrq_u8(<16 x i8> %a, <16 x i8> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vorrq_u8: ; CHECK-LABEL: test_vorrq_u8:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = or <16 x i8> %b, %a %0 = or <16 x i8> %b, %a
ret <16 x i8> %0 ret <16 x i8> %0
} }
define arm_aapcs_vfpcc <4 x i32> @test_vorrq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <8 x i16> @test_vorrq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vorrq_u32: ; CHECK-LABEL: test_vorrq_s16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = or <4 x i32> %b, %a %0 = or <8 x i16> %b, %a
ret <4 x i32> %0 ret <8 x i16> %0
} }
define arm_aapcs_vfpcc <8 x i16> @test_vorrq_s16(<8 x i16> %a, <8 x i16> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x i32> @test_vorrq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vorrq_s16: ; CHECK-LABEL: test_vorrq_u32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = or <8 x i16> %b, %a %0 = or <4 x i32> %b, %a
ret <8 x i16> %0 ret <4 x i32> %0
} }
define arm_aapcs_vfpcc <4 x float> @test_vorrq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 { define arm_aapcs_vfpcc <4 x float> @test_vorrq_f32(<4 x float> %a, <4 x float> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vorrq_f32: ; CHECK-LABEL: test_vorrq_f32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
Show All 35 Linesentry:
%2 = tail call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive) %2 = tail call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> %inactive)
ret <8 x i16> %2 ret <8 x i16> %2
} }
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
declare <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2 declare <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2
; Function Attrs: nounwind readnone define arm_aapcs_vfpcc <4 x i32> @test_vorrq_m_s32(<4 x i32> %inactive, <4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
define arm_aapcs_vfpcc <8 x half> @test_vorrq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 { ; CHECK-LABEL: test_vorrq_m_s32:
; CHECK-LABEL: test_vorrq_m_f32: ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vorrt q0, q1, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2
}
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2
define arm_aapcs_vfpcc <8 x half> @test_vorrq_m_f16(<8 x half> %inactive, <8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vorrq_m_f16:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0 ; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst ; CHECK-NEXT: vpst
; CHECK-NEXT: vorrt q0, q1, q2 ; CHECK-NEXT: vorrt q0, q1, q2
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%0 = bitcast <8 x half> %a to <8 x i16>
%1 = bitcast <8 x half> %b to <8 x i16>
%2 = zext i16 %p to i32
%3 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %2)
%4 = bitcast <8 x half> %inactive to <8 x i16>
%5 = tail call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %0, <8 x i16> %1, <8 x i1> %3, <8 x i16> %4)
%6 = bitcast <8 x i16> %5 to <8 x half>
ret <8 x half> %6
}
define arm_aapcs_vfpcc <16 x i8> @test_vorrq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vorrq_x_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vorrt q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.orr.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vorrq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vorrq_x_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vorrt q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.orr.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vorrq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vorrq_x_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vorrt q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2
}
define arm_aapcs_vfpcc <4 x float> @test_vorrq_m_f32(<4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vorrq_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vorrt q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = bitcast <4 x float> %a to <4 x i32> %0 = bitcast <4 x float> %a to <4 x i32>
%1 = bitcast <4 x float> %b to <4 x i32> %1 = bitcast <4 x float> %b to <4 x i32>
%2 = zext i16 %p to i32 %2 = zext i16 %p to i32
%3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2) %3 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %2)
%4 = bitcast <4 x float> %inactive to <4 x i32> %4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %3, <4 x i32> undef)
%5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %0, <4 x i32> %1, <4 x i1> %3, <4 x i32> %4) %5 = bitcast <4 x i32> %4 to <4 x float>
%6 = bitcast <4 x i32> %5 to <8 x half> ret <4 x float> %5
ret <8 x half> %6
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #2

llvm/test/CodeGen/Thumb2/mve-intrinsics/vrhaddq.ll

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Linesentry:
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
declare <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 declare <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
define arm_aapcs_vfpcc <16 x i8> @test_vrhaddq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vrhaddq_x_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vrhaddt.s8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vrhaddq_x_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vrhaddq_x_u16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vrhaddt.s16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.rhadd.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vrhaddq_x_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vrhaddq_x_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vrhaddt.s32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.rhadd.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2
}

llvm/test/CodeGen/Thumb2/mve-intrinsics/vrmulhq.ll

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Linesentry:
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0) %1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive) %2 = tail call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> %inactive)
ret <4 x i32> %2 ret <4 x i32> %2
} }
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #1
declare <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1 declare <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>) #1
define arm_aapcs_vfpcc <16 x i8> @test_vrmulhq_x_u8(<16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vrmulhq_x_u8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vrmulht.s8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> undef)
ret <16 x i8> %2
}
define arm_aapcs_vfpcc <8 x i16> @test_vrmulhq_x_s16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vrmulhq_x_s16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vrmulht.s16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.rmulh.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2
}
define arm_aapcs_vfpcc <4 x i32> @test_vrmulhq_m_u32(<4 x i32> %a, <4 x i32> %b, i16 zeroext %p) local_unnamed_addr #0 {
; CHECK-LABEL: test_vrmulhq_m_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vrmulht.s32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x i32> @llvm.arm.mve.rmulh.predicated.v4i32.v4i1(<4 x i32> %a, <4 x i32> %b, <4 x i1> %1, <4 x i32> undef)
ret <4 x i32> %2
}

llvm/test/CodeGen/Thumb2/mve-intrinsics/vsubq.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
define arm_aapcs_vfpcc <4 x i32> @test_vsubq_u32(<4 x i32> %a, <4 x i32> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vsubq_u32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vsub.i32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = sub <4 x i32> %a, %b
ret <4 x i32> %0
}
define arm_aapcs_vfpcc <8 x half> @test_vsubq_f16(<8 x half> %a, <8 x half> %b) local_unnamed_addr #0 {
; CHECK-LABEL: test_vsubq_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vsub.f16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = fsub <8 x half> %a, %b
ret <8 x half> %0
}
define arm_aapcs_vfpcc <16 x i8> @test_vsubq_m_s8(<16 x i8> %inactive, <16 x i8> %a, <16 x i8> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vsubq_m_s8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vsubt.i8 q0, q1, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
%2 = tail call <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 x i1> %1, <16 x i8> %inactive)
ret <16 x i8> %2
}
declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
declare <16 x i8> @llvm.arm.mve.sub.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i8>) #2
define arm_aapcs_vfpcc <4 x float> @test_vsubq_m_f32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vsubq_m_f32:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vsubt.f32 q0, q1, q2
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %0)
%2 = tail call <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float> %a, <4 x float> %b, <4 x i1> %1, <4 x float> %inactive)
ret <4 x float> %2
}
declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32) #2
declare <4 x float> @llvm.arm.mve.sub.predicated.v4f32.v4i1(<4 x float>, <4 x float>, <4 x i1>, <4 x float>) #2
define arm_aapcs_vfpcc <8 x i16> @test_vsubq_x_u16(<8 x i16> %a, <8 x i16> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vsubq_x_u16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vsubt.i16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16> %a, <8 x i16> %b, <8 x i1> %1, <8 x i16> undef)
ret <8 x i16> %2
}
declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32) #2
declare <8 x i16> @llvm.arm.mve.sub.predicated.v8i16.v8i1(<8 x i16>, <8 x i16>, <8 x i1>, <8 x i16>) #2
define arm_aapcs_vfpcc <8 x half> @test_vsubq_x_f16(<8 x half> %a, <8 x half> %b, i16 zeroext %p) local_unnamed_addr #1 {
; CHECK-LABEL: test_vsubq_x_f16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpst
; CHECK-NEXT: vsubt.f16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = zext i16 %p to i32
%1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
%2 = tail call <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half> %a, <8 x half> %b, <8 x i1> %1, <8 x half> undef)
ret <8 x half> %2
}
declare <8 x half> @llvm.arm.mve.sub.predicated.v8f16.v8i1(<8 x half>, <8 x half>, <8 x i1>, <8 x half>) #2