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[AArch64][SVE] Add permutation and selection intrinsics
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Authored by c-rhodes on Dec 12 2019, 1:33 AM.

Details

Summary

Adds the following intrinsics:

  • @llvm.aarch64.sve.clasta
  • @llvm.aarch64.sve.clasta_n
  • @llvm.aarch64.sve.clastb
  • @llvm.aarch64.sve.clastb_n
  • @llvm.aarch64.sve.compact
  • @llvm.aarch64.sve.ext
  • @llvm.aarch64.sve.lasta
  • @llvm.aarch64.sve.lastb
  • @llvm.aarch64.sve.rev
  • @llvm.aarch64.sve.splice
  • @llvm.aarch64.sve.tbl
  • @llvm.aarch64.sve.trn1
  • @llvm.aarch64.sve.trn2
  • @llvm.aarch64.sve.uzp1
  • @llvm.aarch64.sve.uzp2
  • @llvm.aarch64.sve.zip1
  • @llvm.aarch64.sve.zip2

Diff Detail

Event Timeline

c-rhodes created this revision.Dec 12 2019, 1:33 AM
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efriedma added inline comments.Dec 12 2019, 9:51 AM
llvm/include/llvm/IR/IntrinsicsAArch64.td
796

I guess this is sort of orthogonal to your patch, but this is missing ImmArg marking

1284–1286

Any thoughts on naming tbl for one-register and two-register forms?

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
12787

Can you check here that the result type is i8 or i16?

llvm/lib/Target/AArch64/SVEInstrFormats.td
5200

This unconditionally maps the "splice" intrinsic to the destructive form? I guess that's fine.

c-rhodes added inline comments.Dec 13 2019, 5:26 AM
llvm/include/llvm/IR/IntrinsicsAArch64.td
796

Using ImmArg for this class opens up a can of worms, I know Kerry ran into similar issues in a separate patch. From what I understand it requires using TImmLeaf instead of ImmLeaf for the imm args in instruction definitions and some of those operands are used all over the AArch64 backend.

1284–1286

By two-register I assume you're referring to the SVE2 form which has two source registers? Downstream we name this int_aarch64_sve_tbl2 and it's implemented with the same class as TBX.

llvm/lib/Target/AArch64/SVEInstrFormats.td
5200

Correct, SVE only defines a destructive form for splice, SVE2 introduced a constructive form which is implemented with a separate class but the ACLE defines no intrinsic for it.

c-rhodes updated this revision to Diff 233787.Dec 13 2019, 5:27 AM

Add assert in custom lowering of INTRINSIC_WO_CHAIN for types that aren’t MVT::i8 or MVT::i16.

c-rhodes marked an inline comment as done.Dec 13 2019, 5:27 AM
sdesmalen added inline comments.
llvm/include/llvm/IR/IntrinsicsAArch64.td
796

@kmclaughlin is currently looking into a fix for the ImmArg issue for these intrinsics (introduced by D69707 and D70253).

efriedma accepted this revision.Dec 13 2019, 11:10 AM

LGTM

llvm/include/llvm/IR/IntrinsicsAArch64.td
1284–1286

I guess that's fine.

This revision is now accepted and ready to land.Dec 13 2019, 11:10 AM
sdesmalen accepted this revision.Dec 16 2019, 3:04 AM

LGTM!

llvm/lib/Target/AArch64/SVEInstrFormats.td
1032

nit: this could be a multiclass with pattern to follow the convention in the rest of the file.

This revision was automatically updated to reflect the committed changes.
c-rhodes marked an inline comment as done.Dec 19 2019, 5:20 AM