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Differential D71390

[PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0
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Authored by ZhangKang on Dec 11 2019, 9:55 PM.

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hfinkel
jsji
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rG6d88b7d6e712: [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0
Summary

If we didn't set the value for hasSideEffects bit in our td file, llvm-tblgen will set it as true for those instructions which has no match pattern.
The instructions MTLR and MFLR don't set the hasSideEffects flag and don't have match pattern, so their hasSideEffects flag will be set true by llvm-tblgen.
But in fact, we can use [LR] to model the two instructions, so they should not have SideEffects.

This patch is to modify the hasSideEffects of MTLR and MFLR from 1 to 0.

Diff Detail

Event Timeline

ZhangKang created this revision.Dec 11 2019, 9:55 PM
Herald added a project: Restricted Project. · View Herald TranscriptDec 11 2019, 9:55 PM
Herald added subscribers: llvm-commits, shchenz, jsji and 3 others. · View Herald Transcript
ZhangKang added reviewers: Restricted Project, hfinkel.Dec 11 2019, 9:57 PM
ZhangKang added subscribers: power-llvm-team, echristo.
Herald added a subscriber: • wuzish. · View Herald TranscriptDec 11 2019, 9:57 PM
ZhangKang edited the summary of this revision. (Show Details)Dec 11 2019, 10:18 PM
lkail added a subscriber: lkail.Dec 11 2019, 11:05 PM
This comment was removed by lkail.
jsji requested changes to this revision.Dec 12 2019, 10:20 AM
jsji added a subscriber: steven.zhang.

@steven.zhang can you work with @ZhangKang to see why, and whether we rely on hasSideEffects for a better schedule right now. Thanks.

llvm/test/CodeGen/PowerPC/CSR-fit.ll
32

I see this is actually causing degradation here. mtlr is 5 cycle instruction, moving them together is not a good idea.

This revision now requires changes to proceed.Dec 12 2019, 10:20 AM
steven.zhang added inline comments.Dec 13 2019, 12:16 AM
llvm/test/CodeGen/PowerPC/CSR-fit.ll
32

It is trying to move it away from the dependency of "ld r0, 16(r1)" which is 4 cycle. The critical path of the region is 9 cycles(4 cycles(ld) + 5 cycles(mtlr)), and the two loads here won't matter too much. So, the scheduling works fine from my view.

jsji added a comment.Dec 13 2019, 7:10 AM

@ZhangKang Can we get some performance data for this change. Thanks.

llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
1383

This is way to far from ld 0,16(1) now.

ZhangKang added a comment.Dec 14 2019, 12:31 AM
In D71390#1780987, @lkail wrote:

Seems currently we haven't modeled mtlr correctly. In PPCFrameLowering

if (MustSaveLR)
  BuildMI(MBB, StackUpdateLoc, dl, MTLRInst).addReg(ScratchReg);

We might lack a implicit-def of $lr here. As a result, we might get wrong code if set hasSideEffect = 0 for mtlr. What do you think?

I have do the test, if we use Uses = [LR8] like MFLR, we will get M$x0 = MFLR8 implicit $lr8. And if we use Defs = [LR8] like MTLR, we will get MTLR8 $x0, implicit-def $lr8. So the code you pointed out is right.
In fact, those instructions which use Uses=[ ] or Defs = [ ] in td files will be added implicit register automatically in MIR.

In D71390#1783562, @jsji wrote:

@ZhangKang Can we get some performance data for this change. Thanks.

@jsji , Ok, I will do it soon.

steven.zhang added inline comments.Dec 15 2019, 6:42 PM
llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll
1383

But those load in between didn't have any dependency. So, it is likely an heuristic between the resource and latency.

Jim added a subscriber: Jim.Dec 15 2019, 7:24 PM

If an instruction has side effects, it would be a scheduling barrier.
Not any instruction can be scheduled crossing it.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td
412

Blank line shouldn't deleted here.

ZhangKang updated this revision to Diff 233992.Dec 15 2019, 10:24 PM

Fix the empty line.

ZhangKang marked 2 inline comments as done.Dec 15 2019, 10:25 PM
ZhangKang added inline comments.
llvm/lib/Target/PowerPC/PPCInstr64Bit.td
412

Done.

nemanjai added a comment.Dec 17 2019, 10:35 AM

Something doesn't match up here. The description/title say that you are changing the flag for both MFLR/MTLR. But in the code I only see the change for MTLR. Why is that?
Also, the context is missing from this patch so it cannot be reviewed properly, please fix that.

ZhangKang updated this revision to Diff 234431.Dec 17 2019, 5:30 PM
ZhangKang marked an inline comment as done.

Add the context.

ZhangKang added a comment.Dec 17 2019, 5:31 PM
In D71390#1788249, @nemanjai wrote:

Something doesn't match up here. The description/title say that you are changing the flag for both MFLR/MTLR. But in the code I only see the change for MTLR. Why is that?
Also, the context is missing from this patch so it cannot be reviewed properly, please fix that.

Have updated the patch to add the context.

ZhangKang added a comment.Dec 23 2019, 7:29 PM

I have run the performance for this patch, there is no regression.

ZhangKang removed a reviewer: jsji.Dec 24 2019, 6:21 PM
ZhangKang removed a reviewer: Restricted Project.
ZhangKang added reviewers: Restricted Project, jsji.
jsji accepted this revision as: jsji.Dec 24 2019, 6:50 PM

LGTM.

This revision is now accepted and ready to land.Dec 24 2019, 6:50 PM
Closed by commit rG6d88b7d6e712: [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0 (authored by ZhangKang). · Explain WhyDec 25 2019, 6:14 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 234431

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

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// the POWER3. // the POWER3.
let Defs = [X1], Uses = [X1] in let Defs = [X1], Uses = [X1] in
def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", def DYNALLOC8 : PPCEmitTimePseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
[(set i64:$result, [(set i64:$result,
(PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8", def DYNAREAOFFSET8 : PPCEmitTimePseudo<(outs i64imm:$result), (ins memri:$fpsi), "#DYNAREAOFFSET8",
[(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>; [(set i64:$result, (PPCdynareaoffset iaddr:$fpsi))]>;
JimUnsubmitted
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Blank line shouldn't deleted here.

Jim: Blank line shouldn't deleted here.
ZhangKangAuthorUnsubmitted
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Done.

ZhangKang: Done.
let hasSideEffects = 0 in {
let Defs = [LR8] in { let Defs = [LR8] in {
def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
"mtlr $rS", IIC_SprMTSPR>, "mtlr $rS", IIC_SprMTSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
let Uses = [LR8] in { let Uses = [LR8] in {
def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
"mflr $rT", IIC_SprMFSPR>, "mflr $rT", IIC_SprMFSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
} // Interpretation64Bit } // Interpretation64Bit
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Fixed point instructions. // Fixed point instructions.
// //
let PPC970_Unit = 1 in { // FXU Operations. let PPC970_Unit = 1 in { // FXU Operations.
let Interpretation64Bit = 1 in { let Interpretation64Bit = 1 in {
let hasSideEffects = 0 in { let hasSideEffects = 0 in {
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llvm/lib/Target/PowerPC/PPCInstrInfo.td

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} }
let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in { let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR] in {
let Pattern = [(int_set_loop_iterations i32:$rS)] in let Pattern = [(int_set_loop_iterations i32:$rS)] in
def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS), def MTCTRloop : XFXForm_7_ext<31, 467, 9, (outs), (ins gprc:$rS),
"mtctr $rS", IIC_SprMTSPR>, "mtctr $rS", IIC_SprMTSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
let hasSideEffects = 0 in {
let Defs = [LR] in { let Defs = [LR] in {
def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS), def MTLR : XFXForm_7_ext<31, 467, 8, (outs), (ins gprc:$rS),
"mtlr $rS", IIC_SprMTSPR>, "mtlr $rS", IIC_SprMTSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
let Uses = [LR] in { let Uses = [LR] in {
def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins), def MFLR : XFXForm_1_ext<31, 339, 8, (outs gprc:$rT), (ins),
"mflr $rT", IIC_SprMFSPR>, "mflr $rT", IIC_SprMFSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
}
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
// Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed // Move to/from VRSAVE: despite being a SPR, the VRSAVE register is renamed
// like a GPR on the PPC970. As such, copies in and out have the same // like a GPR on the PPC970. As such, copies in and out have the same
// performance characteristics as an OR instruction. // performance characteristics as an OR instruction.
def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS), def MTVRSAVE : XFXForm_7_ext<31, 467, 256, (outs), (ins gprc:$rS),
"mtspr 256, $rS", IIC_IntGeneral>, "mtspr 256, $rS", IIC_IntGeneral>,
PPC970_DGroup_Single, PPC970_Unit_FXU; PPC970_DGroup_Single, PPC970_Unit_FXU;
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llvm/test/CodeGen/PowerPC/CSR-fit.ll

Show All 21 Lines
; CHECK-PWR8-NEXT: #APP ; CHECK-PWR8-NEXT: #APP
; CHECK-PWR8-NEXT: add r3, r3, r4 ; CHECK-PWR8-NEXT: add r3, r3, r4
; CHECK-PWR8-NEXT: #NO_APP ; CHECK-PWR8-NEXT: #NO_APP
; CHECK-PWR8-NEXT: extsw r3, r3 ; CHECK-PWR8-NEXT: extsw r3, r3
; CHECK-PWR8-NEXT: bl callee ; CHECK-PWR8-NEXT: bl callee
; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: nop
; CHECK-PWR8-NEXT: addi r1, r1, 176 ; CHECK-PWR8-NEXT: addi r1, r1, 176
; CHECK-PWR8-NEXT: ld r0, 16(r1) ; CHECK-PWR8-NEXT: ld r0, 16(r1)
; CHECK-PWR8-NEXT: mtlr r0
; CHECK-PWR8-NEXT: ld r15, -136(r1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: ld r15, -136(r1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: ld r14, -144(r1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: ld r14, -144(r1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: mtlr r0
jsjiUnsubmitted
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I see this is actually causing degradation here. mtlr is 5 cycle instruction, moving them together is not a good idea.

jsji: I see this is actually causing degradation here. `mtlr` is 5 cycle instruction, moving them…
steven.zhangUnsubmitted
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It is trying to move it away from the dependency of "ld r0, 16(r1)" which is 4 cycle. The critical path of the region is 9 cycles(4 cycles(ld) + 5 cycles(mtlr)), and the two loads here won't matter too much. So, the scheduling works fine from my view.

steven.zhang: It is trying to move it away from the dependency of "ld r0, 16(r1)" which is 4 cycle. The…
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
; ;
; CHECK-PWR9-LABEL: caller1: ; CHECK-PWR9-LABEL: caller1:
; CHECK-PWR9: # %bb.0: # %entry ; CHECK-PWR9: # %bb.0: # %entry
; CHECK-PWR9-NEXT: mflr r0 ; CHECK-PWR9-NEXT: mflr r0
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 176 ; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 176
; CHECK-PWR9-NEXT: .cfi_offset lr, 16 ; CHECK-PWR9-NEXT: .cfi_offset lr, 16
; CHECK-PWR9-NEXT: .cfi_offset r14, -144 ; CHECK-PWR9-NEXT: .cfi_offset r14, -144
; CHECK-PWR9-NEXT: .cfi_offset r15, -136 ; CHECK-PWR9-NEXT: .cfi_offset r15, -136
; CHECK-PWR9-NEXT: std r14, -144(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r14, -144(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r15, -136(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: std r15, -136(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r0, 16(r1) ; CHECK-PWR9-NEXT: std r0, 16(r1)
; CHECK-PWR9-NEXT: stdu r1, -176(r1) ; CHECK-PWR9-NEXT: stdu r1, -176(r1)
; CHECK-PWR9-NEXT: #APP ; CHECK-PWR9-NEXT: #APP
; CHECK-PWR9-NEXT: add r3, r3, r4 ; CHECK-PWR9-NEXT: add r3, r3, r4
; CHECK-PWR9-NEXT: #NO_APP ; CHECK-PWR9-NEXT: #NO_APP
; CHECK-PWR9-NEXT: extsw r3, r3 ; CHECK-PWR9-NEXT: extsw r3, r3
; CHECK-PWR9-NEXT: bl callee ; CHECK-PWR9-NEXT: bl callee
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: addi r1, r1, 176 ; CHECK-PWR9-NEXT: addi r1, r1, 176
; CHECK-PWR9-NEXT: ld r0, 16(r1) ; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: ld r15, -136(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r15, -136(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r14, -144(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r14, -144(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: blr ; CHECK-PWR9-NEXT: blr
entry: entry:
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15}"(i32 %a, i32 %b) %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{r14},~{r15}"(i32 %a, i32 %b)
%call = tail call signext i32 @callee(i32 signext %0) %call = tail call signext i32 @callee(i32 signext %0)
ret i32 %call ret i32 %call
} }
define dso_local signext i32 @caller2(i32 signext %a, i32 signext %b) local_unnamed_addr { define dso_local signext i32 @caller2(i32 signext %a, i32 signext %b) local_unnamed_addr {
Show All 11 Lines
; CHECK-PWR8-NEXT: #APP ; CHECK-PWR8-NEXT: #APP
; CHECK-PWR8-NEXT: add r3, r3, r4 ; CHECK-PWR8-NEXT: add r3, r3, r4
; CHECK-PWR8-NEXT: #NO_APP ; CHECK-PWR8-NEXT: #NO_APP
; CHECK-PWR8-NEXT: extsw r3, r3 ; CHECK-PWR8-NEXT: extsw r3, r3
; CHECK-PWR8-NEXT: bl callee ; CHECK-PWR8-NEXT: bl callee
; CHECK-PWR8-NEXT: nop ; CHECK-PWR8-NEXT: nop
; CHECK-PWR8-NEXT: addi r1, r1, 176 ; CHECK-PWR8-NEXT: addi r1, r1, 176
; CHECK-PWR8-NEXT: ld r0, 16(r1) ; CHECK-PWR8-NEXT: ld r0, 16(r1)
; CHECK-PWR8-NEXT: mtlr r0
; CHECK-PWR8-NEXT: lfd f15, -136(r1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: lfd f15, -136(r1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: lfd f14, -144(r1) # 8-byte Folded Reload ; CHECK-PWR8-NEXT: lfd f14, -144(r1) # 8-byte Folded Reload
; CHECK-PWR8-NEXT: mtlr r0
; CHECK-PWR8-NEXT: blr ; CHECK-PWR8-NEXT: blr
; ;
; CHECK-PWR9-LABEL: caller2: ; CHECK-PWR9-LABEL: caller2:
; CHECK-PWR9: # %bb.0: # %entry ; CHECK-PWR9: # %bb.0: # %entry
; CHECK-PWR9-NEXT: mflr r0 ; CHECK-PWR9-NEXT: mflr r0
; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 176 ; CHECK-PWR9-NEXT: .cfi_def_cfa_offset 176
; CHECK-PWR9-NEXT: .cfi_offset lr, 16 ; CHECK-PWR9-NEXT: .cfi_offset lr, 16
; CHECK-PWR9-NEXT: .cfi_offset f14, -144 ; CHECK-PWR9-NEXT: .cfi_offset f14, -144
; CHECK-PWR9-NEXT: .cfi_offset f15, -136 ; CHECK-PWR9-NEXT: .cfi_offset f15, -136
; CHECK-PWR9-NEXT: stfd f14, -144(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: stfd f14, -144(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: stfd f15, -136(r1) # 8-byte Folded Spill ; CHECK-PWR9-NEXT: stfd f15, -136(r1) # 8-byte Folded Spill
; CHECK-PWR9-NEXT: std r0, 16(r1) ; CHECK-PWR9-NEXT: std r0, 16(r1)
; CHECK-PWR9-NEXT: stdu r1, -176(r1) ; CHECK-PWR9-NEXT: stdu r1, -176(r1)
; CHECK-PWR9-NEXT: #APP ; CHECK-PWR9-NEXT: #APP
; CHECK-PWR9-NEXT: add r3, r3, r4 ; CHECK-PWR9-NEXT: add r3, r3, r4
; CHECK-PWR9-NEXT: #NO_APP ; CHECK-PWR9-NEXT: #NO_APP
; CHECK-PWR9-NEXT: extsw r3, r3 ; CHECK-PWR9-NEXT: extsw r3, r3
; CHECK-PWR9-NEXT: bl callee ; CHECK-PWR9-NEXT: bl callee
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: addi r1, r1, 176 ; CHECK-PWR9-NEXT: addi r1, r1, 176
; CHECK-PWR9-NEXT: ld r0, 16(r1) ; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: lfd f15, -136(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lfd f15, -136(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: lfd f14, -144(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: lfd f14, -144(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: blr ; CHECK-PWR9-NEXT: blr
entry: entry:
%0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{f14},~{f15}"(i32 %a, i32 %b) %0 = tail call i32 asm "add $0, $1, $2", "=r,r,r,~{f14},~{f15}"(i32 %a, i32 %b)
%call = tail call signext i32 @callee(i32 signext %0) %call = tail call signext i32 @callee(i32 signext %0)
ret i32 %call ret i32 %call
} }
define dso_local signext i32 @caller3(i32 signext %a, i32 signext %b) local_unnamed_addr { define dso_local signext i32 @caller3(i32 signext %a, i32 signext %b) local_unnamed_addr {
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llvm/test/CodeGen/PowerPC/MCSE-caller-preserved-reg.ll

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; CHECK-NEXT: addi 4, 3, 8 ; CHECK-NEXT: addi 4, 3, 8
; CHECK-NEXT: mr 3, 30 ; CHECK-NEXT: mr 3, 30
; CHECK-NEXT: bl _ZN2CC3barEPi ; CHECK-NEXT: bl _ZN2CC3barEPi
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: .LBB0_2: # %if.end ; CHECK-NEXT: .LBB0_2: # %if.end
; CHECK-NEXT: li 3, 0 ; CHECK-NEXT: li 3, 0
; CHECK-NEXT: addi 1, 1, 48 ; CHECK-NEXT: addi 1, 1, 48
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%foo = getelementptr inbounds %class.CC, %class.CC* %this, i64 0, i32 0, i32 0 %foo = getelementptr inbounds %class.CC, %class.CC* %this, i64 0, i32 0, i32 0
%0 = load void ()*, void ()** %foo, align 8 %0 = load void ()*, void ()** %foo, align 8
tail call void %0() tail call void %0()
%1 = load i64, i64* getelementptr inbounds (%"struct.CC::TT", %"struct.CC::TT"* @_ZN2CC2ccE, i64 0, i32 0) %1 = load i64, i64* getelementptr inbounds (%"struct.CC::TT", %"struct.CC::TT"* @_ZN2CC2ccE, i64 0, i32 0)
%tobool = icmp eq i64 %1, 0 %tobool = icmp eq i64 %1, 0
br i1 %tobool, label %if.end, label %if.then br i1 %tobool, label %if.end, label %if.then
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llvm/test/CodeGen/PowerPC/csr-split.ll

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; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: mr r3, r30 ; CHECK-PWR9-NEXT: mr r3, r30
; CHECK-PWR9-NEXT: bl callNonVoid ; CHECK-PWR9-NEXT: bl callNonVoid
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: .LBB0_2: # %if.end ; CHECK-PWR9-NEXT: .LBB0_2: # %if.end
; CHECK-PWR9-NEXT: extsw r3, r3 ; CHECK-PWR9-NEXT: extsw r3, r3
; CHECK-PWR9-NEXT: addi r1, r1, 48 ; CHECK-PWR9-NEXT: addi r1, r1, 48
; CHECK-PWR9-NEXT: ld r0, 16(r1) ; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: blr ; CHECK-PWR9-NEXT: blr
; ;
; CHECK-LABEL: test1: ; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1) ; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -128(r1) ; CHECK-NEXT: stdu r1, -128(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 128 ; CHECK-NEXT: .cfi_def_cfa_offset 128
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; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: mr r3, r30 ; CHECK-PWR9-NEXT: mr r3, r30
; CHECK-PWR9-NEXT: bl callNonVoid ; CHECK-PWR9-NEXT: bl callNonVoid
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: .LBB1_3: # %return ; CHECK-PWR9-NEXT: .LBB1_3: # %return
; CHECK-PWR9-NEXT: extsw r3, r3 ; CHECK-PWR9-NEXT: extsw r3, r3
; CHECK-PWR9-NEXT: addi r1, r1, 48 ; CHECK-PWR9-NEXT: addi r1, r1, 48
; CHECK-PWR9-NEXT: ld r0, 16(r1) ; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: blr ; CHECK-PWR9-NEXT: blr
; ;
; CHECK-LABEL: test2: ; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1) ; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -128(r1) ; CHECK-NEXT: stdu r1, -128(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 128 ; CHECK-NEXT: .cfi_def_cfa_offset 128
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; CHECK-PWR9-NEXT: mr r3, r30 ; CHECK-PWR9-NEXT: mr r3, r30
; CHECK-PWR9-NEXT: bl bar ; CHECK-PWR9-NEXT: bl bar
; CHECK-PWR9-NEXT: nop ; CHECK-PWR9-NEXT: nop
; CHECK-PWR9-NEXT: std r3, 0(r29) ; CHECK-PWR9-NEXT: std r3, 0(r29)
; CHECK-PWR9-NEXT: .LBB2_2: # %land.end ; CHECK-PWR9-NEXT: .LBB2_2: # %land.end
; CHECK-PWR9-NEXT: mr r3, r30 ; CHECK-PWR9-NEXT: mr r3, r30
; CHECK-PWR9-NEXT: addi r1, r1, 64 ; CHECK-PWR9-NEXT: addi r1, r1, 64
; CHECK-PWR9-NEXT: ld r0, 16(r1) ; CHECK-PWR9-NEXT: ld r0, 16(r1)
; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-PWR9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-PWR9-NEXT: mtlr r0
; CHECK-PWR9-NEXT: blr ; CHECK-PWR9-NEXT: blr
; ;
; CHECK-LABEL: test3: ; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0 ; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1) ; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -144(r1) ; CHECK-NEXT: stdu r1, -144(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 144 ; CHECK-NEXT: .cfi_def_cfa_offset 144
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llvm/test/CodeGen/PowerPC/machine-pre.ll

Show First 20 Lines • Show All 128 Lines • ▼ Show 20 Lines
; CHECK-P9-NEXT: rldicl r4, r4, 1, 63 ; CHECK-P9-NEXT: rldicl r4, r4, 1, 63
; CHECK-P9-NEXT: or r3, r3, r4 ; CHECK-P9-NEXT: or r3, r3, r4
; CHECK-P9-NEXT: b .LBB1_10 ; CHECK-P9-NEXT: b .LBB1_10
; CHECK-P9-NEXT: .LBB1_9: # %cleanup20 ; CHECK-P9-NEXT: .LBB1_9: # %cleanup20
; CHECK-P9-NEXT: li r3, 0 ; CHECK-P9-NEXT: li r3, 0
; CHECK-P9-NEXT: .LBB1_10: # %cleanup20 ; CHECK-P9-NEXT: .LBB1_10: # %cleanup20
; CHECK-P9-NEXT: addi r1, r1, 80 ; CHECK-P9-NEXT: addi r1, r1, 80
; CHECK-P9-NEXT: ld r0, 16(r1) ; CHECK-P9-NEXT: ld r0, 16(r1)
; CHECK-P9-NEXT: mtlr r0
; CHECK-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: mtlr r0
; CHECK-P9-NEXT: ld r27, -40(r1) # 8-byte Folded Reload ; CHECK-P9-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-P9-NEXT: blr ; CHECK-P9-NEXT: blr
entry: entry:
%add = add nsw i32 %y, %x %add = add nsw i32 %y, %x
br label %while.cond br label %while.cond
while.cond: ; preds = %sw.epilog, %entry while.cond: ; preds = %sw.epilog, %entry
%sum.0 = phi i32 [ %add, %entry ], [ %sum.1, %sw.epilog ] %sum.0 = phi i32 [ %add, %entry ], [ %sum.1, %sw.epilog ]
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llvm/test/CodeGen/PowerPC/not-fixed-frame-object.ll

Show First 20 Lines • Show All 55 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ld r4, 40(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r4, 40(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r6, 32(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r6, 32(r1) # 8-byte Folded Reload
; CHECK-NEXT: extsw r3, r3 ; CHECK-NEXT: extsw r3, r3
; CHECK-NEXT: mr r5, r0 ; CHECK-NEXT: mr r5, r0
; CHECK-NEXT: bl callee ; CHECK-NEXT: bl callee
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 192 ; CHECK-NEXT: addi r1, r1, 192
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: ld r31, -8(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r31, -8(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r27, -40(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r27, -40(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r26, -48(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r26, -48(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r25, -56(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r25, -56(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r24, -64(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r24, -64(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r23, -72(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r23, -72(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r22, -80(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r22, -80(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r21, -88(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r21, -88(r1) # 8-byte Folded Reload
Show All 16 Lines

llvm/test/CodeGen/PowerPC/ppcf128-constrained-fp-intrinsics.ll

Show First 20 Lines • Show All 1,369 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: bl __powitf2 ; PC64LE-NEXT: bl __powitf2
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: frsp 0, 1 ; PC64LE-NEXT: frsp 0, 1
; PC64LE-NEXT: stfsx 0, 0, 29 ; PC64LE-NEXT: stfsx 0, 0, 29
; PC64LE-NEXT: stfd 2, -8(30) ; PC64LE-NEXT: stfd 2, -8(30)
; PC64LE-NEXT: stfd 1, -16(30) ; PC64LE-NEXT: stfd 1, -16(30)
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: ld 30, -40(1) # 8-byte Folded Reload ; PC64LE-NEXT: ld 30, -40(1) # 8-byte Folded Reload
; PC64LE-NEXT: ld 29, -48(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload
; PC64LE-NEXT: ld 29, -48(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
jsjiUnsubmitted
Not Done
ReplyInline Actions

This is way to far from ld 0,16(1) now.

jsji: This is way to far from `ld 0,16(1)` now.
steven.zhangUnsubmitted
Not Done
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But those load in between didn't have any dependency. So, it is likely an heuristic between the resource and latency.

steven.zhang: But those load in between didn't have any dependency. So, it is likely an heuristic between the…
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: test_constrained_libcall_multichain: ; PC64LE9-LABEL: test_constrained_libcall_multichain:
; PC64LE9: # %bb.0: ; PC64LE9: # %bb.0:
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: std 29, -48(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 29, -48(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 30, -40(1) # 8-byte Folded Spill ; PC64LE9-NEXT: std 30, -40(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 29, -24(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 29, -24(1) # 8-byte Folded Spill
Show All 29 Lines
; PC64LE9-NEXT: bl __powitf2 ; PC64LE9-NEXT: bl __powitf2
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: frsp 0, 1 ; PC64LE9-NEXT: frsp 0, 1
; PC64LE9-NEXT: stfs 0, 0(29) ; PC64LE9-NEXT: stfs 0, 0(29)
; PC64LE9-NEXT: stfd 2, -8(30) ; PC64LE9-NEXT: stfd 2, -8(30)
; PC64LE9-NEXT: stfd 1, -16(30) ; PC64LE9-NEXT: stfd 1, -16(30)
; PC64LE9-NEXT: addi 1, 1, 80 ; PC64LE9-NEXT: addi 1, 1, 80
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload
; PC64LE9-NEXT: ld 30, -40(1) # 8-byte Folded Reload ; PC64LE9-NEXT: ld 30, -40(1) # 8-byte Folded Reload
; PC64LE9-NEXT: ld 29, -48(1) # 8-byte Folded Reload ; PC64LE9-NEXT: ld 29, -48(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
; ;
; PC64-LABEL: test_constrained_libcall_multichain: ; PC64-LABEL: test_constrained_libcall_multichain:
; PC64: # %bb.0: ; PC64: # %bb.0:
; PC64-NEXT: mflr 0 ; PC64-NEXT: mflr 0
; PC64-NEXT: std 0, 16(1) ; PC64-NEXT: std 0, 16(1)
; PC64-NEXT: stdu 1, -176(1) ; PC64-NEXT: stdu 1, -176(1)
; PC64-NEXT: std 29, 120(1) # 8-byte Folded Spill ; PC64-NEXT: std 29, 120(1) # 8-byte Folded Spill
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llvm/test/CodeGen/PowerPC/pr43527.ll

Show All 28 Lines
; CHECK-NEXT: addi r30, r30, -1 ; CHECK-NEXT: addi r30, r30, -1
; CHECK-NEXT: addi r29, r29, 4 ; CHECK-NEXT: addi r29, r29, 4
; CHECK-NEXT: cmpldi r30, 0 ; CHECK-NEXT: cmpldi r30, 0
; CHECK-NEXT: bne cr0, .LBB0_3 ; CHECK-NEXT: bne cr0, .LBB0_3
; CHECK-NEXT: # %bb.4: # %bb15 ; CHECK-NEXT: # %bb.4: # %bb15
; CHECK-NEXT: stb r3, 0(r3) ; CHECK-NEXT: stb r3, 0(r3)
; CHECK-NEXT: addi r1, r1, 64 ; CHECK-NEXT: addi r1, r1, 64
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
; CHECK-NEXT: .LBB0_5: # %bb2 ; CHECK-NEXT: .LBB0_5: # %bb2
; CHECK-NEXT: .LBB0_6: # %bb14 ; CHECK-NEXT: .LBB0_6: # %bb14
bb: bb:
br i1 undef, label %bb3, label %bb2 br i1 undef, label %bb3, label %bb2
bb2: ; preds = %bb bb2: ; preds = %bb
unreachable unreachable
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llvm/test/CodeGen/PowerPC/pr44183.ll

Show All 25 Lines
; CHECK-NEXT: sldi r3, r3, 60 ; CHECK-NEXT: sldi r3, r3, 60
; CHECK-NEXT: or r3, r4, r3 ; CHECK-NEXT: or r3, r4, r3
; CHECK-NEXT: sldi r3, r3, 31 ; CHECK-NEXT: sldi r3, r3, 31
; CHECK-NEXT: clrldi r4, r3, 32 ; CHECK-NEXT: clrldi r4, r3, 32
; CHECK-NEXT: bl _ZN1llsE1d ; CHECK-NEXT: bl _ZN1llsE1d
; CHECK-NEXT: nop ; CHECK-NEXT: nop
; CHECK-NEXT: addi r1, r1, 48 ; CHECK-NEXT: addi r1, r1, 48
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%bc = getelementptr inbounds %struct.m.2.5.8.11, %struct.m.2.5.8.11* %this, i64 0, i32 2 %bc = getelementptr inbounds %struct.m.2.5.8.11, %struct.m.2.5.8.11* %this, i64 0, i32 2
%0 = bitcast %struct.a.1.4.7.10* %bc to i216* %0 = bitcast %struct.a.1.4.7.10* %bc to i216*
%bf.load = load i216, i216* %0, align 8 %bf.load = load i216, i216* %0, align 8
%bf.lshr = lshr i216 %bf.load, 4 %bf.lshr = lshr i216 %bf.load, 4
%shl.i23 = shl i216 %bf.lshr, 31 %shl.i23 = shl i216 %bf.lshr, 31
%shl.i = trunc i216 %shl.i23 to i32 %shl.i = trunc i216 %shl.i23 to i32
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llvm/test/CodeGen/PowerPC/sjlj.ll

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Lines
; CHECK-DAG: std 1, 16([[REGA]]) ; CHECK-DAG: std 1, 16([[REGA]])
; CHECK-DAG: std 2, 24([[REGA]]) ; CHECK-DAG: std 2, 24([[REGA]])
; CHECK: bcl 20, 31, .LBB1_3 ; CHECK: bcl 20, 31, .LBB1_3
; CHECK: li 3, 1 ; CHECK: li 3, 1
; CHECK: #EH_SjLj_Setup .LBB1_3 ; CHECK: #EH_SjLj_Setup .LBB1_3
; CHECK: # %bb.1: ; CHECK: # %bb.1:
; CHECK: .LBB1_3: ; CHECK: .LBB1_3:
; CHECK: mflr [[REGL:[0-9]+]]
; CHECK: ld [[REG2:[0-9]+]], [[OFF]](31) # 8-byte Folded Reload ; CHECK: ld [[REG2:[0-9]+]], [[OFF]](31) # 8-byte Folded Reload
; CHECK: mflr [[REGL:[0-9]+]]
; CHECK: std [[REGL]], 8([[REG2]]) ; CHECK: std [[REGL]], 8([[REG2]])
; CHECK: li 3, 0 ; CHECK: li 3, 0
; CHECK: .LBB1_5: ; CHECK: .LBB1_5:
; CHECK-DAG: lfd ; CHECK-DAG: lfd
; CHECK-DAG: lxvd2x ; CHECK-DAG: lxvd2x
; CHECK: ld ; CHECK: ld
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llvm/test/CodeGen/PowerPC/sms-phi-1.ll

Show All 30 Lines
; CHECK-NEXT: stwu 4, 4(3) ; CHECK-NEXT: stwu 4, 4(3)
; CHECK-NEXT: mullw 4, 5, 5 ; CHECK-NEXT: mullw 4, 5, 5
; CHECK-NEXT: addi 5, 5, 1 ; CHECK-NEXT: addi 5, 5, 1
; CHECK-NEXT: bdnz .LBB0_2 ; CHECK-NEXT: bdnz .LBB0_2
; CHECK-NEXT: .LBB0_3: ; CHECK-NEXT: .LBB0_3:
; CHECK-NEXT: stwu 4, 4(3) ; CHECK-NEXT: stwu 4, 4(3)
; CHECK-NEXT: addi 1, 1, 48 ; CHECK-NEXT: addi 1, 1, 48
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%1 = tail call i64 @strtol() %1 = tail call i64 @strtol()
%2 = trunc i64 %1 to i32 %2 = trunc i64 %1 to i32
%3 = tail call noalias i8* @calloc() %3 = tail call noalias i8* @calloc()
%4 = bitcast i8* %3 to i32* %4 = bitcast i8* %3 to i32*
%5 = zext i32 %2 to i64 %5 = zext i32 %2 to i64
br label %6 br label %6
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llvm/test/CodeGen/PowerPC/sms-phi-3.ll

Show First 20 Lines • Show All 48 Lines • ▼ Show 20 Lines
; CHECK-NEXT: add 6, 3, 6 ; CHECK-NEXT: add 6, 3, 6
; CHECK-NEXT: stdu 6, 8(4) ; CHECK-NEXT: stdu 6, 8(4)
; CHECK-NEXT: .LBB0_5: ; CHECK-NEXT: .LBB0_5:
; CHECK-NEXT: extswsli 5, 5, 5 ; CHECK-NEXT: extswsli 5, 5, 5
; CHECK-NEXT: add 3, 3, 5 ; CHECK-NEXT: add 3, 3, 5
; CHECK-NEXT: stdu 3, 8(4) ; CHECK-NEXT: stdu 3, 8(4)
; CHECK-NEXT: addi 1, 1, 64 ; CHECK-NEXT: addi 1, 1, 64
; CHECK-NEXT: ld 0, 16(1) ; CHECK-NEXT: ld 0, 16(1)
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 30, -16(1) # 8-byte Folded Reload
; CHECK-NEXT: ld 29, -24(1) # 8-byte Folded Reload ; CHECK-NEXT: ld 29, -24(1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
%2 = tail call noalias i8* @malloc() %2 = tail call noalias i8* @malloc()
%3 = bitcast i8* %2 to %0** %3 = bitcast i8* %2 to %0**
%4 = tail call noalias i8* @malloc() %4 = tail call noalias i8* @malloc()
%5 = bitcast i8* %4 to %0* %5 = bitcast i8* %4 to %0*
br label %6 br label %6
6: ; preds = %6, %1 6: ; preds = %6, %1
Show All 18 Lines

llvm/test/CodeGen/PowerPC/tocSaveInPrologue.ll

Show All 37 Lines
; CHECK-NEXT: .LBB0_3: # %for.cond.cleanup ; CHECK-NEXT: .LBB0_3: # %for.cond.cleanup
; CHECK-NEXT: mtctr r30 ; CHECK-NEXT: mtctr r30
; CHECK-NEXT: mr r3, r28 ; CHECK-NEXT: mr r3, r28
; CHECK-NEXT: mr r12, r30 ; CHECK-NEXT: mr r12, r30
; CHECK-NEXT: bctrl ; CHECK-NEXT: bctrl
; CHECK-NEXT: ld 2, 24(r1) ; CHECK-NEXT: ld 2, 24(r1)
; CHECK-NEXT: addi r1, r1, 64 ; CHECK-NEXT: addi r1, r1, 64
; CHECK-NEXT: ld r0, 16(r1) ; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
; CHECK-NEXT: ld r28, -32(r1) # 8-byte Folded Reload ; CHECK-NEXT: ld r28, -32(r1) # 8-byte Folded Reload
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr ; CHECK-NEXT: blr
entry: entry:
%cmp7 = icmp sgt i32 %Len, 0 %cmp7 = icmp sgt i32 %Len, 0
%cmp1 = icmp sgt i32 %Arg, 10 %cmp1 = icmp sgt i32 %Arg, 10
%or.cond = and i1 %cmp7, %cmp1 %or.cond = and i1 %cmp7, %cmp1
br i1 %or.cond, label %for.body.us, label %for.cond.cleanup br i1 %or.cond, label %for.body.us, label %for.cond.cleanup
for.body.us: ; preds = %entry, %for.body.us for.body.us: ; preds = %entry, %for.body.us
Show All 10 Lines

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 287 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: bl fmod ; PC64LE-NEXT: bl fmod
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: xxmrghd 34, 1, 0 ; PC64LE-NEXT: xxmrghd 34, 1, 0
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_frem_v2f64: ; PC64LE9-LABEL: constrained_vector_frem_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
Show All 11 Lines
; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: bl fmod ; PC64LE9-NEXT: bl fmod
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: xxmrghd 34, 1, 0 ; PC64LE9-NEXT: xxmrghd 34, 1, 0
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%rem = call <2 x double> @llvm.experimental.constrained.frem.v2f64( %rem = call <2 x double> @llvm.experimental.constrained.frem.v2f64(
<2 x double> <double 1.000000e+00, double 2.000000e+00>, <2 x double> <double 1.000000e+00, double 2.000000e+00>,
<2 x double> <double 1.000000e+01, double 1.000000e+01>, <2 x double> <double 1.000000e+01, double 1.000000e+01>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %rem ret <2 x double> %rem
Show All 35 Lines
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: xxsldwi 35, 1, 1, 1 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 1
; PC64LE-NEXT: vmrglw 2, 2, 3 ; PC64LE-NEXT: vmrglw 2, 2, 3
; PC64LE-NEXT: xxsldwi 35, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 35, 0, 0, 1
; PC64LE-NEXT: vperm 2, 3, 2, 4 ; PC64LE-NEXT: vperm 2, 3, 2, 4
; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: addi 1, 1, 64
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_frem_v3f32: ; PC64LE9-LABEL: constrained_vector_frem_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 29, -24(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 29, -24(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
Show All 26 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI7_4@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI7_4@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI7_4@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI7_4@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: vmrglw 2, 3, 2 ; PC64LE9-NEXT: vmrglw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 1 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 1
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%rem = call <3 x float> @llvm.experimental.constrained.frem.v3f32( %rem = call <3 x float> @llvm.experimental.constrained.frem.v3f32(
<3 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, <3 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>,
<3 x float> <float 1.000000e+01, float 1.000000e+01, float 1.000000e+01>, <3 x float> <float 1.000000e+01, float 1.000000e+01, float 1.000000e+01>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
▲ Show 20 Lines • Show All 1,102 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: bl pow ; PC64LE-NEXT: bl pow
; PC64LE-NEXT: nop ; PC64LE-NEXT: nop
; PC64LE-NEXT: li 3, 48 ; PC64LE-NEXT: li 3, 48
; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload ; PC64LE-NEXT: lxvd2x 0, 1, 3 # 16-byte Folded Reload
; PC64LE-NEXT: xxmrghd 34, 1, 0 ; PC64LE-NEXT: xxmrghd 34, 1, 0
; PC64LE-NEXT: addi 1, 1, 80 ; PC64LE-NEXT: addi 1, 1, 80
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_pow_v2f64: ; PC64LE9-LABEL: constrained_vector_pow_v2f64:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
; PC64LE9-NEXT: stdu 1, -64(1) ; PC64LE9-NEXT: stdu 1, -64(1)
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; PC64LE9-NEXT: fmr 2, 31 ; PC64LE9-NEXT: fmr 2, 31
; PC64LE9-NEXT: bl pow ; PC64LE9-NEXT: bl pow
; PC64LE9-NEXT: nop ; PC64LE9-NEXT: nop
; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload ; PC64LE9-NEXT: lxv 0, 32(1) # 16-byte Folded Reload
; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1 ; PC64LE9-NEXT: # kill: def $f1 killed $f1 def $vsl1
; PC64LE9-NEXT: xxmrghd 34, 1, 0 ; PC64LE9-NEXT: xxmrghd 34, 1, 0
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%pow = call <2 x double> @llvm.experimental.constrained.pow.v2f64( %pow = call <2 x double> @llvm.experimental.constrained.pow.v2f64(
<2 x double> <double 42.1, double 42.2>, <2 x double> <double 42.1, double 42.2>,
<2 x double> <double 3.0, double 3.0>, <2 x double> <double 3.0, double 3.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <2 x double> %pow ret <2 x double> %pow
Show All 35 Lines
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: xxsldwi 35, 1, 1, 1 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 1
; PC64LE-NEXT: vmrglw 2, 2, 3 ; PC64LE-NEXT: vmrglw 2, 2, 3
; PC64LE-NEXT: xxsldwi 35, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 35, 0, 0, 1
; PC64LE-NEXT: vperm 2, 3, 2, 4 ; PC64LE-NEXT: vperm 2, 3, 2, 4
; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: addi 1, 1, 64
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_pow_v3f32: ; PC64LE9-LABEL: constrained_vector_pow_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 29, -24(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 29, -24(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
Show All 26 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI32_4@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI32_4@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI32_4@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI32_4@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: vmrglw 2, 3, 2 ; PC64LE9-NEXT: vmrglw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 1 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 1
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%pow = call <3 x float> @llvm.experimental.constrained.pow.v3f32( %pow = call <3 x float> @llvm.experimental.constrained.pow.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>, <3 x float> <float 42.0, float 43.0, float 44.0>,
<3 x float> <float 3.0, float 3.0, float 3.0>, <3 x float> <float 3.0, float 3.0, float 3.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
▲ Show 20 Lines • Show All 343 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: xxsldwi 34, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: xscvdpspn 0, 31 ; PC64LE-NEXT: xscvdpspn 0, 31
; PC64LE-NEXT: xxsldwi 35, 1, 1, 1 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 1
; PC64LE-NEXT: vmrglw 2, 2, 3 ; PC64LE-NEXT: vmrglw 2, 2, 3
; PC64LE-NEXT: xxsldwi 35, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 35, 0, 0, 1
; PC64LE-NEXT: vperm 2, 3, 2, 4 ; PC64LE-NEXT: vperm 2, 3, 2, 4
; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: addi 1, 1, 48
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_powi_v3f32: ; PC64LE9-LABEL: constrained_vector_powi_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
Show All 23 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI37_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI37_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI37_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI37_3@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: vmrglw 2, 3, 2 ; PC64LE9-NEXT: vmrglw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 1 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 1
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%powi = call <3 x float> @llvm.experimental.constrained.powi.v3f32( %powi = call <3 x float> @llvm.experimental.constrained.powi.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>, <3 x float> <float 42.0, float 43.0, float 44.0>,
i32 3, i32 3,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %powi ret <3 x float> %powi
▲ Show 20 Lines • Show All 312 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: xscvdpspn 0, 31 ; PC64LE-NEXT: xscvdpspn 0, 31
; PC64LE-NEXT: xxsldwi 35, 1, 1, 1 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 1
; PC64LE-NEXT: vmrglw 2, 2, 3 ; PC64LE-NEXT: vmrglw 2, 2, 3
; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: lvx 3, 0, 3
; PC64LE-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: addi 1, 1, 48
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_sin_v3f32: ; PC64LE9-LABEL: constrained_vector_sin_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
Show All 20 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI42_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI42_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI42_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI42_3@toc@l
; PC64LE9-NEXT: vmrglw 2, 3, 2 ; PC64LE9-NEXT: vmrglw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%sin = call <3 x float> @llvm.experimental.constrained.sin.v3f32( %sin = call <3 x float> @llvm.experimental.constrained.sin.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>, <3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %sin ret <3 x float> %sin
} }
▲ Show 20 Lines • Show All 295 Lines • ▼ Show 20 Lines
; PC64LE-NEXT: xscvdpspn 0, 31 ; PC64LE-NEXT: xscvdpspn 0, 31
; PC64LE-NEXT: xxsldwi 35, 1, 1, 1 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 1
; PC64LE-NEXT: vmrglw 2, 2, 3 ; PC64LE-NEXT: vmrglw 2, 2, 3
; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: lvx 3, 0, 3
; PC64LE-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: addi 1, 1, 48
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_cos_v3f32: ; PC64LE9-LABEL: constrained_vector_cos_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
Show All 20 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI47_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI47_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI47_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI47_3@toc@l
; PC64LE9-NEXT: vmrglw 2, 3, 2 ; PC64LE9-NEXT: vmrglw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%cos = call <3 x float> @llvm.experimental.constrained.cos.v3f32( %cos = call <3 x float> @llvm.experimental.constrained.cos.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>, <3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %cos ret <3 x float> %cos
} }
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; PC64LE-NEXT: xscvdpspn 0, 31 ; PC64LE-NEXT: xscvdpspn 0, 31
; PC64LE-NEXT: xxsldwi 35, 1, 1, 1 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 1
; PC64LE-NEXT: vmrglw 2, 2, 3 ; PC64LE-NEXT: vmrglw 2, 2, 3
; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: lvx 3, 0, 3
; PC64LE-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: addi 1, 1, 48
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp_v3f32: ; PC64LE9-LABEL: constrained_vector_exp_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
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; PC64LE9-NEXT: addis 3, 2, .LCPI52_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI52_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI52_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI52_3@toc@l
; PC64LE9-NEXT: vmrglw 2, 3, 2 ; PC64LE9-NEXT: vmrglw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%exp = call <3 x float> @llvm.experimental.constrained.exp.v3f32( %exp = call <3 x float> @llvm.experimental.constrained.exp.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>, <3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %exp ret <3 x float> %exp
} }
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; PC64LE-NEXT: xscvdpspn 0, 31 ; PC64LE-NEXT: xscvdpspn 0, 31
; PC64LE-NEXT: xxsldwi 35, 1, 1, 1 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 1
; PC64LE-NEXT: vmrglw 2, 2, 3 ; PC64LE-NEXT: vmrglw 2, 2, 3
; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: lvx 3, 0, 3
; PC64LE-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: addi 1, 1, 48
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_exp2_v3f32: ; PC64LE9-LABEL: constrained_vector_exp2_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
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; PC64LE9-NEXT: addis 3, 2, .LCPI57_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI57_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI57_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI57_3@toc@l
; PC64LE9-NEXT: vmrglw 2, 3, 2 ; PC64LE9-NEXT: vmrglw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%exp2 = call <3 x float> @llvm.experimental.constrained.exp2.v3f32( %exp2 = call <3 x float> @llvm.experimental.constrained.exp2.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>, <3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %exp2 ret <3 x float> %exp2
} }
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; PC64LE-NEXT: xscvdpspn 0, 31 ; PC64LE-NEXT: xscvdpspn 0, 31
; PC64LE-NEXT: xxsldwi 35, 1, 1, 1 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 1
; PC64LE-NEXT: vmrglw 2, 2, 3 ; PC64LE-NEXT: vmrglw 2, 2, 3
; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: lvx 3, 0, 3
; PC64LE-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: addi 1, 1, 48
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log_v3f32: ; PC64LE9-LABEL: constrained_vector_log_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
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; PC64LE9-NEXT: addis 3, 2, .LCPI62_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI62_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI62_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI62_3@toc@l
; PC64LE9-NEXT: vmrglw 2, 3, 2 ; PC64LE9-NEXT: vmrglw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%log = call <3 x float> @llvm.experimental.constrained.log.v3f32( %log = call <3 x float> @llvm.experimental.constrained.log.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>, <3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %log ret <3 x float> %log
} }
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; PC64LE-NEXT: xscvdpspn 0, 31 ; PC64LE-NEXT: xscvdpspn 0, 31
; PC64LE-NEXT: xxsldwi 35, 1, 1, 1 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 1
; PC64LE-NEXT: vmrglw 2, 2, 3 ; PC64LE-NEXT: vmrglw 2, 2, 3
; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: lvx 3, 0, 3
; PC64LE-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: addi 1, 1, 48
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log10_v3f32: ; PC64LE9-LABEL: constrained_vector_log10_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
Show All 20 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI67_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI67_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI67_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI67_3@toc@l
; PC64LE9-NEXT: vmrglw 2, 3, 2 ; PC64LE9-NEXT: vmrglw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%log10 = call <3 x float> @llvm.experimental.constrained.log10.v3f32( %log10 = call <3 x float> @llvm.experimental.constrained.log10.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>, <3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %log10 ret <3 x float> %log10
} }
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; PC64LE-NEXT: xscvdpspn 0, 31 ; PC64LE-NEXT: xscvdpspn 0, 31
; PC64LE-NEXT: xxsldwi 35, 1, 1, 1 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 1
; PC64LE-NEXT: vmrglw 2, 2, 3 ; PC64LE-NEXT: vmrglw 2, 2, 3
; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: lvx 3, 0, 3
; PC64LE-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: addi 1, 1, 48
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_log2_v3f32: ; PC64LE9-LABEL: constrained_vector_log2_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
Show All 20 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI72_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI72_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI72_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI72_3@toc@l
; PC64LE9-NEXT: vmrglw 2, 3, 2 ; PC64LE9-NEXT: vmrglw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%log2 = call <3 x float> @llvm.experimental.constrained.log2.v3f32( %log2 = call <3 x float> @llvm.experimental.constrained.log2.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>, <3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %log2 ret <3 x float> %log2
} }
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; PC64LE-NEXT: xscvdpspn 0, 31 ; PC64LE-NEXT: xscvdpspn 0, 31
; PC64LE-NEXT: xxsldwi 35, 1, 1, 1 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 1
; PC64LE-NEXT: vmrglw 2, 2, 3 ; PC64LE-NEXT: vmrglw 2, 2, 3
; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: lvx 3, 0, 3
; PC64LE-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: addi 1, 1, 48
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_rint_v3f32: ; PC64LE9-LABEL: constrained_vector_rint_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
Show All 20 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI77_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI77_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI77_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI77_3@toc@l
; PC64LE9-NEXT: vmrglw 2, 3, 2 ; PC64LE9-NEXT: vmrglw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%rint = call <3 x float> @llvm.experimental.constrained.rint.v3f32( %rint = call <3 x float> @llvm.experimental.constrained.rint.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>, <3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %rint ret <3 x float> %rint
} }
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; PC64LE-NEXT: xscvdpspn 0, 31 ; PC64LE-NEXT: xscvdpspn 0, 31
; PC64LE-NEXT: xxsldwi 35, 1, 1, 1 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 1
; PC64LE-NEXT: vmrglw 2, 2, 3 ; PC64LE-NEXT: vmrglw 2, 2, 3
; PC64LE-NEXT: lvx 3, 0, 3 ; PC64LE-NEXT: lvx 3, 0, 3
; PC64LE-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE-NEXT: vperm 2, 4, 2, 3 ; PC64LE-NEXT: vperm 2, 4, 2, 3
; PC64LE-NEXT: addi 1, 1, 48 ; PC64LE-NEXT: addi 1, 1, 48
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_nearbyint_v3f32: ; PC64LE9-LABEL: constrained_vector_nearbyint_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
; PC64LE9-NEXT: std 0, 16(1) ; PC64LE9-NEXT: std 0, 16(1)
Show All 20 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI82_3@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI82_3@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI82_3@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI82_3@toc@l
; PC64LE9-NEXT: vmrglw 2, 3, 2 ; PC64LE9-NEXT: vmrglw 2, 3, 2
; PC64LE9-NEXT: lxvx 35, 0, 3 ; PC64LE9-NEXT: lxvx 35, 0, 3
; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1 ; PC64LE9-NEXT: xxsldwi 36, 0, 0, 1
; PC64LE9-NEXT: vperm 2, 4, 2, 3 ; PC64LE9-NEXT: vperm 2, 4, 2, 3
; PC64LE9-NEXT: addi 1, 1, 48 ; PC64LE9-NEXT: addi 1, 1, 48
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%nearby = call <3 x float> @llvm.experimental.constrained.nearbyint.v3f32( %nearby = call <3 x float> @llvm.experimental.constrained.nearbyint.v3f32(
<3 x float> <float 42.0, float 43.0, float 44.0>, <3 x float> <float 42.0, float 43.0, float 44.0>,
metadata !"round.dynamic", metadata !"round.dynamic",
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %nearby ret <3 x float> %nearby
} }
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; PC64LE-NEXT: xxsldwi 34, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: xxsldwi 35, 1, 1, 1 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 1
; PC64LE-NEXT: vmrglw 2, 2, 3 ; PC64LE-NEXT: vmrglw 2, 2, 3
; PC64LE-NEXT: xxsldwi 35, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 35, 0, 0, 1
; PC64LE-NEXT: vperm 2, 3, 2, 4 ; PC64LE-NEXT: vperm 2, 3, 2, 4
; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: addi 1, 1, 64
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_maxnum_v3f32: ; PC64LE9-LABEL: constrained_vector_maxnum_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 29, -24(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 29, -24(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
Show All 27 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI87_5@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI87_5@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI87_5@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI87_5@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: vmrglw 2, 3, 2 ; PC64LE9-NEXT: vmrglw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 1 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 1
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%max = call <3 x float> @llvm.experimental.constrained.maxnum.v3f32( %max = call <3 x float> @llvm.experimental.constrained.maxnum.v3f32(
<3 x float> <float 43.0, float 44.0, float 45.0>, <3 x float> <float 43.0, float 44.0, float 45.0>,
<3 x float> <float 41.0, float 42.0, float 43.0>, <3 x float> <float 41.0, float 42.0, float 43.0>,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %max ret <3 x float> %max
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; PC64LE-NEXT: xxsldwi 34, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 34, 0, 0, 1
; PC64LE-NEXT: xscvdpspn 0, 30 ; PC64LE-NEXT: xscvdpspn 0, 30
; PC64LE-NEXT: xxsldwi 35, 1, 1, 1 ; PC64LE-NEXT: xxsldwi 35, 1, 1, 1
; PC64LE-NEXT: vmrglw 2, 2, 3 ; PC64LE-NEXT: vmrglw 2, 2, 3
; PC64LE-NEXT: xxsldwi 35, 0, 0, 1 ; PC64LE-NEXT: xxsldwi 35, 0, 0, 1
; PC64LE-NEXT: vperm 2, 3, 2, 4 ; PC64LE-NEXT: vperm 2, 3, 2, 4
; PC64LE-NEXT: addi 1, 1, 64 ; PC64LE-NEXT: addi 1, 1, 64
; PC64LE-NEXT: ld 0, 16(1) ; PC64LE-NEXT: ld 0, 16(1)
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE-NEXT: lfd 29, -24(1) # 8-byte Folded Reload
; PC64LE-NEXT: mtlr 0
; PC64LE-NEXT: blr ; PC64LE-NEXT: blr
; ;
; PC64LE9-LABEL: constrained_vector_minnum_v3f32: ; PC64LE9-LABEL: constrained_vector_minnum_v3f32:
; PC64LE9: # %bb.0: # %entry ; PC64LE9: # %bb.0: # %entry
; PC64LE9-NEXT: mflr 0 ; PC64LE9-NEXT: mflr 0
; PC64LE9-NEXT: stfd 29, -24(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 29, -24(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 30, -16(1) # 8-byte Folded Spill
; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill ; PC64LE9-NEXT: stfd 31, -8(1) # 8-byte Folded Spill
Show All 27 Lines
; PC64LE9-NEXT: addis 3, 2, .LCPI92_5@toc@ha ; PC64LE9-NEXT: addis 3, 2, .LCPI92_5@toc@ha
; PC64LE9-NEXT: addi 3, 3, .LCPI92_5@toc@l ; PC64LE9-NEXT: addi 3, 3, .LCPI92_5@toc@l
; PC64LE9-NEXT: lxvx 36, 0, 3 ; PC64LE9-NEXT: lxvx 36, 0, 3
; PC64LE9-NEXT: vmrglw 2, 3, 2 ; PC64LE9-NEXT: vmrglw 2, 3, 2
; PC64LE9-NEXT: xxsldwi 35, 0, 0, 1 ; PC64LE9-NEXT: xxsldwi 35, 0, 0, 1
; PC64LE9-NEXT: vperm 2, 3, 2, 4 ; PC64LE9-NEXT: vperm 2, 3, 2, 4
; PC64LE9-NEXT: addi 1, 1, 64 ; PC64LE9-NEXT: addi 1, 1, 64
; PC64LE9-NEXT: ld 0, 16(1) ; PC64LE9-NEXT: ld 0, 16(1)
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 31, -8(1) # 8-byte Folded Reload
; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 30, -16(1) # 8-byte Folded Reload
; PC64LE9-NEXT: mtlr 0
; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload ; PC64LE9-NEXT: lfd 29, -24(1) # 8-byte Folded Reload
; PC64LE9-NEXT: blr ; PC64LE9-NEXT: blr
entry: entry:
%min = call <3 x float> @llvm.experimental.constrained.minnum.v3f32( %min = call <3 x float> @llvm.experimental.constrained.minnum.v3f32(
<3 x float> <float 43.0, float 44.0, float 45.0>, <3 x float> <float 43.0, float 44.0, float 45.0>,
<3 x float> <float 41.0, float 42.0, float 43.0>, <3 x float> <float 41.0, float 42.0, float 43.0>,
metadata !"fpexcept.strict") #1 metadata !"fpexcept.strict") #1
ret <3 x float> %min ret <3 x float> %min
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