Change-Id: Ic26f915a4acb4c00ecefa9d09d7c24cec370ed06
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Buildable 41557 Build 41789: arc lint + arc unit
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Did the problem manifest in any way?
llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp | ||
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31 | Includes need to be alphabetically sorted. |
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I had a couple of big graphics shaders that generated different but still correct code due to registers being allocated in a different order, depending on whether I had some other change in the front-end compiler that only affected IR metadata, and the difference only happened on one of two machines I tried it on. I spotted it because I had a bunch of front-end compiler changes that were not supposed to affect output code, and I was testing that by compiling as much stuff as I could with before-change and after-change compilers.
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I mean if you have a test, it will detect if it were to fail on some other map implementation
Includes need to be alphabetically sorted.