This is in preparation for adding more test cases for D69661 and other
bug fixes in the same area.
Details
Diff Detail
- Repository
- rG LLVM Github Monorepo
Event Timeline
llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir | ||
---|---|---|
60 | Losing tracksRegLiveness seem like a problem, since this is a case where you're using reg liveness (along with the loss of the liveins lists) |
llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir | ||
---|---|---|
60 | I can put tracksRegLiveness back in of course, but are you saying the insert waitcnts pass depends on liveness? I wasn't aware of that. |
llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir | ||
---|---|---|
60 | It has to check if vccz is live out for example. Not tracking liveness at any point is just insane |
llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir | ||
---|---|---|
15 | vcc doesn't need to be live in here |
Unit tests: pass. 62213 tests passed, 0 failed and 815 were skipped.
clang-tidy: pass.
clang-format: pass.
Build artifacts: diff.json, clang-tidy.txt, clang-format.patch, CMakeCache.txt, console-log.txt, test-results.xml
Pre-merge checks is in beta. Report issue. Please join beta or enable it for your project.
Losing tracksRegLiveness seem like a problem, since this is a case where you're using reg liveness (along with the loss of the liveins lists)