[PowerPC] Separate Features that are known to be Power9 specific from Future CPU

[stefanp]

Summary

The Power 9 CPU has some features that are unlikely to be passed on to future versions of the CPU.
This patch separates this out so that future CPU does not inherit them.

[steven.zhang]

The feature list here assume that, new processor will contain superset of features of those that came before it. And we are trying to break the assumption here. Can we do it another way. That is, keep the TD unchanged and check the CPU Directive in PPCSubtarget ? i.e.

PPCSubtarget::vectorsUseTwoUnits() const { return VectorsUseTwoUnits && DarwinDirective == PPC::DIR_PWR9; }

[nemanjai]

In D70466#1753176, @steven.zhang wrote:

The feature list here assume that, new processor will contain superset of features of those that came before it. And we are trying to break the assumption here. Can we do it another way. That is, keep the TD unchanged and check the CPU Directive in PPCSubtarget ? i.e.

PPCSubtarget::vectorsUseTwoUnits() const { return VectorsUseTwoUnits && DarwinDirective == PPC::DIR_PWR9; }

I strongly disagree with this suggestion. The CPU model should reflect the features that the CPU supports. Separating out checks this way is an unnecessary separation of concerns that make it difficult for the uninitiated reader to decipher what CPU has which feature.
The fact is that the Power9 CPU has some quirks that make it stand out from other CPUs such as Power8 (i.e. no fusion capability, narrower dispatch width for vectors, etc.). There is no reason to expect that these quirks will exist in any future CPUs. It is really helpful in terms of readability to see in one place that this CPU does not follow the regular progression of Power CPUs and to see exactly what it does differently.

[steven.zhang]

If we want to break the assumption, please update the comment for the processor feature which is separated into two parts now, inherit and only, for all cpus. The inherit part still has the assumption, and p9 = p9 inherit + p9 only.

[nemanjai]

LGTM with some clarification in a comment.

llvm/lib/Target/PowerPC/PPC.td

241

Fair enough. So lets add a comment along the lines of the following here:

// Some features are unique to Power9 and there is no reason to assume
// they will be part of any future CPUs. One example is the narrower
// dispatch for vector operations than scalar ones. For the time being,
// this list also includes scheduling-related features since we do not have
// enough info to create custom scheduling strategies for future CPUs.

llvm/lib/Target/PowerPC/PPC.td

list<SubtargetFeature> Power7FeatureList =
        FeatureBPERMD, FeatureExtDiv,
        FeatureMFTB, DeprecatedDST, FeatureTwoConstNR];
   list<SubtargetFeature> Power8SpecificFeatures =
       [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto,
        FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic];
   list<SubtargetFeature> Power8FeatureList =
       !listconcat(Power7FeatureList, Power8SpecificFeatures);
   list<SubtargetFeature> Power9SpecificFeatures =
-      [DirectivePwr9, FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0,
-       FeatureVectorsUseTwoUnits, FeaturePPCPreRASched, FeaturePPCPostRASched];
+      [DirectivePwr9, FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0];
+  list<SubtargetFeature> Power9OnlyFeatures =
+      [FeatureVectorsUseTwoUnits, FeaturePPCPreRASched, FeaturePPCPostRASched];
   list<SubtargetFeature> Power9FeatureList =
       !listconcat(Power8FeatureList, Power9SpecificFeatures);
+  list<SubtargetFeature> Power9ImplList =
+      !listconcat(Power9FeatureList, Power9OnlyFeatures);
 
   // For future CPU we assume that all of the existing features from Power 9
-  // still exist.
+  // still exist with the exception of those we know are Power 9 specific.
   list<SubtargetFeature> FutureSpecificFeatures =
       [];
   list<SubtargetFeature> FutureFeatureList =
       !listconcat(Power9FeatureList, FutureSpecificFeatures);
 }
 
 // Note: Future features to add when support is extended to more
 // recent ISA levels:
def : ProcessorModel<"pwr6x", G5Model,
                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
                    FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
                    FeatureFPRND, Feature64Bit,
                    FeatureMFTB, DeprecatedDST]>;
 def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
-def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9FeatureList>;
+def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.Power9ImplList>;
 // No scheduler model for future CPU.
 def : ProcessorModel<"future", NoSchedModel,
                   ProcessorFeatures.FutureFeatureList>;
 def : Processor<"ppc", G3Itineraries, [Directive32, FeatureHardFloat,
                                        FeatureMFTB]>;
 def : Processor<"ppc32", G3Itineraries, [Directive32, FeatureHardFloat,
                                          FeatureMFTB]>;
 def : ProcessorModel<"ppc64", G5Model,

llvm/test/Analysis/CostModel/PowerPC/future-cost-model.ll

+; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:       -mcpu=future | FileCheck %s --check-prefix=FUTURE
+; RUN: opt < %s -cost-model -analyze -mtriple=powerpc64le-unknown-linux-gnu \
+; RUN:       -mcpu=pwr9 | FileCheck %s --check-prefix=PWR9
+
+define void @test(i16 %p1, i16 %p2, <4 x i16> %p3, <4 x i16> %p4) {
+  %i1 = add i16 %p1, %p2
+  %v1 = add <4 x i16> %p3, %p4
+  ret void
+  ; FUTURE: cost of 1 {{.*}} add
+  ; FUTURE: cost of 1 {{.*}} add
+
+  ; PWR9: cost of 1 {{.*}} add
+  ; PWR9: cost of 2 {{.*}} add
+}
+