[PowerPC] Add new Future CPU for PowerPC

[stefanp]

Summary

This patch will add -mcpu=future into clang for PowerPC.

A CPU type is required for work that may possibly be enabled for some future Power CPU. The CPU type future will serve that purpose.
This patch introduces no new functionality. It is an incremental patch on top of which Power PC work for some future CPU can be done.

[nemanjai]

LGTM.

clang/lib/Basic/Targets/PPC.h

typedef enum {
     ArchDefinePwr4 = 1 << 6,
     ArchDefinePwr5 = 1 << 7,
     ArchDefinePwr5x = 1 << 8,
     ArchDefinePwr6 = 1 << 9,
     ArchDefinePwr6x = 1 << 10,
     ArchDefinePwr7 = 1 << 11,
     ArchDefinePwr8 = 1 << 12,
     ArchDefinePwr9 = 1 << 13,
-    ArchDefineA2 = 1 << 14,
-    ArchDefineA2q = 1 << 15,
-    ArchDefineE500 = 1 << 16
+    ArchDefineFuture = 1 << 14,
+    ArchDefineA2 = 1 << 15,
+    ArchDefineA2q = 1 << 16,
+    ArchDefineE500 = 1 << 17
   } ArchDefineTypes;
 
 
   ArchDefineTypes ArchDefs = ArchDefineNone;
   static const Builtin::Info BuiltinInfo[];
   static const char *const GCCRegNames[];
   static const TargetInfo::GCCRegAlias GCCRegAliases[];
   std::string CPU;
if (CPUKnown) {
               .Cases("power8", "pwr8", "ppc64le",
                      ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
                          ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
                          ArchDefinePpcgr | ArchDefinePpcsq)
               .Cases("power9", "pwr9",
                      ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
                          ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
                          ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
+              .Case("future",
+                    ArchDefineFuture | ArchDefinePwr9 | ArchDefinePwr8 |
+                        ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
+                        ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
+                        ArchDefinePpcsq)
               .Cases("8548", "e500", ArchDefineE500)
               .Default(ArchDefineNone);
     }
     return CPUKnown;
   }
 
   StringRef getABI() const override { return ABI; }
 
   ArrayRef<Builtin::Info> getTargetBuiltins() const override;
 
   bool isCLZForZeroUndef() const override { return false; }
 
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override;
 
   bool
   initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags,
                  StringRef CPU,
                  const std::vector<std::string> &FeaturesVec) const override;
 
+  void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
+
   bool handleTargetFeatures(std::vector<std::string> &Features,
                             DiagnosticsEngine &Diags) override;
 
   bool hasFeature(StringRef Feature) const override;
 
   void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name,
                          bool Enabled) const override;
 

clang/lib/Basic/Targets/PPC.cpp

void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
   if (ArchDefs & ArchDefineA2)
     Builder.defineMacro("_ARCH_A2");
   if (ArchDefs & ArchDefineA2q) {
     Builder.defineMacro("_ARCH_A2Q");
     Builder.defineMacro("_ARCH_QP");
   }
   if (ArchDefs & ArchDefineE500)
     Builder.defineMacro("__NO_LWSYNC__");
+  if (ArchDefs & ArchDefineFuture)
+    Builder.defineMacro("_ARCH_PWR_FUTURE");
 
   if (getTriple().getVendor() == llvm::Triple::BGQ) {
     Builder.defineMacro("__bg__");
     Builder.defineMacro("__THW_BLUEGENE__");
     Builder.defineMacro("__bgq__");
     Builder.defineMacro("__TOS_BGQ__");
   }
 
Features["htm"] = llvm::StringSwitch<bool>(CPU)
                         .Case("pwr8", true)
                         .Default(false);
 
   Features["spe"] = llvm::StringSwitch<bool>(CPU)
                         .Case("8548", true)
                         .Case("e500", true)
                         .Default(false);
 
+  // Future CPU should include all of the features of Power 9 as well as any
+  // additional features (yet to be determined) specific to it.
+  if (CPU == "future") {
+    initFeatureMap(Features, Diags, "pwr9", FeaturesVec);
+    addFutureSpecificFeatures(Features);
+  }
+
   if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
     return false;
 
   if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) &&
       llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
     // We have __float128 on PPC but not power 9 and above.
     Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" << CPU;
     return false;
   }
 
   return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec);
 }
 
+// Add features specific to the "Future" CPU.
+void PPCTargetInfo::addFutureSpecificFeatures(
+    llvm::StringMap<bool> &Features) const {
+  return;
+}
+
 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
   return llvm::StringSwitch<bool>(Feature)
       .Case("powerpc", true)
       .Case("altivec", HasAltivec)
       .Case("vsx", HasVSX)
       .Case("power8-vector", HasP8Vector)
       .Case("crypto", HasP8Crypto)
       .Case("direct-move", HasDirectMove)
static constexpr llvm::StringLiteral ValidCPUNames[] = {
     {"620"},       {"630"},       {"g3"},          {"7400"},        {"g4"},
     {"7450"},      {"g4+"},       {"750"},         {"8548"},        {"970"},
     {"g5"},        {"a2"},        {"a2q"},         {"e500"},        {"e500mc"},
     {"e5500"},     {"power3"},    {"pwr3"},        {"power4"},      {"pwr4"},
     {"power5"},    {"pwr5"},      {"power5x"},     {"pwr5x"},       {"power6"},
     {"pwr6"},      {"power6x"},   {"pwr6x"},       {"power7"},      {"pwr7"},
     {"power8"},    {"pwr8"},      {"power9"},      {"pwr9"},        {"powerpc"},
     {"ppc"},       {"powerpc64"}, {"ppc64"},       {"powerpc64le"}, {"ppc64le"},
+    {"future"}
 };
 
 bool PPCTargetInfo::isValidCPUName(StringRef Name) const {
   return llvm::find(ValidCPUNames, Name) != std::end(ValidCPUNames);
 }
 
 void PPCTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
   Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));

clang/lib/Driver/ToolChains/Arch/PPC.cpp

return llvm::StringSwitch<const char *>(CPUName)
         .Case("power4", "pwr4")
         .Case("power5", "pwr5")
         .Case("power5x", "pwr5x")
         .Case("power6", "pwr6")
         .Case("power6x", "pwr6x")
         .Case("power7", "pwr7")
         .Case("power8", "pwr8")
         .Case("power9", "pwr9")
+        .Case("future", "future")
         .Case("pwr3", "pwr3")
         .Case("pwr4", "pwr4")
         .Case("pwr5", "pwr5")
         .Case("pwr5x", "pwr5x")
         .Case("pwr6", "pwr6")
         .Case("pwr6x", "pwr6x")
         .Case("pwr7", "pwr7")
         .Case("pwr8", "pwr8")

clang/test/Misc/target-invalid-cpu-note.c

 
 // RUN: not %clang_cc1 -triple powerpc--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix PPC
 // PPC: error: unknown target CPU 'not-a-cpu'
 // PPC: note: valid target CPU values are: generic, 440, 450, 601, 602, 603,
 // PPC-SAME: 603e, 603ev, 604, 604e, 620, 630, g3, 7400, g4, 7450, g4+, 750,
 // PPC-SAME: 8548, 970, g5, a2, a2q, e500, e500mc, e5500, power3, pwr3, power4,
 // PPC-SAME: pwr4, power5, pwr5, power5x, pwr5x, power6, pwr6, power6x, pwr6x,
 // PPC-SAME: power7, pwr7, power8, pwr8, power9, pwr9, powerpc, ppc, powerpc64,
-// PPC-SAME: ppc64, powerpc64le, ppc64le
+// PPC-SAME: ppc64, powerpc64le, ppc64le, future
 
 // RUN: not %clang_cc1 -triple mips--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix MIPS
 // MIPS: error: unknown target CPU 'not-a-cpu'
 // MIPS: note: valid target CPU values are: mips1, mips2, mips3, mips4, mips5,
 // MIPS-SAME: mips32, mips32r2, mips32r3, mips32r5, mips32r6, mips64, mips64r2,
 // MIPS-SAME: mips64r3, mips64r5, mips64r6, octeon, octeon+, p5600
 
 // RUN: not %clang_cc1 -triple lanai--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix LANAI

clang/test/Preprocessor/init.c

 // PPCPOWER9:#define _ARCH_PWR4 1
 // PPCPOWER9:#define _ARCH_PWR5 1
 // PPCPOWER9:#define _ARCH_PWR5X 1
 // PPCPOWER9:#define _ARCH_PWR6 1
 // PPCPOWER9-NOT:#define _ARCH_PWR6X 1
 // PPCPOWER9:#define _ARCH_PWR7 1
 // PPCPOWER9:#define _ARCH_PWR9 1
 //
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCFUTURE %s
+//
+// PPCFUTURE:#define _ARCH_PPC 1
+// PPCFUTURE:#define _ARCH_PPC64 1
+// PPCFUTURE:#define _ARCH_PPCGR 1
+// PPCFUTURE:#define _ARCH_PPCSQ 1
+// PPCFUTURE:#define _ARCH_PWR4 1
+// PPCFUTURE:#define _ARCH_PWR5 1
+// PPCFUTURE:#define _ARCH_PWR5X 1
+// PPCFUTURE:#define _ARCH_PWR6 1
+// PPCFUTURE-NOT:#define _ARCH_PWR6X 1
+// PPCFUTURE:#define _ARCH_PWR7 1
+// PPCFUTURE:#define _ARCH_PWR8 1
+// PPCFUTURE:#define _ARCH_PWR9 1
+// PPCFUTURE:#define _ARCH_PWR_FUTURE 1
+//
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-feature +float128 -target-cpu power9 -fno-signed-char < /dev/null | FileCheck -check-prefix PPC-FLOAT128 %s
 // PPC-FLOAT128:#define __FLOAT128__ 1
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-ibm-aix7.1.0.0 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPC64-AIX %s
 //
 // PPC64-AIX:#define _AIX 1
 // PPC64-AIX:#define _ARCH_PPC 1
 // PPC64-AIX:#define _ARCH_PPC64 1