[AMDGPU] NFC target dependent requiresUniformRegister refactored out

[alex-t]

Summary

Target specific method encapsulated into the Target Lowering Info.

[rampitec]

llvm/include/llvm/CodeGen/TargetLowering.h

827

Typo: Divergent Analysis -> Divergence Analysis

llvm/lib/Target/AMDGPU/SIISelLowering.h

422

Formatting is off.

[alex-t]

Typo and formatting fixed.

[rampitec]

LGTM

[arsenm]

llvm/include/llvm/CodeGen/TargetLowering.h

31

No reason to spread this to generic code

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

11231–11232

requiresUniformRegister is an expensive check (which really should be eliminated entirely), so should be made second only when really necessary

[arsenm]

llvm/include/llvm/CodeGen/TargetLowering.h

830

The DA check could have skipped the virtual call

[arsenm]

I've reverted this in 9786e7552d5564268484357866088d0a054bccaf. This will only hurt compile time for what's really an AMDGPU only hack

[alex-t]

llvm/include/llvm/CodeGen/TargetLowering.h

31

Why? LegacyDivergenceAnalysis.h is quite generic - not AMDGPU specific

830

Could you explain how it could happen? Any target with no divergent instructions have DA set to nullptr and method returns false.

[arsenm]

llvm/include/llvm/CodeGen/TargetLowering.h

830

There's no real reason to call isDivergent if DA is false. The hook should probably take a reference. You also don't need to include the header to TargetLowering (which is widely included), and cuold sink that into the implementation file

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

401

This should avoid all calls with no DA available

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

11231–11232

This part is quite important, I had to fix some really bad compile time regressions a few months ago because requiresUniformRegister is extremely slow

llvm/include/llvm/CodeGen/TargetLowering.h

 #define LLVM_CODEGEN_TARGETLOWERING_H
 
 #include "llvm/ADT/APInt.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
+#include "llvm/Analysis/LegacyDivergenceAnalysis.h"
 #include "llvm/CodeGen/DAGCombine.h"
 #include "llvm/CodeGen/ISDOpcodes.h"
 #include "llvm/CodeGen/RuntimeLibcalls.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/CodeGen/SelectionDAGNodes.h"
 #include "llvm/CodeGen/TargetCallingConv.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/IR/Attributes.h"
public:
   /// type.
   virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {
     (void)isDivergent;
     const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
     assert(RC && "This value type is not natively supported!");
     return RC;
   }
 
-  /// Allows target to decide about the register class of the
-  /// specific value that is live outside the defining block.
-  /// Returns true if the value needs uniform register class.
-  virtual bool requiresUniformRegister(MachineFunction &MF,
-                                       const Value *) const {
-    return false;
+  /// Allows target to decide about the divergence of the
+  /// specific value. Base class implementation returns true
+  /// if the Divergece Analysis exists and reports value as divergent.
+  virtual bool isDivergent(const LegacyDivergenceAnalysis *DA,
+                           MachineFunction &MF, const Value *V) const {
+    return DA && DA->isDivergent(V);
   }
 
   /// Return the 'representative' register class for the specified value
   /// type.
   ///
   /// The 'representative' register class is the largest legal super-reg
   /// register class for the register class of the value type.  For example, on
   /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep

llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp

for (unsigned i = 0; i != NumRegs; ++i) {
       Register R = CreateReg(RegisterVT, isDivergent);
       if (!FirstReg) FirstReg = R;
     }
   }
   return FirstReg;
 }
 
 Register FunctionLoweringInfo::CreateRegs(const Value *V) {
-  return CreateRegs(V->getType(), DA && DA->isDivergent(V) &&
-                    !TLI->requiresUniformRegister(*MF, V));
+  return CreateRegs(V->getType(), TLI->isDivergent(DA, *MF, V));
 }
 
 /// GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the
 /// register is a PHI destination and the PHI's LiveOutInfo is not valid. If
 /// the register's LiveOutInfo is for a smaller bit width, it is extended to
 /// the larger bit width by zero extension. The bit width must be no smaller
 /// than the LiveOutInfo's existing bit width.
 const FunctionLoweringInfo::LiveOutInfo *

llvm/lib/Target/AMDGPU/SIISelLowering.h

public:
   bool isKnownNeverNaNForTargetNode(SDValue Op,
                                     const SelectionDAG &DAG,
                                     bool SNaN = false,
                                     unsigned Depth = 0) const override;
   AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const override;
 
   virtual const TargetRegisterClass *
   getRegClassFor(MVT VT, bool isDivergent) const override;
-  virtual bool requiresUniformRegister(MachineFunction &MF,
-                                       const Value *V) const override;
+  virtual bool isDivergent(const LegacyDivergenceAnalysis *DA,
+                           MachineFunction &MF, const Value *V) const override;
+  bool requiresUniformRegister(MachineFunction &MF, const Value *V) const;
   Align getPrefLoopAlignment(MachineLoop *ML) const override;
 
   void allocateHSAUserSGPRs(CCState &CCInfo,
                             MachineFunction &MF,
                             const SIRegisterInfo &TRI,
                             SIMachineFunctionInfo &Info) const;
 
   void allocateSystemSGPRs(CCState &CCInfo,
                            MachineFunction &MF,

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

SITargetLowering::getRegClassFor(MVT VT, bool isDivergent) const {
   if (!TRI->isSGPRClass(RC) && !isDivergent)
     return TRI->getEquivalentSGPRClass(RC);
   else if (TRI->isSGPRClass(RC) && isDivergent)
     return TRI->getEquivalentVGPRClass(RC);
 
   return RC;
 }
 
+bool SITargetLowering::isDivergent(const LegacyDivergenceAnalysis *DA,
+                                   MachineFunction &MF, const Value *V) const {
+  return !requiresUniformRegister(MF, V) &&
+         TargetLoweringBase::isDivergent(DA, MF, V);
+}
+
 // FIXME: This is a workaround for DivergenceAnalysis not understanding always
 // uniform values (as produced by the mask results of control flow intrinsics)
 // used outside of divergent blocks. The phi users need to also be treated as
 // always uniform.
 static bool hasCFUser(const Value *V, SmallPtrSet<const Value *, 16> &Visited,
                       unsigned WaveSize) {
   // FIXME: We asssume we never cast the mask results of a control flow
   // intrinsic.