[AIX] Add support for lowering int, float and double formal arguments.

[ZarkoCA]

Summary

This patch adds LowerFormalArguments_AIX, support is added for lowering int, float, and double formal arguments onto general purpose and floating point registers only.

The aix calling convention testcase have been redone to test for caller and callee functionality.

[sfertile]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6720

My understanding is that when targeting 32-bit codegen any i64 will be split into 2 i32s. If thats correct then we should keep the i64 case separate, with an assert along the lines of assert(IsPPC64 && "i64 should have been split for 32-bit codegen.");.

6811

I believe this is breaking some of the existing AIX lit testing.

6840

Shouldn't we be doing the same thing extendArgForPPC64 is doing, but with the extra generality that the zext/zext type should be i32 when targeting 32-bit codegen?

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6720

I can change it to:

case MVT::i1:
case MVT::i32:
  (!isPPC64)
  return &PPC::GPRCRegClass;
  LLVM_FALLTHROUGH;
case MVT::i64:
  assert(IsPPC64 && "i64 should have been split for 32-bit codegen.");
  return &PPC::G8RCRegClass;

I think a defensive assert like you're suggesting is a good idea. it does complicate the switch a bit but that may be necessary?

6811

Thanks, I missed those in my testing. Adding -mattr=-altivec gets them to pass. I can add that to the testcases and ask the author to review.

6840

All other PPC targets look like they just truncate i1s. Adding a condition to check for any extension flags for all types, including i1s, led to some nodes missing. I will investigate further, however.

[ZarkoCA]

1 .Fixed broken testcases for AIX because of explicit error with altivec, and added reviewer for these.

2. Added additional guard to assert if i64 are not split into i32 before register allocation.
3. Rebased patch on master.

[sfertile]

Patch is getting pretty close, I am just going over the tests more thoroughly now. One observation for the gpr test: We have a lot of cases passing i8, but none passing i16.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6720

Missing an 'if'.
!isPPC64 --> !IsPPC64

6840

All other PPC targets look like they just truncate i1s.

The 32-bit targets only truncate, the 64-bit targets add the Assert[SZ]Ext nodes appropriate for the ArgFlags.

Adding a condition to check for any extension flags for all types, including i1s, led to some nodes missing.

Consider the following test case for 32-bit though:

@b = common local_unnamed_addr global i8 0, align 1

define void @callee(i1 zeroext %_b) local_unnamed_addr {
entry:
  %frombool = zext i1 %_b to i8
  store i8 %frombool, i8* @b, align 1
  ret void
}

If we add the assert nodes, then we would expect a DAG that kind of looks like:

t1: i8 ZeroExt(i1 Truncate(i32 AssertZext(i32 CopyFromReg %_b)))
store<(store 1 into @b)> t1, GlobalAddress:i32<i8* @b>

Without the assert nodes:

t1: i8 ZeroExt(i1 Truncate(i32 CopyFromReg %_b))
store<(store 1 into @b)> t1, GlobalAddress:i32<i8* @b>

In the first DAG we have preserved the information from the IR: namely that the value was original created by zero extending an i1 into an i32. Becuase of the extra info we can optimize away the truncate and zero extend. In the second DAG we have thrown the extra info away, and have to insert an extra clear instruction. If the Argument doesn't have the zeroext or signext attribute, then we end up with the second DAG anyway, and we would end up with a clear instruction as expected.

6854

I think we can get the stack size from the CCState object, since you allocated the linkage area and parameter saver area already.

[sfertile]

A couple high level comments on the tests.

• I like how you extended the 'LowerCall' tests to test both the caller and callee side, as opposed to adding new tests just for the formal argument lowering.

• There are a lot of tests covering quite a few cases. Its good to have thorough coverage. Having separate test cases for things like 1 float vs 3 floats, and 1 i8, vs 4 sext i8s, vs 4 zext i8s might be a little too verbose though. Having a couple calls that mix various extensions of the i8/i16 types i32 and i64 types should give adequate test coverage. Similarly for the fpr tests, a call which mixes doubles and floats should be adequate. I think the most descriptive test are those that are mixing floating and integer/pointer values. For example calling a function with a signature like: (i64 %a, double %d, i1 zeroext %b, float %f, i16 signext %c) shows how we split the i64 for 32-bit codegen, skip gprs for doubls/floats and map the smaller then register sized types into a gpr all in 1 test.

• Most of the test on the callee side we don't really care about the instructions in the callee, the liveins is all we are really interested in. I find the allocas and dead stores a little odd. There is no passes to remove them between llc start and where we dump mir so its OK, but I would prefer just having some arbitrary arthritic with the arguments so they are all used to calculate a return value instead, and don't need any checks other then the liveins except in a couple select tests.

• We probably want a test like the i1 signext/zext/no flags test I posted in one of the comments, and maybe a similar style test for the codegen we expect for say a type that is smaller then register size but not an i1.

• With the reduction in test verbosity (less tests and less CHECK directives) we should be able to combine aix_gpr_param.ll and aix_fpr_param.ll into a single file. We will limit that to passing aruments in registers, and will have seperate files for when we spill arguments to memory.

I think a few more tests that need us to disable the altivec attr have landed since your last update. If you rebase you will pick them up.

[ZarkoCA]

1. Addressed second round of comments.
   • Added truncateScalarIntegerArgs function, now we add sext, zext nodes if they are needed and truncate whenever an int size is smaller than the register size.
   • use CCinfo to allocate stack.
   • consolidated calling convention testcases and removed some non-essential tests

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6840

I added a function that will use the flags passed in and work in a more general way than extendArgForPPC64, this way we do the same thing for 32 and 64Bit.

[ZarkoCA]

In D69578#1741001, @sfertile wrote:

A couple high level comments on the tests.

• I like how you extended the 'LowerCall' tests to test both the caller and callee side, as opposed to adding new tests just for the formal argument lowering.

• There are a lot of tests covering quite a few cases. Its good to have thorough coverage. Having separate test cases for things like 1 float vs 3 floats, and 1 i8, vs 4 sext i8s, vs 4 zext i8s might be a little too verbose though. Having a couple calls that mix various extensions of the i8/i16 types i32 and i64 types should give adequate test coverage. Similarly for the fpr tests, a call which mixes doubles and floats should be adequate. I think the most descriptive test are those that are mixing floating and integer/pointer values. For example calling a function with a signature like: (i64 %a, double %d, i1 zeroext %b, float %f, i16 signext %c) shows how we split the i64 for 32-bit codegen, skip gprs for doubls/floats and map the smaller then register sized types into a gpr all in 1 test.

I removed a few of the somewhat redundant ones, added a few more.

• Most of the test on the callee side we don't really care about the instructions in the callee, the liveins is all we are really interested in. I find the allocas and dead stores a little odd. There is no passes to remove them between llc start and where we dump mir so its OK, but I would prefer just having some arbitrary arthritic with the arguments so they are all used to calculate a return value instead, and don't need any checks other then the liveins except in a couple select tests.

I only check for the liveins now tests, and don't check the lines that follow. I've had some trouble getting tests that have some basic arithmetic to work. The .ll files are correct but using Filecheck and what it reads and doesn't read has been giving me a lot of trouble. I can fix them later since I plan to do more work on the callee side but this patch is holding up some other calling convention work and I'd like to get it in before spending more time figuring Filecheck out.

• We probably want a test like the i1 signext/zext/no flags test I posted in one of the comments, and maybe a similar style test for the codegen we expect for say a type that is smaller then register size but not an i1.

• With the reduction in test verbosity (less tests and less CHECK directives) we should be able to combine aix_gpr_param.ll and aix_fpr_param.ll into a single file. We will limit that to passing aruments in registers, and will have seperate files for when we spill arguments to memory.

I think a few more tests that need us to disable the altivec attr have landed since your last update. If you rebase you will pick them up.

[ZarkoCA]

Updates testcases to use all of the parameters in the function definition.

[sfertile]

llvm/include/llvm/ADT/DirectedGraph.h

51

Unrelated change.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6807

Does it need to be a member of PPCTargetLowering? It looks like we are passing in everything we use. If we can reduce its scope to a static in PPCISelLowering.cpp I would prefer that.

6849

Reporting an error for an unsupported construct is fine, but this ends up being very intrusive since we infer altivec support for pretty much any cpu we would target with AIX. We now have to add -mattr=-altivec on every llc invocation targteing AIX which is not very convenient. If we compare it to the other fatal erros we have here:
QPX, softFloat --> Will never be supported for AIX and we should error if those options are enabled.
isVarArg --> will trigger only if lowering a variadic function.
hasAltivec --> is inferred by the backend for any cpu we target, will be true even if we don't have any vector constructs.

The 'hasAltivec' restriction is simply too restrictive. Instead we should only issue an error there is a use of a vector as an argument. CC_AIX does that already I belive so we can omit any further error handling here.

6881

Why the extra CopyFromReg?

[ZarkoCA]

Made truncateScalarIntegers not a member of PPCISelLowering class.
Removed fatal error for altivec, CC_AIX already errors with vector args.
Removed -mattr=-maltivec on tests where I added it, as we no longer error on those.

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6807

Agreed, I was only following the convention of extendArgforPPC64 but there is no reason for it to be a member.

6810

I removed the fatal error and changed back the tests that were failing.

6881

My mistake, removed now.

[jasonliu]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6889

nit: Extra space before "Tail".

6892

nit: Since we have "Set the size that is at least reserved in caller of this function" in the beginning of this paragraph, "reserved for caller" at the end could be removed?

[cebowleratibm]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6789

I'd rather see this switch written:

assert((IsPPC64 || SVT != MVT::i64) && "i64 should have been split for 32-bit codegen.");

switch (SVT) {
...
case MVT::i1:
case MVT::i32:
case MVT::i64:    
  return IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
...  
}

It's easier for me to follow that all ints in PPC64 are G8RC and all ints in PPC32 are GPR and the complexity of the i64 in PPC32 assertion stays out of the switch.

[sfertile]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6886

Since you have allocated the linkage area and the parameter save area CCInfo.getNextStackOffset() will be at least LinkageSize + MinParameterSaveArea, so you can omit taking the max.

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6789

Thanks, agreed this makes it much simpler and also moves the assert to the earliest possible positin.

6886

Thanks, fixed.

6889

Removed, thanks.

6892

Thanks for catching that.

[ZarkoCA]

Moved assert to earliest position in truncateScalarIntger().
Fixed typos.
Removed std::max when calculating MinReservedArea.
Used opt -mem2reg to remove allocas resulting in body of callee functions looking cleaner with fewer unnecessary lines.

[sfertile]

Patch is very close. I've added a few inline comments on the test.

llvm/test/CodeGen/PowerPC/aix_cc_abi.ll

48

very minor nit: indentation should match the following lines.

123

Minor nit: This test and @test_ints_64bit overlap enough we just need 1. I would suggest getting rid of this one, and renaming '@test_ints_64bit` to just @test_ints.

261

Move this test to beside the zero extended i1 case, and add checks for the body that show we end up with a clear instruction before the strore.

Minor nit: dead store. We can store to a global instead.

@global_i1 = global i8 0, align 1

define  void @test_i1(i1 %b)  {
entry:
  %frombool = zext i1 %b to i8
  store i8 %frombool, i8* @global_i1, align 1, !tbaa !2
  ret void
}

560

r3 and r4 used in the 'LWZtoc` instructions should be variables. They are renamable scratch registers in these uses. The same variables should be used in place of hardcoded gprs in the LFS and LFD instructions.

The LI is right in useing the hardcoded r4 and r7 registers since we are setting up ABI specified registers for the call with those instructions.

And the same holds for the equivalent 64-bit test.

580

This is a very good test: Documents how a float argument only shadows 1 gpr for 32-bit codegen despite being passed as a double in fpr1.

[ZarkoCA]

Fixed testcases.

[ZarkoCA]

llvm/test/CodeGen/PowerPC/aix_cc_abi.ll

123

Thanks, removed and renamed.

261

Moved and updated the function to store a global.

560

Fixed, that's a good point, I'm using variables for these now.

[sfertile]

Only a couple minor comments. Otherwise LGTM.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6828

Minor nit: This should be defined just before it use (FuncInfo->setMinReservedArea(MinReservedArea);)

llvm/test/CodeGen/PowerPC/aix_cc_abi.ll

131

Looks good. We should also have the same function but with a zeroext arg attribute and show that we don't end up with a clear instruction in this case. The new function doesn't need to be called.

[ZarkoCA]

Moved variable declarations and definition to just before they are first used.
Added zext i1 testcase and check for absence of clear instruction.

[ZarkoCA]

In D69578#1760258, @sfertile wrote:

Only a couple minor comments. Otherwise LGTM.

Thank you!

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6828

Moved this and the MF definition to just before they are used. MF is moved to line 6850:

MachineFunction &MF = DAG.getMachineFunction();
 CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());

llvm/test/CodeGen/PowerPC/aix_cc_abi.ll

131

Thanks added it below as @test_i1zext()

[ZarkoCA]

Rebase of latest masters (Nov 26, 2019) and fix testcase register typo.

[ZarkoCA]

Fixed testcase typo.

llvm/include/llvm/ADT/DirectedGraph.h

public:
 
   /// Retrieve the target node this edge connects to.
   const NodeType &getTargetNode() const { return TargetNode; }
   NodeType &getTargetNode() {
     return const_cast<NodeType &>(
         static_cast<const DGEdge<NodeType, EdgeType> &>(*this).getTargetNode());
   }
 
-  /// Set the target node this edge connects to.
-  void setTargetNode(const NodeType &N) { TargetNode = N; }
-
 protected:
   // As the default implementation use address comparison for equality.
   bool isEqualTo(const EdgeType &E) const { return this == &E; }
 
   // Cast the 'this' pointer to the derived type and return a reference.
   EdgeType &getDerived() { return *static_cast<EdgeType *>(this); }
   const EdgeType &getDerived() const {
     return *static_cast<const EdgeType *>(this);

llvm/lib/Target/PowerPC/PPCISelLowering.h

SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
                         const SmallVectorImpl<ISD::OutputArg> &Outs,
                         const SmallVectorImpl<SDValue> &OutVals,
                         const SDLoc &dl, SelectionDAG &DAG) const override;
 
     SDValue extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
                               SelectionDAG &DAG, SDValue ArgVal,
                               const SDLoc &dl) const;
 
+    SDValue truncateScalarIntegerArg(ISD::ArgFlagsTy Flags, EVT ValVT,
+                                     SelectionDAG &DAG, SDValue ArgValue,
+                                     MVT LocVT, const SDLoc &dl) const;
+
+    SDValue LowerFormalArguments_AIX(
+        SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
+        const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
+        SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
     SDValue LowerFormalArguments_Darwin(
         SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
         const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
         SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;
     SDValue LowerFormalArguments_64SVR4(
         SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
         const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
         SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const;

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
   NumBytes = (NumBytes + AlignMask) & ~AlignMask;
   return NumBytes;
 }
 
 SDValue PPCTargetLowering::LowerFormalArguments(
     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
+  if (Subtarget.isAIXABI())
+    return LowerFormalArguments_AIX(Chain, CallConv, isVarArg, Ins, dl, DAG,
+                                    InVals);
   if (Subtarget.is64BitELFABI())
     return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
                                        InVals);
-  else if (Subtarget.is32BitELFABI())
+  if (Subtarget.is32BitELFABI())
     return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins, dl, DAG,
                                        InVals);
 
-  // FIXME: We are using this for both AIX and Darwin. We should add appropriate
-  // AIX testing, and rename it appropriately.
   return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins, dl, DAG,
                                      InVals);
 }
 
 SDValue PPCTargetLowering::LowerFormalArguments_32SVR4(
     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {

 
 static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
                    CCValAssign::LocInfo LocInfo, ISD::ArgFlagsTy ArgFlags,
                    CCState &State) {
 
   if (ValVT == MVT::f128)
     report_fatal_error("f128 is unimplemented on AIX.");
 
   if (ArgFlags.isByVal())
     report_fatal_error("Passing structure by value is unimplemented.");
 
   if (ArgFlags.isSRet())
     report_fatal_error("Struct return arguments are unimplemented.");
 
   if (ArgFlags.isNest())
     report_fatal_error("Nest arguments are unimplemented.");
 
case MVT::f64: {
     // f64 reserves 2 GPRs in PPC32 and 1 GPR in PPC64.
     for (unsigned i = 0; i < StoreSize; i += PtrByteSize)
       State.AllocateReg(IsPPC64 ? GPR_64 : GPR_32);
     return false;
   }
   }
 }
 
+static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT,
+                                                    bool IsPPC64) {
+  switch (SVT) {
+  default:
+    report_fatal_error("Unexpected value type for formal argument");
+  case MVT::i1:
+  case MVT::i32:
+    if (!IsPPC64)
+      return &PPC::GPRCRegClass;
+    LLVM_FALLTHROUGH;
+  case MVT::i64:
+    assert(IsPPC64 && "i64 should have been split for 32-bit codegen.");
+    return &PPC::G8RCRegClass;
+  case MVT::f32:
+    return &PPC::F4RCRegClass;
+  case MVT::f64:
+    return &PPC::F8RCRegClass;
+  }
+}
+
+SDValue PPCTargetLowering::truncateScalarIntegerArg(ISD::ArgFlagsTy Flags,
+                                                    EVT ValVT,
+                                                    SelectionDAG &DAG,
+                                                    SDValue ArgValue, MVT LocVT,
+                                                    const SDLoc &dl) const {
+  assert(ValVT.isScalarInteger() && LocVT.isScalarInteger());
+  assert(ValVT.getSizeInBits() < LocVT.getSizeInBits());
+
+  if (Flags.isSExt())
+    ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
+                           DAG.getValueType(ValVT));
+  else if (Flags.isZExt())
+    ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue,
+                           DAG.getValueType(ValVT));
+
+  return DAG.getNode(ISD::TRUNCATE, dl, ValVT, ArgValue);
+}
+
+SDValue PPCTargetLowering::LowerFormalArguments_AIX(
+    SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
+    const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
+    SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
+
+  MachineFunction &MF = DAG.getMachineFunction();
+  PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
+  assert((CallConv == CallingConv::C || CallConv == CallingConv::Cold ||
+          CallConv == CallingConv::Fast) &&
+         "Unexpected calling convention!");
+
+  if (isVarArg)
+    report_fatal_error("This call type is unimplemented on AIX.");
+
+  if (getTargetMachine().Options.GuaranteedTailCallOpt)
+    report_fatal_error("Tail call support is unimplemented on AIX.");
+
+  if (useSoftFloat())
+    report_fatal_error("Soft float support is unimplemented on AIX.");
+
+  const PPCSubtarget &Subtarget =
+      static_cast<const PPCSubtarget &>(DAG.getSubtarget());
+  if (Subtarget.hasQPX())
+    report_fatal_error("QPX support is not supported on AIX.");
+  if (Subtarget.hasAltivec())
+    report_fatal_error("Altivec support is unimplemented on AIX.");
+
+  const bool IsPPC64 = Subtarget.isPPC64();
+  const unsigned PtrByteSize = IsPPC64 ? 8 : 4;
+
+  // Assign locations to all of the incoming arguments.
+  SmallVector<CCValAssign, 16> ArgLocs;
+  CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
+
+  // Reserve space for the linkage area on the stack.
+  const unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
+  // On AIX a minimum of 8 words is saved to the parameter save area.
+  const unsigned MinParameterSaveArea = 8 * PtrByteSize;
+  CCInfo.AllocateStack(LinkageSize + MinParameterSaveArea, PtrByteSize);
+  CCInfo.AnalyzeFormalArguments(Ins, CC_AIX);
+
+  for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
+    CCValAssign &VA = ArgLocs[i];
+    SDValue ArgValue;
+    ISD::ArgFlagsTy Flags = Ins[i].Flags;
+    if (VA.isRegLoc()) {
+      EVT ValVT = VA.getValVT();
+      MVT LocVT = VA.getLocVT();
+      MVT::SimpleValueType SVT = ValVT.getSimpleVT().SimpleTy;
+      unsigned VReg =
+          MF.addLiveIn(VA.getLocReg(), getRegClassForSVT(SVT, IsPPC64));
+      ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
+      if (ValVT.isScalarInteger() &&
+          (ValVT.getSizeInBits() < LocVT.getSizeInBits())) {
+        ArgValue =
+            truncateScalarIntegerArg(Flags, ValVT, DAG, ArgValue, LocVT, dl);
+        ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
+      }
+      InVals.push_back(ArgValue);
+    } else {
+      report_fatal_error("Handling of formal arguments on the stack is "
+                         "unimplemented!");
+    }
+  }
+
+  // Area that is at least reserved in the caller of this function.
+  unsigned MinReservedArea =
+      std::max(CCInfo.getNextStackOffset(), LinkageSize + MinParameterSaveArea);
+
+  // Set the size that is at least reserved in caller of this function.  Tail
+  // call optimized function's reserved stack space needs to be aligned so
+  // that taking the difference between two stack areas will result in an
+  // aligned stack. reserved for caller
+  MinReservedArea =
+      EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
+  FuncInfo->setMinReservedArea(MinReservedArea);
+
+  return Chain;
+}
+
 SDValue PPCTargetLowering::LowerCall_AIX(
     SDValue Chain, SDValue Callee, CallingConv::ID CallConv, bool isVarArg,
     bool isTailCall, bool isPatchPoint,
     const SmallVectorImpl<ISD::OutputArg> &Outs,
     const SmallVectorImpl<SDValue> &OutVals,
     const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &dl,
     SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals,
     ImmutableCallSite CS) const {
 
   assert((CallConv == CallingConv::C ||
           CallConv == CallingConv::Cold ||
           CallConv == CallingConv::Fast) && "Unexpected calling convention!");
 
   if (isVarArg || isPatchPoint)
     report_fatal_error("This call type is unimplemented on AIX.");
 
   if (!isFunctionGlobalAddress(Callee) && !isa<ExternalSymbolSDNode>(Callee))
     report_fatal_error("Handling of indirect call is unimplemented!");
 
   const PPCSubtarget& Subtarget =
       static_cast<const PPCSubtarget&>(DAG.getSubtarget());
   if (Subtarget.hasQPX())
     report_fatal_error("QPX is not supported on AIX.");
   if (Subtarget.hasAltivec())
     report_fatal_error("Altivec support is unimplemented on AIX.");
 
   MachineFunction &MF = DAG.getMachineFunction();
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(CallConv, isVarArg, MF, ArgLocs, *DAG.getContext());
 
   // Reserve space for the linkage save area (LSA) on the stack.
   // In both PPC32 and PPC64 there are 6 reserved slots in the LSA:
   //   [SP][CR][LR][2 x reserved][TOC].

llvm/test/CodeGen/PowerPC/aix-lower-block-address.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32LARGE-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64LARGE-MIR %s
 
 define void @foo() {
 entry:
   %tmp = alloca i64
   br label %__here
 

llvm/test/CodeGen/PowerPC/aix-lower-constant-pool-index.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32LARGE-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64LARGE-MIR %s
 
 define float @test_float() {
 entry:
   ret float 5.500000e+00
 }
 

llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=32LARGE-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64SMALL-MIR %s
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large -stop-after=machine-cp < %s | FileCheck \
 ; RUN: --check-prefix=64LARGE-MIR %s
 
   define i32 @jump_table(i32 %a) {
   entry:
     switch i32 %a, label %sw.epilog [
       i32 1, label %sw.bb
       i32 2, label %sw.bb1

llvm/test/CodeGen/PowerPC/aix-return55.ll

-; RUN: llc -mcpu=pwr9 -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mcpu=pwr9 -mattr=-altivec -mtriple=powerpc-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s
 
 
 define dso_local signext i32 @foo() {
 entry:
   ret i32 55
 ; CHECK-LABEL: .foo:
 ; CHECK: li 3, 55
 ; CHECK: blr
 }
 

llvm/test/CodeGen/PowerPC/aix-space.ll

-; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
+; RUN: llc -verify-machineinstrs -O0 -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff < %s | FileCheck %s
 
 @a = common global double 0.000000e+00, align 8
 
 ; Get some constants into the constant pool that need spacing for alignment
 define void @e() {
 entry:
   %0 = load double, double* @a, align 8
   %mul = fmul double 1.500000e+00, %0
   store double %mul, double* @a, align 8
   %mul1 = fmul double 0x3F9C71C71C71C71C, %0
   store double %mul1, double* @a, align 8
   ret void
 }
 
 ; CHECK:      .space 4
 ; CHECK-NOT:  .zero

llvm/test/CodeGen/PowerPC/aix_cc_abi.ll

+; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
+; RUN: FileCheck --check-prefixes=CHECK,32BIT %s
+
+; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp -verify-machineinstrs < %s | \
+; RUN: FileCheck --check-prefixes=CHECK,64BIT %s
+
+define void @call_test_chars() {
+entry:
+  call void @test_chars(i8 signext 97, i8 signext 97, i8 signext 97, i8 signext 97)
+  ret void
+}
+
+; CHECK-LABEL: name: call_test_chars
+
+; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
+; 32BIT: $r3 = LI 97
+; 32BIT: $r4 = LI 97
+; 32BIT: $r5 = LI 97
+; 32BIT: $r6 = LI 97
+; 32BIT: BL_NOP <mcsymbol .test_chars>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit $r2, implicit-def $r1
+; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
+
+; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT: $x3 = LI8 97
+; 64BIT: $x4 = LI8 97
+; 64BIT: $x5 = LI8 97
+; 64BIT: $x6 = LI8 97
+; 64BIT: BL8_NOP <mcsymbol .test_chars>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1
+; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+define void @test_chars(i8 signext %c1, i8 signext %c2, i8 signext %c3, i8 signext %c4) {
+entry:
+  %c1.addr = alloca i8, align 1
+  %c2.addr = alloca i8, align 1
+  %c3.addr = alloca i8, align 1
+  %c4.addr = alloca i8, align 1
+  store i8 %c1, i8* %c1.addr, align 1
+  store i8 %c2, i8* %c2.addr, align 1
+  store i8 %c3, i8* %c3.addr, align 1
+  store i8 %c4, i8* %c4.addr, align 1
+  ret void
+}
+
+; CHECK-LABEL: name: test_chars
+
+; 32BIT:       liveins:
+; 32BIT-NEXT:  - { reg: '$r3', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r4', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r5', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r6', virtual-reg: '' }
+; 32BIT:       body:
+; 32BIT-NEXT:    bb.0.entry:
+; 32BIT-NEXT:      liveins: $r3, $r4, $r5, $r6
+ 
+; 64BIT:       liveins:
+; 64BIT-NEXT:  - { reg: '$x3', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x4', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x5', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x6', virtual-reg: '' }
+; 64BIT:       body:
+; 64BIT-NEXT:    bb.0.entry:
+; 64BIT-NEXT:      liveins: $x3, $x4, $x5, $x6
+
+define void @call_test_chars_mix() {
+entry:
+  call void @test_chars_mix(i8 signext 97, i8 zeroext -31, i8 zeroext 97, i8 signext -31)
+  ret void
+}
+
+; CHECK-LABEL: name: call_test_chars_mix
+
+; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
+; 32BIT: $r3 = LI 97
+; 32BIT: $r4 = LI 225
+; 32BIT: $r5 = LI 97
+; 32BIT: $r6 = LI -31
+; 32BIT: BL_NOP <mcsymbol .test_chars_mix>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit $r2, implicit-def $r1
+; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
+
+; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT: $x3 = LI8 97
+; 64BIT: $x4 = LI8 225
+; 64BIT: $x5 = LI8 97
+; 64BIT: $x6 = LI8 -31
+; 64BIT: BL8_NOP <mcsymbol .test_chars_mix>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1
+; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+define void @test_chars_mix(i8 signext %c1, i8 zeroext %c2, i8 zeroext %c3, i8 signext %c4) {
+entry:
+  %c1.addr = alloca i8, align 1
+  %c2.addr = alloca i8, align 1
+  %c3.addr = alloca i8, align 1
+  %c4.addr = alloca i8, align 1
+  store i8 %c1, i8* %c1.addr, align 1
+  store i8 %c2, i8* %c2.addr, align 1
+  store i8 %c3, i8* %c3.addr, align 1
+  store i8 %c4, i8* %c4.addr, align 1
+  ret void
+}
+
+; CHECK-LABEL: name: test_chars_mix
+
+; 32BIT:       liveins:
+; 32BIT-NEXT:  - { reg: '$r3', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r4', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r5', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r6', virtual-reg: '' }
+; 32BIT:       body:
+; 32BIT-NEXT:    bb.0.entry:
+; 32BIT-NEXT:      liveins: $r3, $r4, $r5, $r6
+ 
+; 64BIT:       liveins:
+; 64BIT-NEXT:  - { reg: '$x3', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x4', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x5', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x6', virtual-reg: '' }
+; 64BIT:       body:
+; 64BIT-NEXT:    bb.0.entry:
+; 64BIT-NEXT:      liveins: $x3, $x4, $x5, $x6
+
+
+define void @call_test_ints() {
+entry:
+  call void @test_ints(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8)
+  ret void
+}
+
+; CHECK-LABEL: name: call_test_ints
+
+; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
+; 32BIT: $r3 = LI 1
+; 32BIT: $r4 = LI 2
+; 32BIT: $r5 = LI 3
+; 32BIT: $r6 = LI 4
+; 32BIT: $r7 = LI 5
+; 32BIT: $r8 = LI 6
+; 32BIT: $r9 = LI 7
+; 32BIT: $r10 = LI 8
+; 32BIT: BL_NOP <mcsymbol .test_ints>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $r2, implicit-def $r1
+; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
+
+; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT: $x3 = LI8 1
+; 64BIT: $x4 = LI8 2
+; 64BIT: $x5 = LI8 3
+; 64BIT: $x6 = LI8 4
+; 64BIT: $x7 = LI8 5
+; 64BIT: $x8 = LI8 6
+; 64BIT: $x9 = LI8 7
+; 64BIT: $x10 = LI8 8
+; 64BIT: BL8_NOP <mcsymbol .test_ints>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $x2, implicit-def $r1
+; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+define void @test_ints(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) {
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca i32, align 4
+  %c.addr = alloca i32, align 4
+  %d.addr = alloca i32, align 4
+  %e.addr = alloca i32, align 4
+  %f.addr = alloca i32, align 4
+  %g.addr = alloca i32, align 4
+  %h.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  store i32 %b, i32* %b.addr, align 4
+  store i32 %c, i32* %c.addr, align 4
+  store i32 %d, i32* %d.addr, align 4
+  store i32 %e, i32* %e.addr, align 4
+  store i32 %f, i32* %f.addr, align 4
+  store i32 %g, i32* %g.addr, align 4
+  store i32 %h, i32* %h.addr, align 4
+  %0 = load i32, i32* %a.addr, align 4
+  %1 = load i32, i32* %b.addr, align 4
+  %add = add nsw i32 %0, %1
+  %2 = load i32, i32* %c.addr, align 4
+  %add1 = add nsw i32 %add, %2
+  %3 = load i32, i32* %d.addr, align 4
+  %add2 = add nsw i32 %add1, %3
+  %4 = load i32, i32* %e.addr, align 4
+  %add3 = add nsw i32 %add2, %4
+  %5 = load i32, i32* %h.addr, align 4
+  %add4 = add nsw i32 %add3, %5
+  store i32 %add4, i32* %h.addr, align 4
+  ret void
+}
+
+; CHECK-LABEL: name: test_ints
+
+; 32BIT:       liveins:
+; 32BIT-NEXT:  - { reg: '$r3', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r4', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r5', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r6', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r7', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r8', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r9', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r10', virtual-reg: '' }
+; 32BIT:       body:             |
+; 32BIT-NEXT:    bb.0.entry:
+; 32BIT-NEXT:      liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10
+
+; 64BIT:       liveins:
+; 64BIT-NEXT:  - { reg: '$x3', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x4', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x5', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x6', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x7', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x8', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x9', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x10', virtual-reg: '' }
+; 64BIT:       body:             |
+; 64BIT-NEXT:    bb.0.entry:
+; 64BIT-NEXT:      liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10
+
+define void @call_test_ints_64bit() {
+entry:
+  call void @test_ints_64bit(i32 signext 1, i32 zeroext 1, i32 zeroext 2147483648, i32 signext -2147483648, i32 signext 1, i32 signext 1, i32 signext 1, i32 signext 1)
+  ret void
+}
+
+; CHECK-LABEL: name: call_test_ints_64bit
+
+; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT: renamable $x3 = LI8 1
+; 64BIT: renamable $x5 = RLDICR killed renamable $x3, 31, 32
+; 64BIT: $x3 = LI8 1
+; 64BIT: $x4 = LI8 1
+; 64BIT: $x6 = LIS8 32768
+; 64BIT: $x7 = LI8 1
+; 64BIT: $x8 = LI8 1
+; 64BIT: $x9 = LI8 1
+; 64BIT: $x10 = LI8 1
+; 64BIT: BL8_NOP <mcsymbol .test_ints_64bit>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $x2, implicit-def $r1
+; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+define void @test_ints_64bit(i32 signext %a, i32 zeroext %b, i32 zeroext %c, i32 signext %d, i32 signext %e, i32 signext %f, i32 signext %g, i32 signext %h) {
+entry:
+  %a.addr = alloca i32, align 4
+  %b.addr = alloca i32, align 4
+  %c.addr = alloca i32, align 4
+  %d.addr = alloca i32, align 4
+  %e.addr = alloca i32, align 4
+  %f.addr = alloca i32, align 4
+  %g.addr = alloca i32, align 4
+  %h.addr = alloca i32, align 4
+  store i32 %a, i32* %a.addr, align 4
+  store i32 %b, i32* %b.addr, align 4
+  store i32 %c, i32* %c.addr, align 4
+  store i32 %d, i32* %d.addr, align 4
+  store i32 %e, i32* %e.addr, align 4
+  store i32 %f, i32* %f.addr, align 4
+  store i32 %g, i32* %g.addr, align 4
+  store i32 %h, i32* %h.addr, align 4
+  %0 = load i32, i32* %a.addr, align 4
+  %1 = load i32, i32* %b.addr, align 4
+  %add = add nsw i32 %0, %1
+  %2 = load i32, i32* %c.addr, align 4
+  %add1 = add nsw i32 %add, %2
+  %3 = load i32, i32* %d.addr, align 4
+  %add2 = add nsw i32 %add1, %3
+  %4 = load i32, i32* %e.addr, align 4
+  %add3 = add nsw i32 %add2, %4
+  %5 = load i32, i32* %h.addr, align 4
+  %add4 = add nsw i32 %add3, %5
+  store i32 %add4, i32* %h.addr, align 4
+  ret void
+}
+
+; CHECK-LABEL: name: test_ints_64bit
+
+; 64BIT:       liveins:
+; 64BIT-NEXT:  - { reg: '$x3', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x4', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x5', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x6', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x7', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x8', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x9', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x10', virtual-reg: '' }
+; 64BIT:       body:             |
+; 64BIT-NEXT:    bb.0.entry:
+; 64BIT-NEXT:      liveins: $x3, $x4, $x5, $x6, $x7, $x8, $x9, $x10
+
+define void @call_test_i1() {
+entry:
+  call void @test_i1(i1 1)
+  ret void
+}
+
+; CHECK-LABEL: name: call_test_i1
+
+; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
+; 32BIT: $r3 = LI 1
+; 32BIT: BL_NOP <mcsymbol .test_i1>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit $r2, implicit-def $r1
+; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
+
+; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT: $x3 = LI8 1
+; 64BIT: BL8_NOP <mcsymbol .test_i1>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1
+; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+define void @test_i1(i1 %a) {
+entry:
+  %a.addr = alloca i1, align 1
+  store i1 %a, i1* %a.addr, align 1
+  ret void
+}
+
+; CHECK-LABEL: name: test_i1
+
+; 32BIT:       liveins:
+; 32BIT-NEXT:  - { reg: '$r3', virtual-reg: '' }
+; 32BIT:       body:             |
+; 32BIT-NEXT:    bb.0.entry:
+; 32BIT-NEXT:      liveins: $r3
+
+; 64BIT:       liveins:
+; 64BIT-NEXT:  - { reg: '$x3', virtual-reg: '' }
+; 64BIT:       body:             |
+; 64BIT-NEXT:    bb.0.entry:
+; 64BIT-NEXT:      liveins: $x3
+
+define void @call_test_i64() {
+entry:
+  call void @test_i64(i64 1, i64 2, i64 3, i64 4)
+  ret void
+}
+
+; CHECK-LABEL: name: call_test_i64
+
+; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
+; 32BIT: $r3 = LI 0
+; 32BIT: $r4 = LI 1
+; 32BIT: $r5 = LI 0
+; 32BIT: $r6 = LI 2
+; 32BIT: $r7 = LI 0
+; 32BIT: $r8 = LI 3
+; 32BIT: $r9 = LI 0
+; 32BIT: $r10 = LI 4
+; 32BIT: BL_NOP <mcsymbol .test_i64>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $r2, implicit-def $r1
+; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
+
+; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT: $x3 = LI8 1
+; 64BIT: $x4 = LI8 2
+; 64BIT: $x5 = LI8 3
+; 64BIT: $x6 = LI8 4
+; 64BIT: BL8_NOP <mcsymbol .test_i64>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1
+; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+define void @test_i64(i64 %a, i64 %b, i64 %c, i64 %d) {
+entry:
+  %a.addr = alloca i64, align 8
+  %b.addr = alloca i64, align 8
+  %c.addr = alloca i64, align 8
+  %d.addr = alloca i64, align 8
+  store i64 %a, i64* %a.addr, align 8
+  store i64 %b, i64* %b.addr, align 8
+  store i64 %c, i64* %c.addr, align 8
+  store i64 %d, i64* %d.addr, align 8
+  %0 = load i64, i64* %a.addr, align 8
+  %1 = load i64, i64* %b.addr, align 8
+  %add = add nsw i64 %0, %1
+  %2 = load i64, i64* %c.addr, align 8
+  %add1 = add nsw i64 %add, %2
+  %3 = load i64, i64* %d.addr, align 8
+  %add2 = add nsw i64 %add1, %3
+  store i64 %add2, i64* %d.addr, align 8
+  ret void
+}
+
+; CHECK-LABEL: name: test_i64
+
+; 32BIT:       liveins:
+; 32BIT-NEXT:  - { reg: '$r3', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r4', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r5', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r6', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r7', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r8', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r9', virtual-reg: '' }
+; 32BIT-NEXT:  - { reg: '$r10', virtual-reg: '' }
+; 32BIT:       body:             |
+; 32BIT-NEXT:    bb.0.entry:
+; 32BIT-NEXT:      liveins: $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10
+
+; 64BIT:       liveins:
+; 64BIT-NEXT:  - { reg: '$x3', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x4', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x5', virtual-reg: '' }
+; 64BIT-NEXT:  - { reg: '$x6', virtual-reg: '' }
+; 64BIT:       body:             |
+; 64BIT-NEXT:    bb.0.entry:
+; 64BIT-NEXT:      liveins: $x3, $x4, $x5, $x6
+
+define void @call_test_int_ptr() {
+entry:
+  %b = alloca i32, align 4
+  store i32 0, i32* %b, align 4
+  call void @test_int_ptr(i32* %b)
+  ret void
+}
+
+; CHECK-LABEL: name: call_test_int_ptr
+
+; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
+; 32BIT: renamable $r3 = ADDI %stack.0.b, 0
+; 32BIT: BL_NOP <mcsymbol .test_int_ptr>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
+; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
+
+; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT: renamable $x3 = ADDI8 %stack.0.b, 0
+; 64BIT: BL8_NOP <mcsymbol .test_int_ptr>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
+; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+define void @test_int_ptr(i32* %a) {
+entry:
+  %a.addr = alloca i32*, align 8
+  store i32* %a, i32** %a.addr, align 8
+  ret void
+}
+
+; CHECK-LABEL: name: test_int_ptr
+
+; 32BIT:       liveins:
+; 32BIT-NEXT:  - { reg: '$r3', virtual-reg: '' }
+; 32BIT:       body:             |
+; 32BIT-NEXT:    bb.0.entry:
+; 32BIT-NEXT:      liveins: $r3
+; 32BIT:           STW killed renamable $r3, 0, %stack.0.a.addr :: (store 4 into %ir.a.addr, align 8)
+
+; 64BIT:       liveins:
+; 64BIT-NEXT:  - { reg: '$x3', virtual-reg: '' }
+; 64BIT:       body:             |
+; 64BIT-NEXT:    bb.0.entry:
+; 64BIT-NEXT:      liveins: $x3
+; 64BIT:           STD killed renamable $x3, 0, %stack.0.a.addr :: (store 8 into %ir.a.addr)
+
+; Function Attrs: noinline nounwind optnone
+define i32 @caller(i32 %i)  {
+entry:
+  %i.addr = alloca i32, align 4
+  %b = alloca i8, align 1
+  store i32 %i, i32* %i.addr, align 4
+  %0 = load i32, i32* %i.addr, align 4
+  %cmp = icmp ne i32 %0, 0
+  %frombool = zext i1 %cmp to i8
+  store i8 %frombool, i8* %b, align 1
+  %1 = load i8, i8* %b, align 1
+  %tobool = trunc i8 %1 to i1
+  %call = call i32 @call_test_bool(i1 zeroext %tobool)
+  ret i32 %call
+}
+
+declare i32 @call_test_bool(i1 zeroext)
+  
+; CHECK-LABEL: name:            caller
+
+; 32BIT:       liveins:
+; 32BIT-NEXT:  - { reg: '$r3', virtual-reg: '' }
+; 32BIT:      body:             |
+; 32BIT-NEXT:   bb.0.entry:
+; 32BIT:         liveins: $r3
+; 32BIT:         ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
+; 32BIT:         BL_NOP <mcsymbol .call_test_bool>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1, implicit-def $r3
+; 32BIT:         ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
+
+; 64BIT:       liveins:
+; 64BIT-NEXT:  - { reg: '$x3', virtual-reg: '' }
+; 64BIT:      body:             |
+; 64BIT-NEXT:   bb.0.entry:
+; 64BIT-NEXT:    liveins: $x3
+; 64BIT:         ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT:          BL8_NOP <mcsymbol .call_test_bool>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1, implicit-def $x3
+; 64BIT:         ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+@f1 = global float 0.000000e+00, align 4
+@d1 = global double 0.000000e+00, align 8
+
+define void @call_test_floats() {
+entry:
+  %0 = load float, float* @f1, align 4
+  call void @test_floats(float %0, float %0, float %0)
+  ret void
+}
+
+; CHECK-LABEL: name: call_test_floats{{.*}}
+
+; 32BIT:      renamable $r3 = LWZtoc @f1, $r2 :: (load 4 from got)
+; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r3 :: (dereferenceable load 4 from @f1)
+; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
+; 32BIT-NEXT: $f2 = COPY renamable $f1
+; 32BIT-NEXT: $f3 = COPY renamable $f1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_floats>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
+
+; 64BIT:      renamable $x3 = LDtoc @f1, $x2 :: (load 8 from got)
+; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x3 :: (dereferenceable load 4 from @f1)
+; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT-NEXT: $f2 = COPY renamable $f1
+; 64BIT-NEXT: $f3 = COPY renamable $f1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_floats>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+define void @test_floats(float %f1, float %f2, float %f3) {
+entry:
+  %f1.addr = alloca float, align 4
+  %f2.addr = alloca float, align 4
+  %f3.addr = alloca float, align 4
+  store float %f1, float* %f1.addr, align 4
+  store float %f2, float* %f2.addr, align 4
+  store float %f3, float* %f3.addr, align 4
+  ret void
+}
+
+; CHECK-LABEL: name: test_floats{{.*}}
+
+; CHECK:      liveins:
+; CHECK-NEXT: - { reg: '$f1', virtual-reg: '' }
+; CHECK-NEXT: - { reg: '$f2', virtual-reg: '' }
+; CHECK-NEXT: - { reg: '$f3', virtual-reg: '' }
+; CHECK:      body:             |
+; CHECK-NEXT:   bb.0.entry:
+; CHECK-NEXT:     liveins: $f1, $f2, $f3
+
+define void @call_test_fpr_max() {
+entry:
+  %0 = load double, double* @d1, align 8
+  call void @test_fpr_max(double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0)
+  ret void
+}
+
+; CHECK-LABEL: name: call_test_fpr_max{{.*}}
+
+; 32BIT:      renamable $r3 = LWZtoc @d1, $r2 :: (load 4 from got)
+; 32BIT-NEXT: renamable $f1 = LFD 0, killed renamable $r3 :: (dereferenceable load 8 from @d1)
+; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
+; 32BIT-NEXT: $f2 = COPY renamable $f1
+; 32BIT-NEXT: $f3 = COPY renamable $f1
+; 32BIT-NEXT: $f4 = COPY renamable $f1
+; 32BIT-NEXT: $f5 = COPY renamable $f1
+; 32BIT-NEXT: $f6 = COPY renamable $f1
+; 32BIT-NEXT: $f7 = COPY renamable $f1
+; 32BIT-NEXT: $f8 = COPY renamable $f1
+; 32BIT-NEXT: $f9 = COPY renamable $f1
+; 32BIT-NEXT: $f10 = COPY renamable $f1
+; 32BIT-NEXT: $f11 = COPY renamable $f1
+; 32BIT-NEXT: $f12 = COPY renamable $f1
+; 32BIT-NEXT: $f13 = COPY renamable $f1
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_fpr_max>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
+
+; 64BIT:      renamable $x3 = LDtoc @d1, $x2 :: (load 8 from got)
+; 64BIT-NEXT: renamable $f1 = LFD 0, killed renamable $x3 :: (dereferenceable load 8 from @d1)
+; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT-NEXT: $f2 = COPY renamable $f1
+; 64BIT-NEXT: $f3 = COPY renamable $f1
+; 64BIT-NEXT: $f4 = COPY renamable $f1
+; 64BIT-NEXT: $f5 = COPY renamable $f1
+; 64BIT-NEXT: $f6 = COPY renamable $f1
+; 64BIT-NEXT: $f7 = COPY renamable $f1
+; 64BIT-NEXT: $f8 = COPY renamable $f1
+; 64BIT-NEXT: $f9 = COPY renamable $f1
+; 64BIT-NEXT: $f10 = COPY renamable $f1
+; 64BIT-NEXT: $f11 = COPY renamable $f1
+; 64BIT-NEXT: $f12 = COPY renamable $f1
+; 64BIT-NEXT: $f13 = COPY renamable $f1
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_fpr_max>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+define void @test_fpr_max(double %d1, double %d2, double %d3, double %d4, double %d5, double %d6, double %d7, double %d8, double %d9, double %d10, double %d11, double %d12, double %d13) {
+entry:
+  %d1.addr = alloca double, align 8
+  %d2.addr = alloca double, align 8
+  %d3.addr = alloca double, align 8
+  %d4.addr = alloca double, align 8
+  %d5.addr = alloca double, align 8
+  %d6.addr = alloca double, align 8
+  %d7.addr = alloca double, align 8
+  %d8.addr = alloca double, align 8
+  %d9.addr = alloca double, align 8
+  %d10.addr = alloca double, align 8
+  %d11.addr = alloca double, align 8
+  %d12.addr = alloca double, align 8
+  %d13.addr = alloca double, align 8
+  store double %d1, double* %d1.addr, align 8
+  store double %d2, double* %d2.addr, align 8
+  store double %d3, double* %d3.addr, align 8
+  store double %d4, double* %d4.addr, align 8
+  store double %d5, double* %d5.addr, align 8
+  store double %d6, double* %d6.addr, align 8
+  store double %d7, double* %d7.addr, align 8
+  store double %d8, double* %d8.addr, align 8
+  store double %d9, double* %d9.addr, align 8
+  store double %d10, double* %d10.addr, align 8
+  store double %d11, double* %d11.addr, align 8
+  store double %d12, double* %d12.addr, align 8
+  store double %d13, double* %d13.addr, align 8
+  %0 = load double, double* %d1.addr, align 8
+  %1 = load double, double* %d2.addr, align 8
+  %add = fadd double %0, %1
+  %2 = load double, double* %d3.addr, align 8
+  %add1 = fadd double %add, %2
+  %3 = load double, double* %d4.addr, align 8
+  %add2 = fadd double %add1, %3
+  %4 = load double, double* %d5.addr, align 8
+  %add3 = fadd double %add2, %4
+  %5 = load double, double* %d6.addr, align 8
+  %add4 = fadd double %add3, %5
+  %6 = load double, double* %d7.addr, align 8
+  %add5 = fadd double %add4, %6
+  %7 = load double, double* %d8.addr, align 8
+  %add6 = fadd double %add5, %7
+  %8 = load double, double* %d9.addr, align 8
+  %add7 = fadd double %add6, %8
+  %9 = load double, double* %d10.addr, align 8
+  %add8 = fadd double %add7, %9
+  %10 = load double, double* %d11.addr, align 8
+  %add9 = fadd double %add8, %10
+  %11 = load double, double* %d12.addr, align 8
+  %add10 = fadd double %add9, %11
+  %12 = load double, double* %d13.addr, align 8
+  %add11 = fadd double %add10, %12
+  store double %add11, double* %d1.addr, align 8
+  ret void
+}
+
+; CHECK-LABEL: name: test_fpr_max{{.*}}
+
+; CHECK:      liveins:
+; CHECK-NEXT: - { reg: '$f1', virtual-reg: '' }
+; CHECK-NEXT: - { reg: '$f2', virtual-reg: '' }
+; CHECK-NEXT: - { reg: '$f3', virtual-reg: '' }
+; CHECK-NEXT: - { reg: '$f4', virtual-reg: '' }
+; CHECK-NEXT: - { reg: '$f5', virtual-reg: '' }
+; CHECK-NEXT: - { reg: '$f6', virtual-reg: '' }
+; CHECK-NEXT: - { reg: '$f7', virtual-reg: '' }
+; CHECK-NEXT: - { reg: '$f8', virtual-reg: '' }
+; CHECK-NEXT: - { reg: '$f9', virtual-reg: '' }
+; CHECK-NEXT: - { reg: '$f10', virtual-reg: '' }
+; CHECK-NEXT: - { reg: '$f11', virtual-reg: '' }
+; CHECK-NEXT: - { reg: '$f12', virtual-reg: '' }
+; CHECK-NEXT: - { reg: '$f13', virtual-reg: '' }
+; CHECK:      body:             |
+; CHECK-NEXT:   bb.0.entry:
+; CHECK-NEXT:     liveins: $f1, $f2, $f3, $f4, $f5, $f6, $f7, $f8, $f9, $f10, $f11, $f12, $f13
+
+define void @call_test_mix() {
+entry:
+  %0 = load float, float* @f1, align 4
+  %1 = load double, double* @d1, align 8
+  call void @test_mix(float %0, i32 1, double %1, i8 signext 97)
+  ret void
+}
+
+; CHECK-LABEL: name: call_test_mix{{.*}}
+
+; 32BIT:      renamable $r3 = LWZtoc @f1, $r2 :: (load 4 from got)
+; 32BIT-NEXT: renamable $r4 = LWZtoc @d1, $r2 :: (load 4 from got)
+; 32BIT-NEXT: renamable $f1 = LFS 0, killed renamable $r3 :: (dereferenceable load 4 from @f1)
+; 32BIT-NEXT: renamable $f2 = LFD 0, killed renamable $r4 :: (dereferenceable load 8 from @d1)
+; 32BIT-NEXT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
+; 32BIT-NEXT: $r4 = LI 1
+; 32BIT-NEXT: $r7 = LI 97
+; 32BIT-NEXT: BL_NOP <mcsymbol .test_mix>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $r4, implicit $f2, implicit killed $r7, implicit $r2, implicit-def $r1
+; 32BIT-NEXT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
+
+; 64BIT:      renamable $x3 = LDtoc @f1, $x2 :: (load 8 from got)
+; 64BIT-NEXT: renamable $x4 = LDtoc @d1, $x2 :: (load 8 from got)
+; 64BIT-NEXT: renamable $f1 = LFS 0, killed renamable $x3 :: (dereferenceable load 4 from @f1)
+; 64BIT-NEXT: renamable $f2 = LFD 0, killed renamable $x4 :: (dereferenceable load 8 from @d1)
+; 64BIT-NEXT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
+; 64BIT-NEXT: $x4 = LI8 1
+; 64BIT-NEXT: $x6 = LI8 97
+; 64BIT-NEXT: BL8_NOP <mcsymbol .test_mix>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $x4, implicit $f2, implicit killed $x6, implicit $x2, implicit-def $r1
+; 64BIT-NEXT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
+
+define void @test_mix(float %f, i32 signext %i, double %d, i8 signext %c) {
+entry:
+  %f.addr = alloca float, align 4
+  %i.addr = alloca i32, align 4
+  %d.addr = alloca double, align 8
+  %c.addr = alloca i8, align 1
+  store float %f, float* %f.addr, align 4
+  store i32 %i, i32* %i.addr, align 4
+  store double %d, double* %d.addr, align 8
+  store i8 %c, i8* %c.addr, align 1
+  ret void
+}
+
+; CHECK-LABEL: name: test_mix{{.*}}
+
+; 32BIT:      liveins:
+; 32BIT-NEXT: - { reg: '$f1', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r4', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$f2', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r7', virtual-reg: '' }
+; 32BIT:      body:             |
+; 32BIT-NEXT:   bb.0.entry:
+; 32BIT-NEXT:     liveins: $f1, $f2, $r4, $r7
+
+; 64BIT:      liveins:
+; 64BIT-NEXT: - { reg: '$f1', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x4', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$f2', virtual-reg: '' }
+; 64BIT-NEXT: - { reg: '$x6', virtual-reg: '' }
+; 64BIT:      body:             |
+; 64BIT-NEXT:   bb.0.entry:
+; 64BIT-NEXT:     liveins: $f1, $f2, $x4, $x6
+
+
+  define void @callee_mixed_ints(i32 %a, i8 signext %b, i32 %c, i16 signext %d, i64 %e) {
+  entry:
+    %a.addr = alloca i32, align 4
+    %b.addr = alloca i8, align 1
+    %c.addr = alloca i32, align 4
+    %d.addr = alloca i16, align 2
+    %e.addr = alloca i64, align 8
+    store i32 %a, i32* %a.addr, align 4
+    store i8 %b, i8* %b.addr, align 1
+    store i32 %c, i32* %c.addr, align 4
+    store i16 %d, i16* %d.addr, align 2
+    store i64 %e, i64* %e.addr, align 8
+    %0 = load i32, i32* %a.addr, align 4
+    %1 = load i8, i8* %b.addr, align 1
+    %conv = sext i8 %1 to i32
+    %add = add nsw i32 %0, %conv
+    %2 = load i32, i32* %c.addr, align 4
+    %add1 = add nsw i32 %add, %2
+    %3 = load i16, i16* %d.addr, align 2
+    %conv2 = sext i16 %3 to i32
+    %add3 = add nsw i32 %add1, %conv2
+    %conv4 = sext i32 %add3 to i64
+    %4 = load i64, i64* %e.addr, align 8
+    %add5 = add nsw i64 %conv4, %4
+    store i64 %add5, i64* %e.addr, align 8
+    ret void
+  }
+
+; CHECK-LABEL: name:  callee_mixed_ints
+
+; 32BIT:      liveins:
+; 32BIT-NEXT: - { reg: '$r3', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r4', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r5', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r6', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r7', virtual-reg: '' }
+; 32BIT-NEXT: - { reg: '$r8', virtual-reg: '' }
+; 32BIT:      body:             |
+; 32BIT-NEXT:  bb.0.entry:
+; 32BIT-NEXT:   liveins: $r3, $r4, $r5, $r6, $r7, $r8
+  

llvm/test/CodeGen/PowerPC/aix_fpr_param.ll

-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp < %s | \
-; RUN: FileCheck --check-prefix=32BIT %s
-
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp < %s | \
-; RUN: FileCheck --check-prefix=64BIT %s
-
-@f1 = global float 0.000000e+00, align 4
-@d1 = global double 0.000000e+00, align 8
-
-define void @call_test_float() {
-entry:
-; 32BIT: renamable $r3 = LWZtoc @f1, $r2 :: (load 4 from got)
-; 32BIT: renamable $f1 = LFS 0, killed renamable $r3 :: (dereferenceable load 4 from @f1)
-; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT: BL_NOP <mcsymbol .test_float>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $r2, implicit-def $r1
-; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
-
-; 64BIT: renamable $x3 = LDtoc @f1, $x2 :: (load 8 from got)
-; 64BIT: renamable $f1 = LFS 0, killed renamable $x3 :: (dereferenceable load 4 from @f1)
-; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: BL8_NOP <mcsymbol .test_float>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $x2, implicit-def $r1
-; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
-
-  %0 = load float, float* @f1, align 4
-  call void @test_float(float %0)
-  ret void
-}
-
-declare void @test_float(float)
-
-define void @call_test_floats() {
-entry:
-; 32BIT: renamable $r3 = LWZtoc @f1, $r2 :: (load 4 from got)
-; 32BIT: renamable $f1 = LFS 0, killed renamable $r3 :: (dereferenceable load 4 from @f1)
-; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT: $f2 = COPY renamable $f1
-; 32BIT: $f3 = COPY renamable $f1
-; 32BIT: BL_NOP <mcsymbol .test_floats>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit $r2, implicit-def $r1
-; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
-
-; 64BIT: renamable $x3 = LDtoc @f1, $x2 :: (load 8 from got)
-; 64BIT: renamable $f1 = LFS 0, killed renamable $x3 :: (dereferenceable load 4 from @f1)
-; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: $f2 = COPY renamable $f1
-; 64BIT: $f3 = COPY renamable $f1
-; 64BIT: BL8_NOP <mcsymbol .test_floats>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit $x2, implicit-def $r1
-; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
-
-  %0 = load float, float* @f1, align 4
-  call void @test_floats(float %0, float %0, float %0)
-  ret void
-}
-
-declare void @test_floats(float, float, float)
-
-define void @call_test_double() {
-entry:
-; 32BIT: renamable $r3 = LWZtoc @d1, $r2 :: (load 4 from got)
-; 32BIT: renamable $f1 = LFD 0, killed renamable $r3 :: (dereferenceable load 8 from @d1)
-; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT: BL_NOP <mcsymbol .test_double>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $r2, implicit-def $r1
-; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
-
-; 64BIT: renamable $x3 = LDtoc @d1, $x2 :: (load 8 from got)
-; 64BIT: renamable $f1 = LFD 0, killed renamable $x3 :: (dereferenceable load 8 from @d1)
-; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: BL8_NOP <mcsymbol .test_double>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $x2, implicit-def $r1
-; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
-
-  %0 = load double, double* @d1, align 8
-  call void @test_double(double %0)
-  ret void
-}
-
-declare void @test_double(double)
-
-define void @call_test_fpr_max() {
-entry:
-; 32BIT: renamable $r3 = LWZtoc @d1, $r2 :: (load 4 from got)
-; 32BIT: renamable $f1 = LFD 0, killed renamable $r3 :: (dereferenceable load 8 from @d1)
-; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT: $f2 = COPY renamable $f1
-; 32BIT: $f3 = COPY renamable $f1
-; 32BIT: $f4 = COPY renamable $f1
-; 32BIT: $f5 = COPY renamable $f1
-; 32BIT: $f6 = COPY renamable $f1
-; 32BIT: $f7 = COPY renamable $f1
-; 32BIT: $f8 = COPY renamable $f1
-; 32BIT: $f9 = COPY renamable $f1
-; 32BIT: $f10 = COPY renamable $f1
-; 32BIT: $f11 = COPY renamable $f1
-; 32BIT: $f12 = COPY renamable $f1
-; 32BIT: $f13 = COPY renamable $f1
-; 32BIT: BL_NOP <mcsymbol .test_fpr_max>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $r2, implicit-def $r1
-; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
-
-; 64BIT: renamable $x3 = LDtoc @d1, $x2 :: (load 8 from got)
-; 64BIT: renamable $f1 = LFD 0, killed renamable $x3 :: (dereferenceable load 8 from @d1)
-; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: $f2 = COPY renamable $f1
-; 64BIT: $f3 = COPY renamable $f1
-; 64BIT: $f4 = COPY renamable $f1
-; 64BIT: $f5 = COPY renamable $f1
-; 64BIT: $f6 = COPY renamable $f1
-; 64BIT: $f7 = COPY renamable $f1
-; 64BIT: $f8 = COPY renamable $f1
-; 64BIT: $f9 = COPY renamable $f1
-; 64BIT: $f10 = COPY renamable $f1
-; 64BIT: $f11 = COPY renamable $f1
-; 64BIT: $f12 = COPY renamable $f1
-; 64BIT: $f13 = COPY renamable $f1
-; 64BIT: BL8_NOP <mcsymbol .test_fpr_max>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit killed $f2, implicit killed $f3, implicit killed $f4, implicit killed $f5, implicit killed $f6, implicit killed $f7, implicit killed $f8, implicit killed $f9, implicit killed $f10, implicit killed $f11, implicit killed $f12, implicit killed $f13, implicit $x2, implicit-def $r1
-; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
-
-  %0 = load double, double* @d1, align 8
-  call void @test_fpr_max(double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0, double %0)
-  ret void
-}
-
-declare void @test_fpr_max(double, double, double, double, double, double, double, double, double, double, double, double, double)
-
-define void @call_test_mix() {
-entry:
-; 32BIT: renamable $r3 = LWZtoc @f1, $r2 :: (load 4 from got)
-; 32BIT: renamable $r4 = LWZtoc @d1, $r2 :: (load 4 from got)
-; 32BIT: renamable $f1 = LFS 0, killed renamable $r3 :: (dereferenceable load 4 from @f1)
-; 32BIT: renamable $f2 = LFD 0, killed renamable $r4 :: (dereferenceable load 8 from @d1)
-; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT: $r4 = LI 1
-; 32BIT: $r7 = LI 97
-; 32BIT: BL_NOP <mcsymbol .test_mix>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $f1, implicit $r4, implicit $f2, implicit killed $r7, implicit $r2, implicit-def $r1
-; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
-
-; 64BIT: renamable $x3 = LDtoc @f1, $x2 :: (load 8 from got)
-; 64BIT: renamable $x4 = LDtoc @d1, $x2 :: (load 8 from got)
-; 64BIT: renamable $f1 = LFS 0, killed renamable $x3 :: (dereferenceable load 4 from @f1)
-; 64BIT: renamable $f2 = LFD 0, killed renamable $x4 :: (dereferenceable load 8 from @d1)
-; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: $x4 = LI8 1
-; 64BIT: $x6 = LI8 97
-; 64BIT: BL8_NOP <mcsymbol .test_mix>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $f1, implicit $x4, implicit $f2, implicit killed $x6, implicit $x2, implicit-def $r1
-; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
-
-  %0 = load float, float* @f1, align 4
-  %1 = load double, double* @d1, align 8
-  call void @test_mix(float %0, i32 1, double %1, i8 signext 97)
-  ret void
-}
-
-declare void @test_mix(float, i32, double, i8 signext)

llvm/test/CodeGen/PowerPC/aix_gpr_param.ll

-; RUN: llc -mtriple powerpc-ibm-aix-xcoff -stop-after=machine-cp < %s | \
-; RUN: FileCheck --check-prefix=32BIT %s
-
-; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -stop-after=machine-cp < %s | \
-; RUN: FileCheck --check-prefix=64BIT %s
-
-define void @call_test_char() {
-entry:
-; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT: $r3 = LI 97
-; 32BIT: BL_NOP <mcsymbol .test_char>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit $r2, implicit-def $r1
-; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
-
-; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: $x3 = LI8 97
-; 64BIT: BL8_NOP <mcsymbol .test_char>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1
-; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
-
-  call void @test_char(i8 signext 97)
-  ret void
-}
-
-define void @call_test_chars() {
-entry:
-; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT: $r3 = LI 97
-; 32BIT: $r4 = LI 97
-; 32BIT: $r5 = LI 97
-; 32BIT: $r6 = LI 97
-; 32BIT: BL_NOP <mcsymbol .test_chars>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit $r2, implicit-def $r1
-; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
-
-; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: $x3 = LI8 97
-; 64BIT: $x4 = LI8 97
-; 64BIT: $x5 = LI8 97
-; 64BIT: $x6 = LI8 97
-; 64BIT: BL8_NOP <mcsymbol .test_chars>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1
-; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
-
-  call void @test_chars(i8 signext 97, i8 signext 97, i8 signext 97, i8 signext 97)
-  ret void
-}
-
-define void @call_test_chars_mix() {
-entry:
-; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT: $r3 = LI 97
-; 32BIT: $r4 = LI 225
-; 32BIT: $r5 = LI 97
-; 32BIT: $r6 = LI -31
-; 32BIT: BL_NOP <mcsymbol .test_chars_mix>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit $r2, implicit-def $r1
-; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
-
-; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: $x3 = LI8 97
-; 64BIT: $x4 = LI8 225
-; 64BIT: $x5 = LI8 97
-; 64BIT: $x6 = LI8 -31
-; 64BIT: BL8_NOP <mcsymbol .test_chars_mix>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit $x2, implicit-def $r1
-; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
-
-  call void @test_chars_mix(i8 signext 97, i8 zeroext -31, i8 zeroext 97, i8 signext -31)
-  ret void
-}
-
-define void @call_test_int() {
-entry:
-; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT: $r3 = LI 1
-; 32BIT: BL_NOP <mcsymbol .test_int>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit $r2, implicit-def $r1
-; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
-
-; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: $x3 = LI8 1
-; 64BIT: BL8_NOP <mcsymbol .test_int>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1
-; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
-
-  call void @test_int(i32 1)
-  ret void
-}
-
-define void @call_test_ints() {
-entry:
-; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT: $r3 = LI 1
-; 32BIT: $r4 = LI 1
-; 32BIT: $r5 = LI 1
-; 32BIT: $r6 = LI 1
-; 32BIT: $r7 = LI 1
-; 32BIT: $r8 = LI 1
-; 32BIT: $r9 = LI 1
-; 32BIT: $r10 = LI 1
-; 32BIT: BL_NOP <mcsymbol .test_ints>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit killed $r5, implicit killed $r6, implicit killed $r7, implicit killed $r8, implicit killed $r9, implicit killed $r10, implicit $r2, implicit-def $r1
-; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
-
-; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: $x3 = LI8 1
-; 64BIT: $x4 = LI8 1
-; 64BIT: $x5 = LI8 1
-; 64BIT: $x6 = LI8 1
-; 64BIT: $x7 = LI8 1
-; 64BIT: $x8 = LI8 1
-; 64BIT: $x9 = LI8 1
-; 64BIT: $x10 = LI8 1
-; 64BIT: BL8_NOP <mcsymbol .test_ints>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $x2, implicit-def $r1
-; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
-
-  call void @test_ints(i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1)
-  ret void
-}
-
-define void @call_test_ints_64bit() {
-entry:
-; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: renamable $x3 = LI8 1
-; 64BIT: renamable $x5 = RLDICR killed renamable $x3, 31, 32
-; 64BIT: $x3 = LI8 1
-; 64BIT: $x4 = LI8 1
-; 64BIT: $x6 = LIS8 32768
-; 64BIT: $x7 = LI8 1
-; 64BIT: $x8 = LI8 1
-; 64BIT: $x9 = LI8 1
-; 64BIT: $x10 = LI8 1
-; 64BIT: BL8_NOP <mcsymbol .test_ints_64bit>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $x2, implicit-def $r1
-; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
-
-  call void @test_ints_64bit(i32 signext 1, i32 zeroext 1, i32 zeroext 2147483648, i32 signext -2147483648, i32 signext 1, i32 signext 1, i32 signext 1, i32 signext 1)
-  ret void
-}
-
-define void @call_test_i1() {
-entry:
-; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT: $r3 = LI 1
-; 32BIT: BL_NOP <mcsymbol .test_i1>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit $r2, implicit-def $r1
-; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
-
-; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: $x3 = LI8 1
-; 64BIT: BL8_NOP <mcsymbol .test_i1>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1
-; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
-
-  call void @test_i1(i1 1)
-  ret void
-}
-
-define void @call_test_i64() {
-entry:
-; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT: $r3 = LI 0
-; 32BIT: $r4 = LI 1
-; 32BIT: BL_NOP <mcsymbol .test_i64>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit killed $r3, implicit killed $r4, implicit $r2, implicit-def $r1
-; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
-
-; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: $x3 = LI8 1
-; 64BIT: BL8_NOP <mcsymbol .test_i64>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit killed $x3, implicit $x2, implicit-def $r1
-; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
-
-  call void @test_i64(i64 1)
-  ret void
-}
-
-define void @call_test_int_ptr() {
-entry:
-  %b = alloca i32, align 4
-; 32BIT: ADJCALLSTACKDOWN 56, 0, implicit-def dead $r1, implicit $r1
-; 32BIT: renamable $r3 = ADDI %stack.0.b, 0
-; 32BIT: BL_NOP <mcsymbol .test_int_ptr>, csr_aix32, implicit-def dead $lr, implicit $rm, implicit $r3, implicit $r2, implicit-def $r1
-; 32BIT: ADJCALLSTACKUP 56, 0, implicit-def dead $r1, implicit $r1
-
-; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: renamable $x3 = ADDI8 %stack.0.b, 0
-; 64BIT: BL8_NOP <mcsymbol .test_int_ptr>, csr_aix64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit $x2, implicit-def $r1
-; 64BIT: ADJCALLSTACKUP 112, 0, implicit-def dead $r1, implicit $r1
-
-  store i32 0, i32* %b, align 4
-  call void @test_int_ptr(i32* %b)
-  ret void
-}
-
-declare void @test_char(i8 signext)
-
-declare void @test_chars(i8 signext, i8 signext, i8 signext, i8 signext)
-
-declare void @test_chars_mix(i8 signext, i8 zeroext, i8 zeroext, i8 signext)
-
-declare void @test_int(i32)
-
-declare void @test_ints(i32, i32, i32, i32, i32, i32, i32, i32)
-
-declare void @test_ints_64bit(i32 signext, i32 zeroext, i32 zeroext, i32 signext, i32 signext, i32 signext, i32 signext, i32 signext)
-
-declare void @test_i1(i1)
-
-declare void @test_i64(i64)
-
-declare void @test_int_ptr(i32*)

llvm/test/CodeGen/PowerPC/lower-globaladdr32-aix-asm.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefixes=CHECK,SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefixes=CHECK,LARGE
 
 @a = common global i32 0
 
 define i32 @test_load() {
 entry:
   %0 = load i32, i32* @a
   ret i32 %0

llvm/test/CodeGen/PowerPC/lower-globaladdr64-aix-asm.ll

-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=small < %s | FileCheck %s --check-prefixes=CHECK,SMALL
 
-; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple powerpc64-ibm-aix-xcoff \
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \
 ; RUN: -code-model=large < %s | FileCheck %s --check-prefixes=CHECK,LARGE
 
 @a = common global i32 0
 
 define zeroext i32 @test_load() {
 entry:
   %0 = load i32, i32* @a
   ret i32 %0