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[AArch64] Improve codegen of volatile load/store of i128
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Authored by vhscampos on Oct 29 2019, 6:07 AM.

Details

Summary

Instead of generating two i64 instructions for each load or store of a
volatile i128 value (two LDRs or STRs), now emit a single LDP or STP.

Diff Detail

Event Timeline

vhscampos created this revision.Oct 29 2019, 6:07 AM
vhscampos updated this revision to Diff 227092.Oct 30 2019, 7:24 AM

Amending patch to include the transfer of memory operands from the original
SDNode to the new MachineSDNode.

vhscampos updated this revision to Diff 229053.Nov 13 2019, 3:05 AM
  1. Create new AArch64ISD nodes specific to load/store of pairs of registers.
  2. Custom lower i128 volatile loads/stores to these new AArch64ISD nodes.
vhscampos updated this revision to Diff 233621.Dec 12 2019, 8:16 AM
  1. Move new ISD node definitions to TableGen.
  2. Instruction selection done in TableGen using patterns.
efriedma added inline comments.Dec 12 2019, 10:33 AM
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
3025

Not sure we're actually guaranteed here that StoreNode->getValue() is an i128.

efriedma added inline comments.Dec 12 2019, 10:34 AM
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
3025

Actually, we're probably fine here if it's a volatile store. Maybe worth adding an assert, though.

vhscampos updated this revision to Diff 234012.Dec 16 2019, 2:50 AM

Add an assertion.

This revision is now accepted and ready to land.Dec 17 2019, 4:15 PM
This revision was automatically updated to reflect the committed changes.