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[PowerPC] Test case for vector float gather on ppc64le and ppc64

Authored by kamaub on Oct 25 2019, 12:20 PM.



Test case to verify that the expected code is generated for a
vector float gather based on the patterns in tablegen for big
and little endian cases.

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kamaub created this revision.Oct 25 2019, 12:20 PM
Herald added a project: Restricted Project. · View Herald TranscriptOct 25 2019, 12:20 PM
kamaub added a reviewer: Restricted Project.Oct 25 2019, 12:20 PM
amyk accepted this revision.Nov 3 2019, 7:22 PM


This revision is now accepted and ready to land.Nov 3 2019, 7:22 PM
stefanp requested changes to this revision.Nov 4 2019, 11:52 AM

Please make sure that your test does not put restrictions on the allocation of output registers. See my comments.
Otherwise I think this looks fine.


generate -> generated


So xxmrghd computes the contents of one register based on the other two.
xxmrghd vs[[Newly Defined Output Register]], vs[[REG2]], vs[[REG0]]
Nothing says that we need to allocate the same register for the output of xxmrghd as the output of lfs(REG0).


Same as above. The outputs of the two xxmrghd instructions don't need to be [[REG0]] or [[REG1]]. The register allocator may decide to use a different register there.

This revision now requires changes to proceed.Nov 4 2019, 11:52 AM
kamaub updated this revision to Diff 228706.Nov 11 2019, 8:56 AM
kamaub marked 3 inline comments as done.
  • Updating test case to be less restrictive.

I think this patch is fine now.
I only have one minor comment.


I think you mean v4f32 and not v4i32 since they are all floats.

kamaub updated this revision to Diff 229616.Nov 15 2019, 12:43 PM
  • Minor spelling change to test case.
kamaub marked an inline comment as done.Nov 15 2019, 12:44 PM

Fixed it, thank you.

stefanp accepted this revision.Nov 15 2019, 12:49 PM
This revision is now accepted and ready to land.Nov 15 2019, 12:49 PM
This revision was automatically updated to reflect the committed changes.