This is an archive of the discontinued LLVM Phabricator instance.

Differential D69374

[AArch64] Select sadd_sat, uadd_sat, usub_sat and ssub_sat.
ClosedPublic

Authored by dmgreen on Oct 24 2019, 4:15 AM.

Details

Reviewers
t.p.northover
SjoerdMeijer
samparker
efriedma
Commits
rG2179867ddc29: [AArch64] Select saturating Neon instructions
Summary

This adds some extra patterns to select AArch64 Neon SQADD, UQADD, SQSUB and UQSUB from the existing target independent _sat nodes.

It does not attempt to replace the existing int_aarch64_neon_uqadd intrinsic nodes as they are apparently used for both scalar and vector, and need to be legal on scalar types for some of the patterns to work. The int_aarch64_neon_uqadd on scalar would move the two integers into floating point registers, perform a Neon uqadd and move the value back. I don't believe this is good idea for uadd_sat to do the same as the scalar alternative is simpler (an adds with a csinv). For signed it may be smaller, but I'm not sure about it being better.

So this just adds some extra patterns for the existing vector instructions, matching on the _sat nodes.

Diff Detail

Event Timeline

dmgreen created this revision.Oct 24 2019, 4:15 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 24 2019, 4:15 AM
Herald added subscribers: hiraditya, kristof.beyls. · View Herald Transcript
efriedma added a comment.Oct 24 2019, 4:04 PM

Do we care about FPSR.QC? I remember we had some discussion about it in the past, but I'm not remembering off the top of my head.

I agree it doesn't make sense to move an integer from a GPR to an FPR just to perform a saturating add. Maybe GlobalISel could do something more clever here.

Otherwise looks fine.

dmgreen added a comment.Oct 27 2019, 2:23 PM

Thanks.

In D69374#1720649, @efriedma wrote:

Do we care about FPSR.QC? I remember we had some discussion about it in the past, but I'm not remembering off the top of my head.

I had not seen anything on FPSR.QC for AArch64 (or AArch32 Neon), and was presuming it would be fine to generate them from _sats. Was this discussion on the llvm lists somewhere? The aarch32 ACLE intrinsics tried to make some rules regarding q flags, but that's not something that either clang or gcc honour. And I've not seen anything similar for Neon.

efriedma accepted this revision.Oct 28 2019, 5:31 PM

I might be getting QC confused with one of the other flags. I think there was an issue at some point when someone was trying to add intrinsics to read/write the flags, but we didn't provide appropriate guarantees. Not sure that ever got merged.

LGTM

This revision is now accepted and ready to land.Oct 28 2019, 5:31 PM
Closed by commit rG2179867ddc29: [AArch64] Select saturating Neon instructions (authored by dmgreen). · Explain WhyOct 31 2019, 10:30 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
8 lines
18 lines
6 lines
test/
CodeGen/
AArch64/
10 lines
363 lines
10 lines
363 lines
168 lines
130 lines

Diff 226221

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 728 Lines • ▼ Show 20 Lines if (Subtarget->hasNEON()) {
// AArch64 doesn't have MUL.2d: // AArch64 doesn't have MUL.2d:
setOperationAction(ISD::MUL, MVT::v2i64, Expand); setOperationAction(ISD::MUL, MVT::v2i64, Expand);
// Custom handling for some quad-vector types to detect MULL. // Custom handling for some quad-vector types to detect MULL.
setOperationAction(ISD::MUL, MVT::v8i16, Custom); setOperationAction(ISD::MUL, MVT::v8i16, Custom);
setOperationAction(ISD::MUL, MVT::v4i32, Custom); setOperationAction(ISD::MUL, MVT::v4i32, Custom);
setOperationAction(ISD::MUL, MVT::v2i64, Custom); setOperationAction(ISD::MUL, MVT::v2i64, Custom);
// Vector reductions
for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32, for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32,
MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) { MVT::v16i8, MVT::v8i16, MVT::v4i32, MVT::v2i64 }) {
// Vector reductions
setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); setOperationAction(ISD::VECREDUCE_ADD, VT, Custom);
setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom);
setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom);
setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom); setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom);
setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom); setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom);
// Saturates
setOperationAction(ISD::SADDSAT, VT, Legal);
setOperationAction(ISD::UADDSAT, VT, Legal);
setOperationAction(ISD::SSUBSAT, VT, Legal);
setOperationAction(ISD::USUBSAT, VT, Legal);
} }
for (MVT VT : { MVT::v4f16, MVT::v2f32, for (MVT VT : { MVT::v4f16, MVT::v2f32,
MVT::v8f16, MVT::v4f32, MVT::v2f64 }) { MVT::v8f16, MVT::v4f32, MVT::v2f64 }) {
setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom);
setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom);
} }
setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal); setOperationAction(ISD::ANY_EXTEND, MVT::v4i32, Legal);
▲ Show 20 Lines • Show All 11,692 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64InstrFormats.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,060 Lines • ▼ Show 20 Linesmulticlass SIMDThreeSameVector<bit U, bits<5> opc, string asm,
def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128, def v4i32 : BaseSIMDThreeSameVector<1, U, 0b101, opc, V128,
asm, ".4s", asm, ".4s",
[(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>; [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
def v2i64 : BaseSIMDThreeSameVector<1, U, 0b111, opc, V128, def v2i64 : BaseSIMDThreeSameVector<1, U, 0b111, opc, V128,
asm, ".2d", asm, ".2d",
[(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>; [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
} }
multiclass SIMDThreeSameVectorExtraPatterns<string inst, SDPatternOperator OpNode> {
def : Pat<(v8i8 (OpNode V64:$LHS, V64:$RHS)),
(!cast<Instruction>(inst#"v8i8") V64:$LHS, V64:$RHS)>;
def : Pat<(v4i16 (OpNode V64:$LHS, V64:$RHS)),
(!cast<Instruction>(inst#"v4i16") V64:$LHS, V64:$RHS)>;
def : Pat<(v2i32 (OpNode V64:$LHS, V64:$RHS)),
(!cast<Instruction>(inst#"v2i32") V64:$LHS, V64:$RHS)>;
def : Pat<(v16i8 (OpNode V128:$LHS, V128:$RHS)),
(!cast<Instruction>(inst#"v16i8") V128:$LHS, V128:$RHS)>;
def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)),
(!cast<Instruction>(inst#"v8i16") V128:$LHS, V128:$RHS)>;
def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
(!cast<Instruction>(inst#"v4i32") V128:$LHS, V128:$RHS)>;
def : Pat<(v2i64 (OpNode V128:$LHS, V128:$RHS)),
(!cast<Instruction>(inst#"v2i64") V128:$LHS, V128:$RHS)>;
}
// As above, but D sized elements unsupported. // As above, but D sized elements unsupported.
multiclass SIMDThreeSameVectorBHS<bit U, bits<5> opc, string asm, multiclass SIMDThreeSameVectorBHS<bit U, bits<5> opc, string asm,
SDPatternOperator OpNode> { SDPatternOperator OpNode> {
def v8i8 : BaseSIMDThreeSameVector<0, U, 0b001, opc, V64, def v8i8 : BaseSIMDThreeSameVector<0, U, 0b001, opc, V64,
asm, ".8b", asm, ".8b",
[(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>; [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>;
def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128, def v16i8 : BaseSIMDThreeSameVector<1, U, 0b001, opc, V128,
asm, ".16b", asm, ".16b",
▲ Show 20 Lines • Show All 5,650 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64InstrInfo.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,754 Lines • ▼ Show 20 Lines
defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>; defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_aarch64_neon_urhadd>;
defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>; defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_aarch64_neon_urshl>;
defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>; defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_aarch64_neon_ushl>;
defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah", defm SQRDMLAH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10000,"sqrdmlah",
int_aarch64_neon_sqadd>; int_aarch64_neon_sqadd>;
defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh", defm SQRDMLSH : SIMDThreeSameVectorSQRDMLxHTiedHS<1,0b10001,"sqrdmlsh",
int_aarch64_neon_sqsub>; int_aarch64_neon_sqsub>;
// Extra saturate patterns, other than the intrinsics matches above
defm : SIMDThreeSameVectorExtraPatterns<"SQADD", saddsat>;
defm : SIMDThreeSameVectorExtraPatterns<"UQADD", uaddsat>;
defm : SIMDThreeSameVectorExtraPatterns<"SQSUB", ssubsat>;
defm : SIMDThreeSameVectorExtraPatterns<"UQSUB", usubsat>;
defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>; defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic", defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >; BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">; defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>; defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", AArch64bit>;
defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl", defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>; TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>; defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
▲ Show 20 Lines • Show All 3,358 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/sadd_sat.ll

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y); %tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);
ret i4 %tmp; ret i4 %tmp;
} }
define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: vec: ; CHECK-LABEL: vec:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v2.4s, v0.4s, v1.4s ; CHECK-NEXT: sqadd v0.4s, v0.4s, v1.4s
; CHECK-NEXT: cmlt v4.4s, v2.4s, #0
; CHECK-NEXT: mvni v3.4s, #128, lsl #24
; CHECK-NEXT: cmlt v1.4s, v1.4s, #0
; CHECK-NEXT: cmgt v0.4s, v0.4s, v2.4s
; CHECK-NEXT: mvn v5.16b, v4.16b
; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y); %tmp = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y);
ret <4 x i32> %tmp; ret <4 x i32> %tmp;
} }

llvm/test/CodeGen/AArch64/sadd_sat_vec.ll

Show All 29 Lines
declare <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64>, <8 x i64>) declare <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64>, <8 x i64>)
declare <4 x i24> @llvm.sadd.sat.v4i24(<4 x i24>, <4 x i24>) declare <4 x i24> @llvm.sadd.sat.v4i24(<4 x i24>, <4 x i24>)
declare <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128>, <2 x i128>) declare <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128>, <2 x i128>)
define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind { define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; CHECK-LABEL: v16i8: ; CHECK-LABEL: v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v2.16b, v0.16b, v1.16b ; CHECK-NEXT: sqadd v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmlt v4.16b, v2.16b, #0
; CHECK-NEXT: movi v3.16b, #127
; CHECK-NEXT: cmlt v1.16b, v1.16b, #0
; CHECK-NEXT: cmgt v0.16b, v0.16b, v2.16b
; CHECK-NEXT: mvn v5.16b, v4.16b
; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y) %z = call <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
ret <16 x i8> %z ret <16 x i8> %z
} }
define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind { define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
; CHECK-LABEL: v32i8: ; CHECK-LABEL: v32i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v4.16b, v0.16b, v2.16b ; CHECK-NEXT: sqadd v0.16b, v0.16b, v2.16b
; CHECK-NEXT: cmlt v7.16b, v4.16b, #0 ; CHECK-NEXT: sqadd v1.16b, v1.16b, v3.16b
; CHECK-NEXT: movi v6.16b, #127
; CHECK-NEXT: mvn v16.16b, v7.16b
; CHECK-NEXT: bsl v6.16b, v7.16b, v16.16b
; CHECK-NEXT: add v7.16b, v1.16b, v3.16b
; CHECK-NEXT: cmlt v2.16b, v2.16b, #0
; CHECK-NEXT: cmgt v0.16b, v0.16b, v4.16b
; CHECK-NEXT: cmlt v16.16b, v7.16b, #0
; CHECK-NEXT: movi v5.16b, #127
; CHECK-NEXT: cmlt v3.16b, v3.16b, #0
; CHECK-NEXT: cmgt v1.16b, v1.16b, v7.16b
; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
; CHECK-NEXT: mvn v2.16b, v16.16b
; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
; CHECK-NEXT: bsl v5.16b, v16.16b, v2.16b
; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <32 x i8> @llvm.sadd.sat.v32i8(<32 x i8> %x, <32 x i8> %y) %z = call <32 x i8> @llvm.sadd.sat.v32i8(<32 x i8> %x, <32 x i8> %y)
ret <32 x i8> %z ret <32 x i8> %z
} }
define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind { define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
; CHECK-LABEL: v64i8: ; CHECK-LABEL: v64i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v16.16b, v0.16b, v4.16b ; CHECK-NEXT: sqadd v0.16b, v0.16b, v4.16b
; CHECK-NEXT: cmlt v24.16b, v16.16b, #0 ; CHECK-NEXT: sqadd v1.16b, v1.16b, v5.16b
; CHECK-NEXT: movi v18.16b, #127 ; CHECK-NEXT: sqadd v2.16b, v2.16b, v6.16b
; CHECK-NEXT: add v19.16b, v1.16b, v5.16b ; CHECK-NEXT: sqadd v3.16b, v3.16b, v7.16b
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.16b, v19.16b, #0
; CHECK-NEXT: movi v20.16b, #127
; CHECK-NEXT: add v21.16b, v2.16b, v6.16b
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.16b, v21.16b, #0
; CHECK-NEXT: cmlt v4.16b, v4.16b, #0
; CHECK-NEXT: cmgt v0.16b, v0.16b, v16.16b
; CHECK-NEXT: movi v22.16b, #127
; CHECK-NEXT: add v23.16b, v3.16b, v7.16b
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
; CHECK-NEXT: cmlt v4.16b, v5.16b, #0
; CHECK-NEXT: cmgt v1.16b, v1.16b, v19.16b
; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.16b, v23.16b, #0
; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
; CHECK-NEXT: cmlt v4.16b, v6.16b, #0
; CHECK-NEXT: cmgt v2.16b, v2.16b, v21.16b
; CHECK-NEXT: movi v17.16b, #127
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
; CHECK-NEXT: cmlt v4.16b, v7.16b, #0
; CHECK-NEXT: cmgt v3.16b, v3.16b, v23.16b
; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> %x, <64 x i8> %y) %z = call <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8> %x, <64 x i8> %y)
ret <64 x i8> %z ret <64 x i8> %z
} }
define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind { define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; CHECK-LABEL: v8i16: ; CHECK-LABEL: v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v2.8h, v0.8h, v1.8h ; CHECK-NEXT: sqadd v0.8h, v0.8h, v1.8h
; CHECK-NEXT: cmlt v4.8h, v2.8h, #0
; CHECK-NEXT: mvni v3.8h, #128, lsl #8
; CHECK-NEXT: cmlt v1.8h, v1.8h, #0
; CHECK-NEXT: cmgt v0.8h, v0.8h, v2.8h
; CHECK-NEXT: mvn v5.16b, v4.16b
; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y) %z = call <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
ret <8 x i16> %z ret <8 x i16> %z
} }
define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind { define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {
; CHECK-LABEL: v16i16: ; CHECK-LABEL: v16i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v4.8h, v0.8h, v2.8h ; CHECK-NEXT: sqadd v0.8h, v0.8h, v2.8h
; CHECK-NEXT: cmlt v7.8h, v4.8h, #0 ; CHECK-NEXT: sqadd v1.8h, v1.8h, v3.8h
; CHECK-NEXT: mvni v6.8h, #128, lsl #8
; CHECK-NEXT: mvn v16.16b, v7.16b
; CHECK-NEXT: bsl v6.16b, v7.16b, v16.16b
; CHECK-NEXT: add v7.8h, v1.8h, v3.8h
; CHECK-NEXT: cmlt v2.8h, v2.8h, #0
; CHECK-NEXT: cmgt v0.8h, v0.8h, v4.8h
; CHECK-NEXT: cmlt v16.8h, v7.8h, #0
; CHECK-NEXT: mvni v5.8h, #128, lsl #8
; CHECK-NEXT: cmlt v3.8h, v3.8h, #0
; CHECK-NEXT: cmgt v1.8h, v1.8h, v7.8h
; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
; CHECK-NEXT: mvn v2.16b, v16.16b
; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
; CHECK-NEXT: bsl v5.16b, v16.16b, v2.16b
; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> %x, <16 x i16> %y) %z = call <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16> %x, <16 x i16> %y)
ret <16 x i16> %z ret <16 x i16> %z
} }
define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind { define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {
; CHECK-LABEL: v32i16: ; CHECK-LABEL: v32i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v16.8h, v0.8h, v4.8h ; CHECK-NEXT: sqadd v0.8h, v0.8h, v4.8h
; CHECK-NEXT: cmlt v24.8h, v16.8h, #0 ; CHECK-NEXT: sqadd v1.8h, v1.8h, v5.8h
; CHECK-NEXT: mvni v18.8h, #128, lsl #8 ; CHECK-NEXT: sqadd v2.8h, v2.8h, v6.8h
; CHECK-NEXT: add v19.8h, v1.8h, v5.8h ; CHECK-NEXT: sqadd v3.8h, v3.8h, v7.8h
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.8h, v19.8h, #0
; CHECK-NEXT: mvni v20.8h, #128, lsl #8
; CHECK-NEXT: add v21.8h, v2.8h, v6.8h
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.8h, v21.8h, #0
; CHECK-NEXT: cmlt v4.8h, v4.8h, #0
; CHECK-NEXT: cmgt v0.8h, v0.8h, v16.8h
; CHECK-NEXT: mvni v22.8h, #128, lsl #8
; CHECK-NEXT: add v23.8h, v3.8h, v7.8h
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
; CHECK-NEXT: cmlt v4.8h, v5.8h, #0
; CHECK-NEXT: cmgt v1.8h, v1.8h, v19.8h
; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.8h, v23.8h, #0
; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
; CHECK-NEXT: cmlt v4.8h, v6.8h, #0
; CHECK-NEXT: cmgt v2.8h, v2.8h, v21.8h
; CHECK-NEXT: mvni v17.8h, #128, lsl #8
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
; CHECK-NEXT: cmlt v4.8h, v7.8h, #0
; CHECK-NEXT: cmgt v3.8h, v3.8h, v23.8h
; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <32 x i16> @llvm.sadd.sat.v32i16(<32 x i16> %x, <32 x i16> %y) %z = call <32 x i16> @llvm.sadd.sat.v32i16(<32 x i16> %x, <32 x i16> %y)
ret <32 x i16> %z ret <32 x i16> %z
} }
define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind { define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind {
; CHECK-LABEL: v8i8: ; CHECK-LABEL: v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: movi v2.8b, #127 ; CHECK-NEXT: sqadd v0.8b, v0.8b, v1.8b
; CHECK-NEXT: add v3.8b, v0.8b, v1.8b
; CHECK-NEXT: cmlt v4.8b, v3.8b, #0
; CHECK-NEXT: cmlt v1.8b, v1.8b, #0
; CHECK-NEXT: cmgt v0.8b, v0.8b, v3.8b
; CHECK-NEXT: mvn v5.8b, v4.8b
; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
; CHECK-NEXT: str d0, [x2] ; CHECK-NEXT: str d0, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <8 x i8>, <8 x i8>* %px %x = load <8 x i8>, <8 x i8>* %px
%y = load <8 x i8>, <8 x i8>* %py %y = load <8 x i8>, <8 x i8>* %py
%z = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> %x, <8 x i8> %y) %z = call <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8> %x, <8 x i8> %y)
store <8 x i8> %z, <8 x i8>* %pz store <8 x i8> %z, <8 x i8>* %pz
ret void ret void
} }
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret void ret void
} }
define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind { define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind {
; CHECK-LABEL: v4i16: ; CHECK-LABEL: v4i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: mvni v2.4h, #128, lsl #8 ; CHECK-NEXT: sqadd v0.4h, v0.4h, v1.4h
; CHECK-NEXT: add v3.4h, v0.4h, v1.4h
; CHECK-NEXT: cmlt v4.4h, v3.4h, #0
; CHECK-NEXT: cmlt v1.4h, v1.4h, #0
; CHECK-NEXT: cmgt v0.4h, v0.4h, v3.4h
; CHECK-NEXT: mvn v5.8b, v4.8b
; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
; CHECK-NEXT: str d0, [x2] ; CHECK-NEXT: str d0, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <4 x i16>, <4 x i16>* %px %x = load <4 x i16>, <4 x i16>* %px
%y = load <4 x i16>, <4 x i16>* %py %y = load <4 x i16>, <4 x i16>* %py
%z = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %x, <4 x i16> %y) %z = call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> %x, <4 x i16> %y)
store <4 x i16> %z, <4 x i16>* %pz store <4 x i16> %z, <4 x i16>* %pz
ret void ret void
} }
Show All 24 Lines; CHECK-NEXT: ret
%z = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %x, <2 x i16> %y) %z = call <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
store <2 x i16> %z, <2 x i16>* %pz store <2 x i16> %z, <2 x i16>* %pz
ret void ret void
} }
define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind { define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {
; CHECK-LABEL: v12i8: ; CHECK-LABEL: v12i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v2.16b, v0.16b, v1.16b ; CHECK-NEXT: sqadd v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmlt v4.16b, v2.16b, #0
; CHECK-NEXT: movi v3.16b, #127
; CHECK-NEXT: cmlt v1.16b, v1.16b, #0
; CHECK-NEXT: cmgt v0.16b, v0.16b, v2.16b
; CHECK-NEXT: mvn v5.16b, v4.16b
; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <12 x i8> @llvm.sadd.sat.v12i8(<12 x i8> %x, <12 x i8> %y) %z = call <12 x i8> @llvm.sadd.sat.v12i8(<12 x i8> %x, <12 x i8> %y)
ret <12 x i8> %z ret <12 x i8> %z
} }
define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind { define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind {
; CHECK-LABEL: v12i16: ; CHECK-LABEL: v12i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ldp q3, q2, [x1] ; CHECK-NEXT: ldp q3, q2, [x1]
; CHECK-NEXT: mvni v5.8h, #128, lsl #8 ; CHECK-NEXT: sqadd v1.8h, v1.8h, v2.8h
; CHECK-NEXT: mvni v4.8h, #128, lsl #8 ; CHECK-NEXT: sqadd v0.8h, v0.8h, v3.8h
; CHECK-NEXT: add v6.8h, v1.8h, v2.8h
; CHECK-NEXT: cmlt v7.8h, v6.8h, #0
; CHECK-NEXT: mvn v16.16b, v7.16b
; CHECK-NEXT: bsl v5.16b, v7.16b, v16.16b
; CHECK-NEXT: add v7.8h, v0.8h, v3.8h
; CHECK-NEXT: cmlt v2.8h, v2.8h, #0
; CHECK-NEXT: cmgt v1.8h, v1.8h, v6.8h
; CHECK-NEXT: cmlt v16.8h, v7.8h, #0
; CHECK-NEXT: cmlt v3.8h, v3.8h, #0
; CHECK-NEXT: cmgt v0.8h, v0.8h, v7.8h
; CHECK-NEXT: eor v1.16b, v2.16b, v1.16b
; CHECK-NEXT: mvn v2.16b, v16.16b
; CHECK-NEXT: eor v0.16b, v3.16b, v0.16b
; CHECK-NEXT: bsl v4.16b, v16.16b, v2.16b
; CHECK-NEXT: bsl v1.16b, v5.16b, v6.16b
; CHECK-NEXT: bsl v0.16b, v4.16b, v7.16b
; CHECK-NEXT: str q0, [x2] ; CHECK-NEXT: str q0, [x2]
; CHECK-NEXT: str d1, [x2, #16] ; CHECK-NEXT: str d1, [x2, #16]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <12 x i16>, <12 x i16>* %px %x = load <12 x i16>, <12 x i16>* %px
%y = load <12 x i16>, <12 x i16>* %py %y = load <12 x i16>, <12 x i16>* %py
%z = call <12 x i16> @llvm.sadd.sat.v12i16(<12 x i16> %x, <12 x i16> %y) %z = call <12 x i16> @llvm.sadd.sat.v12i16(<12 x i16> %x, <12 x i16> %y)
store <12 x i16> %z, <12 x i16>* %pz store <12 x i16> %z, <12 x i16>* %pz
ret void ret void
} }
define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind { define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
; CHECK-LABEL: v1i8: ; CHECK-LABEL: v1i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr b0, [x0] ; CHECK-NEXT: ldr b0, [x0]
; CHECK-NEXT: ldr b1, [x1] ; CHECK-NEXT: ldr b1, [x1]
; CHECK-NEXT: movi v2.8b, #127 ; CHECK-NEXT: sqadd v0.8b, v0.8b, v1.8b
; CHECK-NEXT: add v3.8b, v0.8b, v1.8b
; CHECK-NEXT: cmlt v4.8b, v3.8b, #0
; CHECK-NEXT: cmlt v1.8b, v1.8b, #0
; CHECK-NEXT: cmgt v0.8b, v0.8b, v3.8b
; CHECK-NEXT: mvn v5.8b, v4.8b
; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
; CHECK-NEXT: st1 { v0.b }[0], [x2] ; CHECK-NEXT: st1 { v0.b }[0], [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <1 x i8>, <1 x i8>* %px %x = load <1 x i8>, <1 x i8>* %px
%y = load <1 x i8>, <1 x i8>* %py %y = load <1 x i8>, <1 x i8>* %py
%z = call <1 x i8> @llvm.sadd.sat.v1i8(<1 x i8> %x, <1 x i8> %y) %z = call <1 x i8> @llvm.sadd.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
store <1 x i8> %z, <1 x i8>* %pz store <1 x i8> %z, <1 x i8>* %pz
ret void ret void
} }
define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind { define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
; CHECK-LABEL: v1i16: ; CHECK-LABEL: v1i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr h0, [x0] ; CHECK-NEXT: ldr h0, [x0]
; CHECK-NEXT: ldr h1, [x1] ; CHECK-NEXT: ldr h1, [x1]
; CHECK-NEXT: mvni v2.4h, #128, lsl #8 ; CHECK-NEXT: sqadd v0.4h, v0.4h, v1.4h
; CHECK-NEXT: add v3.4h, v0.4h, v1.4h
; CHECK-NEXT: cmlt v4.4h, v3.4h, #0
; CHECK-NEXT: cmlt v1.4h, v1.4h, #0
; CHECK-NEXT: cmgt v0.4h, v0.4h, v3.4h
; CHECK-NEXT: mvn v5.8b, v4.8b
; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
; CHECK-NEXT: str h0, [x2] ; CHECK-NEXT: str h0, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <1 x i16>, <1 x i16>* %px %x = load <1 x i16>, <1 x i16>* %px
%y = load <1 x i16>, <1 x i16>* %py %y = load <1 x i16>, <1 x i16>* %py
%z = call <1 x i16> @llvm.sadd.sat.v1i16(<1 x i16> %x, <1 x i16> %y) %z = call <1 x i16> @llvm.sadd.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
store <1 x i16> %z, <1 x i16>* %pz store <1 x i16> %z, <1 x i16>* %pz
ret void ret void
} }
Show All 28 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i1> @llvm.sadd.sat.v16i1(<16 x i1> %x, <16 x i1> %y) %z = call <16 x i1> @llvm.sadd.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
ret <16 x i1> %z ret <16 x i1> %z
} }
define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind { define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; CHECK-LABEL: v2i32: ; CHECK-LABEL: v2i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v2.2s, v0.2s, v1.2s ; CHECK-NEXT: sqadd v0.2s, v0.2s, v1.2s
; CHECK-NEXT: cmlt v4.2s, v2.2s, #0
; CHECK-NEXT: mvni v3.2s, #128, lsl #24
; CHECK-NEXT: cmlt v1.2s, v1.2s, #0
; CHECK-NEXT: cmgt v0.2s, v0.2s, v2.2s
; CHECK-NEXT: mvn v5.8b, v4.8b
; CHECK-NEXT: bsl v3.8b, v4.8b, v5.8b
; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
; CHECK-NEXT: bsl v0.8b, v3.8b, v2.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %x, <2 x i32> %y) %z = call <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32> %x, <2 x i32> %y)
ret <2 x i32> %z ret <2 x i32> %z
} }
define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: v4i32: ; CHECK-LABEL: v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v2.4s, v0.4s, v1.4s ; CHECK-NEXT: sqadd v0.4s, v0.4s, v1.4s
; CHECK-NEXT: cmlt v4.4s, v2.4s, #0
; CHECK-NEXT: mvni v3.4s, #128, lsl #24
; CHECK-NEXT: cmlt v1.4s, v1.4s, #0
; CHECK-NEXT: cmgt v0.4s, v0.4s, v2.4s
; CHECK-NEXT: mvn v5.16b, v4.16b
; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y) %z = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
ret <4 x i32> %z ret <4 x i32> %z
} }
define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind { define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
; CHECK-LABEL: v8i32: ; CHECK-LABEL: v8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v4.4s, v0.4s, v2.4s ; CHECK-NEXT: sqadd v0.4s, v0.4s, v2.4s
; CHECK-NEXT: cmlt v7.4s, v4.4s, #0 ; CHECK-NEXT: sqadd v1.4s, v1.4s, v3.4s
; CHECK-NEXT: mvni v6.4s, #128, lsl #24
; CHECK-NEXT: mvn v16.16b, v7.16b
; CHECK-NEXT: bsl v6.16b, v7.16b, v16.16b
; CHECK-NEXT: add v7.4s, v1.4s, v3.4s
; CHECK-NEXT: cmlt v2.4s, v2.4s, #0
; CHECK-NEXT: cmgt v0.4s, v0.4s, v4.4s
; CHECK-NEXT: cmlt v16.4s, v7.4s, #0
; CHECK-NEXT: mvni v5.4s, #128, lsl #24
; CHECK-NEXT: cmlt v3.4s, v3.4s, #0
; CHECK-NEXT: cmgt v1.4s, v1.4s, v7.4s
; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
; CHECK-NEXT: mvn v2.16b, v16.16b
; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
; CHECK-NEXT: bsl v5.16b, v16.16b, v2.16b
; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> %x, <8 x i32> %y) %z = call <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32> %x, <8 x i32> %y)
ret <8 x i32> %z ret <8 x i32> %z
} }
define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind { define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
; CHECK-LABEL: v16i32: ; CHECK-LABEL: v16i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v16.4s, v0.4s, v4.4s ; CHECK-NEXT: sqadd v0.4s, v0.4s, v4.4s
; CHECK-NEXT: cmlt v24.4s, v16.4s, #0 ; CHECK-NEXT: sqadd v1.4s, v1.4s, v5.4s
; CHECK-NEXT: mvni v18.4s, #128, lsl #24 ; CHECK-NEXT: sqadd v2.4s, v2.4s, v6.4s
; CHECK-NEXT: add v19.4s, v1.4s, v5.4s ; CHECK-NEXT: sqadd v3.4s, v3.4s, v7.4s
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.4s, v19.4s, #0
; CHECK-NEXT: mvni v20.4s, #128, lsl #24
; CHECK-NEXT: add v21.4s, v2.4s, v6.4s
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.4s, v21.4s, #0
; CHECK-NEXT: cmlt v4.4s, v4.4s, #0
; CHECK-NEXT: cmgt v0.4s, v0.4s, v16.4s
; CHECK-NEXT: mvni v22.4s, #128, lsl #24
; CHECK-NEXT: add v23.4s, v3.4s, v7.4s
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
; CHECK-NEXT: cmlt v4.4s, v5.4s, #0
; CHECK-NEXT: cmgt v1.4s, v1.4s, v19.4s
; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.4s, v23.4s, #0
; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
; CHECK-NEXT: cmlt v4.4s, v6.4s, #0
; CHECK-NEXT: cmgt v2.4s, v2.4s, v21.4s
; CHECK-NEXT: mvni v17.4s, #128, lsl #24
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
; CHECK-NEXT: cmlt v4.4s, v7.4s, #0
; CHECK-NEXT: cmgt v3.4s, v3.4s, v23.4s
; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %x, <16 x i32> %y) %z = call <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32> %x, <16 x i32> %y)
ret <16 x i32> %z ret <16 x i32> %z
} }
define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind { define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; CHECK-LABEL: v2i64: ; CHECK-LABEL: v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v2.2d, v0.2d, v1.2d ; CHECK-NEXT: sqadd v0.2d, v0.2d, v1.2d
; CHECK-NEXT: mov x8, #9223372036854775807
; CHECK-NEXT: cmlt v3.2d, v2.2d, #0
; CHECK-NEXT: cmlt v1.2d, v1.2d, #0
; CHECK-NEXT: dup v4.2d, x8
; CHECK-NEXT: cmgt v0.2d, v0.2d, v2.2d
; CHECK-NEXT: mvn v5.16b, v3.16b
; CHECK-NEXT: bsl v4.16b, v3.16b, v5.16b
; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
; CHECK-NEXT: bsl v0.16b, v4.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %x, <2 x i64> %y) %z = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
ret <2 x i64> %z ret <2 x i64> %z
} }
define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind { define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
; CHECK-LABEL: v4i64: ; CHECK-LABEL: v4i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v4.2d, v0.2d, v2.2d ; CHECK-NEXT: sqadd v0.2d, v0.2d, v2.2d
; CHECK-NEXT: mov x8, #9223372036854775807 ; CHECK-NEXT: sqadd v1.2d, v1.2d, v3.2d
; CHECK-NEXT: cmlt v5.2d, v4.2d, #0
; CHECK-NEXT: dup v6.2d, x8
; CHECK-NEXT: mvn v7.16b, v5.16b
; CHECK-NEXT: mov v16.16b, v6.16b
; CHECK-NEXT: bsl v16.16b, v5.16b, v7.16b
; CHECK-NEXT: add v5.2d, v1.2d, v3.2d
; CHECK-NEXT: cmlt v2.2d, v2.2d, #0
; CHECK-NEXT: cmgt v0.2d, v0.2d, v4.2d
; CHECK-NEXT: cmlt v7.2d, v5.2d, #0
; CHECK-NEXT: cmlt v3.2d, v3.2d, #0
; CHECK-NEXT: cmgt v1.2d, v1.2d, v5.2d
; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
; CHECK-NEXT: mvn v2.16b, v7.16b
; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
; CHECK-NEXT: bsl v6.16b, v7.16b, v2.16b
; CHECK-NEXT: bsl v0.16b, v16.16b, v4.16b
; CHECK-NEXT: bsl v1.16b, v6.16b, v5.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> %x, <4 x i64> %y) %z = call <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
ret <4 x i64> %z ret <4 x i64> %z
} }
define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind { define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
; CHECK-LABEL: v8i64: ; CHECK-LABEL: v8i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v16.2d, v0.2d, v4.2d ; CHECK-NEXT: sqadd v0.2d, v0.2d, v4.2d
; CHECK-NEXT: mov x8, #9223372036854775807 ; CHECK-NEXT: sqadd v1.2d, v1.2d, v5.2d
; CHECK-NEXT: add v17.2d, v1.2d, v5.2d ; CHECK-NEXT: sqadd v2.2d, v2.2d, v6.2d
; CHECK-NEXT: cmlt v20.2d, v16.2d, #0 ; CHECK-NEXT: sqadd v3.2d, v3.2d, v7.2d
; CHECK-NEXT: dup v21.2d, x8
; CHECK-NEXT: add v18.2d, v2.2d, v6.2d
; CHECK-NEXT: cmlt v22.2d, v17.2d, #0
; CHECK-NEXT: mvn v24.16b, v20.16b
; CHECK-NEXT: mov v25.16b, v21.16b
; CHECK-NEXT: cmlt v23.2d, v18.2d, #0
; CHECK-NEXT: bsl v25.16b, v20.16b, v24.16b
; CHECK-NEXT: mvn v20.16b, v22.16b
; CHECK-NEXT: mov v24.16b, v21.16b
; CHECK-NEXT: cmlt v4.2d, v4.2d, #0
; CHECK-NEXT: cmgt v0.2d, v0.2d, v16.2d
; CHECK-NEXT: add v19.2d, v3.2d, v7.2d
; CHECK-NEXT: bsl v24.16b, v22.16b, v20.16b
; CHECK-NEXT: mvn v20.16b, v23.16b
; CHECK-NEXT: mov v22.16b, v21.16b
; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
; CHECK-NEXT: cmlt v4.2d, v5.2d, #0
; CHECK-NEXT: cmgt v1.2d, v1.2d, v17.2d
; CHECK-NEXT: bsl v22.16b, v23.16b, v20.16b
; CHECK-NEXT: cmlt v20.2d, v19.2d, #0
; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
; CHECK-NEXT: cmlt v4.2d, v6.2d, #0
; CHECK-NEXT: cmgt v2.2d, v2.2d, v18.2d
; CHECK-NEXT: mvn v23.16b, v20.16b
; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
; CHECK-NEXT: cmlt v4.2d, v7.2d, #0
; CHECK-NEXT: cmgt v3.2d, v3.2d, v19.2d
; CHECK-NEXT: bsl v21.16b, v20.16b, v23.16b
; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
; CHECK-NEXT: bsl v0.16b, v25.16b, v16.16b
; CHECK-NEXT: bsl v1.16b, v24.16b, v17.16b
; CHECK-NEXT: bsl v2.16b, v22.16b, v18.16b
; CHECK-NEXT: bsl v3.16b, v21.16b, v19.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> %x, <8 x i64> %y) %z = call <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
ret <8 x i64> %z ret <8 x i64> %z
} }
define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind { define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; CHECK-LABEL: v2i128: ; CHECK-LABEL: v2i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/ssub_sat.ll

Show First 20 Lines • Show All 82 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y); %tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y);
ret i4 %tmp; ret i4 %tmp;
} }
define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: vec: ; CHECK-LABEL: vec:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v2.4s, v0.4s, v1.4s ; CHECK-NEXT: sqsub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: cmlt v4.4s, v2.4s, #0
; CHECK-NEXT: mvni v3.4s, #128, lsl #24
; CHECK-NEXT: cmgt v1.4s, v1.4s, #0
; CHECK-NEXT: cmgt v0.4s, v0.4s, v2.4s
; CHECK-NEXT: mvn v5.16b, v4.16b
; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y); %tmp = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y);
ret <4 x i32> %tmp; ret <4 x i32> %tmp;
} }

llvm/test/CodeGen/AArch64/ssub_sat_vec.ll

Show All 30 Lines
declare <4 x i24> @llvm.ssub.sat.v4i24(<4 x i24>, <4 x i24>) declare <4 x i24> @llvm.ssub.sat.v4i24(<4 x i24>, <4 x i24>)
declare <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128>, <2 x i128>) declare <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128>, <2 x i128>)
define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind { define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; CHECK-LABEL: v16i8: ; CHECK-LABEL: v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v2.16b, v0.16b, v1.16b ; CHECK-NEXT: sqsub v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmlt v4.16b, v2.16b, #0
; CHECK-NEXT: movi v3.16b, #127
; CHECK-NEXT: cmgt v1.16b, v1.16b, #0
; CHECK-NEXT: cmgt v0.16b, v0.16b, v2.16b
; CHECK-NEXT: mvn v5.16b, v4.16b
; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %y) %z = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
ret <16 x i8> %z ret <16 x i8> %z
} }
define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind { define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
; CHECK-LABEL: v32i8: ; CHECK-LABEL: v32i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v4.16b, v0.16b, v2.16b ; CHECK-NEXT: sqsub v0.16b, v0.16b, v2.16b
; CHECK-NEXT: cmlt v7.16b, v4.16b, #0 ; CHECK-NEXT: sqsub v1.16b, v1.16b, v3.16b
; CHECK-NEXT: movi v6.16b, #127
; CHECK-NEXT: mvn v16.16b, v7.16b
; CHECK-NEXT: bsl v6.16b, v7.16b, v16.16b
; CHECK-NEXT: sub v7.16b, v1.16b, v3.16b
; CHECK-NEXT: cmgt v2.16b, v2.16b, #0
; CHECK-NEXT: cmgt v0.16b, v0.16b, v4.16b
; CHECK-NEXT: cmlt v16.16b, v7.16b, #0
; CHECK-NEXT: movi v5.16b, #127
; CHECK-NEXT: cmgt v3.16b, v3.16b, #0
; CHECK-NEXT: cmgt v1.16b, v1.16b, v7.16b
; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
; CHECK-NEXT: mvn v2.16b, v16.16b
; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
; CHECK-NEXT: bsl v5.16b, v16.16b, v2.16b
; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8> %x, <32 x i8> %y) %z = call <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8> %x, <32 x i8> %y)
ret <32 x i8> %z ret <32 x i8> %z
} }
define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind { define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
; CHECK-LABEL: v64i8: ; CHECK-LABEL: v64i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v16.16b, v0.16b, v4.16b ; CHECK-NEXT: sqsub v0.16b, v0.16b, v4.16b
; CHECK-NEXT: cmlt v24.16b, v16.16b, #0 ; CHECK-NEXT: sqsub v1.16b, v1.16b, v5.16b
; CHECK-NEXT: movi v18.16b, #127 ; CHECK-NEXT: sqsub v2.16b, v2.16b, v6.16b
; CHECK-NEXT: sub v19.16b, v1.16b, v5.16b ; CHECK-NEXT: sqsub v3.16b, v3.16b, v7.16b
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.16b, v19.16b, #0
; CHECK-NEXT: movi v20.16b, #127
; CHECK-NEXT: sub v21.16b, v2.16b, v6.16b
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.16b, v21.16b, #0
; CHECK-NEXT: cmgt v4.16b, v4.16b, #0
; CHECK-NEXT: cmgt v0.16b, v0.16b, v16.16b
; CHECK-NEXT: movi v22.16b, #127
; CHECK-NEXT: sub v23.16b, v3.16b, v7.16b
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
; CHECK-NEXT: cmgt v4.16b, v5.16b, #0
; CHECK-NEXT: cmgt v1.16b, v1.16b, v19.16b
; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.16b, v23.16b, #0
; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
; CHECK-NEXT: cmgt v4.16b, v6.16b, #0
; CHECK-NEXT: cmgt v2.16b, v2.16b, v21.16b
; CHECK-NEXT: movi v17.16b, #127
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
; CHECK-NEXT: cmgt v4.16b, v7.16b, #0
; CHECK-NEXT: cmgt v3.16b, v3.16b, v23.16b
; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8> %x, <64 x i8> %y) %z = call <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8> %x, <64 x i8> %y)
ret <64 x i8> %z ret <64 x i8> %z
} }
define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind { define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; CHECK-LABEL: v8i16: ; CHECK-LABEL: v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v2.8h, v0.8h, v1.8h ; CHECK-NEXT: sqsub v0.8h, v0.8h, v1.8h
; CHECK-NEXT: cmlt v4.8h, v2.8h, #0
; CHECK-NEXT: mvni v3.8h, #128, lsl #8
; CHECK-NEXT: cmgt v1.8h, v1.8h, #0
; CHECK-NEXT: cmgt v0.8h, v0.8h, v2.8h
; CHECK-NEXT: mvn v5.16b, v4.16b
; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %y) %z = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
ret <8 x i16> %z ret <8 x i16> %z
} }
define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind { define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {
; CHECK-LABEL: v16i16: ; CHECK-LABEL: v16i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v4.8h, v0.8h, v2.8h ; CHECK-NEXT: sqsub v0.8h, v0.8h, v2.8h
; CHECK-NEXT: cmlt v7.8h, v4.8h, #0 ; CHECK-NEXT: sqsub v1.8h, v1.8h, v3.8h
; CHECK-NEXT: mvni v6.8h, #128, lsl #8
; CHECK-NEXT: mvn v16.16b, v7.16b
; CHECK-NEXT: bsl v6.16b, v7.16b, v16.16b
; CHECK-NEXT: sub v7.8h, v1.8h, v3.8h
; CHECK-NEXT: cmgt v2.8h, v2.8h, #0
; CHECK-NEXT: cmgt v0.8h, v0.8h, v4.8h
; CHECK-NEXT: cmlt v16.8h, v7.8h, #0
; CHECK-NEXT: mvni v5.8h, #128, lsl #8
; CHECK-NEXT: cmgt v3.8h, v3.8h, #0
; CHECK-NEXT: cmgt v1.8h, v1.8h, v7.8h
; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
; CHECK-NEXT: mvn v2.16b, v16.16b
; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
; CHECK-NEXT: bsl v5.16b, v16.16b, v2.16b
; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> %x, <16 x i16> %y) %z = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> %x, <16 x i16> %y)
ret <16 x i16> %z ret <16 x i16> %z
} }
define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind { define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {
; CHECK-LABEL: v32i16: ; CHECK-LABEL: v32i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v16.8h, v0.8h, v4.8h ; CHECK-NEXT: sqsub v0.8h, v0.8h, v4.8h
; CHECK-NEXT: cmlt v24.8h, v16.8h, #0 ; CHECK-NEXT: sqsub v1.8h, v1.8h, v5.8h
; CHECK-NEXT: mvni v18.8h, #128, lsl #8 ; CHECK-NEXT: sqsub v2.8h, v2.8h, v6.8h
; CHECK-NEXT: sub v19.8h, v1.8h, v5.8h ; CHECK-NEXT: sqsub v3.8h, v3.8h, v7.8h
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.8h, v19.8h, #0
; CHECK-NEXT: mvni v20.8h, #128, lsl #8
; CHECK-NEXT: sub v21.8h, v2.8h, v6.8h
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.8h, v21.8h, #0
; CHECK-NEXT: cmgt v4.8h, v4.8h, #0
; CHECK-NEXT: cmgt v0.8h, v0.8h, v16.8h
; CHECK-NEXT: mvni v22.8h, #128, lsl #8
; CHECK-NEXT: sub v23.8h, v3.8h, v7.8h
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
; CHECK-NEXT: cmgt v4.8h, v5.8h, #0
; CHECK-NEXT: cmgt v1.8h, v1.8h, v19.8h
; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.8h, v23.8h, #0
; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
; CHECK-NEXT: cmgt v4.8h, v6.8h, #0
; CHECK-NEXT: cmgt v2.8h, v2.8h, v21.8h
; CHECK-NEXT: mvni v17.8h, #128, lsl #8
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
; CHECK-NEXT: cmgt v4.8h, v7.8h, #0
; CHECK-NEXT: cmgt v3.8h, v3.8h, v23.8h
; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16> %x, <32 x i16> %y) %z = call <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16> %x, <32 x i16> %y)
ret <32 x i16> %z ret <32 x i16> %z
} }
define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind { define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind {
; CHECK-LABEL: v8i8: ; CHECK-LABEL: v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: movi v2.8b, #127 ; CHECK-NEXT: sqsub v0.8b, v0.8b, v1.8b
; CHECK-NEXT: sub v3.8b, v0.8b, v1.8b
; CHECK-NEXT: cmlt v4.8b, v3.8b, #0
; CHECK-NEXT: cmgt v1.8b, v1.8b, #0
; CHECK-NEXT: cmgt v0.8b, v0.8b, v3.8b
; CHECK-NEXT: mvn v5.8b, v4.8b
; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
; CHECK-NEXT: str d0, [x2] ; CHECK-NEXT: str d0, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <8 x i8>, <8 x i8>* %px %x = load <8 x i8>, <8 x i8>* %px
%y = load <8 x i8>, <8 x i8>* %py %y = load <8 x i8>, <8 x i8>* %py
%z = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> %x, <8 x i8> %y) %z = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> %x, <8 x i8> %y)
store <8 x i8> %z, <8 x i8>* %pz store <8 x i8> %z, <8 x i8>* %pz
ret void ret void
} }
▲ Show 20 Lines • Show All 60 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret void ret void
} }
define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind { define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind {
; CHECK-LABEL: v4i16: ; CHECK-LABEL: v4i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: mvni v2.4h, #128, lsl #8 ; CHECK-NEXT: sqsub v0.4h, v0.4h, v1.4h
; CHECK-NEXT: sub v3.4h, v0.4h, v1.4h
; CHECK-NEXT: cmlt v4.4h, v3.4h, #0
; CHECK-NEXT: cmgt v1.4h, v1.4h, #0
; CHECK-NEXT: cmgt v0.4h, v0.4h, v3.4h
; CHECK-NEXT: mvn v5.8b, v4.8b
; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
; CHECK-NEXT: str d0, [x2] ; CHECK-NEXT: str d0, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <4 x i16>, <4 x i16>* %px %x = load <4 x i16>, <4 x i16>* %px
%y = load <4 x i16>, <4 x i16>* %py %y = load <4 x i16>, <4 x i16>* %py
%z = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %x, <4 x i16> %y) %z = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %x, <4 x i16> %y)
store <4 x i16> %z, <4 x i16>* %pz store <4 x i16> %z, <4 x i16>* %pz
ret void ret void
} }
Show All 24 Lines; CHECK-NEXT: ret
%z = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %x, <2 x i16> %y) %z = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
store <2 x i16> %z, <2 x i16>* %pz store <2 x i16> %z, <2 x i16>* %pz
ret void ret void
} }
define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind { define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {
; CHECK-LABEL: v12i8: ; CHECK-LABEL: v12i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v2.16b, v0.16b, v1.16b ; CHECK-NEXT: sqsub v0.16b, v0.16b, v1.16b
; CHECK-NEXT: cmlt v4.16b, v2.16b, #0
; CHECK-NEXT: movi v3.16b, #127
; CHECK-NEXT: cmgt v1.16b, v1.16b, #0
; CHECK-NEXT: cmgt v0.16b, v0.16b, v2.16b
; CHECK-NEXT: mvn v5.16b, v4.16b
; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <12 x i8> @llvm.ssub.sat.v12i8(<12 x i8> %x, <12 x i8> %y) %z = call <12 x i8> @llvm.ssub.sat.v12i8(<12 x i8> %x, <12 x i8> %y)
ret <12 x i8> %z ret <12 x i8> %z
} }
define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind { define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind {
; CHECK-LABEL: v12i16: ; CHECK-LABEL: v12i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ldp q3, q2, [x1] ; CHECK-NEXT: ldp q3, q2, [x1]
; CHECK-NEXT: mvni v5.8h, #128, lsl #8 ; CHECK-NEXT: sqsub v1.8h, v1.8h, v2.8h
; CHECK-NEXT: mvni v4.8h, #128, lsl #8 ; CHECK-NEXT: sqsub v0.8h, v0.8h, v3.8h
; CHECK-NEXT: sub v6.8h, v1.8h, v2.8h
; CHECK-NEXT: cmlt v7.8h, v6.8h, #0
; CHECK-NEXT: mvn v16.16b, v7.16b
; CHECK-NEXT: bsl v5.16b, v7.16b, v16.16b
; CHECK-NEXT: sub v7.8h, v0.8h, v3.8h
; CHECK-NEXT: cmgt v2.8h, v2.8h, #0
; CHECK-NEXT: cmgt v1.8h, v1.8h, v6.8h
; CHECK-NEXT: cmlt v16.8h, v7.8h, #0
; CHECK-NEXT: cmgt v3.8h, v3.8h, #0
; CHECK-NEXT: cmgt v0.8h, v0.8h, v7.8h
; CHECK-NEXT: eor v1.16b, v2.16b, v1.16b
; CHECK-NEXT: mvn v2.16b, v16.16b
; CHECK-NEXT: eor v0.16b, v3.16b, v0.16b
; CHECK-NEXT: bsl v4.16b, v16.16b, v2.16b
; CHECK-NEXT: bsl v1.16b, v5.16b, v6.16b
; CHECK-NEXT: bsl v0.16b, v4.16b, v7.16b
; CHECK-NEXT: str q0, [x2] ; CHECK-NEXT: str q0, [x2]
; CHECK-NEXT: str d1, [x2, #16] ; CHECK-NEXT: str d1, [x2, #16]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <12 x i16>, <12 x i16>* %px %x = load <12 x i16>, <12 x i16>* %px
%y = load <12 x i16>, <12 x i16>* %py %y = load <12 x i16>, <12 x i16>* %py
%z = call <12 x i16> @llvm.ssub.sat.v12i16(<12 x i16> %x, <12 x i16> %y) %z = call <12 x i16> @llvm.ssub.sat.v12i16(<12 x i16> %x, <12 x i16> %y)
store <12 x i16> %z, <12 x i16>* %pz store <12 x i16> %z, <12 x i16>* %pz
ret void ret void
} }
define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind { define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
; CHECK-LABEL: v1i8: ; CHECK-LABEL: v1i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr b0, [x0] ; CHECK-NEXT: ldr b0, [x0]
; CHECK-NEXT: ldr b1, [x1] ; CHECK-NEXT: ldr b1, [x1]
; CHECK-NEXT: movi v2.8b, #127 ; CHECK-NEXT: sqsub v0.8b, v0.8b, v1.8b
; CHECK-NEXT: sub v3.8b, v0.8b, v1.8b
; CHECK-NEXT: cmlt v4.8b, v3.8b, #0
; CHECK-NEXT: cmgt v1.8b, v1.8b, #0
; CHECK-NEXT: cmgt v0.8b, v0.8b, v3.8b
; CHECK-NEXT: mvn v5.8b, v4.8b
; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
; CHECK-NEXT: st1 { v0.b }[0], [x2] ; CHECK-NEXT: st1 { v0.b }[0], [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <1 x i8>, <1 x i8>* %px %x = load <1 x i8>, <1 x i8>* %px
%y = load <1 x i8>, <1 x i8>* %py %y = load <1 x i8>, <1 x i8>* %py
%z = call <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8> %x, <1 x i8> %y) %z = call <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
store <1 x i8> %z, <1 x i8>* %pz store <1 x i8> %z, <1 x i8>* %pz
ret void ret void
} }
define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind { define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
; CHECK-LABEL: v1i16: ; CHECK-LABEL: v1i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr h0, [x0] ; CHECK-NEXT: ldr h0, [x0]
; CHECK-NEXT: ldr h1, [x1] ; CHECK-NEXT: ldr h1, [x1]
; CHECK-NEXT: mvni v2.4h, #128, lsl #8 ; CHECK-NEXT: sqsub v0.4h, v0.4h, v1.4h
; CHECK-NEXT: sub v3.4h, v0.4h, v1.4h
; CHECK-NEXT: cmlt v4.4h, v3.4h, #0
; CHECK-NEXT: cmgt v1.4h, v1.4h, #0
; CHECK-NEXT: cmgt v0.4h, v0.4h, v3.4h
; CHECK-NEXT: mvn v5.8b, v4.8b
; CHECK-NEXT: bsl v2.8b, v4.8b, v5.8b
; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
; CHECK-NEXT: bsl v0.8b, v2.8b, v3.8b
; CHECK-NEXT: str h0, [x2] ; CHECK-NEXT: str h0, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <1 x i16>, <1 x i16>* %px %x = load <1 x i16>, <1 x i16>* %px
%y = load <1 x i16>, <1 x i16>* %py %y = load <1 x i16>, <1 x i16>* %py
%z = call <1 x i16> @llvm.ssub.sat.v1i16(<1 x i16> %x, <1 x i16> %y) %z = call <1 x i16> @llvm.ssub.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
store <1 x i16> %z, <1 x i16>* %pz store <1 x i16> %z, <1 x i16>* %pz
ret void ret void
} }
Show All 30 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i1> @llvm.ssub.sat.v16i1(<16 x i1> %x, <16 x i1> %y) %z = call <16 x i1> @llvm.ssub.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
ret <16 x i1> %z ret <16 x i1> %z
} }
define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind { define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; CHECK-LABEL: v2i32: ; CHECK-LABEL: v2i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v2.2s, v0.2s, v1.2s ; CHECK-NEXT: sqsub v0.2s, v0.2s, v1.2s
; CHECK-NEXT: cmlt v4.2s, v2.2s, #0
; CHECK-NEXT: mvni v3.2s, #128, lsl #24
; CHECK-NEXT: cmgt v1.2s, v1.2s, #0
; CHECK-NEXT: cmgt v0.2s, v0.2s, v2.2s
; CHECK-NEXT: mvn v5.8b, v4.8b
; CHECK-NEXT: bsl v3.8b, v4.8b, v5.8b
; CHECK-NEXT: eor v0.8b, v1.8b, v0.8b
; CHECK-NEXT: bsl v0.8b, v3.8b, v2.8b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %x, <2 x i32> %y) %z = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %x, <2 x i32> %y)
ret <2 x i32> %z ret <2 x i32> %z
} }
define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: v4i32: ; CHECK-LABEL: v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v2.4s, v0.4s, v1.4s ; CHECK-NEXT: sqsub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: cmlt v4.4s, v2.4s, #0
; CHECK-NEXT: mvni v3.4s, #128, lsl #24
; CHECK-NEXT: cmgt v1.4s, v1.4s, #0
; CHECK-NEXT: cmgt v0.4s, v0.4s, v2.4s
; CHECK-NEXT: mvn v5.16b, v4.16b
; CHECK-NEXT: bsl v3.16b, v4.16b, v5.16b
; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
; CHECK-NEXT: bsl v0.16b, v3.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y) %z = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
ret <4 x i32> %z ret <4 x i32> %z
} }
define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind { define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
; CHECK-LABEL: v8i32: ; CHECK-LABEL: v8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v4.4s, v0.4s, v2.4s ; CHECK-NEXT: sqsub v0.4s, v0.4s, v2.4s
; CHECK-NEXT: cmlt v7.4s, v4.4s, #0 ; CHECK-NEXT: sqsub v1.4s, v1.4s, v3.4s
; CHECK-NEXT: mvni v6.4s, #128, lsl #24
; CHECK-NEXT: mvn v16.16b, v7.16b
; CHECK-NEXT: bsl v6.16b, v7.16b, v16.16b
; CHECK-NEXT: sub v7.4s, v1.4s, v3.4s
; CHECK-NEXT: cmgt v2.4s, v2.4s, #0
; CHECK-NEXT: cmgt v0.4s, v0.4s, v4.4s
; CHECK-NEXT: cmlt v16.4s, v7.4s, #0
; CHECK-NEXT: mvni v5.4s, #128, lsl #24
; CHECK-NEXT: cmgt v3.4s, v3.4s, #0
; CHECK-NEXT: cmgt v1.4s, v1.4s, v7.4s
; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
; CHECK-NEXT: mvn v2.16b, v16.16b
; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
; CHECK-NEXT: bsl v5.16b, v16.16b, v2.16b
; CHECK-NEXT: bsl v0.16b, v6.16b, v4.16b
; CHECK-NEXT: bsl v1.16b, v5.16b, v7.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %x, <8 x i32> %y) %z = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %x, <8 x i32> %y)
ret <8 x i32> %z ret <8 x i32> %z
} }
define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind { define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
; CHECK-LABEL: v16i32: ; CHECK-LABEL: v16i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v16.4s, v0.4s, v4.4s ; CHECK-NEXT: sqsub v0.4s, v0.4s, v4.4s
; CHECK-NEXT: cmlt v24.4s, v16.4s, #0 ; CHECK-NEXT: sqsub v1.4s, v1.4s, v5.4s
; CHECK-NEXT: mvni v18.4s, #128, lsl #24 ; CHECK-NEXT: sqsub v2.4s, v2.4s, v6.4s
; CHECK-NEXT: sub v19.4s, v1.4s, v5.4s ; CHECK-NEXT: sqsub v3.4s, v3.4s, v7.4s
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: bsl v18.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.4s, v19.4s, #0
; CHECK-NEXT: mvni v20.4s, #128, lsl #24
; CHECK-NEXT: sub v21.4s, v2.4s, v6.4s
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: bsl v20.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.4s, v21.4s, #0
; CHECK-NEXT: cmgt v4.4s, v4.4s, #0
; CHECK-NEXT: cmgt v0.4s, v0.4s, v16.4s
; CHECK-NEXT: mvni v22.4s, #128, lsl #24
; CHECK-NEXT: sub v23.4s, v3.4s, v7.4s
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
; CHECK-NEXT: cmgt v4.4s, v5.4s, #0
; CHECK-NEXT: cmgt v1.4s, v1.4s, v19.4s
; CHECK-NEXT: bsl v22.16b, v24.16b, v25.16b
; CHECK-NEXT: cmlt v24.4s, v23.4s, #0
; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
; CHECK-NEXT: cmgt v4.4s, v6.4s, #0
; CHECK-NEXT: cmgt v2.4s, v2.4s, v21.4s
; CHECK-NEXT: mvni v17.4s, #128, lsl #24
; CHECK-NEXT: mvn v25.16b, v24.16b
; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
; CHECK-NEXT: cmgt v4.4s, v7.4s, #0
; CHECK-NEXT: cmgt v3.4s, v3.4s, v23.4s
; CHECK-NEXT: bsl v17.16b, v24.16b, v25.16b
; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
; CHECK-NEXT: bsl v0.16b, v18.16b, v16.16b
; CHECK-NEXT: bsl v1.16b, v20.16b, v19.16b
; CHECK-NEXT: bsl v2.16b, v22.16b, v21.16b
; CHECK-NEXT: bsl v3.16b, v17.16b, v23.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %x, <16 x i32> %y) %z = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %x, <16 x i32> %y)
ret <16 x i32> %z ret <16 x i32> %z
} }
define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind { define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; CHECK-LABEL: v2i64: ; CHECK-LABEL: v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v2.2d, v0.2d, v1.2d ; CHECK-NEXT: sqsub v0.2d, v0.2d, v1.2d
; CHECK-NEXT: mov x8, #9223372036854775807
; CHECK-NEXT: cmlt v3.2d, v2.2d, #0
; CHECK-NEXT: cmgt v1.2d, v1.2d, #0
; CHECK-NEXT: dup v4.2d, x8
; CHECK-NEXT: cmgt v0.2d, v0.2d, v2.2d
; CHECK-NEXT: mvn v5.16b, v3.16b
; CHECK-NEXT: bsl v4.16b, v3.16b, v5.16b
; CHECK-NEXT: eor v0.16b, v1.16b, v0.16b
; CHECK-NEXT: bsl v0.16b, v4.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %x, <2 x i64> %y) %z = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
ret <2 x i64> %z ret <2 x i64> %z
} }
define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind { define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
; CHECK-LABEL: v4i64: ; CHECK-LABEL: v4i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v4.2d, v0.2d, v2.2d ; CHECK-NEXT: sqsub v0.2d, v0.2d, v2.2d
; CHECK-NEXT: mov x8, #9223372036854775807 ; CHECK-NEXT: sqsub v1.2d, v1.2d, v3.2d
; CHECK-NEXT: cmlt v5.2d, v4.2d, #0
; CHECK-NEXT: dup v6.2d, x8
; CHECK-NEXT: mvn v7.16b, v5.16b
; CHECK-NEXT: mov v16.16b, v6.16b
; CHECK-NEXT: bsl v16.16b, v5.16b, v7.16b
; CHECK-NEXT: sub v5.2d, v1.2d, v3.2d
; CHECK-NEXT: cmgt v2.2d, v2.2d, #0
; CHECK-NEXT: cmgt v0.2d, v0.2d, v4.2d
; CHECK-NEXT: cmlt v7.2d, v5.2d, #0
; CHECK-NEXT: cmgt v3.2d, v3.2d, #0
; CHECK-NEXT: cmgt v1.2d, v1.2d, v5.2d
; CHECK-NEXT: eor v0.16b, v2.16b, v0.16b
; CHECK-NEXT: mvn v2.16b, v7.16b
; CHECK-NEXT: eor v1.16b, v3.16b, v1.16b
; CHECK-NEXT: bsl v6.16b, v7.16b, v2.16b
; CHECK-NEXT: bsl v0.16b, v16.16b, v4.16b
; CHECK-NEXT: bsl v1.16b, v6.16b, v5.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> %x, <4 x i64> %y) %z = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
ret <4 x i64> %z ret <4 x i64> %z
} }
define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind { define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
; CHECK-LABEL: v8i64: ; CHECK-LABEL: v8i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v16.2d, v0.2d, v4.2d ; CHECK-NEXT: sqsub v0.2d, v0.2d, v4.2d
; CHECK-NEXT: mov x8, #9223372036854775807 ; CHECK-NEXT: sqsub v1.2d, v1.2d, v5.2d
; CHECK-NEXT: sub v17.2d, v1.2d, v5.2d ; CHECK-NEXT: sqsub v2.2d, v2.2d, v6.2d
; CHECK-NEXT: cmlt v20.2d, v16.2d, #0 ; CHECK-NEXT: sqsub v3.2d, v3.2d, v7.2d
; CHECK-NEXT: dup v21.2d, x8
; CHECK-NEXT: sub v18.2d, v2.2d, v6.2d
; CHECK-NEXT: cmlt v22.2d, v17.2d, #0
; CHECK-NEXT: mvn v24.16b, v20.16b
; CHECK-NEXT: mov v25.16b, v21.16b
; CHECK-NEXT: cmlt v23.2d, v18.2d, #0
; CHECK-NEXT: bsl v25.16b, v20.16b, v24.16b
; CHECK-NEXT: mvn v20.16b, v22.16b
; CHECK-NEXT: mov v24.16b, v21.16b
; CHECK-NEXT: cmgt v4.2d, v4.2d, #0
; CHECK-NEXT: cmgt v0.2d, v0.2d, v16.2d
; CHECK-NEXT: sub v19.2d, v3.2d, v7.2d
; CHECK-NEXT: bsl v24.16b, v22.16b, v20.16b
; CHECK-NEXT: mvn v20.16b, v23.16b
; CHECK-NEXT: mov v22.16b, v21.16b
; CHECK-NEXT: eor v0.16b, v4.16b, v0.16b
; CHECK-NEXT: cmgt v4.2d, v5.2d, #0
; CHECK-NEXT: cmgt v1.2d, v1.2d, v17.2d
; CHECK-NEXT: bsl v22.16b, v23.16b, v20.16b
; CHECK-NEXT: cmlt v20.2d, v19.2d, #0
; CHECK-NEXT: eor v1.16b, v4.16b, v1.16b
; CHECK-NEXT: cmgt v4.2d, v6.2d, #0
; CHECK-NEXT: cmgt v2.2d, v2.2d, v18.2d
; CHECK-NEXT: mvn v23.16b, v20.16b
; CHECK-NEXT: eor v2.16b, v4.16b, v2.16b
; CHECK-NEXT: cmgt v4.2d, v7.2d, #0
; CHECK-NEXT: cmgt v3.2d, v3.2d, v19.2d
; CHECK-NEXT: bsl v21.16b, v20.16b, v23.16b
; CHECK-NEXT: eor v3.16b, v4.16b, v3.16b
; CHECK-NEXT: bsl v0.16b, v25.16b, v16.16b
; CHECK-NEXT: bsl v1.16b, v24.16b, v17.16b
; CHECK-NEXT: bsl v2.16b, v22.16b, v18.16b
; CHECK-NEXT: bsl v3.16b, v21.16b, v19.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %x, <8 x i64> %y) %z = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
ret <8 x i64> %z ret <8 x i64> %z
} }
define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind { define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; CHECK-LABEL: v2i128: ; CHECK-LABEL: v2i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
▲ Show 20 Lines • Show All 48 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/uadd_sat_vec.ll

Show All 29 Lines
declare <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64>, <8 x i64>) declare <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64>, <8 x i64>)
declare <4 x i24> @llvm.uadd.sat.v4i24(<4 x i24>, <4 x i24>) declare <4 x i24> @llvm.uadd.sat.v4i24(<4 x i24>, <4 x i24>)
declare <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128>, <2 x i128>) declare <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128>, <2 x i128>)
define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind { define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; CHECK-LABEL: v16i8: ; CHECK-LABEL: v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mvn v2.16b, v1.16b ; CHECK-NEXT: uqadd v0.16b, v0.16b, v1.16b
; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y) %z = call <16 x i8> @llvm.uadd.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
ret <16 x i8> %z ret <16 x i8> %z
} }
define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind { define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
; CHECK-LABEL: v32i8: ; CHECK-LABEL: v32i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mvn v4.16b, v2.16b ; CHECK-NEXT: uqadd v0.16b, v0.16b, v2.16b
; CHECK-NEXT: mvn v5.16b, v3.16b ; CHECK-NEXT: uqadd v1.16b, v1.16b, v3.16b
; CHECK-NEXT: umin v0.16b, v0.16b, v4.16b
; CHECK-NEXT: umin v1.16b, v1.16b, v5.16b
; CHECK-NEXT: add v0.16b, v0.16b, v2.16b
; CHECK-NEXT: add v1.16b, v1.16b, v3.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8> %x, <32 x i8> %y) %z = call <32 x i8> @llvm.uadd.sat.v32i8(<32 x i8> %x, <32 x i8> %y)
ret <32 x i8> %z ret <32 x i8> %z
} }
define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind { define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
; CHECK-LABEL: v64i8: ; CHECK-LABEL: v64i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mvn v16.16b, v4.16b ; CHECK-NEXT: uqadd v0.16b, v0.16b, v4.16b
; CHECK-NEXT: umin v0.16b, v0.16b, v16.16b ; CHECK-NEXT: uqadd v1.16b, v1.16b, v5.16b
; CHECK-NEXT: mvn v16.16b, v5.16b ; CHECK-NEXT: uqadd v2.16b, v2.16b, v6.16b
; CHECK-NEXT: umin v1.16b, v1.16b, v16.16b ; CHECK-NEXT: uqadd v3.16b, v3.16b, v7.16b
; CHECK-NEXT: mvn v16.16b, v6.16b
; CHECK-NEXT: umin v2.16b, v2.16b, v16.16b
; CHECK-NEXT: mvn v16.16b, v7.16b
; CHECK-NEXT: umin v3.16b, v3.16b, v16.16b
; CHECK-NEXT: add v0.16b, v0.16b, v4.16b
; CHECK-NEXT: add v1.16b, v1.16b, v5.16b
; CHECK-NEXT: add v2.16b, v2.16b, v6.16b
; CHECK-NEXT: add v3.16b, v3.16b, v7.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> %x, <64 x i8> %y) %z = call <64 x i8> @llvm.uadd.sat.v64i8(<64 x i8> %x, <64 x i8> %y)
ret <64 x i8> %z ret <64 x i8> %z
} }
define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind { define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; CHECK-LABEL: v8i16: ; CHECK-LABEL: v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mvn v2.16b, v1.16b ; CHECK-NEXT: uqadd v0.8h, v0.8h, v1.8h
; CHECK-NEXT: umin v0.8h, v0.8h, v2.8h
; CHECK-NEXT: add v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y) %z = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
ret <8 x i16> %z ret <8 x i16> %z
} }
define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind { define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {
; CHECK-LABEL: v16i16: ; CHECK-LABEL: v16i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mvn v4.16b, v2.16b ; CHECK-NEXT: uqadd v0.8h, v0.8h, v2.8h
; CHECK-NEXT: mvn v5.16b, v3.16b ; CHECK-NEXT: uqadd v1.8h, v1.8h, v3.8h
; CHECK-NEXT: umin v0.8h, v0.8h, v4.8h
; CHECK-NEXT: umin v1.8h, v1.8h, v5.8h
; CHECK-NEXT: add v0.8h, v0.8h, v2.8h
; CHECK-NEXT: add v1.8h, v1.8h, v3.8h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> %x, <16 x i16> %y) %z = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> %x, <16 x i16> %y)
ret <16 x i16> %z ret <16 x i16> %z
} }
define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind { define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {
; CHECK-LABEL: v32i16: ; CHECK-LABEL: v32i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mvn v16.16b, v4.16b ; CHECK-NEXT: uqadd v0.8h, v0.8h, v4.8h
; CHECK-NEXT: umin v0.8h, v0.8h, v16.8h ; CHECK-NEXT: uqadd v1.8h, v1.8h, v5.8h
; CHECK-NEXT: mvn v16.16b, v5.16b ; CHECK-NEXT: uqadd v2.8h, v2.8h, v6.8h
; CHECK-NEXT: umin v1.8h, v1.8h, v16.8h ; CHECK-NEXT: uqadd v3.8h, v3.8h, v7.8h
; CHECK-NEXT: mvn v16.16b, v6.16b
; CHECK-NEXT: umin v2.8h, v2.8h, v16.8h
; CHECK-NEXT: mvn v16.16b, v7.16b
; CHECK-NEXT: umin v3.8h, v3.8h, v16.8h
; CHECK-NEXT: add v0.8h, v0.8h, v4.8h
; CHECK-NEXT: add v1.8h, v1.8h, v5.8h
; CHECK-NEXT: add v2.8h, v2.8h, v6.8h
; CHECK-NEXT: add v3.8h, v3.8h, v7.8h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16> %x, <32 x i16> %y) %z = call <32 x i16> @llvm.uadd.sat.v32i16(<32 x i16> %x, <32 x i16> %y)
ret <32 x i16> %z ret <32 x i16> %z
} }
define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind { define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind {
; CHECK-LABEL: v8i8: ; CHECK-LABEL: v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x1] ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x0] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: mvn v2.8b, v0.8b ; CHECK-NEXT: uqadd v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umin v1.8b, v1.8b, v2.8b
; CHECK-NEXT: add v0.8b, v1.8b, v0.8b
; CHECK-NEXT: str d0, [x2] ; CHECK-NEXT: str d0, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <8 x i8>, <8 x i8>* %px %x = load <8 x i8>, <8 x i8>* %px
%y = load <8 x i8>, <8 x i8>* %py %y = load <8 x i8>, <8 x i8>* %py
%z = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> %x, <8 x i8> %y) %z = call <8 x i8> @llvm.uadd.sat.v8i8(<8 x i8> %x, <8 x i8> %y)
store <8 x i8> %z, <8 x i8>* %pz store <8 x i8> %z, <8 x i8>* %pz
ret void ret void
} }
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%z = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %x, <2 x i8> %y) %z = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
store <2 x i8> %z, <2 x i8>* %pz store <2 x i8> %z, <2 x i8>* %pz
ret void ret void
} }
define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind { define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind {
; CHECK-LABEL: v4i16: ; CHECK-LABEL: v4i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x1] ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x0] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: mvn v2.8b, v0.8b ; CHECK-NEXT: uqadd v0.4h, v0.4h, v1.4h
; CHECK-NEXT: umin v1.4h, v1.4h, v2.4h
; CHECK-NEXT: add v0.4h, v1.4h, v0.4h
; CHECK-NEXT: str d0, [x2] ; CHECK-NEXT: str d0, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <4 x i16>, <4 x i16>* %px %x = load <4 x i16>, <4 x i16>* %px
%y = load <4 x i16>, <4 x i16>* %py %y = load <4 x i16>, <4 x i16>* %py
%z = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %x, <4 x i16> %y) %z = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %x, <4 x i16> %y)
store <4 x i16> %z, <4 x i16>* %pz store <4 x i16> %z, <4 x i16>* %pz
ret void ret void
} }
Show All 22 Lines; CHECK-NEXT: ret
%z = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %x, <2 x i16> %y) %z = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
store <2 x i16> %z, <2 x i16>* %pz store <2 x i16> %z, <2 x i16>* %pz
ret void ret void
} }
define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind { define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {
; CHECK-LABEL: v12i8: ; CHECK-LABEL: v12i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mvn v2.16b, v1.16b ; CHECK-NEXT: uqadd v0.16b, v0.16b, v1.16b
; CHECK-NEXT: umin v0.16b, v0.16b, v2.16b
; CHECK-NEXT: add v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <12 x i8> @llvm.uadd.sat.v12i8(<12 x i8> %x, <12 x i8> %y) %z = call <12 x i8> @llvm.uadd.sat.v12i8(<12 x i8> %x, <12 x i8> %y)
ret <12 x i8> %z ret <12 x i8> %z
} }
define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind { define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind {
; CHECK-LABEL: v12i16: ; CHECK-LABEL: v12i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x1] ; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ldp q3, q2, [x0] ; CHECK-NEXT: ldp q3, q2, [x1]
; CHECK-NEXT: mvn v4.16b, v0.16b ; CHECK-NEXT: uqadd v1.8h, v1.8h, v2.8h
; CHECK-NEXT: mvn v5.16b, v1.16b ; CHECK-NEXT: uqadd v0.8h, v0.8h, v3.8h
; CHECK-NEXT: umin v2.8h, v2.8h, v4.8h ; CHECK-NEXT: str q0, [x2]
; CHECK-NEXT: umin v3.8h, v3.8h, v5.8h ; CHECK-NEXT: str d1, [x2, #16]
; CHECK-NEXT: add v0.8h, v2.8h, v0.8h
; CHECK-NEXT: add v1.8h, v3.8h, v1.8h
; CHECK-NEXT: str q1, [x2]
; CHECK-NEXT: str d0, [x2, #16]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <12 x i16>, <12 x i16>* %px %x = load <12 x i16>, <12 x i16>* %px
%y = load <12 x i16>, <12 x i16>* %py %y = load <12 x i16>, <12 x i16>* %py
%z = call <12 x i16> @llvm.uadd.sat.v12i16(<12 x i16> %x, <12 x i16> %y) %z = call <12 x i16> @llvm.uadd.sat.v12i16(<12 x i16> %x, <12 x i16> %y)
store <12 x i16> %z, <12 x i16>* %pz store <12 x i16> %z, <12 x i16>* %pz
ret void ret void
} }
define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind { define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
; CHECK-LABEL: v1i8: ; CHECK-LABEL: v1i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr b0, [x1] ; CHECK-NEXT: ldr b0, [x0]
; CHECK-NEXT: ldr b1, [x0] ; CHECK-NEXT: ldr b1, [x1]
; CHECK-NEXT: mvn v2.8b, v0.8b ; CHECK-NEXT: uqadd v0.8b, v0.8b, v1.8b
; CHECK-NEXT: umin v1.8b, v1.8b, v2.8b
; CHECK-NEXT: add v0.8b, v1.8b, v0.8b
; CHECK-NEXT: st1 { v0.b }[0], [x2] ; CHECK-NEXT: st1 { v0.b }[0], [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <1 x i8>, <1 x i8>* %px %x = load <1 x i8>, <1 x i8>* %px
%y = load <1 x i8>, <1 x i8>* %py %y = load <1 x i8>, <1 x i8>* %py
%z = call <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8> %x, <1 x i8> %y) %z = call <1 x i8> @llvm.uadd.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
store <1 x i8> %z, <1 x i8>* %pz store <1 x i8> %z, <1 x i8>* %pz
ret void ret void
} }
define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind { define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
; CHECK-LABEL: v1i16: ; CHECK-LABEL: v1i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr h0, [x1] ; CHECK-NEXT: ldr h0, [x0]
; CHECK-NEXT: ldr h1, [x0] ; CHECK-NEXT: ldr h1, [x1]
; CHECK-NEXT: mvn v2.8b, v0.8b ; CHECK-NEXT: uqadd v0.4h, v0.4h, v1.4h
; CHECK-NEXT: umin v1.4h, v1.4h, v2.4h
; CHECK-NEXT: add v0.4h, v1.4h, v0.4h
; CHECK-NEXT: str h0, [x2] ; CHECK-NEXT: str h0, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <1 x i16>, <1 x i16>* %px %x = load <1 x i16>, <1 x i16>* %px
%y = load <1 x i16>, <1 x i16>* %py %y = load <1 x i16>, <1 x i16>* %py
%z = call <1 x i16> @llvm.uadd.sat.v1i16(<1 x i16> %x, <1 x i16> %y) %z = call <1 x i16> @llvm.uadd.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
store <1 x i16> %z, <1 x i16>* %pz store <1 x i16> %z, <1 x i16>* %pz
ret void ret void
} }
Show All 22 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i1> @llvm.uadd.sat.v16i1(<16 x i1> %x, <16 x i1> %y) %z = call <16 x i1> @llvm.uadd.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
ret <16 x i1> %z ret <16 x i1> %z
} }
define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind { define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; CHECK-LABEL: v2i32: ; CHECK-LABEL: v2i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mvn v2.8b, v1.8b ; CHECK-NEXT: uqadd v0.2s, v0.2s, v1.2s
; CHECK-NEXT: umin v0.2s, v0.2s, v2.2s
; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %x, <2 x i32> %y) %z = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %x, <2 x i32> %y)
ret <2 x i32> %z ret <2 x i32> %z
} }
define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: v4i32: ; CHECK-LABEL: v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mvn v2.16b, v1.16b ; CHECK-NEXT: uqadd v0.4s, v0.4s, v1.4s
; CHECK-NEXT: umin v0.4s, v0.4s, v2.4s
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y) %z = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
ret <4 x i32> %z ret <4 x i32> %z
} }
define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind { define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
; CHECK-LABEL: v8i32: ; CHECK-LABEL: v8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mvn v4.16b, v2.16b ; CHECK-NEXT: uqadd v0.4s, v0.4s, v2.4s
; CHECK-NEXT: mvn v5.16b, v3.16b ; CHECK-NEXT: uqadd v1.4s, v1.4s, v3.4s
; CHECK-NEXT: umin v0.4s, v0.4s, v4.4s
; CHECK-NEXT: umin v1.4s, v1.4s, v5.4s
; CHECK-NEXT: add v0.4s, v0.4s, v2.4s
; CHECK-NEXT: add v1.4s, v1.4s, v3.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %x, <8 x i32> %y) %z = call <8 x i32> @llvm.uadd.sat.v8i32(<8 x i32> %x, <8 x i32> %y)
ret <8 x i32> %z ret <8 x i32> %z
} }
define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind { define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
; CHECK-LABEL: v16i32: ; CHECK-LABEL: v16i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mvn v16.16b, v4.16b ; CHECK-NEXT: uqadd v0.4s, v0.4s, v4.4s
; CHECK-NEXT: umin v0.4s, v0.4s, v16.4s ; CHECK-NEXT: uqadd v1.4s, v1.4s, v5.4s
; CHECK-NEXT: mvn v16.16b, v5.16b ; CHECK-NEXT: uqadd v2.4s, v2.4s, v6.4s
; CHECK-NEXT: umin v1.4s, v1.4s, v16.4s ; CHECK-NEXT: uqadd v3.4s, v3.4s, v7.4s
; CHECK-NEXT: mvn v16.16b, v6.16b
; CHECK-NEXT: umin v2.4s, v2.4s, v16.4s
; CHECK-NEXT: mvn v16.16b, v7.16b
; CHECK-NEXT: umin v3.4s, v3.4s, v16.4s
; CHECK-NEXT: add v0.4s, v0.4s, v4.4s
; CHECK-NEXT: add v1.4s, v1.4s, v5.4s
; CHECK-NEXT: add v2.4s, v2.4s, v6.4s
; CHECK-NEXT: add v3.4s, v3.4s, v7.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %x, <16 x i32> %y) %z = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %x, <16 x i32> %y)
ret <16 x i32> %z ret <16 x i32> %z
} }
define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind { define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; CHECK-LABEL: v2i64: ; CHECK-LABEL: v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v1.2d, v0.2d, v1.2d ; CHECK-NEXT: uqadd v0.2d, v0.2d, v1.2d
; CHECK-NEXT: cmhi v0.2d, v0.2d, v1.2d
; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %x, <2 x i64> %y) %z = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
ret <2 x i64> %z ret <2 x i64> %z
} }
define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind { define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
; CHECK-LABEL: v4i64: ; CHECK-LABEL: v4i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v2.2d, v0.2d, v2.2d ; CHECK-NEXT: uqadd v0.2d, v0.2d, v2.2d
; CHECK-NEXT: add v3.2d, v1.2d, v3.2d ; CHECK-NEXT: uqadd v1.2d, v1.2d, v3.2d
; CHECK-NEXT: cmhi v0.2d, v0.2d, v2.2d
; CHECK-NEXT: cmhi v1.2d, v1.2d, v3.2d
; CHECK-NEXT: orr v0.16b, v2.16b, v0.16b
; CHECK-NEXT: orr v1.16b, v3.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> %x, <4 x i64> %y) %z = call <4 x i64> @llvm.uadd.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
ret <4 x i64> %z ret <4 x i64> %z
} }
define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind { define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
; CHECK-LABEL: v8i64: ; CHECK-LABEL: v8i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: add v4.2d, v0.2d, v4.2d ; CHECK-NEXT: uqadd v0.2d, v0.2d, v4.2d
; CHECK-NEXT: add v5.2d, v1.2d, v5.2d ; CHECK-NEXT: uqadd v1.2d, v1.2d, v5.2d
; CHECK-NEXT: add v6.2d, v2.2d, v6.2d ; CHECK-NEXT: uqadd v2.2d, v2.2d, v6.2d
; CHECK-NEXT: add v7.2d, v3.2d, v7.2d ; CHECK-NEXT: uqadd v3.2d, v3.2d, v7.2d
; CHECK-NEXT: cmhi v0.2d, v0.2d, v4.2d
; CHECK-NEXT: cmhi v1.2d, v1.2d, v5.2d
; CHECK-NEXT: cmhi v2.2d, v2.2d, v6.2d
; CHECK-NEXT: cmhi v3.2d, v3.2d, v7.2d
; CHECK-NEXT: orr v0.16b, v4.16b, v0.16b
; CHECK-NEXT: orr v1.16b, v5.16b, v1.16b
; CHECK-NEXT: orr v2.16b, v6.16b, v2.16b
; CHECK-NEXT: orr v3.16b, v7.16b, v3.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> %x, <8 x i64> %y) %z = call <8 x i64> @llvm.uadd.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
ret <8 x i64> %z ret <8 x i64> %z
} }
define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind { define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; CHECK-LABEL: v2i128: ; CHECK-LABEL: v2i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
Show All 27 Lines

llvm/test/CodeGen/AArch64/usub_sat_vec.ll

Show All 30 Lines
declare <4 x i24> @llvm.usub.sat.v4i24(<4 x i24>, <4 x i24>) declare <4 x i24> @llvm.usub.sat.v4i24(<4 x i24>, <4 x i24>)
declare <2 x i128> @llvm.usub.sat.v2i128(<2 x i128>, <2 x i128>) declare <2 x i128> @llvm.usub.sat.v2i128(<2 x i128>, <2 x i128>)
define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind { define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; CHECK-LABEL: v16i8: ; CHECK-LABEL: v16i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umax v0.16b, v0.16b, v1.16b ; CHECK-NEXT: uqsub v0.16b, v0.16b, v1.16b
; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %x, <16 x i8> %y) %z = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
ret <16 x i8> %z ret <16 x i8> %z
} }
define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind { define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {
; CHECK-LABEL: v32i8: ; CHECK-LABEL: v32i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umax v0.16b, v0.16b, v2.16b ; CHECK-NEXT: uqsub v0.16b, v0.16b, v2.16b
; CHECK-NEXT: umax v1.16b, v1.16b, v3.16b ; CHECK-NEXT: uqsub v1.16b, v1.16b, v3.16b
; CHECK-NEXT: sub v0.16b, v0.16b, v2.16b
; CHECK-NEXT: sub v1.16b, v1.16b, v3.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <32 x i8> @llvm.usub.sat.v32i8(<32 x i8> %x, <32 x i8> %y) %z = call <32 x i8> @llvm.usub.sat.v32i8(<32 x i8> %x, <32 x i8> %y)
ret <32 x i8> %z ret <32 x i8> %z
} }
define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind { define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {
; CHECK-LABEL: v64i8: ; CHECK-LABEL: v64i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umax v0.16b, v0.16b, v4.16b ; CHECK-NEXT: uqsub v0.16b, v0.16b, v4.16b
; CHECK-NEXT: umax v1.16b, v1.16b, v5.16b ; CHECK-NEXT: uqsub v1.16b, v1.16b, v5.16b
; CHECK-NEXT: umax v2.16b, v2.16b, v6.16b ; CHECK-NEXT: uqsub v2.16b, v2.16b, v6.16b
; CHECK-NEXT: umax v3.16b, v3.16b, v7.16b ; CHECK-NEXT: uqsub v3.16b, v3.16b, v7.16b
; CHECK-NEXT: sub v0.16b, v0.16b, v4.16b
; CHECK-NEXT: sub v1.16b, v1.16b, v5.16b
; CHECK-NEXT: sub v2.16b, v2.16b, v6.16b
; CHECK-NEXT: sub v3.16b, v3.16b, v7.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <64 x i8> @llvm.usub.sat.v64i8(<64 x i8> %x, <64 x i8> %y) %z = call <64 x i8> @llvm.usub.sat.v64i8(<64 x i8> %x, <64 x i8> %y)
ret <64 x i8> %z ret <64 x i8> %z
} }
define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind { define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; CHECK-LABEL: v8i16: ; CHECK-LABEL: v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umax v0.8h, v0.8h, v1.8h ; CHECK-NEXT: uqsub v0.8h, v0.8h, v1.8h
; CHECK-NEXT: sub v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %x, <8 x i16> %y) %z = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
ret <8 x i16> %z ret <8 x i16> %z
} }
define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind { define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {
; CHECK-LABEL: v16i16: ; CHECK-LABEL: v16i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umax v0.8h, v0.8h, v2.8h ; CHECK-NEXT: uqsub v0.8h, v0.8h, v2.8h
; CHECK-NEXT: umax v1.8h, v1.8h, v3.8h ; CHECK-NEXT: uqsub v1.8h, v1.8h, v3.8h
; CHECK-NEXT: sub v0.8h, v0.8h, v2.8h
; CHECK-NEXT: sub v1.8h, v1.8h, v3.8h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> %x, <16 x i16> %y) %z = call <16 x i16> @llvm.usub.sat.v16i16(<16 x i16> %x, <16 x i16> %y)
ret <16 x i16> %z ret <16 x i16> %z
} }
define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind { define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {
; CHECK-LABEL: v32i16: ; CHECK-LABEL: v32i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umax v0.8h, v0.8h, v4.8h ; CHECK-NEXT: uqsub v0.8h, v0.8h, v4.8h
; CHECK-NEXT: umax v1.8h, v1.8h, v5.8h ; CHECK-NEXT: uqsub v1.8h, v1.8h, v5.8h
; CHECK-NEXT: umax v2.8h, v2.8h, v6.8h ; CHECK-NEXT: uqsub v2.8h, v2.8h, v6.8h
; CHECK-NEXT: umax v3.8h, v3.8h, v7.8h ; CHECK-NEXT: uqsub v3.8h, v3.8h, v7.8h
; CHECK-NEXT: sub v0.8h, v0.8h, v4.8h
; CHECK-NEXT: sub v1.8h, v1.8h, v5.8h
; CHECK-NEXT: sub v2.8h, v2.8h, v6.8h
; CHECK-NEXT: sub v3.8h, v3.8h, v7.8h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <32 x i16> @llvm.usub.sat.v32i16(<32 x i16> %x, <32 x i16> %y) %z = call <32 x i16> @llvm.usub.sat.v32i16(<32 x i16> %x, <32 x i16> %y)
ret <32 x i16> %z ret <32 x i16> %z
} }
define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind { define void @v8i8(<8 x i8>* %px, <8 x i8>* %py, <8 x i8>* %pz) nounwind {
; CHECK-LABEL: v8i8: ; CHECK-LABEL: v8i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: umax v0.8b, v0.8b, v1.8b ; CHECK-NEXT: uqsub v0.8b, v0.8b, v1.8b
; CHECK-NEXT: sub v0.8b, v0.8b, v1.8b
; CHECK-NEXT: str d0, [x2] ; CHECK-NEXT: str d0, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <8 x i8>, <8 x i8>* %px %x = load <8 x i8>, <8 x i8>* %px
%y = load <8 x i8>, <8 x i8>* %py %y = load <8 x i8>, <8 x i8>* %py
%z = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> %x, <8 x i8> %y) %z = call <8 x i8> @llvm.usub.sat.v8i8(<8 x i8> %x, <8 x i8> %y)
store <8 x i8> %z, <8 x i8>* %pz store <8 x i8> %z, <8 x i8>* %pz
ret void ret void
} }
Show All 12 Lines
; CHECK-NEXT: mov v0.h[1], w10 ; CHECK-NEXT: mov v0.h[1], w10
; CHECK-NEXT: mov v1.h[1], w11 ; CHECK-NEXT: mov v1.h[1], w11
; CHECK-NEXT: ldrb w10, [x0, #3] ; CHECK-NEXT: ldrb w10, [x0, #3]
; CHECK-NEXT: ldrb w11, [x1, #3] ; CHECK-NEXT: ldrb w11, [x1, #3]
; CHECK-NEXT: mov v0.h[2], w8 ; CHECK-NEXT: mov v0.h[2], w8
; CHECK-NEXT: mov v1.h[2], w9 ; CHECK-NEXT: mov v1.h[2], w9
; CHECK-NEXT: mov v0.h[3], w10 ; CHECK-NEXT: mov v0.h[3], w10
; CHECK-NEXT: mov v1.h[3], w11 ; CHECK-NEXT: mov v1.h[3], w11
; CHECK-NEXT: umax v0.4h, v0.4h, v1.4h ; CHECK-NEXT: uqsub v0.4h, v0.4h, v1.4h
; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h
; CHECK-NEXT: xtn v0.8b, v0.8h ; CHECK-NEXT: xtn v0.8b, v0.8h
; CHECK-NEXT: str s0, [x2] ; CHECK-NEXT: str s0, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <4 x i8>, <4 x i8>* %px %x = load <4 x i8>, <4 x i8>* %px
%y = load <4 x i8>, <4 x i8>* %py %y = load <4 x i8>, <4 x i8>* %py
%z = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %x, <4 x i8> %y) %z = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %x, <4 x i8> %y)
store <4 x i8> %z, <4 x i8>* %pz store <4 x i8> %z, <4 x i8>* %pz
ret void ret void
} }
define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind { define void @v2i8(<2 x i8>* %px, <2 x i8>* %py, <2 x i8>* %pz) nounwind {
; CHECK-LABEL: v2i8: ; CHECK-LABEL: v2i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldrb w8, [x0] ; CHECK-NEXT: ldrb w8, [x0]
; CHECK-NEXT: ldrb w9, [x1] ; CHECK-NEXT: ldrb w9, [x1]
; CHECK-NEXT: ldrb w10, [x0, #1] ; CHECK-NEXT: ldrb w10, [x0, #1]
; CHECK-NEXT: ldrb w11, [x1, #1] ; CHECK-NEXT: ldrb w11, [x1, #1]
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: mov v0.s[1], w10 ; CHECK-NEXT: mov v0.s[1], w10
; CHECK-NEXT: mov v1.s[1], w11 ; CHECK-NEXT: mov v1.s[1], w11
; CHECK-NEXT: umax v0.2s, v0.2s, v1.2s ; CHECK-NEXT: uqsub v0.2s, v0.2s, v1.2s
; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strb w8, [x2, #1] ; CHECK-NEXT: strb w8, [x2, #1]
; CHECK-NEXT: strb w9, [x2] ; CHECK-NEXT: strb w9, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i8>, <2 x i8>* %px %x = load <2 x i8>, <2 x i8>* %px
%y = load <2 x i8>, <2 x i8>* %py %y = load <2 x i8>, <2 x i8>* %py
%z = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %x, <2 x i8> %y) %z = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %x, <2 x i8> %y)
store <2 x i8> %z, <2 x i8>* %pz store <2 x i8> %z, <2 x i8>* %pz
ret void ret void
} }
define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind { define void @v4i16(<4 x i16>* %px, <4 x i16>* %py, <4 x i16>* %pz) nounwind {
; CHECK-LABEL: v4i16: ; CHECK-LABEL: v4i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: umax v0.4h, v0.4h, v1.4h ; CHECK-NEXT: uqsub v0.4h, v0.4h, v1.4h
; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h
; CHECK-NEXT: str d0, [x2] ; CHECK-NEXT: str d0, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <4 x i16>, <4 x i16>* %px %x = load <4 x i16>, <4 x i16>* %px
%y = load <4 x i16>, <4 x i16>* %py %y = load <4 x i16>, <4 x i16>* %py
%z = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %x, <4 x i16> %y) %z = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %x, <4 x i16> %y)
store <4 x i16> %z, <4 x i16>* %pz store <4 x i16> %z, <4 x i16>* %pz
ret void ret void
} }
define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind { define void @v2i16(<2 x i16>* %px, <2 x i16>* %py, <2 x i16>* %pz) nounwind {
; CHECK-LABEL: v2i16: ; CHECK-LABEL: v2i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldrh w8, [x0] ; CHECK-NEXT: ldrh w8, [x0]
; CHECK-NEXT: ldrh w9, [x1] ; CHECK-NEXT: ldrh w9, [x1]
; CHECK-NEXT: ldrh w10, [x0, #2] ; CHECK-NEXT: ldrh w10, [x0, #2]
; CHECK-NEXT: ldrh w11, [x1, #2] ; CHECK-NEXT: ldrh w11, [x1, #2]
; CHECK-NEXT: fmov s0, w8 ; CHECK-NEXT: fmov s0, w8
; CHECK-NEXT: fmov s1, w9 ; CHECK-NEXT: fmov s1, w9
; CHECK-NEXT: mov v0.s[1], w10 ; CHECK-NEXT: mov v0.s[1], w10
; CHECK-NEXT: mov v1.s[1], w11 ; CHECK-NEXT: mov v1.s[1], w11
; CHECK-NEXT: umax v0.2s, v0.2s, v1.2s ; CHECK-NEXT: uqsub v0.2s, v0.2s, v1.2s
; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s
; CHECK-NEXT: mov w8, v0.s[1] ; CHECK-NEXT: mov w8, v0.s[1]
; CHECK-NEXT: fmov w9, s0 ; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strh w8, [x2, #2] ; CHECK-NEXT: strh w8, [x2, #2]
; CHECK-NEXT: strh w9, [x2] ; CHECK-NEXT: strh w9, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <2 x i16>, <2 x i16>* %px %x = load <2 x i16>, <2 x i16>* %px
%y = load <2 x i16>, <2 x i16>* %py %y = load <2 x i16>, <2 x i16>* %py
%z = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %x, <2 x i16> %y) %z = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %x, <2 x i16> %y)
store <2 x i16> %z, <2 x i16>* %pz store <2 x i16> %z, <2 x i16>* %pz
ret void ret void
} }
define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind { define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {
; CHECK-LABEL: v12i8: ; CHECK-LABEL: v12i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umax v0.16b, v0.16b, v1.16b ; CHECK-NEXT: uqsub v0.16b, v0.16b, v1.16b
; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <12 x i8> @llvm.usub.sat.v12i8(<12 x i8> %x, <12 x i8> %y) %z = call <12 x i8> @llvm.usub.sat.v12i8(<12 x i8> %x, <12 x i8> %y)
ret <12 x i8> %z ret <12 x i8> %z
} }
define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind { define void @v12i16(<12 x i16>* %px, <12 x i16>* %py, <12 x i16>* %pz) nounwind {
; CHECK-LABEL: v12i16: ; CHECK-LABEL: v12i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0] ; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ldp q3, q2, [x1] ; CHECK-NEXT: ldp q3, q2, [x1]
; CHECK-NEXT: umax v1.8h, v1.8h, v2.8h ; CHECK-NEXT: uqsub v1.8h, v1.8h, v2.8h
; CHECK-NEXT: umax v0.8h, v0.8h, v3.8h ; CHECK-NEXT: uqsub v0.8h, v0.8h, v3.8h
; CHECK-NEXT: sub v1.8h, v1.8h, v2.8h
; CHECK-NEXT: sub v0.8h, v0.8h, v3.8h
; CHECK-NEXT: str q0, [x2] ; CHECK-NEXT: str q0, [x2]
; CHECK-NEXT: str d1, [x2, #16] ; CHECK-NEXT: str d1, [x2, #16]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <12 x i16>, <12 x i16>* %px %x = load <12 x i16>, <12 x i16>* %px
%y = load <12 x i16>, <12 x i16>* %py %y = load <12 x i16>, <12 x i16>* %py
%z = call <12 x i16> @llvm.usub.sat.v12i16(<12 x i16> %x, <12 x i16> %y) %z = call <12 x i16> @llvm.usub.sat.v12i16(<12 x i16> %x, <12 x i16> %y)
store <12 x i16> %z, <12 x i16>* %pz store <12 x i16> %z, <12 x i16>* %pz
ret void ret void
} }
define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind { define void @v1i8(<1 x i8>* %px, <1 x i8>* %py, <1 x i8>* %pz) nounwind {
; CHECK-LABEL: v1i8: ; CHECK-LABEL: v1i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr b0, [x0] ; CHECK-NEXT: ldr b0, [x0]
; CHECK-NEXT: ldr b1, [x1] ; CHECK-NEXT: ldr b1, [x1]
; CHECK-NEXT: umax v0.8b, v0.8b, v1.8b ; CHECK-NEXT: uqsub v0.8b, v0.8b, v1.8b
; CHECK-NEXT: sub v0.8b, v0.8b, v1.8b
; CHECK-NEXT: st1 { v0.b }[0], [x2] ; CHECK-NEXT: st1 { v0.b }[0], [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <1 x i8>, <1 x i8>* %px %x = load <1 x i8>, <1 x i8>* %px
%y = load <1 x i8>, <1 x i8>* %py %y = load <1 x i8>, <1 x i8>* %py
%z = call <1 x i8> @llvm.usub.sat.v1i8(<1 x i8> %x, <1 x i8> %y) %z = call <1 x i8> @llvm.usub.sat.v1i8(<1 x i8> %x, <1 x i8> %y)
store <1 x i8> %z, <1 x i8>* %pz store <1 x i8> %z, <1 x i8>* %pz
ret void ret void
} }
define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind { define void @v1i16(<1 x i16>* %px, <1 x i16>* %py, <1 x i16>* %pz) nounwind {
; CHECK-LABEL: v1i16: ; CHECK-LABEL: v1i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr h0, [x0] ; CHECK-NEXT: ldr h0, [x0]
; CHECK-NEXT: ldr h1, [x1] ; CHECK-NEXT: ldr h1, [x1]
; CHECK-NEXT: umax v0.4h, v0.4h, v1.4h ; CHECK-NEXT: uqsub v0.4h, v0.4h, v1.4h
; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h
; CHECK-NEXT: str h0, [x2] ; CHECK-NEXT: str h0, [x2]
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%x = load <1 x i16>, <1 x i16>* %px %x = load <1 x i16>, <1 x i16>* %px
%y = load <1 x i16>, <1 x i16>* %py %y = load <1 x i16>, <1 x i16>* %py
%z = call <1 x i16> @llvm.usub.sat.v1i16(<1 x i16> %x, <1 x i16> %y) %z = call <1 x i16> @llvm.usub.sat.v1i16(<1 x i16> %x, <1 x i16> %y)
store <1 x i16> %z, <1 x i16>* %pz store <1 x i16> %z, <1 x i16>* %pz
ret void ret void
} }
define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind { define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {
; CHECK-LABEL: v16i4: ; CHECK-LABEL: v16i4:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.16b, #15 ; CHECK-NEXT: movi v2.16b, #15
; CHECK-NEXT: and v1.16b, v1.16b, v2.16b ; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
; CHECK-NEXT: umax v0.16b, v0.16b, v1.16b ; CHECK-NEXT: uqsub v0.16b, v0.16b, v1.16b
; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i4> @llvm.usub.sat.v16i4(<16 x i4> %x, <16 x i4> %y) %z = call <16 x i4> @llvm.usub.sat.v16i4(<16 x i4> %x, <16 x i4> %y)
ret <16 x i4> %z ret <16 x i4> %z
} }
define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind { define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
; CHECK-LABEL: v16i1: ; CHECK-LABEL: v16i1:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v2.16b, #1 ; CHECK-NEXT: movi v2.16b, #1
; CHECK-NEXT: and v1.16b, v1.16b, v2.16b ; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b ; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
; CHECK-NEXT: umax v0.16b, v0.16b, v1.16b ; CHECK-NEXT: uqsub v0.16b, v0.16b, v1.16b
; CHECK-NEXT: sub v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i1> @llvm.usub.sat.v16i1(<16 x i1> %x, <16 x i1> %y) %z = call <16 x i1> @llvm.usub.sat.v16i1(<16 x i1> %x, <16 x i1> %y)
ret <16 x i1> %z ret <16 x i1> %z
} }
define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind { define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
; CHECK-LABEL: v2i32: ; CHECK-LABEL: v2i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umax v0.2s, v0.2s, v1.2s ; CHECK-NEXT: uqsub v0.2s, v0.2s, v1.2s
; CHECK-NEXT: sub v0.2s, v0.2s, v1.2s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %x, <2 x i32> %y) %z = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %x, <2 x i32> %y)
ret <2 x i32> %z ret <2 x i32> %z
} }
define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: v4i32: ; CHECK-LABEL: v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umax v0.4s, v0.4s, v1.4s ; CHECK-NEXT: uqsub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: sub v0.4s, v0.4s, v1.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %y) %z = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
ret <4 x i32> %z ret <4 x i32> %z
} }
define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind { define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {
; CHECK-LABEL: v8i32: ; CHECK-LABEL: v8i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umax v0.4s, v0.4s, v2.4s ; CHECK-NEXT: uqsub v0.4s, v0.4s, v2.4s
; CHECK-NEXT: umax v1.4s, v1.4s, v3.4s ; CHECK-NEXT: uqsub v1.4s, v1.4s, v3.4s
; CHECK-NEXT: sub v0.4s, v0.4s, v2.4s
; CHECK-NEXT: sub v1.4s, v1.4s, v3.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %x, <8 x i32> %y) %z = call <8 x i32> @llvm.usub.sat.v8i32(<8 x i32> %x, <8 x i32> %y)
ret <8 x i32> %z ret <8 x i32> %z
} }
define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind { define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
; CHECK-LABEL: v16i32: ; CHECK-LABEL: v16i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: umax v0.4s, v0.4s, v4.4s ; CHECK-NEXT: uqsub v0.4s, v0.4s, v4.4s
; CHECK-NEXT: umax v1.4s, v1.4s, v5.4s ; CHECK-NEXT: uqsub v1.4s, v1.4s, v5.4s
; CHECK-NEXT: umax v2.4s, v2.4s, v6.4s ; CHECK-NEXT: uqsub v2.4s, v2.4s, v6.4s
; CHECK-NEXT: umax v3.4s, v3.4s, v7.4s ; CHECK-NEXT: uqsub v3.4s, v3.4s, v7.4s
; CHECK-NEXT: sub v0.4s, v0.4s, v4.4s
; CHECK-NEXT: sub v1.4s, v1.4s, v5.4s
; CHECK-NEXT: sub v2.4s, v2.4s, v6.4s
; CHECK-NEXT: sub v3.4s, v3.4s, v7.4s
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %x, <16 x i32> %y) %z = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %x, <16 x i32> %y)
ret <16 x i32> %z ret <16 x i32> %z
} }
define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind { define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; CHECK-LABEL: v2i64: ; CHECK-LABEL: v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v1.2d, v0.2d, v1.2d ; CHECK-NEXT: uqsub v0.2d, v0.2d, v1.2d
; CHECK-NEXT: cmhi v0.2d, v1.2d, v0.2d
; CHECK-NEXT: bic v0.16b, v1.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %x, <2 x i64> %y) %z = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
ret <2 x i64> %z ret <2 x i64> %z
} }
define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind { define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {
; CHECK-LABEL: v4i64: ; CHECK-LABEL: v4i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v2.2d, v0.2d, v2.2d ; CHECK-NEXT: uqsub v0.2d, v0.2d, v2.2d
; CHECK-NEXT: sub v3.2d, v1.2d, v3.2d ; CHECK-NEXT: uqsub v1.2d, v1.2d, v3.2d
; CHECK-NEXT: cmhi v0.2d, v2.2d, v0.2d
; CHECK-NEXT: cmhi v1.2d, v3.2d, v1.2d
; CHECK-NEXT: bic v0.16b, v2.16b, v0.16b
; CHECK-NEXT: bic v1.16b, v3.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> %x, <4 x i64> %y) %z = call <4 x i64> @llvm.usub.sat.v4i64(<4 x i64> %x, <4 x i64> %y)
ret <4 x i64> %z ret <4 x i64> %z
} }
define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind { define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {
; CHECK-LABEL: v8i64: ; CHECK-LABEL: v8i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sub v4.2d, v0.2d, v4.2d ; CHECK-NEXT: uqsub v0.2d, v0.2d, v4.2d
; CHECK-NEXT: sub v5.2d, v1.2d, v5.2d ; CHECK-NEXT: uqsub v1.2d, v1.2d, v5.2d
; CHECK-NEXT: sub v6.2d, v2.2d, v6.2d ; CHECK-NEXT: uqsub v2.2d, v2.2d, v6.2d
; CHECK-NEXT: sub v7.2d, v3.2d, v7.2d ; CHECK-NEXT: uqsub v3.2d, v3.2d, v7.2d
; CHECK-NEXT: cmhi v0.2d, v4.2d, v0.2d
; CHECK-NEXT: cmhi v1.2d, v5.2d, v1.2d
; CHECK-NEXT: cmhi v2.2d, v6.2d, v2.2d
; CHECK-NEXT: cmhi v3.2d, v7.2d, v3.2d
; CHECK-NEXT: bic v0.16b, v4.16b, v0.16b
; CHECK-NEXT: bic v1.16b, v5.16b, v1.16b
; CHECK-NEXT: bic v2.16b, v6.16b, v2.16b
; CHECK-NEXT: bic v3.16b, v7.16b, v3.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%z = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> %x, <8 x i64> %y) %z = call <8 x i64> @llvm.usub.sat.v8i64(<8 x i64> %x, <8 x i64> %y)
ret <8 x i64> %z ret <8 x i64> %z
} }
define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind { define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {
; CHECK-LABEL: v2i128: ; CHECK-LABEL: v2i128:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
Show All 27 Lines