[X86] Add strict fp support for operations of X87 instructions

[LiuChen3]

Summary

This is the following patch of D68854.

This patch adds basic operations of X87 instructions, including +, -, *, / , fp extensions and fp truncations.

[craig.topper]

llvm/lib/Target/X86/X86ISelLowering.cpp

601

Doesn't this stop working if sse1 is enabled? By we still need x87 for f64/f80.

llvm/lib/Target/X86/X86InstrFPStack.td

370–371

SIN/COS are not mentioned in the X86ISelLowering code you added.

llvm/test/CodeGen/X86/x87-fp-strict-sub.ll

84 ↗

(On Diff #224531)

Is all this metadata needed?

[LiuChen3]

llvm/lib/Target/X86/X86ISelLowering.cpp

601

Yes . This can only be enabled when disable sse. I'll find which will still be needed when SSE enabled. I think most of them are related to f80.

llvm/lib/Target/X86/X86InstrFPStack.td

370–371

X86 uses library to calculate SIN/COS. X87 set SIN/COS as Expand. So I leave strict_fsin/strict_fcos as "expand" as default.

llvm/test/CodeGen/X86/x87-fp-strict-sub.ll

84 ↗

(On Diff #224531)

It's not necessay. I'll delete them.

[craig.topper]

llvm/lib/Target/X86/X86InstrFPStack.td

370–371

Ok then don't change these lines. We shouldn't have entries in the isel table that we don't need.

[LiuChen3]

llvm/lib/Target/X86/X86InstrFPStack.td

370–371

ok

[LiuChen3]

Rebase and change the name of tests in fp-strict-scalar.ll . Add a test file which only process 80-bit long double type, because tests for 80-bit FP is complex to put into fp-strict-scalar.ll without changing the '–check-prefix'.

[craig.topper]

llvm/test/CodeGen/X86/fp-strict-scalar.ll

22–23

How about fadd_f64 and fadd_f32 instead of fadd1/fadd2?

llvm/test/CodeGen/X86/fp80-strict-scalar.ll

2

I don't think we need to test all these combinations. But if you want to keep them, I suggest adding a CHECK-X86 and CHECK-X64 prefix so that we get more commonality.

22

fadd_f80

166

fpext_f32_to_f80

[LiuChen3]

llvm/test/CodeGen/X86/fp80-strict-scalar.ll

2

How about just keep the "; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=-sse -O3 | FileCheck %s --check-prefixes=CHECK,X87". I think fp80 mostly uses X87 instructions.

[LiuChen3]

Modify the name of tests and delete some RUN line in fp80-strict-scalar.ll.

[LiuChen3]

Modify the name of tests

[craig.topper]

I think we need to re-evaluate our testing strategy here. These tests pass on trunk without any of the other changes.

I was going to suggest adding -stop-after=finalize-isel so we could check the fpexcept bit, but the mutating code preserves the fpexcept bit from the strict fp node we mutated. So I'm not sure how we can tell that this patch works correctly.

[pengfei]

This comment was removed by pengfei.

[craig.topper]

How about we add a command line option to SelectionDAGISel to disable the mutation code and pass that option on the tests?

[LiuChen3]

OK, I 'll make a try.

[pengfei]

In D68857#1743355, @craig.topper wrote:

How about we add a command line option to SelectionDAGISel to disable the mutation code and pass that option on the tests?

I think it's reasonable.

[RKSimon]

The new tests and test renames can be done as an NFC commit - then please rebase this patch

[LiuChen3]

In D68857#1755370, @RKSimon wrote:

The new tests and test renames can be done as an NFC commit - then please rebase this patch

Sorry, I am not clear of what you mean. Do you mean I should make a new patch to add these tests? The tests in my current patch is not just renamed, but also doing functional test. I think it's better to keep them together.
And I think make a new patch to rename the tests is reasonable.

[RKSimon]

In D68857#1756222, @LiuChen3 wrote:

In D68857#1755370, @RKSimon wrote:

The new tests and test renames can be done as an NFC commit - then please rebase this patch

Sorry, I am not clear of what you mean. Do you mean I should make a new patch to add these tests? The tests in my current patch is not just renamed, but also doing functional test. I think it's better to keep them together.
And I think make a new patch to rename the tests is reasonable.

I've updated/added the tests in rG5aaca2355ec2 (matching Craig's changes in rG0cc12b8a8310) - the changes were an NFC cleanup and don't require a new patch. Please can you now rebase?

[LiuChen3]

Rebase

[LiuChen3]

In D68857#1756615, @RKSimon wrote:

In D68857#1756222, @LiuChen3 wrote:

In D68857#1755370, @RKSimon wrote:

The new tests and test renames can be done as an NFC commit - then please rebase this patch

Sorry, I am not clear of what you mean. Do you mean I should make a new patch to add these tests? The tests in my current patch is not just renamed, but also doing functional test. I think it's better to keep them together.
And I think make a new patch to rename the tests is reasonable.

I've updated/added the tests in rG5aaca2355ec2 (matching Craig's changes in rG0cc12b8a8310) - the changes were an NFC cleanup and don't require a new patch. Please can you now rebase?

I have rebase. Thanks.

[craig.topper]

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

5227

This isn't the right check for the fp80 operations. They're independent of sse.

5228

Need an LLVM_FALLTHROUGH marker here

llvm/test/CodeGen/X86/fp80-strict-scalar.ll

2

Why are we disabling sse on x86_64?

[LiuChen3]

llvm/test/CodeGen/X86/fp80-strict-scalar.ll

2

Make sure we are using X87 instructions. This option is actually useless when using fp80, I'll delete it.

[LiuChen3]

Rebase.
STRICT_FP_ROUND has been set as custom so I remove setting it as legal. When entering the custom processing function, if the operand type is legal,the function behaves the same as setOperationAction(ISD:STRICT_FP_ROUND, TYPE, legal)
Modify the test case. Since we do not disable sse, we can pass float-pointer value by register instead of passing by pointer.

[craig.topper]

In D68857#1759727, @LiuChen3 wrote:

Rebase.
STRICT_FP_ROUND has been set as custom so I remove setting it as legal. When entering the custom processing function, if the operand type is legal,the function behaves the same as setOperationAction(ISD:STRICT_FP_ROUND, TYPE, legal)
Modify the test case. Since we do not disable sse, we can pass float-pointer value by register instead of passing by pointer.

STRICT_FP_ROUND should only be Custom on a 64-bit target. This probably only works because LegalizeDAG bailed out of ExpandNode due to strictfp mutation being disabled. And there is no libcall support for STRICT_FP_ROUND so LegalizeDAG gave up and just left the node alone.

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

5227

For FP_ROUND isn't the input type f80 not the result type?

5237–5238

I think this code should also call TLI.isStrictFPEnabled() before doing the mutate.

[LiuChen3]

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

5228

I think there is still some problems here, I'll work on it

[craig.topper]

Please pre-commit the test modifications with the old codegen and rebase this patch.

[LiuChen3]

In D68857#1759743, @craig.topper wrote:

Please pre-commit the test modifications with the old codegen and rebase this patch.

OK. Thanks for your help.

[LiuChen3]

Pengfei has helped me commit the test cases.
I rebase and add the option "-disable-strictnode-mutation" to the test case.

[LiuChen3]

llvm/test/CodeGen/X86/fp-strict-scalar.ll

18

Hi, Craig. Is the sequence of "fpext.f64.f32" important? I thought it should be fpext.sourcetype.destinationtype, but fpext.f64.f32 can output right code, too.
Did this Intrinsic only use pass value type fpext.f64.f32(float, metadata) and return value type double to determine the source type and return type?

[craig.topper]

llvm/test/CodeGen/X86/fp-strict-scalar.ll

18

Its supposed to be fpext.destinationtype.sourcetype. The types are determined by the order of the llvm_anyint_ty/llvm_anyfloat_ty listed in the Intrinsics.td file with output types before input types.

But I think the parser doesn't rely on the types in the name and just use the types mentioned. I bet if you feed the test into 'opt' with no other arguments when it gets printed back out the name will have been fixed.

[LiuChen3]

llvm/test/CodeGen/X86/fp-strict-scalar.ll

18

Yes, you are right. opt will fix the problems.
Then llvm.experimental.constrained.fptrunc has wrong sequence. Should I update the testcase in this patch or pre-commit the testcase and rebase this patch?

[craig.topper]

LGTM

llvm/lib/Target/X86/X86ISelDAGToDAG.cpp

SDValue Res = CurDAG->getNode(X86ISD::VRNDSCALE, dl, Node->getValueType(0),
                                   Node->getOperand(0),
                                   CurDAG->getTargetConstant(Imm, dl, MVT::i8));
     ReplaceNode(Node, Res.getNode());
     SelectCode(Res.getNode());
     return;
   }
   case ISD::STRICT_FADD:
   case ISD::STRICT_FSUB:
+  case ISD::STRICT_FP_ROUND: {
+    // X87 instructions has enabled these strict fp operation.
+    bool UsingFp80 = Node->getSimpleValueType(0) == MVT::f80 ||
+                     Node->getOperand(1).getSimpleValueType() == MVT::f80;
+    if (UsingFp80 || (!Subtarget->hasSSE1() && Subtarget->hasX87()))
+      break;
+    LLVM_FALLTHROUGH;
+  }
   case ISD::STRICT_FP_TO_SINT:
   case ISD::STRICT_FP_TO_UINT:
-  case ISD::STRICT_FP_ROUND:
     // FIXME: Remove when we have isel patterns for strict versions of these
     // nodes.
+    if (!TLI->isStrictFPEnabled())
       CurDAG->mutateStrictFPToFP(Node);
     break;
   }
 
   SelectCode(Node);
 }
 
 bool X86DAGToDAGISel::
 SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,

llvm/lib/Target/X86/X86ISelLowering.cpp

if (!Subtarget.useSoftFloat() && X86ScalarSSEf64) {
     for (auto VT : { MVT::f32, MVT::f64 }) {
       setOperationAction(ISD::UNDEF,     VT, Expand);
       setOperationAction(ISD::FCOPYSIGN, VT, Expand);
 
       // Always expand sin/cos functions even though x87 has an instruction.
       setOperationAction(ISD::FSIN   , VT, Expand);
       setOperationAction(ISD::FCOS   , VT, Expand);
       setOperationAction(ISD::FSINCOS, VT, Expand);
+
+      // Handle constrained floating-point operations of scalar.
+      setOperationAction(ISD::STRICT_FMUL     , VT, Legal);
+      setOperationAction(ISD::STRICT_FDIV     , VT, Legal);
+      setOperationAction(ISD::STRICT_FSQRT    , VT, Legal);
+      setOperationAction(ISD::STRICT_FP_EXTEND, VT, Legal);
+      // FIXME: When the target is 64-bit, STRICT_FP_ROUND will be overwritten
+      // as Custom.
+      setOperationAction(ISD::STRICT_FP_ROUND, VT, Legal);
     }
   }
 
   // Expand FP32 immediates into loads from the stack, save special cases.
   if (isTypeLegal(MVT::f32)) {
     if (UseX87 && (getRegClassFor(MVT::f32) == &X86::RFP32RegClass)) {
       addLegalFPImmediate(APFloat(+0.0f)); // FLD0
       addLegalFPImmediate(APFloat(+1.0f)); // FLD1
       addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS
       addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS
     } else // SSE immediates.
if (UseX87) {
     setOperationAction(ISD::FTRUNC, MVT::f80, Expand);
     setOperationAction(ISD::FRINT,  MVT::f80, Expand);
     setOperationAction(ISD::FNEARBYINT, MVT::f80, Expand);
     setOperationAction(ISD::FMA, MVT::f80, Expand);
     setOperationAction(ISD::LROUND, MVT::f80, Expand);
     setOperationAction(ISD::LLROUND, MVT::f80, Expand);
     setOperationAction(ISD::LRINT, MVT::f80, Expand);
     setOperationAction(ISD::LLRINT, MVT::f80, Expand);
+
+    // Handle constrained floating-point operations of scalar.
+    setOperationAction(ISD::STRICT_FADD     , MVT::f80, Legal);
+    setOperationAction(ISD::STRICT_FSUB     , MVT::f80, Legal);
+    setOperationAction(ISD::STRICT_FMUL     , MVT::f80, Legal);
+    setOperationAction(ISD::STRICT_FDIV     , MVT::f80, Legal);
+    setOperationAction(ISD::STRICT_FSQRT    , MVT::f80, Legal);
+    setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f80, Legal);
+    // FIXME: When the target is 64-bit, STRICT_FP_ROUND will be overwritten
+    // as Custom.
+    setOperationAction(ISD::STRICT_FP_ROUND, MVT::f80, Legal);
   }
 
   // f128 uses xmm registers, but most operations require libcalls.
   if (!Subtarget.useSoftFloat() && Subtarget.is64Bit() && Subtarget.hasSSE1()) {
     addRegisterClass(MVT::f128, Subtarget.hasVLX() ? &X86::VR128XRegClass
                                                    : &X86::VR128RegClass);
 
     addLegalFPImmediate(APFloat::getZero(APFloat::IEEEquad())); // xorps

llvm/lib/Target/X86/X86InstrFPStack.td

 def _FI32m  : FPI<0xDA, fp, (outs), (ins i32mem:$src),
                   !strconcat("fi", asmstring, "{l}\t$src")>;
 }
 
 let Uses = [FPCW], mayRaiseFPException = 1 in {
 // FPBinary_rr just defines pseudo-instructions, no need to set a scheduling
 // resources.
 let hasNoSchedulingInfo = 1 in {
-defm ADD : FPBinary_rr<fadd>;
-defm SUB : FPBinary_rr<fsub>;
-defm MUL : FPBinary_rr<fmul>;
-defm DIV : FPBinary_rr<fdiv>;
+defm ADD : FPBinary_rr<any_fadd>;
+defm SUB : FPBinary_rr<any_fsub>;
+defm MUL : FPBinary_rr<any_fmul>;
+defm DIV : FPBinary_rr<any_fdiv>;
 }
 
 // Sets the scheduling resources for the actual NAME#_F<size>m defintions.
 let SchedRW = [WriteFAddLd] in {
-defm ADD : FPBinary<fadd, MRM0m, "add">;
-defm SUB : FPBinary<fsub, MRM4m, "sub">;
-defm SUBR: FPBinary<fsub ,MRM5m, "subr", 0>;
+defm ADD : FPBinary<any_fadd, MRM0m, "add">;
+defm SUB : FPBinary<any_fsub, MRM4m, "sub">;
+defm SUBR: FPBinary<any_fsub ,MRM5m, "subr", 0>;
 }
 
 let SchedRW = [WriteFMulLd] in {
-defm MUL : FPBinary<fmul, MRM1m, "mul">;
+defm MUL : FPBinary<any_fmul, MRM1m, "mul">;
 }
 
 let SchedRW = [WriteFDivLd] in {
-defm DIV : FPBinary<fdiv, MRM6m, "div">;
-defm DIVR: FPBinary<fdiv, MRM7m, "divr", 0>;
+defm DIV : FPBinary<any_fdiv, MRM6m, "div">;
+defm DIVR: FPBinary<any_fdiv, MRM7m, "divr", 0>;
 }
 } // Uses = [FPCW], mayRaiseFPException = 1
 
 class FPST0rInst<Format fp, string asm>
   : FPI<0xD8, fp, (outs), (ins RSTi:$op), asm>;
 class FPrST0Inst<Format fp, string asm>
   : FPI<0xDC, fp, (outs), (ins RSTi:$op), asm>;
 class FPrST0PInst<Format fp, string asm>

 
 let SchedRW = [WriteFSign] in {
 defm CHS : FPUnary<fneg, MRM_E0, "fchs">;
 defm ABS : FPUnary<fabs, MRM_E1, "fabs">;
 }
 
 let Uses = [FPCW], mayRaiseFPException = 1 in {
 let SchedRW = [WriteFSqrt80] in
-defm SQRT: FPUnary<fsqrt,MRM_FA, "fsqrt">;
+defm SQRT: FPUnary<any_fsqrt,MRM_FA, "fsqrt">;
 
 let SchedRW = [WriteFCom] in {
 let hasSideEffects = 0 in {
 def TST_Fp32  : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;
 def TST_Fp64  : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
 def TST_Fp80  : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
 } // hasSideEffects
 
 def TST_F  : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">;
 } // SchedRW

 def : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m64 addr:$src)>;
 
 // Used to conv. between f80 and i64 for i64 atomic loads.
 def : Pat<(X86fildflag64 addr:$src), (ILD_Fp64m80 addr:$src)>;
 def : Pat<(X86fist64 RFP80:$src, addr:$op), (IST_Fp64m80 addr:$op, RFP80:$src)>;
 
 // FP extensions map onto simple pseudo-value conversions if they are to/from
 // the FP stack.
-def : Pat<(f64 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>,
+def : Pat<(f64 (any_fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP64)>,
           Requires<[FPStackf32]>;
-def : Pat<(f80 (fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>,
+def : Pat<(f80 (any_fpextend RFP32:$src)), (COPY_TO_REGCLASS RFP32:$src, RFP80)>,
            Requires<[FPStackf32]>;
-def : Pat<(f80 (fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>,
+def : Pat<(f80 (any_fpextend RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP80)>,
            Requires<[FPStackf64]>;
 
 // FP truncations map onto simple pseudo-value conversions if they are to/from
 // the FP stack.  We have validated that only value-preserving truncations make
 // it through isel.
-def : Pat<(f32 (fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>,
+def : Pat<(f32 (any_fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>,
           Requires<[FPStackf32]>;
-def : Pat<(f32 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>,
+def : Pat<(f32 (any_fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>,
            Requires<[FPStackf32]>;
-def : Pat<(f64 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>,
+def : Pat<(f64 (any_fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>,
            Requires<[FPStackf64]>;

llvm/test/CodeGen/X86/fp-strict-scalar.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefixes=CHECK,SSE,SSE-X86
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefixes=CHECK,SSE,SSE-X64
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX-X86
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX-X64
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx512f -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX-X86
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK,AVX,AVX-X64
-; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=-sse -O3 | FileCheck %s --check-prefixes=CHECK,X87
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=-sse -O3 -disable-strictnode-mutation | FileCheck %s --check-prefixes=CHECK,X87
 
 declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata)
 declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata)
 declare double @llvm.experimental.constrained.fsub.f64(double, double, metadata, metadata)
 declare float @llvm.experimental.constrained.fsub.f32(float, float, metadata, metadata)
 declare double @llvm.experimental.constrained.fmul.f64(double, double, metadata, metadata)
 declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata)
 declare double @llvm.experimental.constrained.fdiv.f64(double, double, metadata, metadata)
 declare float @llvm.experimental.constrained.fdiv.f32(float, float, metadata, metadata)
 declare double @llvm.experimental.constrained.fpext.f64.f32(float, metadata)
 declare float @llvm.experimental.constrained.fptrunc.f32.f64(double, metadata, metadata)
 declare float @llvm.experimental.constrained.sqrt.f32(float, metadata, metadata)
 declare double @llvm.experimental.constrained.sqrt.f64(double, metadata, metadata)
 
 define double @fadd_f64(double %a, double %b) nounwind strictfp {
 ; SSE-X86-LABEL: fadd_f64:
 ; SSE-X86:       # %bb.0:
 ; SSE-X86-NEXT:    pushl %ebp
 ; SSE-X86-NEXT:    movl %esp, %ebp
 ; SSE-X86-NEXT:    andl $-8, %esp
 ; SSE-X86-NEXT:    subl $8, %esp
 ; SSE-X86-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; SSE-X86-NEXT:    addsd 16(%ebp), %xmm0

llvm/test/CodeGen/X86/fp80-strict-scalar.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-unknown-unknown -O3 | FileCheck %s --check-prefixes=CHECK,X86
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -O3 | FileCheck %s --check-prefixes=CHECK,X64
+; RUN: llc < %s -mtriple=i686-unknown-unknown -O3 -disable-strictnode-mutation | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -O3 -disable-strictnode-mutation | FileCheck %s --check-prefixes=CHECK,X64
 
 declare x86_fp80 @llvm.experimental.constrained.fadd.x86_fp80(x86_fp80, x86_fp80, metadata, metadata)
 declare x86_fp80 @llvm.experimental.constrained.fsub.x86_fp80(x86_fp80, x86_fp80, metadata, metadata)
 declare x86_fp80 @llvm.experimental.constrained.fmul.x86_fp80(x86_fp80, x86_fp80, metadata, metadata)
 declare x86_fp80 @llvm.experimental.constrained.fdiv.x86_fp80(x86_fp80, x86_fp80, metadata, metadata)
 declare x86_fp80 @llvm.experimental.constrained.fpext.x86_fp80.f32(float, metadata)
 declare x86_fp80 @llvm.experimental.constrained.fpext.x86_fp80.f64(double, metadata)
 declare x86_fp80 @llvm.experimental.constrained.sqrt.x86_fp80(x86_fp80, metadata, metadata)
 declare float @llvm.experimental.constrained.fptrunc.f32.x86_fp80(x86_fp80, metadata, metadata)
 declare double @llvm.experimental.constrained.fptrunc.f64.x86_fp80(x86_fp80, metadata, metadata)
 
 define x86_fp80 @fadd_fp80(x86_fp80 %a, x86_fp80 %b) nounwind strictfp {
 ; X86-LABEL: fadd_fp80:
 ; X86:       # %bb.0:
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X86-NEXT:    fldt {{[0-9]+}}(%esp)
 ; X86-NEXT:    faddp %st, %st(1)
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fadd_fp80:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X64-NEXT:    faddp %st, %st(1)
 ; X64-NEXT:    retq
   %ret = call x86_fp80 @llvm.experimental.constrained.fadd.x86_fp80(x86_fp80 %a, x86_fp80 %b,
                                                                     metadata !"round.dynamic",

 ; X86-NEXT:    fldl (%esp)
 ; X86-NEXT:    movl %ebp, %esp
 ; X86-NEXT:    popl %ebp
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: fptrunc_fp80_to_f64:
 ; X64:       # %bb.0:
 ; X64-NEXT:    fldt {{[0-9]+}}(%rsp)
 ; X64-NEXT:    fstpl -{{[0-9]+}}(%rsp)
 ; X64-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
 ; X64-NEXT:    retq
   %ret = call double @llvm.experimental.constrained.fptrunc.f64.x86_fp80(x86_fp80 %a,
                                                                          metadata !"round.dynamic",
                                                                          metadata !"fpexcept.strict") #0
   ret double %ret
 }