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[X86] Model MXCSR for [v]add|sub|mul|div* instructions

Authored by pengfei on Oct 9 2019, 12:29 AM.



This patch adds MXCSR as a reserved physical register and models its use
by releated instructions. It also adds flag "mayRaiseFPException" for them.

Following what SystemZ and other targets does, only the current rounding
modes and the IEEE exception masks are modeled. *Changes* of the MXCSR
due to exceptions are not modeled.

Event Timeline

pengfei created this revision.Oct 9 2019, 12:29 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 9 2019, 12:29 AM

This looks good to me, but other users should review it as well...

This patch seems to be doing at least two different things. Can you separate the changes related to strict node handling into a separate patch?

craig.topper added inline comments.Oct 9 2019, 6:02 PM
1 ↗(On Diff #223995)

We tend to prefer to split tests by vector width rather than features. So we should have 128-bit test with sse, avx, and avx512 command lines. A 256-bit test with avx and avx512 command lines. And a 512-bit test with avx512 command line. This way we can make sure a given function is generated in a similar way for all isas.

pengfei updated this revision to Diff 224236.Oct 9 2019, 7:13 PM

Separate strict node handling from former patch. This patch only models MXCSR.

Separate strict node handling from former patch. This patch only models MXCSR.

Please update this patch's title

pengfei retitled this revision from [X86] Add strict fp support for instructions fadd/fsub/fmul/fdiv to [X86] Model MXCSR for [v]add|sub|mul|div* instructions.Oct 10 2019, 5:40 PM
pengfei abandoned this revision.Oct 31 2019, 12:06 AM

This patch is abandoned due to the similar patch D68121 was accepted.