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[AMDGPU] Support mov dpp with 64 bit operands
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Authored by rampitec on Oct 8 2019, 5:05 PM.

Details

Summary

We define mov/update dpp intrinsics as overloaded but do not
support i64, which is a practically useful type. Fix the
selection and lowering.

Diff Detail

Event Timeline

rampitec created this revision.Oct 8 2019, 5:05 PM
Herald added a project: Restricted Project. · View Herald TranscriptOct 8 2019, 5:05 PM
arsenm added inline comments.Oct 8 2019, 5:17 PM
llvm/lib/Target/AMDGPU/SIInstructions.td
1869–1875

Why not do the split here? Why treat it as a post-RA pseudo? At latest I would have expected this to be expanded in FinalizeISel

rampitec updated this revision to Diff 224506.Oct 10 2019, 5:27 PM
rampitec marked an inline comment as done.

GCNDPPCombiner can split the new pseudo and then handle the split.
Post-RA split is needed anyway since combining is an optimization.
Tests are updated to handle case w/o optimization.

rampitec updated this revision to Diff 224701.Oct 11 2019, 3:50 PM

Rebased.
Removed special handling of gfx10, it uses the same pseudo now.

vpykhtin added inline comments.Oct 14 2019, 9:57 AM
llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
577

Changed should depend on the Split done.

llvm/lib/Target/AMDGPU/SIInstrInfo.h
232

please add short desc

rampitec updated this revision to Diff 224876.Oct 14 2019, 10:50 AM
rampitec marked 2 inline comments as done.

Addressed comments.

arsenm added inline comments.Oct 14 2019, 10:56 AM
llvm/lib/Target/AMDGPU/SIInstructions.td
1869–1875

I still don't see the point of the pseudo. You can just emit the reg_sequence directly here?

This revision is now accepted and ready to land.Oct 15 2019, 6:28 AM
This revision was automatically updated to reflect the committed changes.