[ARM][MVE] validForTailPredication insts

[samparker]

Summary

'Blacklist' a few more instruction classes, including:

• instructions that 'narrow' their result.
• lane moves.
• byte swapping instructions.
• interleaving loads and stores.
• cross-beat carries.
• top/bottom instructions.
• complex operations.
• long shifts and muls.

Please shout if you know of any other instructions that could be troublesome to predict.

[dmgreen]

Exactly which instructions can and cannot go into tail predicated loops is still a bit of a mystery to me. As we talked about, a whitelist may be simpler than a blacklist to make sure we account for everything. (Thats maybe an approach if this ends up needing more in the future).

One thing I thought of, some lane moves may go through standard vmovs, or the vmovx and vins fp16 instructions. Also will interleaved fp instructions be fine in the same loop?

lib/Target/ARM/ARMInstrMVE.td

1945

This has a cross beat carry, although I'm not sure that makes it invalid for tail predication.

1976

VMOVL is used to perform widening.

2089

VSHLL?

3365

Some of the complex instructions needed earlyclobber on them as they reach cross beat.

3387

VMULL?

3489

Is anything that is top/bottom a problem?

3536

Cross beat carry again.

3931

VDUP puts the value into all lanes, but I presume that would be OK.

[samparker]

Cheers Dave, top-bottom and early clobber sound like complications. Having a whitelist sounds like a good idea, with the list of our unknowns growing, it sounds like the switch statement could be smaller too!

[samparker]

Inverted the predicate and created a whitelist instead.

[danilaml]

unittests/Target/ARM/CMakeLists.txt

2

Thanks! I realize that two other tests in this (Target) folder also have the same pattern in their CMakeLists and would benefit from the same adjustment. Not sure if it makes sense to include them in the same patch though.

[samparker]

Added support for VFMA and VMLA

[dmgreen]

Sounds good to me. Looks like a improvement over what was already here.

[Yi-Hong.Lyu]

This comment was removed by Yi-Hong.Lyu.

lib/Target/ARM/ARMInstrFormats.td

class InstTemplate<AddrMode am, int sz, IndexMode im,
   Domain D = d;
   bit isUnaryDataProc = 0;
   bit canXformTo16Bit = 0;
   // The instruction is a 16-bit flag setting Thumb instruction. Used
   // by the parser to determine whether to require the 'S' suffix on the
   // mnemonic (when not in an IT block) or preclude it (when in an IT block).
   bit thumbArithFlagSetting = 0;
 
-  bit invalidForTailPredication = 0;
+  bit validForTailPredication = 0;
 
   // If this is a pseudo instruction, mark it isCodeGenOnly.
   let isCodeGenOnly = !eq(!cast<string>(f), "Pseudo");
 
   // The layout of TSFlags should be kept in sync with ARMBaseInfo.h.
   let TSFlags{4-0}   = AM.Value;
   let TSFlags{6-5}   = IndexModeBits;
   let TSFlags{12-7} = Form;
   let TSFlags{13}    = isUnaryDataProc;
   let TSFlags{14}    = canXformTo16Bit;
   let TSFlags{18-15} = D.Value;
   let TSFlags{19}    = thumbArithFlagSetting;
-  let TSFlags{20}    = invalidForTailPredication;
+  let TSFlags{20}    = validForTailPredication;
 
   let Constraints = cstr;
   let Itinerary = itin;
 }
 
 class Encoding {
   field bits<32> Inst;
   // Mask of bits that cause an encoding to be UNPREDICTABLE.

lib/Target/ARM/ARMInstrMVE.td

class MVE_VABAV<string suffix, bit U, bits<2> size, list<dag> pattern=[]>
   let Inst{16} = 0b0;
   let Inst{15-12} = Rda{3-0};
   let Inst{8} = 0b1;
   let Inst{7} = Qn{3};
   let Inst{6} = 0b0;
   let Inst{5} = Qm{3};
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b1;
-  let invalidForTailPredication = 1;
 }
 
 def MVE_VABAVs8  : MVE_VABAV<"s8", 0b0, 0b00>;
 def MVE_VABAVs16 : MVE_VABAV<"s16", 0b0, 0b01>;
 def MVE_VABAVs32 : MVE_VABAV<"s32", 0b0, 0b10>;
 def MVE_VABAVu8  : MVE_VABAV<"u8", 0b1, 0b00>;
 def MVE_VABAVu16 : MVE_VABAV<"u16", 0b1, 0b01>;
 def MVE_VABAVu32 : MVE_VABAV<"u32", 0b1, 0b10>;
class MVE_VADDV<string iname, string suffix, dag iops, string cstr,
   let Inst{19-18} = size{1-0};
   let Inst{17-16} = 0b01;
   let Inst{15-13} = Rda{3-1};
   let Inst{12} = 0b0;
   let Inst{8-6} = 0b100;
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
-  let invalidForTailPredication = 1;
 }
 
 multiclass MVE_VADDV_A<string suffix, bit U, bits<2> size,
                        list<dag> pattern=[]> {
   def acc    : MVE_VADDV<"vaddva", suffix,
                          (ins tGPREven:$Rda_src, MQPR:$Qm), "$Rda = $Rda_src",
                          0b1, U, size, pattern>;
   def no_acc : MVE_VADDV<"vaddv", suffix,
class MVE_VADDLV<string iname, string suffix, dag iops, string cstr,
   let Inst{19-18} = 0b10;
   let Inst{17-16} = 0b01;
   let Inst{15-13} = RdaLo{3-1};
   let Inst{12} = 0b0;
   let Inst{8-6} = 0b100;
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
-  let invalidForTailPredication = 1;
 }
 
 multiclass MVE_VADDLV_A<string suffix, bit U, list<dag> pattern=[]> {
   def acc    : MVE_VADDLV<"vaddlva", suffix,
                         (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, MQPR:$Qm),
                         "$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
                         0b1, U, pattern>;
   def no_acc : MVE_VADDLV<"vaddlv", suffix,
class MVE_VMINMAXNMV<string iname, string suffix, bit sz,
   let Inst{15-12} = RdaDest{3-0};
   let Inst{8} = 0b1;
   let Inst{7} = bit_7;
   let Inst{6-5} = 0b00;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
 
   let Predicates = [HasMVEFloat];
-  let invalidForTailPredication = 1;
 }
 
 multiclass MVE_VMINMAXNMV_fty<string iname, bit bit_7, list<dag> pattern=[]> {
   def f32 : MVE_VMINMAXNMV<iname, "f32", 0b0, 0b1, bit_7, pattern>;
   def f16 : MVE_VMINMAXNMV<iname, "f16", 0b1, 0b1, bit_7, pattern>;
 }
 
 defm MVE_VMINNMV : MVE_VMINMAXNMV_fty<"vminnmv", 0b1>;
class MVE_VMINMAXV<string iname, string suffix, bit U, bits<2> size,
   let Inst{17} = bit_17;
   let Inst{16} = 0b0;
   let Inst{15-12} = RdaDest{3-0};
   let Inst{8} = 0b1;
   let Inst{7} = bit_7;
   let Inst{6-5} = 0b00;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
-  let invalidForTailPredication = 1;
 }
 
 multiclass MVE_VMINMAXV_ty<string iname, bit bit_7, list<dag> pattern=[]> {
   def s8  : MVE_VMINMAXV<iname, "s8",  0b0, 0b00, 0b1, bit_7>;
   def s16 : MVE_VMINMAXV<iname, "s16", 0b0, 0b01, 0b1, bit_7>;
   def s32 : MVE_VMINMAXV<iname, "s32", 0b0, 0b10, 0b1, bit_7>;
   def u8  : MVE_VMINMAXV<iname, "u8",  0b1, 0b00, 0b1, bit_7>;
   def u16 : MVE_VMINMAXV<iname, "u16", 0b1, 0b01, 0b1, bit_7>;
class MVE_VMLAMLSDAV<string iname, string suffix, dag iops, string cstr,
   let Inst{16} = sz;
   let Inst{15-13} = RdaDest{3-1};
   let Inst{12} = X;
   let Inst{8} = bit_8;
   let Inst{7-6} = 0b00;
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = bit_0;
-  let invalidForTailPredication = 1;
 }
 
 multiclass MVE_VMLAMLSDAV_A<string iname, string x, string suffix,
                             bit sz, bit bit_28, bit X, bit bit_8, bit bit_0,
                             list<dag> pattern=[]> {
   def ""#x#suffix : MVE_VMLAMLSDAV<iname # x, suffix,
                                    (ins MQPR:$Qn, MQPR:$Qm), "",
                                    sz, bit_28, 0b0, X, bit_8, bit_0, pattern>;
class MVE_VMLALDAVBase<string iname, string suffix, dag iops, string cstr,
   let Inst{16} = sz;
   let Inst{15-13} = RdaLoDest{3-1};
   let Inst{12} = X;
   let Inst{8} = bit_8;
   let Inst{7-6} = 0b00;
   let Inst{5} = A;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = bit_0;
-  let invalidForTailPredication = 1;
 }
 
 multiclass MVE_VMLALDAVBase_A<string iname, string x, string suffix,
                                bit sz, bit bit_28, bit X, bit bit_8, bit bit_0,
                                list<dag> pattern=[]> {
   def ""#x#suffix : MVE_VMLALDAVBase<
      iname # x, suffix, (ins MQPR:$Qn, MQPR:$Qm), "",
      sz, bit_28, 0b0, X, bit_8, bit_0, pattern>;
def MVE_VBIC : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm),
   let Inst{21-20} = 0b01;
   let Inst{19-17} = Qn{2-0};
   let Inst{16} = 0b0;
   let Inst{12-8} = 0b00001;
   let Inst{7} = Qn{3};
   let Inst{6} = 0b1;
   let Inst{4} = 0b1;
   let Inst{0} = 0b0;
+  let validForTailPredication = 1;
 }
 
 class MVE_VREV<string iname, string suffix, bits<2> size, bits<2> bit_8_7, string cstr="">
   : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qm), iname,
                   suffix, "$Qd, $Qm", cstr> {
 
   let Inst{28} = 0b1;
   let Inst{25-23} = 0b111;

 def MVE_VMVN : MVE_bit_arith<(outs MQPR:$Qd), (ins MQPR:$Qm),
                              "vmvn", "", "$Qd, $Qm", ""> {
   let Inst{28} = 0b1;
   let Inst{25-23} = 0b111;
   let Inst{21-16} = 0b110000;
   let Inst{12-6} = 0b0010111;
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
+  let validForTailPredication = 1;
 }
 
 let Predicates = [HasMVEInt] in {
   def : Pat<(v16i8 (vnotq  (v16i8 MQPR:$val1))),
             (v16i8 (MVE_VMVN (v16i8 MQPR:$val1)))>;
   def : Pat<(v8i16 (vnotq  (v8i16 MQPR:$val1))),
             (v8i16 (MVE_VMVN (v8i16 MQPR:$val1)))>;
   def : Pat<(v4i32 (vnotq  (v4i32 MQPR:$val1))),
class MVE_bit_ops<string iname, bits<2> bit_21_20, bit bit_28>
   let Inst{21-20} = bit_21_20;
   let Inst{19-17} = Qn{2-0};
   let Inst{16} = 0b0;
   let Inst{12-8} = 0b00001;
   let Inst{7} = Qn{3};
   let Inst{6} = 0b1;
   let Inst{4} = 0b1;
   let Inst{0} = 0b0;
+  let validForTailPredication = 1;
 }
 
 def MVE_VEOR : MVE_bit_ops<"veor", 0b00, 0b1>;
 def MVE_VORN : MVE_bit_ops<"vorn", 0b11, 0b0>;
 def MVE_VORR : MVE_bit_ops<"vorr", 0b10, 0b0>;
 def MVE_VAND : MVE_bit_ops<"vand", 0b00, 0b0>;
 
 // add ignored suffixes as aliases
class MVE_bit_cmode<string iname, string suffix, bits<4> cmode, dag inOps>
   let Inst{7-6} = 0b01;
   let Inst{4} = 0b1;
   let Inst{3-0} = imm{3-0};
 }
 
 class MVE_VORR<string suffix, bits<4> cmode, ExpandImm imm_type>
   : MVE_bit_cmode<"vorr", suffix, cmode, (ins MQPR:$Qd_src, imm_type:$imm)> {
   let Inst{5} = 0b0;
+  let validForTailPredication = 1;
 }
 
 def MVE_VORRIZ0v4i32  : MVE_VORR<"i32", 0b0001, expzero00>;
 def MVE_VORRIZ0v8i16  : MVE_VORR<"i16", 0b1001, expzero00>;
 def MVE_VORRIZ8v4i32  : MVE_VORR<"i32", 0b0011, expzero08>;
 def MVE_VORRIZ8v8i16  : MVE_VORR<"i16", 0b1011, expzero08>;
 def MVE_VORRIZ16v4i32 : MVE_VORR<"i32", 0b0101, expzero16>;
 def MVE_VORRIZ24v4i32 : MVE_VORR<"i32", 0b0111, expzero24>;
def MVE_VORNIZ24v4i32 : MVEAsmPseudo<"vorn${vp}.i32\t$Qd, $imm",
     (ins MQPR:$Qd_src, expzero24inv32:$imm, vpred_n:$vp), (outs MQPR:$Qd)>;
 
 def MVE_VMOV : MVEInstAlias<"vmov${vp}\t$Qd, $Qm",
     (MVE_VORR MQPR:$Qd, MQPR:$Qm, MQPR:$Qm, vpred_r:$vp)>;
 
 class MVE_VBIC<string suffix, bits<4> cmode, ExpandImm imm_type>
   : MVE_bit_cmode<"vbic", suffix, cmode, (ins MQPR:$Qd_src, imm_type:$imm)> {
   let Inst{5} = 0b1;
+  let validForTailPredication = 1;
 }
 
 def MVE_VBICIZ0v4i32  : MVE_VBIC<"i32", 0b0001, expzero00>;
 def MVE_VBICIZ0v8i16  : MVE_VBIC<"i16", 0b1001, expzero00>;
 def MVE_VBICIZ8v4i32  : MVE_VBIC<"i32", 0b0011, expzero08>;
 def MVE_VBICIZ8v8i16  : MVE_VBIC<"i16", 0b1011, expzero08>;
 def MVE_VBICIZ16v4i32 : MVE_VBIC<"i32", 0b0101, expzero16>;
 def MVE_VBICIZ24v4i32 : MVE_VBIC<"i32", 0b0111, expzero24>;
class MVE_VADDSUB<string iname, string suffix, bits<2> size, bit subtract,
   : MVE_int<iname, suffix, size, pattern> {
 
   let Inst{28} = subtract;
   let Inst{25-23} = 0b110;
   let Inst{16} = 0b0;
   let Inst{12-8} = 0b01000;
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
+  let validForTailPredication = 1;
 }
 
 class MVE_VADD<string suffix, bits<2> size, list<dag> pattern=[]>
   : MVE_VADDSUB<"vadd", suffix, size, 0b0, pattern>;
 class MVE_VSUB<string suffix, bits<2> size, list<dag> pattern=[]>
   : MVE_VADDSUB<"vsub", suffix, size, 0b1, pattern>;
 
 def MVE_VADDi8  : MVE_VADD<"i8",  0b00>;
class MVE_VQADDSUB<string iname, string suffix, bit U, bit subtract,
   let Inst{28} = U;
   let Inst{25-23} = 0b110;
   let Inst{16} = 0b0;
   let Inst{12-10} = 0b000;
   let Inst{9} = subtract;
   let Inst{8} = 0b0;
   let Inst{4} = 0b1;
   let Inst{0} = 0b0;
+  let validForTailPredication = 1;
 }
 
 class MVE_VQADD<string suffix, bit U, bits<2> size, list<dag> pattern=[]>
   : MVE_VQADDSUB<"vqadd", suffix, U, 0b0, size, pattern>;
 class MVE_VQSUB<string suffix, bit U, bits<2> size, list<dag> pattern=[]>
   : MVE_VQADDSUB<"vqsub", suffix, U, 0b1, size, pattern>;
 
 def MVE_VQADDs8  : MVE_VQADD<"s8",  0b0, 0b00>;
class MVE_VABD_int<string suffix, bit U, bits<2> size, list<dag> pattern=[]>
   : MVE_int<"vabd", suffix, size, pattern> {
 
   let Inst{28} = U;
   let Inst{25-23} = 0b110;
   let Inst{16} = 0b0;
   let Inst{12-8} = 0b00111;
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
+  let validForTailPredication = 1;
 }
 
 def MVE_VABDs8  : MVE_VABD_int<"s8", 0b0, 0b00>;
 def MVE_VABDs16 : MVE_VABD_int<"s16", 0b0, 0b01>;
 def MVE_VABDs32 : MVE_VABD_int<"s32", 0b0, 0b10>;
 def MVE_VABDu8  : MVE_VABD_int<"u8", 0b1, 0b00>;
 def MVE_VABDu16 : MVE_VABD_int<"u16", 0b1, 0b01>;
 def MVE_VABDu32 : MVE_VABD_int<"u32", 0b1, 0b10>;
 
 class MVE_VRHADD<string suffix, bit U, bits<2> size, list<dag> pattern=[]>
   : MVE_int<"vrhadd", suffix, size, pattern> {
 
   let Inst{28} = U;
   let Inst{25-23} = 0b110;
   let Inst{16} = 0b0;
   let Inst{12-8} = 0b00001;
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
+  let validForTailPredication = 1;
 }
 
 def MVE_VRHADDs8  : MVE_VRHADD<"s8", 0b0, 0b00>;
 def MVE_VRHADDs16 : MVE_VRHADD<"s16", 0b0, 0b01>;
 def MVE_VRHADDs32 : MVE_VRHADD<"s32", 0b0, 0b10>;
 def MVE_VRHADDu8  : MVE_VRHADD<"u8", 0b1, 0b00>;
 def MVE_VRHADDu16 : MVE_VRHADD<"u16", 0b1, 0b01>;
 def MVE_VRHADDu32 : MVE_VRHADD<"u32", 0b1, 0b10>;
 
 class MVE_VHADDSUB<string iname, string suffix, bit U, bit subtract,
                    bits<2> size, list<dag> pattern=[]>
   : MVE_int<iname, suffix, size, pattern> {
 
   let Inst{28} = U;
   let Inst{25-23} = 0b110;
   let Inst{16} = 0b0;
   let Inst{12-10} = 0b000;
   let Inst{9} = subtract;
   let Inst{8} = 0b0;
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
+  let validForTailPredication = 1;
 }
 
 class MVE_VHADD<string suffix, bit U, bits<2> size,
               list<dag> pattern=[]>
   : MVE_VHADDSUB<"vhadd", suffix, U, 0b0, size, pattern>;
 class MVE_VHSUB<string suffix, bit U, bits<2> size,
               list<dag> pattern=[]>
   : MVE_VHADDSUB<"vhsub", suffix, U, 0b1, size, pattern>;
class MVE_VDUP<string suffix, bit B, bit E, list<dag> pattern=[]>
   let Inst{19-17} = Qd{2-0};
   let Inst{16} = 0b0;
   let Inst{15-12} = Rt;
   let Inst{11-8} = 0b1011;
   let Inst{7} = Qd{3};
   let Inst{6} = 0b0;
   let Inst{5} = E;
   let Inst{4-0} = 0b10000;
+  let validForTailPredication = 1;
 }
 
 def MVE_VDUP32 : MVE_VDUP<"32", 0b0, 0b0>;
 def MVE_VDUP16 : MVE_VDUP<"16", 0b0, 0b1>;
 def MVE_VDUP8  : MVE_VDUP<"8",  0b1, 0b0>;
 
 let Predicates = [HasMVEInt] in {
   def : Pat<(v16i8 (ARMvdup (i32 rGPR:$elem))),
class MVE_VCLSCLZ<string iname, string suffix, bits<2> size,
   let Inst{25-23} = 0b111;
   let Inst{21-20} = 0b11;
   let Inst{17-16} = 0b00;
   let Inst{12-8} = 0b00100;
   let Inst{7} = count_zeroes;
   let Inst{6} = 0b1;
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
+  let validForTailPredication = 1;
 }
 
 def MVE_VCLSs8  : MVE_VCLSCLZ<"vcls", "s8",  0b00, 0b0>;
 def MVE_VCLSs16 : MVE_VCLSCLZ<"vcls", "s16", 0b01, 0b0>;
 def MVE_VCLSs32 : MVE_VCLSCLZ<"vcls", "s32", 0b10, 0b0>;
 
 def MVE_VCLZs8  : MVE_VCLSCLZ<"vclz", "i8",  0b00, 0b1>;
 def MVE_VCLZs16 : MVE_VCLSCLZ<"vclz", "i16", 0b01, 0b1>;
class MVE_VABSNEG_int<string iname, string suffix, bits<2> size, bit negate,
   let Inst{25-23} = 0b111;
   let Inst{21-20} = 0b11;
   let Inst{17-16} = 0b01;
   let Inst{12-8} = 0b00011;
   let Inst{7} = negate;
   let Inst{6} = 0b1;
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
+  let validForTailPredication = 1;
 }
 
 def MVE_VABSs8  : MVE_VABSNEG_int<"vabs", "s8",  0b00, 0b0>;
 def MVE_VABSs16 : MVE_VABSNEG_int<"vabs", "s16", 0b01, 0b0>;
 def MVE_VABSs32 : MVE_VABSNEG_int<"vabs", "s32", 0b10, 0b0>;
 
 let Predicates = [HasMVEInt] in {
   def : Pat<(v16i8 (abs (v16i8 MQPR:$v))),
class MVE_VQABSNEG<string iname, string suffix, bits<2> size,
   let Inst{25-23} = 0b111;
   let Inst{21-20} = 0b11;
   let Inst{17-16} = 0b00;
   let Inst{12-8} = 0b00111;
   let Inst{7} = negate;
   let Inst{6} = 0b1;
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
+  let validForTailPredication = 1;
 }
 
 def MVE_VQABSs8  : MVE_VQABSNEG<"vqabs", "s8",  0b00, 0b0>;
 def MVE_VQABSs16 : MVE_VQABSNEG<"vqabs", "s16", 0b01, 0b0>;
 def MVE_VQABSs32 : MVE_VQABSNEG<"vqabs", "s32", 0b10, 0b0>;
 
 def MVE_VQNEGs8  : MVE_VQABSNEG<"vqneg", "s8",  0b00, 0b1>;
 def MVE_VQNEGs16 : MVE_VQABSNEG<"vqneg", "s16", 0b01, 0b1>;
class MVE_mod_imm<string iname, string suffix, bits<4> cmode, bit op,
   let Inst{12} = 0b0;
   let Inst{11-8} = cmode{3-0};
   let Inst{7-6} = 0b01;
   let Inst{5} = op;
   let Inst{4} = 0b1;
   let Inst{3-0} = imm{3-0};
 
   let DecoderMethod = "DecodeMVEModImmInstruction";
+  let validForTailPredication = 1;
 }
 
 let isReMaterializable = 1 in {
 let isAsCheapAsAMove = 1 in {
 def MVE_VMOVimmi8  : MVE_mod_imm<"vmov", "i8",  {1,1,1,0}, 0b0, (ins nImmSplatI8:$imm)>;
 def MVE_VMOVimmi16 : MVE_mod_imm<"vmov", "i16", {1,0,?,0}, 0b0, (ins nImmSplatI16:$imm)> {
   let Inst{9} = imm{9};
 }

 }
 
 def MVE_VMAXAs8  : MVE_VMINMAXA<"vmaxa", "s8",  0b00, 0b0>;
 def MVE_VMAXAs16 : MVE_VMINMAXA<"vmaxa", "s16", 0b01, 0b0>;
 def MVE_VMAXAs32 : MVE_VMINMAXA<"vmaxa", "s32", 0b10, 0b0>;
 
 def MVE_VMINAs8  : MVE_VMINMAXA<"vmina", "s8",  0b00, 0b1>;
 def MVE_VMINAs16 : MVE_VMINMAXA<"vmina", "s16", 0b01, 0b1>;
 def MVE_VMINAs32 : MVE_VMINMAXA<"vmina", "s32", 0b10, 0b1>;
 
 // end of MVE Integer instructions
 
 // start of mve_imm_shift instructions
 
 def MVE_VSHLC : MVE_p<(outs rGPR:$RdmDest, MQPR:$Qd),
                       (ins MQPR:$QdSrc, rGPR:$RdmSrc, long_shift:$imm),
                       NoItinerary, "vshlc", "", "$QdSrc, $RdmSrc, $imm",

 
 class MVE_shift_imm<dag oops, dag iops, string iname, string suffix,
                     string ops, vpred_ops vpred, string cstr,
                     list<dag> pattern=[]>
   : MVE_p<oops, iops, NoItinerary, iname, suffix, ops, vpred, cstr, pattern> {
   bits<4> Qd;
   bits<4> Qm;
 
   let Inst{22} = Qd{3};
   let Inst{15-13} = Qd{2-0};
   let Inst{5} = Qm{3};
   let Inst{3-1} = Qm{2-0};
 }
 
 class MVE_VMOVL<string iname, string suffix, bits<2> sz, bit U,
               list<dag> pattern=[]>
   : MVE_shift_imm<(outs MQPR:$Qd), (ins MQPR:$Qm),
class MVE_VSHLL_by_lane_width<string iname, string suffix, bits<2> size,
   let Inst{4} = 0b0;
   let Inst{0} = 0b1;
 }
 
 multiclass MVE_VSHLL_lw<string iname, string suffix, bits<2> sz, bit U,
                               string ops, list<dag> pattern=[]> {
   def bh : MVE_VSHLL_by_lane_width<iname#"b", suffix, sz, U, ops, pattern> {
     let Inst{12} = 0b0;
   }
   def th : MVE_VSHLL_by_lane_width<iname#"t", suffix, sz, U, ops, pattern> {
     let Inst{12} = 0b1;
   }
 }
 
 defm MVE_VSHLL_lws8  : MVE_VSHLL_lw<"vshll", "s8",  0b00, 0b0, "$Qd, $Qm, #8">;
 defm MVE_VSHLL_lws16 : MVE_VSHLL_lw<"vshll", "s16", 0b01, 0b0, "$Qd, $Qm, #16">;
 defm MVE_VSHLL_lwu8  : MVE_VSHLL_lw<"vshll", "u8",  0b00, 0b1, "$Qd, $Qm, #8">;
class MVE_shift_by_vec<string iname, string suffix, bit U,
   let Inst{12-9} = 0b0010;
   let Inst{8} = bit_8;
   let Inst{7} = Qn{3};
   let Inst{6} = 0b1;
   let Inst{5} = Qm{3};
   let Inst{4} = bit_4;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
+  let validForTailPredication = 1;
 }
 
 multiclass mve_shift_by_vec_multi<string iname, bit bit_4, bit bit_8> {
   def s8  : MVE_shift_by_vec<iname, "s8", 0b0, 0b00, bit_4, bit_8>;
   def s16 : MVE_shift_by_vec<iname, "s16", 0b0, 0b01, bit_4, bit_8>;
   def s32 : MVE_shift_by_vec<iname, "s32", 0b0, 0b10, bit_4, bit_8>;
   def u8  : MVE_shift_by_vec<iname, "u8", 0b1, 0b00, bit_4, bit_8>;
   def u16 : MVE_shift_by_vec<iname, "u16", 0b1, 0b01, bit_4, bit_8>;
class MVE_shift_with_imm<string iname, string suffix, dag oops, dag iops,
   let Inst{22} = Qd{3};
   let Inst{15-13} = Qd{2-0};
   let Inst{12-11} = 0b00;
   let Inst{7-6} = 0b01;
   let Inst{5} = Qm{3};
   let Inst{4} = 0b1;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b0;
+  let validForTailPredication = 1;
 }
 
 class MVE_VSxI_imm<string iname, string suffix, bit bit_8, dag imm>
   : MVE_shift_with_imm<iname, suffix, (outs MQPR:$Qd),
                        !con((ins MQPR:$Qd_src, MQPR:$Qm), imm),
                        "$Qd, $Qm, $imm", vpred_n, "$Qd = $Qd_src"> {
   bits<6> imm;
   let Inst{28} = 0b1;
   let Inst{25-24} = 0b11;
   let Inst{21-16} = imm;
   let Inst{10-9} = 0b10;
   let Inst{8} = bit_8;
+  let validForTailPredication = 1;
 }
 
 def MVE_VSRIimm8 : MVE_VSxI_imm<"vsri", "8", 0b0, (ins shr_imm8:$imm)> {
   let Inst{21-19} = 0b001;
 }
 
 def MVE_VSRIimm16 : MVE_VSxI_imm<"vsri", "16", 0b0, (ins shr_imm16:$imm)> {
   let Inst{21-20} = 0b01;
class MVE_VRINT<string rmode, bits<3> op, string suffix, bits<2> size,
   let Inst{22} = Qd{3};
   let Inst{21-20} = 0b11;
   let Inst{19-18} = size;
   let Inst{17-16} = 0b10;
   let Inst{15-13} = Qd{2-0};
   let Inst{11-10} = 0b01;
   let Inst{9-7} = op{2-0};
   let Inst{4} = 0b0;
+  let validForTailPredication = 1;
 
 }
 
 multiclass MVE_VRINT_ops<string suffix, bits<2> size, list<dag> pattern=[]> {
   def N : MVE_VRINT<"n", 0b000, suffix, size, pattern>;
   def X : MVE_VRINT<"x", 0b001, suffix, size, pattern>;
   def A : MVE_VRINT<"a", 0b010, suffix, size, pattern>;
   def Z : MVE_VRINT<"z", 0b011, suffix, size, pattern>;
class MVE_VMUL_fp<string suffix, bit size, list<dag> pattern=[]>
   let Inst{25-23} = 0b110;
   let Inst{22} = Qd{3};
   let Inst{21} = 0b0;
   let Inst{19-17} = Qn{2-0};
   let Inst{15-13} = Qd{2-0};
   let Inst{12-8} = 0b01101;
   let Inst{7} = Qn{3};
   let Inst{4} = 0b1;
+  let validForTailPredication = 1;
 }
 
 def MVE_VMULf32 : MVE_VMUL_fp<"f32", 0b0>;
 def MVE_VMULf16 : MVE_VMUL_fp<"f16", 0b1>;
 
 let Predicates = [HasMVEFloat] in {
   def : Pat<(v4f32 (fmul (v4f32 MQPR:$val1), (v4f32 MQPR:$val2))),
             (v4f32 (MVE_VMULf32 (v4f32 MQPR:$val1), (v4f32 MQPR:$val2)))>;

 let Predicates = [HasMVEFloat] in {
   def : Pat<(v8f16 (fma (v8f16 MQPR:$src1), (v8f16 MQPR:$src2), (v8f16 MQPR:$src3))),
             (v8f16 (MVE_VFMAf16 $src3, $src1, $src2))>;
   def : Pat<(v4f32 (fma (v4f32 MQPR:$src1), (v4f32 MQPR:$src2), (v4f32 MQPR:$src3))),
             (v4f32 (MVE_VFMAf32 $src3, $src1, $src2))>;
 }
 
 
+let validForTailPredication = 1 in {
   def MVE_VADDf32 : MVE_VADDSUBFMA_fp<"vadd", "f32", 0b0, 0b0, 0b1, 0b0>;
   def MVE_VADDf16 : MVE_VADDSUBFMA_fp<"vadd", "f16", 0b1, 0b0, 0b1, 0b0>;
+}
 
 let Predicates = [HasMVEFloat] in {
   def : Pat<(v4f32 (fadd (v4f32 MQPR:$val1), (v4f32 MQPR:$val2))),
             (v4f32 (MVE_VADDf32 (v4f32 MQPR:$val1), (v4f32 MQPR:$val2)))>;
   def : Pat<(v8f16 (fadd (v8f16 MQPR:$val1), (v8f16 MQPR:$val2))),
             (v8f16 (MVE_VADDf16 (v8f16 MQPR:$val1), (v8f16 MQPR:$val2)))>;
 }
 
+
+let validForTailPredication = 1 in {
   def MVE_VSUBf32 : MVE_VADDSUBFMA_fp<"vsub", "f32", 0b0, 0b0, 0b1, 0b1>;
   def MVE_VSUBf16 : MVE_VADDSUBFMA_fp<"vsub", "f16", 0b1, 0b0, 0b1, 0b1>;
+}
 
 let Predicates = [HasMVEFloat] in {
   def : Pat<(v4f32 (fsub (v4f32 MQPR:$val1), (v4f32 MQPR:$val2))),
             (v4f32 (MVE_VSUBf32 (v4f32 MQPR:$val1), (v4f32 MQPR:$val2)))>;
   def : Pat<(v8f16 (fsub (v8f16 MQPR:$val1), (v8f16 MQPR:$val2))),
             (v8f16 (MVE_VSUBf16 (v8f16 MQPR:$val1), (v8f16 MQPR:$val2)))>;
 }
 
class MVE_VABD_fp<string suffix, bit size>
   let Inst{21} = 0b1;
   let Inst{20} = size;
   let Inst{19-17} = Qn{2-0};
   let Inst{16} = 0b0;
   let Inst{15-13} = Qd{2-0};
   let Inst{11-8} = 0b1101;
   let Inst{7} = Qn{3};
   let Inst{4} = 0b0;
+  let validForTailPredication = 1;
 }
 
 def MVE_VABDf32 : MVE_VABD_fp<"f32", 0b0>;
 def MVE_VABDf16 : MVE_VABD_fp<"f16", 0b1>;
 
 class MVE_VCVT_fix<string suffix, bit fsi, bit U, bit op,
                    Operand imm_operand_type, list<dag> pattern=[]>
   : MVE_float<"vcvt", suffix,
class MVE_VCVT_fix<string suffix, bit fsi, bit U, bit op,
   let Inst{15-13} = Qd{2-0};
   let Inst{11-10} = 0b11;
   let Inst{9} = fsi;
   let Inst{8} = op;
   let Inst{7} = 0b0;
   let Inst{4} = 0b1;
 
   let DecoderMethod = "DecodeMVEVCVTt1fp";
+  let validForTailPredication = 1;
 }
 
 class MVE_VCVT_imm_asmop<int Bits> : AsmOperandClass {
   let PredicateMethod = "isImmediate<1," # Bits # ">";
   let DiagnosticString =
       "MVE fixed-point immediate operand must be between 1 and " # Bits;
   let Name = "MVEVcvtImm" # Bits;
   let RenderMethod = "addImmOperands";
class MVE_VCVT_fp_int_anpm<string suffix, bits<2> size, bit op, string anpm,
   let Inst{21-20} = 0b11;
   let Inst{19-18} = size;
   let Inst{17-16} = 0b11;
   let Inst{15-13} = Qd{2-0};
   let Inst{12-10} = 0b000;
   let Inst{9-8} = rm;
   let Inst{7} = op;
   let Inst{4} = 0b0;
+  let validForTailPredication = 1;
 }
 
 multiclass MVE_VCVT_fp_int_anpm_multi<string suffix, bits<2> size, bit op,
                                 list<dag> pattern=[]> {
   def a : MVE_VCVT_fp_int_anpm<suffix, size, op, "a", 0b00>;
   def n : MVE_VCVT_fp_int_anpm<suffix, size, op, "n", 0b01>;
   def p : MVE_VCVT_fp_int_anpm<suffix, size, op, "p", 0b10>;
   def m : MVE_VCVT_fp_int_anpm<suffix, size, op, "m", 0b11>;
class MVE_VCVT_fp_int<string suffix, bits<2> size, bits<2> op,
   let Inst{22} = Qd{3};
   let Inst{21-20} = 0b11;
   let Inst{19-18} = size;
   let Inst{17-16} = 0b11;
   let Inst{15-13} = Qd{2-0};
   let Inst{12-9} = 0b0011;
   let Inst{8-7} = op;
   let Inst{4} = 0b0;
+  let validForTailPredication = 1;
 }
 
 // The unsuffixed VCVT for float->int implicitly rounds toward zero,
 // which I reflect here in the llvm instruction names
 def MVE_VCVTs16f16z : MVE_VCVT_fp_int<"s16.f16", 0b01, 0b10>;
 def MVE_VCVTu16f16z : MVE_VCVT_fp_int<"u16.f16", 0b01, 0b11>;
 def MVE_VCVTs32f32z : MVE_VCVT_fp_int<"s32.f32", 0b10, 0b10>;
 def MVE_VCVTu32f32z : MVE_VCVT_fp_int<"u32.f32", 0b10, 0b11>;
class MVE_VABSNEG_fp<string iname, string suffix, bits<2> size, bit negate,
   let Inst{22} = Qd{3};
   let Inst{21-20} = 0b11;
   let Inst{19-18} = size;
   let Inst{17-16} = 0b01;
   let Inst{15-13} = Qd{2-0};
   let Inst{11-8} = 0b0111;
   let Inst{7} = negate;
   let Inst{4} = 0b0;
+  let validForTailPredication = 1;
 }
 
 def MVE_VABSf16 : MVE_VABSNEG_fp<"vabs", "f16", 0b01, 0b0>;
 def MVE_VABSf32 : MVE_VABSNEG_fp<"vabs", "f32", 0b10, 0b0>;
 
 let Predicates = [HasMVEFloat] in {
   def : Pat<(v8f16 (fabs MQPR:$src)),
             (MVE_VABSf16 MQPR:$src)>;
class MVE_VCMPqq<string suffix, bit bit_28, bits<2> bits_21_20,
   // the output VCCR operand, which isn't encoded in the instruction
   // bits anywhere (there is only one choice for it) but has to be
   // included in the MC operands so that codegen will be able to track
   // its data flow between instructions, spill/reload it when
   // necessary, etc. There seems to be no way to get the Tablegen
   // decoder to emit an operand that isn't affected by any instruction
   // bit.
   let DecoderMethod = "DecodeMVEVCMP<false," # predtype.DecoderMethod # ">";
+  let validForTailPredication = 1;
 }
 
 class MVE_VCMPqqf<string suffix, bit size>
     : MVE_VCMPqq<suffix, size, 0b11, pred_basic_fp> {
   let Predicates = [HasMVEFloat];
 }
 
 class MVE_VCMPqqi<string suffix, bits<2> size>
class MVE_VCMPqr<string suffix, bit bit_28, bits<2> bits_21_20,
   let Inst{6} = 0b1;
   let Inst{5} = fc{1};
   let Inst{4} = 0b0;
   let Inst{3-0} = Rm{3-0};
 
   let Constraints = "";
   // Custom decoder method, for the same reason as MVE_VCMPqq
   let DecoderMethod = "DecodeMVEVCMP<true," # predtype.DecoderMethod # ">";
+  let validForTailPredication = 1;
 }
 
 class MVE_VCMPqrf<string suffix, bit size>
     : MVE_VCMPqr<suffix, size, 0b11, pred_basic_fp> {
   let Predicates = [HasMVEFloat];
 }
 
 class MVE_VCMPqri<string suffix, bits<2> size>
class MVE_VQxDMLxDH<string iname, bit exch, bit round, bit subtract,
 
   let Inst{28} = subtract;
   let Inst{21-20} = size;
   let Inst{19-17} = Qn{2-0};
   let Inst{16} = 0b0;
   let Inst{12} = exch;
   let Inst{8} = 0b0;
   let Inst{7} = Qn{3};
   let Inst{0} = round;
 }
 
 multiclass MVE_VQxDMLxDH_multi<string iname, bit exch,
                                bit round, bit subtract> {
   def s8  : MVE_VQxDMLxDH<iname, exch, round, subtract, "s8",  0b00>;
   def s16 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s16", 0b01>;
   def s32 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s32", 0b10, ",@earlyclobber $Qd">;
 }
 
 defm MVE_VQDMLADH   : MVE_VQxDMLxDH_multi<"vqdmladh",   0b0, 0b0, 0b0>;
 defm MVE_VQDMLADHX  : MVE_VQxDMLxDH_multi<"vqdmladhx",  0b1, 0b0, 0b0>;
 defm MVE_VQRDMLADH  : MVE_VQxDMLxDH_multi<"vqrdmladh",  0b0, 0b1, 0b0>;
 defm MVE_VQRDMLADHX : MVE_VQxDMLxDH_multi<"vqrdmladhx", 0b1, 0b1, 0b0>;
 defm MVE_VQDMLSDH   : MVE_VQxDMLxDH_multi<"vqdmlsdh",   0b0, 0b0, 0b1>;
 defm MVE_VQDMLSDHX  : MVE_VQxDMLxDH_multi<"vqdmlsdhx",  0b1, 0b0, 0b1>;
 defm MVE_VQRDMLSDH  : MVE_VQxDMLxDH_multi<"vqrdmlsdh",  0b0, 0b1, 0b1>;
 defm MVE_VQRDMLSDHX : MVE_VQxDMLxDH_multi<"vqrdmlsdhx", 0b1, 0b1, 0b1>;
 
 class MVE_VCMUL<string iname, string suffix, bit size, string cstr="", list<dag> pattern=[]>
   : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
                    (ins MQPR:$Qn, MQPR:$Qm, complexrotateop:$rot),
                    "$Qd, $Qn, $Qm, $rot", vpred_r, cstr, pattern> {
   bits<4> Qn;
   bits<2> rot;
 
   let Inst{28} = size;
   let Inst{21-20} = 0b11;
   let Inst{19-17} = Qn{2-0};
   let Inst{16} = 0b0;
   let Inst{12} = rot{1};
class MVE_VxMOVxN<string iname, string suffix, bit bit_28, bit bit_17,
   let Inst{28} = bit_28;
   let Inst{21-20} = 0b11;
   let Inst{19-18} = size;
   let Inst{17} = bit_17;
   let Inst{16} = 0b1;
   let Inst{12} = T;
   let Inst{8} = 0b0;
   let Inst{7} = !if(!eq(bit_17, 0), 1, 0);
   let Inst{0} = 0b1;
 }
 
 multiclass MVE_VxMOVxN_halves<string iname, string suffix,
                               bit bit_28, bit bit_17, bits<2> size> {
   def bh : MVE_VxMOVxN<iname # "b", suffix, bit_28, bit_17, size, 0b0>;
   def th : MVE_VxMOVxN<iname # "t", suffix, bit_28, bit_17, size, 0b1>;
 }
 

 class MVE_VxCADD<string iname, string suffix, bits<2> size, bit halve,
                  string cstr="", list<dag> pattern=[]>
   : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
                    (ins MQPR:$Qn, MQPR:$Qm, complexrotateopodd:$rot),
                    "$Qd, $Qn, $Qm, $rot", vpred_r, cstr, pattern> {
   bits<4> Qn;
   bit rot;
 
   let Inst{28} = halve;
   let Inst{21-20} = size;
   let Inst{19-17} = Qn{2-0};
   let Inst{16} = 0b0;
   let Inst{12} = rot;
   let Inst{8} = 0b1;
   let Inst{7} = Qn{3};
   let Inst{0} = 0b0;
 }
class MVE_VADDSUB_qr<string iname, string suffix, bits<2> size,
   : MVE_qDest_rSrc<iname, suffix, "", pattern> {
 
   let Inst{28} = bit_28;
   let Inst{21-20} = size;
   let Inst{16} = bit_16;
   let Inst{12} = bit_12;
   let Inst{8} = 0b1;
   let Inst{5} = bit_5;
+  let validForTailPredication = 1;
 }
 
 multiclass MVE_VADDSUB_qr_sizes<string iname, string suffix,
                                 bit bit_5, bit bit_12, bit bit_16,
                                 bit bit_28, list<dag> pattern=[]> {
   def "8"  : MVE_VADDSUB_qr<iname, suffix#"8",  0b00,
                             bit_5, bit_12, bit_16, bit_28>;
   def "16" : MVE_VADDSUB_qr<iname, suffix#"16", 0b01,
class MVE_VxADDSUB_qr<string iname, string suffix,
   : MVE_qDest_rSrc<iname, suffix, "", pattern> {
 
   let Inst{28} = bit_28;
   let Inst{21-20} = bits_21_20;
   let Inst{16} = 0b0;
   let Inst{12} = subtract;
   let Inst{8} = 0b1;
   let Inst{5} = 0b0;
+  let validForTailPredication = 1;
 }
 
 def MVE_VHADD_qr_s8   : MVE_VxADDSUB_qr<"vhadd", "s8",  0b0, 0b00, 0b0>;
 def MVE_VHADD_qr_s16  : MVE_VxADDSUB_qr<"vhadd", "s16", 0b0, 0b01, 0b0>;
 def MVE_VHADD_qr_s32  : MVE_VxADDSUB_qr<"vhadd", "s32", 0b0, 0b10, 0b0>;
 def MVE_VHADD_qr_u8   : MVE_VxADDSUB_qr<"vhadd", "u8",  0b1, 0b00, 0b0>;
 def MVE_VHADD_qr_u16  : MVE_VxADDSUB_qr<"vhadd", "u16", 0b1, 0b01, 0b0>;
 def MVE_VHADD_qr_u32  : MVE_VxADDSUB_qr<"vhadd", "u32", 0b1, 0b10, 0b0>;
class MVE_VxSHL_qr<string iname, string suffix, bit U, bits<2> size,
   let Inst{25-23} = 0b100;
   let Inst{21-20} = 0b11;
   let Inst{19-18} = size;
   let Inst{17} = bit_17;
   let Inst{16} = 0b1;
   let Inst{12-8} = 0b11110;
   let Inst{7} = bit_7;
   let Inst{6-4} = 0b110;
+  let validForTailPredication = 1;
 }
 
 multiclass MVE_VxSHL_qr_types<string iname, bit bit_7, bit bit_17> {
   def s8  : MVE_VxSHL_qr<iname, "s8", 0b0, 0b00, bit_7, bit_17>;
   def s16 : MVE_VxSHL_qr<iname, "s16", 0b0, 0b01, bit_7, bit_17>;
   def s32 : MVE_VxSHL_qr<iname, "s32", 0b0, 0b10, bit_7, bit_17>;
   def u8  : MVE_VxSHL_qr<iname, "u8", 0b1, 0b00, bit_7, bit_17>;
   def u16 : MVE_VxSHL_qr<iname, "u16", 0b1, 0b01, bit_7, bit_17>;
class MVE_VBRSR<string iname, string suffix, bits<2> size, list<dag> pattern=[]>
   : MVE_qDest_rSrc<iname, suffix, "", pattern> {
 
   let Inst{28} = 0b1;
   let Inst{21-20} = size;
   let Inst{16} = 0b1;
   let Inst{12} = 0b1;
   let Inst{8} = 0b0;
   let Inst{5} = 0b1;
+  let validForTailPredication = 1;
 }
 
 def MVE_VBRSR8  : MVE_VBRSR<"vbrsr", "8", 0b00>;
 def MVE_VBRSR16 : MVE_VBRSR<"vbrsr", "16", 0b01>;
 def MVE_VBRSR32 : MVE_VBRSR<"vbrsr", "32", 0b10>;
 
 let Predicates = [HasMVEInt] in {
   def : Pat<(v16i8 ( bitreverse (v16i8 MQPR:$val1))),
class MVE_VMUL_qr_int<string iname, string suffix,
   : MVE_qDest_rSrc<iname, suffix, "", pattern> {
 
   let Inst{28} = 0b0;
   let Inst{21-20} = size;
   let Inst{16} = 0b1;
   let Inst{12} = 0b1;
   let Inst{8} = 0b0;
   let Inst{5} = 0b1;
+  let validForTailPredication = 1;
 }
 
 def MVE_VMUL_qr_i8  : MVE_VMUL_qr_int<"vmul", "i8",  0b00>;
 def MVE_VMUL_qr_i16 : MVE_VMUL_qr_int<"vmul", "i16", 0b01>;
 def MVE_VMUL_qr_i32 : MVE_VMUL_qr_int<"vmul", "i32", 0b10>;
 
 let Predicates = [HasMVEInt] in {
   def : Pat<(v16i8 (mul (v16i8 MQPR:$val1), (v16i8 (ARMvdup GPR:$val2)))),

 def MVE_VQDMULH_qr_s8   : MVE_VxxMUL_qr<"vqdmulh",  "s8",  0b0, 0b00>;
 def MVE_VQDMULH_qr_s16  : MVE_VxxMUL_qr<"vqdmulh",  "s16", 0b0, 0b01>;
 def MVE_VQDMULH_qr_s32  : MVE_VxxMUL_qr<"vqdmulh",  "s32", 0b0, 0b10>;
 
 def MVE_VQRDMULH_qr_s8  : MVE_VxxMUL_qr<"vqrdmulh", "s8",  0b1, 0b00>;
 def MVE_VQRDMULH_qr_s16 : MVE_VxxMUL_qr<"vqrdmulh", "s16", 0b1, 0b01>;
 def MVE_VQRDMULH_qr_s32 : MVE_VxxMUL_qr<"vqrdmulh", "s32", 0b1, 0b10>;
 
-let Predicates = [HasMVEFloat] in {
+let Predicates = [HasMVEFloat], validForTailPredication = 1 in {
   def MVE_VMUL_qr_f16   : MVE_VxxMUL_qr<"vmul", "f16", 0b1, 0b11>;
   def MVE_VMUL_qr_f32   : MVE_VxxMUL_qr<"vmul", "f32", 0b0, 0b11>;
 }
 
 class MVE_VFMAMLA_qr<string iname, string suffix,
                      bit bit_28, bits<2> bits_21_20, bit S,
                      list<dag> pattern=[]>
   : MVE_qDestSrc_rSrc<iname, suffix, pattern> {

 let Predicates = [HasMVEFloat] in {
   def MVE_VFMA_qr_f16  : MVE_VFMAMLA_qr<"vfma",  "f16", 0b1, 0b11, 0b0>;
   def MVE_VFMA_qr_f32  : MVE_VFMAMLA_qr<"vfma",  "f32", 0b0, 0b11, 0b0>;
   def MVE_VFMA_qr_Sf16 : MVE_VFMAMLA_qr<"vfmas", "f16", 0b1, 0b11, 0b1>;
   def MVE_VFMA_qr_Sf32 : MVE_VFMAMLA_qr<"vfmas", "f32", 0b0, 0b11, 0b1>;
 }
 
 class MVE_VQDMLAH_qr<string iname, string suffix, bit U, bits<2> size,
                      bit bit_5, bit bit_12, list<dag> pattern=[]>
   : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
 
   let Inst{28} = U;
   let Inst{21-20} = size;
   let Inst{16} = 0b0;
   let Inst{12} = bit_12;
   let Inst{8} = 0b0;
   let Inst{5} = bit_5;
class MVE_VxDUP<string iname, string suffix, bits<2> size, bit bit_12,
   let Inst{19-17} = Rn{3-1};
   let Inst{16} = 0b1;
   let Inst{15-13} = Qd{2-0};
   let Inst{12} = bit_12;
   let Inst{11-8} = 0b1111;
   let Inst{7} = imm{1};
   let Inst{6-1} = 0b110111;
   let Inst{0} = imm{0};
+  let validForTailPredication = 1;
 }
 
 def MVE_VIDUPu8  : MVE_VxDUP<"vidup", "u8",  0b00, 0b0>;
 def MVE_VIDUPu16 : MVE_VxDUP<"vidup", "u16", 0b01, 0b0>;
 def MVE_VIDUPu32 : MVE_VxDUP<"vidup", "u32", 0b10, 0b0>;
 
 def MVE_VDDUPu8  : MVE_VxDUP<"vddup", "u8",  0b00, 0b1>;
 def MVE_VDDUPu16 : MVE_VxDUP<"vddup", "u16", 0b01, 0b1>;
class MVE_VxWDUP<string iname, string suffix, bits<2> size, bit bit_12,
   let Inst{16} = 0b1;
   let Inst{15-13} = Qd{2-0};
   let Inst{12} = bit_12;
   let Inst{11-8} = 0b1111;
   let Inst{7} = imm{1};
   let Inst{6-4} = 0b110;
   let Inst{3-1} = Rm{3-1};
   let Inst{0} = imm{0};
+  let validForTailPredication = 1;
 }
 
 def MVE_VIWDUPu8  : MVE_VxWDUP<"viwdup", "u8",  0b00, 0b0>;
 def MVE_VIWDUPu16 : MVE_VxWDUP<"viwdup", "u16", 0b01, 0b0>;
 def MVE_VIWDUPu32 : MVE_VxWDUP<"viwdup", "u32", 0b10, 0b0>;
 
 def MVE_VDWDUPu8  : MVE_VxWDUP<"vdwdup", "u8",  0b00, 0b1>;
 def MVE_VDWDUPu16 : MVE_VxWDUP<"vdwdup", "u16", 0b01, 0b1>;
class MVE_VCTP<string suffix, bits<2> size, list<dag> pattern=[]>
   let Inst{21-20} = size;
   let Inst{19-16} = Rn{3-0};
   let Inst{15-11} = 0b11101;
   let Inst{10-0}  = 0b00000000001;
   let Unpredictable{10-0} = 0b11111111111;
 
   let Constraints = "";
   let DecoderMethod = "DecodeMveVCTP";
+  let validForTailPredication = 1;
 }
 
 def MVE_VCTP8  : MVE_VCTP<"8",  0b00>;
 def MVE_VCTP16 : MVE_VCTP<"16", 0b01>;
 def MVE_VCTP32 : MVE_VCTP<"32", 0b10>;
 def MVE_VCTP64 : MVE_VCTP<"64", 0b11>;
 
 let Predicates = [HasMVEInt] in {
: MVE_p<oops, iops, NoItinerary, asm, suffix, ops, vpred_n, cstr, pattern> {
   let Inst{21} = W;
   let Inst{20} = dir.load;
   let Inst{15-13} = Qd{2-0};
   let Inst{12} = opc;
   let Inst{11-9} = 0b111;
 
   let mayLoad = dir.load;
   let mayStore = !eq(dir.load,0);
+  let validForTailPredication = 1;
 }
 
 // Contiguous load and store instructions. These come in two main
 // categories: same-size loads/stores in which 128 bits of vector
 // register is transferred to or from 128 bits of memory in the most
 // obvious way, and widening loads / narrowing stores, in which the
 // size of memory accessed is less than the size of a vector register,
 // so the load instructions sign- or zero-extend each memory value
class MVE_VPT<string suffix, bits<2> size, dag iops, string asm, list<dag> pattern=[]>
   let Inst{16} = 0b1;
   let Inst{15-13} = Mk{2-0};
   let Inst{12} = fc{2};
   let Inst{11-8} = 0b1111;
   let Inst{7} = fc{0};
   let Inst{4} = 0b0;
 
   let Defs = [VPR];
+  let validForTailPredication = 1;
 }
 
 class MVE_VPTt1<string suffix, bits<2> size, dag iops>
   : MVE_VPT<suffix, size, iops, "$fc, $Qn, $Qm"> {
   bits<4> Qm;
   bits<4> Mk;
 
   let Inst{6} = 0b0;
   let Inst{5} = Qm{3};
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = fc{1};
+  let validForTailPredication = 1;
 }
 
 class MVE_VPTt1i<string suffix, bits<2> size>
  : MVE_VPTt1<suffix, size,
            (ins vpt_mask:$Mk, MQPR:$Qn, MQPR:$Qm, pred_basic_i:$fc)> {
   let Inst{12} = 0b0;
   let Inst{0} = 0b0;
 }
class MVE_VPTf<string suffix, bit size, dag iops, string asm, list<dag> pattern=[]>
   let Inst{15-13} = Mk{2-0};
   let Inst{12} = fc{2};
   let Inst{11-8} = 0b1111;
   let Inst{7} = fc{0};
   let Inst{4} = 0b0;
 
   let Defs = [VPR];
   let Predicates = [HasMVEFloat];
+  let validForTailPredication = 1;
 }
 
 class MVE_VPTft1<string suffix, bit size>
   : MVE_VPTf<suffix, size, (ins vpt_mask:$Mk, MQPR:$Qn, MQPR:$Qm, pred_basic_fp:$fc),
           "$fc, $Qn, $Qm"> {
   bits<3> fc;
   bits<4> Qm;
 
def MVE_VPST : MVE_MI<(outs ), (ins vpt_mask:$Mk), NoItinerary,
   let Inst{21-16} = 0b110001;
   let Inst{15-13} = Mk{2-0};
   let Inst{12-0} = 0b0111101001101;
   let Unpredictable{12} = 0b1;
   let Unpredictable{7} = 0b1;
   let Unpredictable{5} = 0b1;
 
   let Defs = [VPR];
+  let validForTailPredication = 1;
 }
 
 def MVE_VPSEL : MVE_p<(outs MQPR:$Qd), (ins MQPR:$Qn, MQPR:$Qm), NoItinerary,
                       "vpsel", "", "$Qd, $Qn, $Qm", vpred_n, "", []> {
   bits<4> Qn;
   bits<4> Qd;
   bits<4> Qm;
 
   let Inst{28} = 0b1;
   let Inst{25-23} = 0b100;
   let Inst{22} = Qd{3};
   let Inst{21-20} = 0b11;
   let Inst{19-17} = Qn{2-0};
   let Inst{16} = 0b1;
   let Inst{15-13} = Qd{2-0};
   let Inst{12-9} = 0b0111;
   let Inst{8} = 0b1;
   let Inst{7} = Qn{3};
   let Inst{6} = 0b0;
   let Inst{5} = Qm{3};
   let Inst{4} = 0b0;
   let Inst{3-1} = Qm{2-0};
   let Inst{0} = 0b1;
+  let validForTailPredication = 1;
 }
 
 foreach suffix = ["s8", "s16", "s32", "u8", "u16", "u32",
                   "i8", "i16", "i32",       "f16", "f32"] in
 def : MVEInstAlias<"vpsel${vp}." # suffix # "\t$Qd, $Qn, $Qm",
                    (MVE_VPSEL MQPR:$Qd, MQPR:$Qn, MQPR:$Qm, vpred_n:$vp)>;
 
 let Predicates = [HasMVEInt] in {

lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h

enum {
     Xform16Bit    = 1 << 14,
 
     // ThumbArithFlagSetting - The instruction is a 16-bit flag setting Thumb
     // instruction. Used by the parser to determine whether to require the 'S'
     // suffix on the mnemonic (when not in an IT block) or preclude it (when
     // in an IT block).
     ThumbArithFlagSetting = 1 << 19,
 
-    // Whether an instruction should be excluded from an MVE tail-predicated
-    // loop.
-    InvalidForTailPredication = 1 << 20,
+    // Whether an instruction can be included in an MVE tail-predicated loop.
+    ValidForTailPredication = 1 << 20,
 
     //===------------------------------------------------------------------===//
     // Code domain.
     DomainShift   = 15,
     DomainMask    = 15 << DomainShift,
     DomainGeneral = 0 << DomainShift,
     DomainVFP     = 1 << DomainShift,
     DomainNEON    = 2 << DomainShift,

unittests/Target/ARM/CMakeLists.txt

 include_directories(
-  ${CMAKE_SOURCE_DIR}/lib/Target/ARM
-  ${CMAKE_BINARY_DIR}/lib/Target/ARM
+  ${LLVM_MAIN_SRC_DIR}/lib/Target/ARM
+  ${LLVM_BINARY_DIR}/lib/Target/ARM
   )
 
 set(LLVM_LINK_COMPONENTS
   ARMCodeGen
   ARMDesc
   ARMInfo
+  CodeGen
   MC
+  SelectionDAG
   Support
   Target
 )
 
 add_llvm_unittest(ARMTests
   MachineInstrTest.cpp
   )

unittests/Target/ARM/MachineInstrTest.cpp

 #include "ARMBaseInstrInfo.h"
 #include "ARMSubtarget.h"
 #include "ARMTargetMachine.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 
 #include "gtest/gtest.h"
 
 using namespace llvm;
 
 // Test for instructions that aren't immediately obviously valid within a
 // tail-predicated loop. This should be marked up in their tablegen
-// descriptions. Currently the horizontal vector operations are tagged.
-// TODO Add instructions that perform:
-// - truncation,
-// - extensions,
-// - byte swapping,
-// - others?
-TEST(MachineInstrInvalidTailPredication, IsCorrect) {
+// descriptions. Currently we, conservatively, disallow:
+// - cross beat carries.
+// - narrowing of results.
+// - top/bottom operations.
+// - complex operations.
+// - horizontal operations.
+// - byte swapping.
+// - interleaved memory instructions.
+// TODO: Add to this list once we can handle them safely.
+TEST(MachineInstrValidTailPredication, IsCorrect) {
+
+  using namespace ARM;
+
+  auto IsValidTPOpcode = [](unsigned Opcode) {
+    switch (Opcode) {
+    default:
+      return false;
+    case MVE_ASRLi:
+    case MVE_ASRLr:
+    case MVE_LSRL:  
+    case MVE_SQRSHR:
+    case MVE_SQSHL:
+    case MVE_SRSHR:
+    case MVE_UQRSHL:
+    case MVE_UQSHL:
+    case MVE_URSHR:
+    case MVE_VABDf16:
+    case MVE_VABDf32:
+    case MVE_VABDs16:
+    case MVE_VABDs32:
+    case MVE_VABDs8:  
+    case MVE_VABDu16:
+    case MVE_VABDu32:
+    case MVE_VABDu8:
+    case MVE_VABSf16:
+    case MVE_VABSf32:
+    case MVE_VABSs16:
+    case MVE_VABSs32:
+    case MVE_VABSs8:
+    case MVE_VADD_qr_f16:
+    case MVE_VADD_qr_f32:
+    case MVE_VADD_qr_i16:
+    case MVE_VADD_qr_i32:
+    case MVE_VADD_qr_i8:
+    case MVE_VADDf16:
+    case MVE_VADDf32:
+    case MVE_VADDi16:
+    case MVE_VADDi32:
+    case MVE_VADDi8:
+    case MVE_VAND:
+    case MVE_VBIC:
+    case MVE_VBICIZ0v4i32:
+    case MVE_VBICIZ0v8i16:
+    case MVE_VBICIZ16v4i32:
+    case MVE_VBICIZ24v4i32:
+    case MVE_VBICIZ8v4i32:
+    case MVE_VBICIZ8v8i16:
+    case MVE_VBRSR16:
+    case MVE_VBRSR32:
+    case MVE_VBRSR8:
+    case MVE_VCLSs16:
+    case MVE_VCLSs32:
+    case MVE_VCLSs8:
+    case MVE_VCLZs16:
+    case MVE_VCLZs32:
+    case MVE_VCLZs8:
+    case MVE_VCMPf16:
+    case MVE_VCMPf16r:
+    case MVE_VCMPf32:
+    case MVE_VCMPf32r:
+    case MVE_VCMPi16:
+    case MVE_VCMPi16r:
+    case MVE_VCMPi32:
+    case MVE_VCMPi32r:
+    case MVE_VCMPi8:
+    case MVE_VCMPi8r:
+    case MVE_VCMPs16:
+    case MVE_VCMPs16r:
+    case MVE_VCMPs32:
+    case MVE_VCMPs32r:
+    case MVE_VCMPs8:
+    case MVE_VCMPs8r:
+    case MVE_VCMPu16:
+    case MVE_VCMPu16r:
+    case MVE_VCMPu32:
+    case MVE_VCMPu32r:
+    case MVE_VCMPu8:
+    case MVE_VCMPu8r:
+    case MVE_VCTP16:
+    case MVE_VCTP32:
+    case MVE_VCTP64:
+    case MVE_VCTP8:
+    case MVE_VCVTf16s16_fix:
+    case MVE_VCVTf16s16n:
+    case MVE_VCVTf16u16_fix:
+    case MVE_VCVTf16u16n:
+    case MVE_VCVTf32s32_fix:
+    case MVE_VCVTf32s32n:
+    case MVE_VCVTf32u32_fix:
+    case MVE_VCVTf32u32n:
+    case MVE_VCVTs16f16_fix:
+    case MVE_VCVTs16f16a:
+    case MVE_VCVTs16f16m:
+    case MVE_VCVTs16f16n:
+    case MVE_VCVTs16f16p:
+    case MVE_VCVTs16f16z:
+    case MVE_VCVTs32f32_fix:
+    case MVE_VCVTs32f32a:
+    case MVE_VCVTs32f32m:
+    case MVE_VCVTs32f32n:
+    case MVE_VCVTs32f32p:
+    case MVE_VCVTs32f32z:
+    case MVE_VCVTu16f16_fix:
+    case MVE_VCVTu16f16a:
+    case MVE_VCVTu16f16m:
+    case MVE_VCVTu16f16n:
+    case MVE_VCVTu16f16p:
+    case MVE_VCVTu16f16z:
+    case MVE_VCVTu32f32_fix:
+    case MVE_VCVTu32f32a:
+    case MVE_VCVTu32f32m:
+    case MVE_VCVTu32f32n:
+    case MVE_VCVTu32f32p:
+    case MVE_VCVTu32f32z:
+    case MVE_VDDUPu16:
+    case MVE_VDDUPu32:
+    case MVE_VDDUPu8:
+    case MVE_VDUP16:
+    case MVE_VDUP32:
+    case MVE_VDUP8:
+    case MVE_VDWDUPu16:
+    case MVE_VDWDUPu32:
+    case MVE_VDWDUPu8:
+    case MVE_VEOR:
+    case MVE_VHADD_qr_s16:
+    case MVE_VHADD_qr_s32:
+    case MVE_VHADD_qr_s8:
+    case MVE_VHADD_qr_u16:
+    case MVE_VHADD_qr_u32:
+    case MVE_VHADD_qr_u8:
+    case MVE_VHADDs16:
+    case MVE_VHADDs32:
+    case MVE_VHADDs8:
+    case MVE_VHADDu16:
+    case MVE_VHADDu32:
+    case MVE_VHADDu8:
+    case MVE_VHSUB_qr_s16:
+    case MVE_VHSUB_qr_s32:
+    case MVE_VHSUB_qr_s8:
+    case MVE_VHSUB_qr_u16:
+    case MVE_VHSUB_qr_u32:
+    case MVE_VHSUB_qr_u8:
+    case MVE_VHSUBs16:
+    case MVE_VHSUBs32:
+    case MVE_VHSUBs8:
+    case MVE_VHSUBu16:
+    case MVE_VHSUBu32:
+    case MVE_VHSUBu8:
+    case MVE_VIDUPu16:
+    case MVE_VIDUPu32:
+    case MVE_VIDUPu8:
+    case MVE_VIWDUPu16:
+    case MVE_VIWDUPu32:
+    case MVE_VIWDUPu8:
+    case MVE_VLDRBS16:
+    case MVE_VLDRBS16_post:
+    case MVE_VLDRBS16_pre:
+    case MVE_VLDRBS16_rq:
+    case MVE_VLDRBS32:
+    case MVE_VLDRBS32_post:
+    case MVE_VLDRBS32_pre:
+    case MVE_VLDRBS32_rq:
+    case MVE_VLDRBU16:
+    case MVE_VLDRBU16_post:
+    case MVE_VLDRBU16_pre:
+    case MVE_VLDRBU16_rq:
+    case MVE_VLDRBU32:
+    case MVE_VLDRBU32_post:
+    case MVE_VLDRBU32_pre:
+    case MVE_VLDRBU32_rq:
+    case MVE_VLDRBU8:
+    case MVE_VLDRBU8_post:
+    case MVE_VLDRBU8_pre:
+    case MVE_VLDRBU8_rq:
+    case MVE_VLDRDU64_qi:
+    case MVE_VLDRDU64_qi_pre:
+    case MVE_VLDRDU64_rq:
+    case MVE_VLDRDU64_rq_u:
+    case MVE_VLDRHS32:
+    case MVE_VLDRHS32_post:
+    case MVE_VLDRHS32_pre:
+    case MVE_VLDRHS32_rq:
+    case MVE_VLDRHS32_rq_u:
+    case MVE_VLDRHU16:
+    case MVE_VLDRHU16_post:
+    case MVE_VLDRHU16_pre:
+    case MVE_VLDRHU16_rq:
+    case MVE_VLDRHU16_rq_u:
+    case MVE_VLDRHU32:
+    case MVE_VLDRHU32_post:
+    case MVE_VLDRHU32_pre:
+    case MVE_VLDRHU32_rq:
+    case MVE_VLDRHU32_rq_u:
+    case MVE_VLDRWU32:
+    case MVE_VLDRWU32_post:
+    case MVE_VLDRWU32_pre:
+    case MVE_VLDRWU32_qi:
+    case MVE_VLDRWU32_qi_pre:
+    case MVE_VLDRWU32_rq:
+    case MVE_VLDRWU32_rq_u:
+    case MVE_VMOVimmf32:
+    case MVE_VMOVimmi16:
+    case MVE_VMOVimmi32:  
+    case MVE_VMOVimmi64:
+    case MVE_VMOVimmi8: 
+    case MVE_VMUL_qr_f16:
+    case MVE_VMUL_qr_f32:
+    case MVE_VMUL_qr_i16:
+    case MVE_VMUL_qr_i32:
+    case MVE_VMUL_qr_i8:
+    case MVE_VMULf16:
+    case MVE_VMULf32:
+    case MVE_VMVN:
+    case MVE_VMVNimmi16:
+    case MVE_VMVNimmi32:
+    case MVE_VNEGf16:
+    case MVE_VNEGf32:
+    case MVE_VNEGs16:
+    case MVE_VNEGs32:
+    case MVE_VNEGs8:
+    case MVE_VORN:
+    case MVE_VORR:
+    case MVE_VORRIZ0v4i32:
+    case MVE_VORRIZ0v8i16:
+    case MVE_VORRIZ16v4i32:
+    case MVE_VORRIZ24v4i32:
+    case MVE_VORRIZ8v4i32:
+    case MVE_VORRIZ8v8i16:
+    case MVE_VPNOT:
+    case MVE_VPSEL:
+    case MVE_VPST:  
+    case MVE_VPTv16i8:
+    case MVE_VPTv16i8r:
+    case MVE_VPTv16s8:
+    case MVE_VPTv16s8r:
+    case MVE_VPTv16u8:  
+    case MVE_VPTv16u8r:
+    case MVE_VPTv4f32:
+    case MVE_VPTv4f32r:
+    case MVE_VPTv4i32:
+    case MVE_VPTv4i32r:
+    case MVE_VPTv4s32:
+    case MVE_VPTv4s32r:
+    case MVE_VPTv4u32:
+    case MVE_VPTv4u32r:
+    case MVE_VPTv8f16:
+    case MVE_VPTv8f16r:
+    case MVE_VPTv8i16:
+    case MVE_VPTv8i16r:
+    case MVE_VPTv8s16:
+    case MVE_VPTv8s16r:
+    case MVE_VPTv8u16:
+    case MVE_VPTv8u16r:
+    case MVE_VQABSs16:
+    case MVE_VQABSs32:
+    case MVE_VQABSs8:
+    case MVE_VQADD_qr_s16:
+    case MVE_VQADD_qr_s32:
+    case MVE_VQADD_qr_s8:
+    case MVE_VQADD_qr_u16:
+    case MVE_VQADD_qr_u32:
+    case MVE_VQADD_qr_u8:
+    case MVE_VQADDs16:
+    case MVE_VQADDs32:
+    case MVE_VQADDs8:
+    case MVE_VQADDu16:
+    case MVE_VQADDu32:
+    case MVE_VQADDu8:
+    case MVE_VQNEGs16:
+    case MVE_VQNEGs32:
+    case MVE_VQNEGs8:
+    case MVE_VQRSHL_by_vecs16:
+    case MVE_VQRSHL_by_vecs32:
+    case MVE_VQRSHL_by_vecs8:
+    case MVE_VQRSHL_by_vecu16:
+    case MVE_VQRSHL_by_vecu32:
+    case MVE_VQRSHL_by_vecu8:
+    case MVE_VQRSHL_qrs16:
+    case MVE_VQRSHL_qrs32:
+    case MVE_VQRSHL_qrs8:
+    case MVE_VQRSHL_qru16:
+    case MVE_VQRSHL_qru8:
+    case MVE_VQRSHL_qru32:
+    case MVE_VQSHLU_imms16:
+    case MVE_VQSHLU_imms32:
+    case MVE_VQSHLU_imms8:
+    case MVE_VQSHL_by_vecs16:
+    case MVE_VQSHL_by_vecs32:
+    case MVE_VQSHL_by_vecs8:
+    case MVE_VQSHL_by_vecu16:
+    case MVE_VQSHL_by_vecu32:
+    case MVE_VQSHL_by_vecu8:
+    case MVE_VQSHL_qrs16:
+    case MVE_VQSHL_qrs32:
+    case MVE_VQSHL_qrs8:
+    case MVE_VQSHL_qru16:
+    case MVE_VQSHL_qru32:
+    case MVE_VQSHL_qru8:
+    case MVE_VQSUB_qr_s16:
+    case MVE_VQSUB_qr_s32:
+    case MVE_VQSUB_qr_s8:
+    case MVE_VQSUB_qr_u16:
+    case MVE_VQSUB_qr_u32:
+    case MVE_VQSUB_qr_u8:
+    case MVE_VQSUBs16:
+    case MVE_VQSUBs32:
+    case MVE_VQSUBs8:
+    case MVE_VQSUBu16:
+    case MVE_VQSUBu32:
+    case MVE_VQSUBu8:
+    case MVE_VRHADDs16:
+    case MVE_VRHADDs32:
+    case MVE_VRHADDs8:
+    case MVE_VRHADDu16:
+    case MVE_VRHADDu32: 
+    case MVE_VRHADDu8:
+    case MVE_VRINTf16A:
+    case MVE_VRINTf16M:
+    case MVE_VRINTf16N:
+    case MVE_VRINTf16P:
+    case MVE_VRINTf16X:
+    case MVE_VRINTf16Z:
+    case MVE_VRINTf32A:
+    case MVE_VRINTf32M:
+    case MVE_VRINTf32N:
+    case MVE_VRINTf32P: 
+    case MVE_VRINTf32X: 
+    case MVE_VRINTf32Z:
+    case MVE_VRSHL_by_vecs16:
+    case MVE_VRSHL_by_vecs32:
+    case MVE_VRSHL_by_vecs8:  
+    case MVE_VRSHL_by_vecu16:
+    case MVE_VRSHL_by_vecu32:
+    case MVE_VRSHL_by_vecu8:
+    case MVE_VRSHL_qrs16:
+    case MVE_VRSHL_qrs32:
+    case MVE_VRSHL_qrs8:
+    case MVE_VRSHL_qru16:
+    case MVE_VRSHL_qru32:
+    case MVE_VRSHL_qru8:
+    case MVE_VRSHR_imms16:
+    case MVE_VRSHR_imms32:
+    case MVE_VRSHR_imms8:
+    case MVE_VRSHR_immu16:
+    case MVE_VRSHR_immu32:
+    case MVE_VRSHR_immu8:
+    case MVE_VSHL_by_vecs16:
+    case MVE_VSHL_by_vecs32:
+    case MVE_VSHL_by_vecs8:
+    case MVE_VSHL_by_vecu16:
+    case MVE_VSHL_by_vecu32:
+    case MVE_VSHL_by_vecu8:
+    case MVE_VSHL_immi16:
+    case MVE_VSHL_immi32:
+    case MVE_VSHL_immi8:
+    case MVE_VSHL_qrs16:
+    case MVE_VSHL_qrs32:
+    case MVE_VSHL_qrs8:
+    case MVE_VSHL_qru16:
+    case MVE_VSHL_qru32:
+    case MVE_VSHL_qru8:
+    case MVE_VSHR_imms16:
+    case MVE_VSHR_imms32:
+    case MVE_VSHR_imms8:
+    case MVE_VSHR_immu16:
+    case MVE_VSHR_immu32:
+    case MVE_VSHR_immu8:
+    case MVE_VSLIimm16:
+    case MVE_VSLIimm32:
+    case MVE_VSLIimm8:
+    case MVE_VSLIimms16:  
+    case MVE_VSLIimms32:
+    case MVE_VSLIimms8:
+    case MVE_VSLIimmu16:
+    case MVE_VSLIimmu32:
+    case MVE_VSLIimmu8:
+    case MVE_VSRIimm16:
+    case MVE_VSRIimm32:
+    case MVE_VSRIimm8:
+    case MVE_VSTRB16:
+    case MVE_VSTRB16_post:
+    case MVE_VSTRB16_pre:
+    case MVE_VSTRB16_rq:
+    case MVE_VSTRB32:
+    case MVE_VSTRB32_post:
+    case MVE_VSTRB32_pre: 
+    case MVE_VSTRB32_rq:
+    case MVE_VSTRB8_rq:
+    case MVE_VSTRBU8:
+    case MVE_VSTRBU8_post:
+    case MVE_VSTRBU8_pre:
+    case MVE_VSTRD64_qi:
+    case MVE_VSTRD64_qi_pre:
+    case MVE_VSTRD64_rq:
+    case MVE_VSTRD64_rq_u:
+    case MVE_VSTRH16_rq:
+    case MVE_VSTRH16_rq_u:
+    case MVE_VSTRH32:
+    case MVE_VSTRH32_post:
+    case MVE_VSTRH32_pre:
+    case MVE_VSTRH32_rq:
+    case MVE_VSTRH32_rq_u:
+    case MVE_VSTRHU16:
+    case MVE_VSTRHU16_post:
+    case MVE_VSTRHU16_pre:
+    case MVE_VSTRW32_qi:
+    case MVE_VSTRW32_qi_pre:
+    case MVE_VSTRW32_rq:
+    case MVE_VSTRW32_rq_u:
+    case MVE_VSTRWU32:
+    case MVE_VSTRWU32_post:
+    case MVE_VSTRWU32_pre:
+    case MVE_VSUB_qr_f16:
+    case MVE_VSUB_qr_f32:
+    case MVE_VSUB_qr_i16:
+    case MVE_VSUB_qr_i32:
+    case MVE_VSUB_qr_i8:
+    case MVE_VSUBf16:
+    case MVE_VSUBf32:
+    case MVE_VSUBi16:
+    case MVE_VSUBi32:
+    case MVE_VSUBi8:
+      return true;
+    }
+  };
+
   LLVMInitializeARMTargetInfo();
   LLVMInitializeARMTarget();
   LLVMInitializeARMTargetMC();
 
   auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
   std::string Error;
   const Target *T = TargetRegistry::lookupTarget(TT, Error);
   if (!T) {
     dbgs() << Error;
     return;
   }
 
   TargetOptions Options;
   auto TM = std::unique_ptr<LLVMTargetMachine>(
     static_cast<LLVMTargetMachine*>(
       T->createTargetMachine(TT, "generic", "", Options, None, None,
                              CodeGenOpt::Default)));
+  ARMSubtarget ST(TM->getTargetTriple(), TM->getTargetCPU(),
+                  TM->getTargetFeatureString(),
+                  *static_cast<const ARMBaseTargetMachine*>(TM.get()), false);
+  const ARMBaseInstrInfo *TII = ST.getInstrInfo();
   auto MII = TM->getMCInstrInfo();
 
-  using namespace ARM;
+  for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
+    const MCInstrDesc &Desc = TII->get(i);
 
-  auto IsInvalidTPOpcode = [](unsigned Opcode) {
-    switch (Opcode) {
-    case MVE_VABAVs8:
-    case MVE_VABAVs16:
-    case MVE_VABAVs32:
-    case MVE_VABAVu8:
-    case MVE_VABAVu16:
-    case MVE_VABAVu32:
-    case MVE_VADDVs8acc:
-    case MVE_VADDVs16acc:
-    case MVE_VADDVs32acc:
-    case MVE_VADDVu8acc:
-    case MVE_VADDVu16acc:
-    case MVE_VADDVu32acc:
-    case MVE_VADDVs8no_acc:
-    case MVE_VADDVs16no_acc:
-    case MVE_VADDVs32no_acc:
-    case MVE_VADDVu8no_acc:
-    case MVE_VADDVu16no_acc:
-    case MVE_VADDVu32no_acc:
-    case MVE_VADDLVs32no_acc:
-    case MVE_VADDLVu32no_acc:
-    case MVE_VADDLVs32acc:
-    case MVE_VADDLVu32acc:
-    case MVE_VMLADAVas16:
-    case MVE_VMLADAVas32:
-    case MVE_VMLADAVas8:
-    case MVE_VMLADAVau16:
-    case MVE_VMLADAVau32:
-    case MVE_VMLADAVau8:
-    case MVE_VMLADAVaxs16:
-    case MVE_VMLADAVaxs32:
-    case MVE_VMLADAVaxs8:
-    case MVE_VMLADAVs16:
-    case MVE_VMLADAVs32:
-    case MVE_VMLADAVs8:
-    case MVE_VMLADAVu16:
-    case MVE_VMLADAVu32:
-    case MVE_VMLADAVu8:
-    case MVE_VMLADAVxs16:
-    case MVE_VMLADAVxs32:
-    case MVE_VMLADAVxs8:
-    case MVE_VMLALDAVas16:
-    case MVE_VMLALDAVas32:
-    case MVE_VMLALDAVau16:
-    case MVE_VMLALDAVau32:
-    case MVE_VMLALDAVaxs16:
-    case MVE_VMLALDAVaxs32:
-    case MVE_VMLALDAVs16:
-    case MVE_VMLALDAVs32:
-    case MVE_VMLALDAVu16:
-    case MVE_VMLALDAVu32:
-    case MVE_VMLALDAVxs16:
-    case MVE_VMLALDAVxs32:
-    case MVE_VMLSDAVas16:
-    case MVE_VMLSDAVas32:
-    case MVE_VMLSDAVas8:
-    case MVE_VMLSDAVaxs16:
-    case MVE_VMLSDAVaxs32:
-    case MVE_VMLSDAVaxs8:
-    case MVE_VMLSDAVs16:
-    case MVE_VMLSDAVs32:
-    case MVE_VMLSDAVs8:
-    case MVE_VMLSDAVxs16:
-    case MVE_VMLSDAVxs32:
-    case MVE_VMLSDAVxs8:
-    case MVE_VMLSLDAVas16:
-    case MVE_VMLSLDAVas32:
-    case MVE_VMLSLDAVaxs16:
-    case MVE_VMLSLDAVaxs32:
-    case MVE_VMLSLDAVs16:
-    case MVE_VMLSLDAVs32:
-    case MVE_VMLSLDAVxs16:
-    case MVE_VMLSLDAVxs32:
-    case MVE_VRMLALDAVHas32:
-    case MVE_VRMLALDAVHau32:
-    case MVE_VRMLALDAVHaxs32:
-    case MVE_VRMLALDAVHs32:
-    case MVE_VRMLALDAVHu32:
-    case MVE_VRMLALDAVHxs32:
-    case MVE_VRMLSLDAVHas32:
-    case MVE_VRMLSLDAVHaxs32:
-    case MVE_VRMLSLDAVHs32:
-    case MVE_VRMLSLDAVHxs32:
-    case MVE_VMAXNMVf16:
-    case MVE_VMINNMVf16:
-    case MVE_VMAXNMVf32:
-    case MVE_VMINNMVf32:
-    case MVE_VMAXNMAVf16:
-    case MVE_VMINNMAVf16:
-    case MVE_VMAXNMAVf32:
-    case MVE_VMINNMAVf32:
-    case MVE_VMAXVs8:
-    case MVE_VMAXVs16:
-    case MVE_VMAXVs32:
-    case MVE_VMAXVu8:
-    case MVE_VMAXVu16:
-    case MVE_VMAXVu32:
-    case MVE_VMINVs8:
-    case MVE_VMINVs16:
-    case MVE_VMINVs32:
-    case MVE_VMINVu8:
-    case MVE_VMINVu16:
-    case MVE_VMINVu32:
-    case MVE_VMAXAVs8:
-    case MVE_VMAXAVs16:
-    case MVE_VMAXAVs32:
-    case MVE_VMINAVs8:
-    case MVE_VMINAVs16:
-    case MVE_VMINAVs32:
-      return true;
-    default:
-      return false;
-    }
-  };
+    for (auto &Op : Desc.operands()) {
+      // Only check instructions that access the MQPR regs.
+      if ((Op.OperandType & MCOI::OPERAND_REGISTER) == 0 ||
+          Op.RegClass != ARM::MQPRRegClassID)
+        continue;
 
-  for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
       uint64_t Flags = MII->get(i).TSFlags;
-    bool Invalid = (Flags & ARMII::InvalidForTailPredication) != 0;
-    ASSERT_EQ(IsInvalidTPOpcode(i), Invalid)
+      bool Valid = (Flags & ARMII::ValidForTailPredication) != 0;
+      ASSERT_EQ(IsValidTPOpcode(i), Valid)
                 << MII->getName(i)
                 << ": mismatched expectation for tail-predicated safety\n";
+      break;
+    }
   }
 }