[ARM][MVE] validForTailPredication insts

[samparker]

Summary

'Blacklist' a few more instruction classes, including:

• instructions that 'narrow' their result.
• lane moves.
• byte swapping instructions.
• interleaving loads and stores.
• cross-beat carries.
• top/bottom instructions.
• complex operations.
• long shifts and muls.

Please shout if you know of any other instructions that could be troublesome to predict.

[dmgreen]

Exactly which instructions can and cannot go into tail predicated loops is still a bit of a mystery to me. As we talked about, a whitelist may be simpler than a blacklist to make sure we account for everything. (Thats maybe an approach if this ends up needing more in the future).

One thing I thought of, some lane moves may go through standard vmovs, or the vmovx and vins fp16 instructions. Also will interleaved fp instructions be fine in the same loop?

lib/Target/ARM/ARMInstrMVE.td

1945

This has a cross beat carry, although I'm not sure that makes it invalid for tail predication.

1976

VMOVL is used to perform widening.

2089

VSHLL?

3365

Some of the complex instructions needed earlyclobber on them as they reach cross beat.

3387

VMULL?

3489

Is anything that is top/bottom a problem?

3536

Cross beat carry again.

3931

VDUP puts the value into all lanes, but I presume that would be OK.

[samparker]

Cheers Dave, top-bottom and early clobber sound like complications. Having a whitelist sounds like a good idea, with the list of our unknowns growing, it sounds like the switch statement could be smaller too!

[samparker]

Inverted the predicate and created a whitelist instead.

[danilaml]

unittests/Target/ARM/CMakeLists.txt

2 ↗

(On Diff #221926)

Thanks! I realize that two other tests in this (Target) folder also have the same pattern in their CMakeLists and would benefit from the same adjustment. Not sure if it makes sense to include them in the same patch though.

[samparker]

Added support for VFMA and VMLA

[dmgreen]

Sounds good to me. Looks like a improvement over what was already here.

[Yi-Hong.Lyu]

This comment was removed by Yi-Hong.Lyu.

lib/Target/ARM/ARMInstrMVE.td

                          string suffix, string ops, string cstr,
                          list<dag> pattern>
   : Thumb2I<oops, iops, AddrModeNone, 4, itin, asm,
             !if(!eq(suffix, ""), "", "." # suffix) # "\t" # ops,
             cstr, pattern>,
     Requires<[HasV8_1MMainline, HasMVEInt]> {
   let D = MVEDomain;
   let DecoderNamespace = "MVE";
+  let invalidForTailPredication = 1;
 }
 
 class MVE_ScalarShift<string iname, dag oops, dag iops, string asm, string cstr,
             list<dag> pattern=[]>
   : MVE_MI_with_pred<oops, iops, NoItinerary, iname, asm, cstr, pattern> {
   let Inst{31-20} = 0b111010100101;
   let Inst{8} = 0b1;
 

   let Inst{21-20} = 0b11;
   let Inst{19-18} = size;
   let Inst{17-16} = 0b00;
   let Inst{12-9} = 0b0000;
   let Inst{8-7} = bit_8_7;
   let Inst{6} = 0b1;
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
+  let invalidForTailPredication = 1;
 }
 
 def MVE_VREV64_8  : MVE_VREV<"vrev64", "8", 0b00, 0b00, "@earlyclobber $Qd">;
 def MVE_VREV64_16 : MVE_VREV<"vrev64", "16", 0b01, 0b00, "@earlyclobber $Qd">;
 def MVE_VREV64_32 : MVE_VREV<"vrev64", "32", 0b10, 0b00, "@earlyclobber $Qd">;
 
 def MVE_VREV32_8  : MVE_VREV<"vrev32", "8", 0b00, 0b01>;
 def MVE_VREV32_16 : MVE_VREV<"vrev32", "16", 0b01, 0b01>;

 def MVE_VMINAs8  : MVE_VMINMAXA<"vmina", "s8",  0b00, 0b1>;
 def MVE_VMINAs16 : MVE_VMINMAXA<"vmina", "s16", 0b01, 0b1>;
 def MVE_VMINAs32 : MVE_VMINMAXA<"vmina", "s32", 0b10, 0b1>;
 
 // end of MVE Integer instructions
 
 // start of mve_imm_shift instructions
 
 def MVE_VSHLC : MVE_p<(outs rGPR:$RdmDest, MQPR:$Qd),
                       (ins MQPR:$QdSrc, rGPR:$RdmSrc, long_shift:$imm),
                       NoItinerary, "vshlc", "", "$QdSrc, $RdmSrc, $imm",
                       vpred_n, "$RdmDest = $RdmSrc,$Qd = $QdSrc"> {
   bits<5> imm;
   bits<4> Qd;
   bits<4> RdmDest;
 
   let Inst{28} = 0b0;

   bits<4> Qm;
 
   let Inst{22} = Qd{3};
   let Inst{15-13} = Qd{2-0};
   let Inst{5} = Qm{3};
   let Inst{3-1} = Qm{2-0};
 }
 
 class MVE_VMOVL<string iname, string suffix, bits<2> sz, bit U,
               list<dag> pattern=[]>
   : MVE_shift_imm<(outs MQPR:$Qd), (ins MQPR:$Qm),
                   iname, suffix, "$Qd, $Qm", vpred_r, "",
                   pattern> {
   let Inst{28} = U;
   let Inst{25-23} = 0b101;
   let Inst{21} = 0b1;
   let Inst{20-19} = sz{1-0};

   def bh : MVE_VSHLL_by_lane_width<iname#"b", suffix, sz, U, ops, pattern> {
     let Inst{12} = 0b0;
   }
   def th : MVE_VSHLL_by_lane_width<iname#"t", suffix, sz, U, ops, pattern> {
     let Inst{12} = 0b1;
   }
 }
 
 defm MVE_VSHLL_lws8  : MVE_VSHLL_lw<"vshll", "s8",  0b00, 0b0, "$Qd, $Qm, #8">;
 defm MVE_VSHLL_lws16 : MVE_VSHLL_lw<"vshll", "s16", 0b01, 0b0, "$Qd, $Qm, #16">;
 defm MVE_VSHLL_lwu8  : MVE_VSHLL_lw<"vshll", "u8",  0b00, 0b1, "$Qd, $Qm, #8">;
 defm MVE_VSHLL_lwu16 : MVE_VSHLL_lw<"vshll", "u16", 0b01, 0b1, "$Qd, $Qm, #16">;
 
 class MVE_VxSHRN<string iname, string suffix, bit bit_12, bit bit_28,
                dag immops, list<dag> pattern=[]>
   : MVE_shift_imm<(outs MQPR:$Qd), !con((ins MQPR:$QdSrc, MQPR:$Qm), immops),
                   iname, suffix, "$Qd, $Qm, $imm", vpred_n, "$Qd = $QdSrc",
                   pattern> {
   bits<5> imm;
 
   let Inst{28} = bit_28;
   let Inst{25-23} = 0b101;
   let Inst{21} = 0b0;
   let Inst{20-16} = imm{4-0};
   let Inst{12} = bit_12;
   let Inst{11-6} = 0b111111;
   let Inst{4} = 0b0;
   let Inst{0} = 0b1;
+  let invalidForTailPredication = 1;
 }
 
 def MVE_VRSHRNi16bh : MVE_VxSHRN<
     "vrshrnb", "i16", 0b0, 0b1, (ins shr_imm8:$imm)> {
   let Inst{20-19} = 0b01;
 }
 def MVE_VRSHRNi16th : MVE_VxSHRN<
     "vrshrnt", "i16", 0b1, 0b1,(ins shr_imm8:$imm)> {

   let Inst{28} = bit_28;
   let Inst{25-23} = 0b101;
   let Inst{21} = 0b0;
   let Inst{20-16} = imm{4-0};
   let Inst{12} = bit_12;
   let Inst{11-6} = 0b111111;
   let Inst{4} = 0b0;
   let Inst{0} = 0b0;
+  let invalidForTailPredication = 1;
 }
 
 def MVE_VQRSHRUNs16bh : MVE_VxQRSHRUN<
     "vqrshrunb", "s16", 0b1, 0b0, (ins shr_imm8:$imm)> {
   let Inst{20-19} = 0b01;
 }
 def MVE_VQRSHRUNs16th : MVE_VxQRSHRUN<
     "vqrshrunt", "s16", 0b1, 0b1, (ins shr_imm8:$imm)> {

 
   let Inst{25-23} = 0b101;
   let Inst{21} = 0b0;
   let Inst{20-16} = imm{4-0};
   let Inst{12} = bit_12;
   let Inst{11-6} = 0b111101;
   let Inst{4} = 0b0;
   let Inst{0} = bit_0;
+  let invalidForTailPredication = 1;
 }
 
 multiclass MVE_VxQRSHRN_types<string iname, bit bit_0, bit bit_12> {
   def s16 : MVE_VxQRSHRN<iname, "s16", bit_0, bit_12, (ins shr_imm8:$imm)> {
     let Inst{28} = 0b0;
     let Inst{20-19} = 0b01;
   }
   def u16 : MVE_VxQRSHRN<iname, "u16", bit_0, bit_12, (ins shr_imm8:$imm)> {

   let Inst{28} = subtract;
   let Inst{21-20} = size;
   let Inst{19-17} = Qn{2-0};
   let Inst{16} = 0b0;
   let Inst{12} = exch;
   let Inst{8} = 0b0;
   let Inst{7} = Qn{3};
   let Inst{0} = round;
+  let invalidForTailPredication = 1;
 }
 
 multiclass MVE_VQxDMLxDH_multi<string iname, bit exch,
                                bit round, bit subtract> {
   def s8  : MVE_VQxDMLxDH<iname, exch, round, subtract, "s8",  0b00>;
   def s16 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s16", 0b01>;
   def s32 : MVE_VQxDMLxDH<iname, exch, round, subtract, "s32", 0b10, ",@earlyclobber $Qd">;
 }
 
 defm MVE_VQDMLADH   : MVE_VQxDMLxDH_multi<"vqdmladh",   0b0, 0b0, 0b0>;
 defm MVE_VQDMLADHX  : MVE_VQxDMLxDH_multi<"vqdmladhx",  0b1, 0b0, 0b0>;
 defm MVE_VQRDMLADH  : MVE_VQxDMLxDH_multi<"vqrdmladh",  0b0, 0b1, 0b0>;
 defm MVE_VQRDMLADHX : MVE_VQxDMLxDH_multi<"vqrdmladhx", 0b1, 0b1, 0b0>;
 defm MVE_VQDMLSDH   : MVE_VQxDMLxDH_multi<"vqdmlsdh",   0b0, 0b0, 0b1>;
 defm MVE_VQDMLSDHX  : MVE_VQxDMLxDH_multi<"vqdmlsdhx",  0b1, 0b0, 0b1>;
 defm MVE_VQRDMLSDH  : MVE_VQxDMLxDH_multi<"vqrdmlsdh",  0b0, 0b1, 0b1>;
 defm MVE_VQRDMLSDHX : MVE_VQxDMLxDH_multi<"vqrdmlsdhx", 0b1, 0b1, 0b1>;
 
 class MVE_VCMUL<string iname, string suffix, bit size, string cstr="", list<dag> pattern=[]>
   : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
                    (ins MQPR:$Qn, MQPR:$Qm, complexrotateop:$rot),
                    "$Qd, $Qn, $Qm, $rot", vpred_r, cstr, pattern> {
   bits<4> Qn;
   bits<2> rot;
 
   let Inst{28} = size;
   let Inst{21-20} = 0b11;
   let Inst{19-17} = Qn{2-0};
   let Inst{16} = 0b0;
   let Inst{12} = rot{1};
   let Inst{8} = 0b0;
   let Inst{7} = Qn{3};
   let Inst{0} = rot{0};
 
   let Predicates = [HasMVEFloat];
 }
 
 def MVE_VCMULf16 : MVE_VCMUL<"vcmul", "f16", 0b0>;
 def MVE_VCMULf32 : MVE_VCMUL<"vcmul", "f32", 0b1, "@earlyclobber $Qd">;
 
 class MVE_VMULL<string iname, string suffix, bit bit_28, bits<2> bits_21_20,
                 bit T, string cstr, list<dag> pattern=[]>
   : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd),
                    (ins MQPR:$Qn, MQPR:$Qm), "$Qd, $Qn, $Qm",
                    vpred_r, cstr, pattern> {
   bits<4> Qd;
   bits<4> Qn;
   bits<4> Qm;
 

   let Inst{21-20} = 0b11;
   let Inst{19-18} = size;
   let Inst{17} = bit_17;
   let Inst{16} = 0b1;
   let Inst{12} = T;
   let Inst{8} = 0b0;
   let Inst{7} = !if(!eq(bit_17, 0), 1, 0);
   let Inst{0} = 0b1;
+  let invalidForTailPredication = 1;
 }
 
 multiclass MVE_VxMOVxN_halves<string iname, string suffix,
                               bit bit_28, bit bit_17, bits<2> size> {
   def bh : MVE_VxMOVxN<iname # "b", suffix, bit_28, bit_17, size, 0b0>;
   def th : MVE_VxMOVxN<iname # "t", suffix, bit_28, bit_17, size, 0b1>;
 }
 
 defm MVE_VMOVNi16   : MVE_VxMOVxN_halves<"vmovn",   "i16", 0b1, 0b0, 0b00>;
 defm MVE_VMOVNi32   : MVE_VxMOVxN_halves<"vmovn",   "i32", 0b1, 0b0, 0b01>;
 defm MVE_VQMOVNs16  : MVE_VxMOVxN_halves<"vqmovn",  "s16", 0b0, 0b1, 0b00>;
 defm MVE_VQMOVNs32  : MVE_VxMOVxN_halves<"vqmovn",  "s32", 0b0, 0b1, 0b01>;
 defm MVE_VQMOVNu16  : MVE_VxMOVxN_halves<"vqmovn",  "u16", 0b1, 0b1, 0b00>;
 defm MVE_VQMOVNu32  : MVE_VxMOVxN_halves<"vqmovn",  "u32", 0b1, 0b1, 0b01>;
 defm MVE_VQMOVUNs16 : MVE_VxMOVxN_halves<"vqmovun", "s16", 0b0, 0b0, 0b00>;
 defm MVE_VQMOVUNs32 : MVE_VxMOVxN_halves<"vqmovun", "s32", 0b0, 0b0, 0b01>;
 
 class MVE_VCVT_ff<string iname, string suffix, bit op, bit T,
                   list<dag> pattern=[]>
   : MVE_qDest_qSrc<iname, suffix, (outs MQPR:$Qd), (ins MQPR:$Qd_src, MQPR:$Qm),
                    "$Qd, $Qm", vpred_n, "$Qd = $Qd_src", pattern> {
   let Inst{28} = op;
   let Inst{21-16} = 0b111111;
   let Inst{12} = T;
   let Inst{8-7} = 0b00;
   let Inst{0} = 0b1;

 def MVE_VCADDi8   : MVE_VxCADD<"vcadd", "i8", 0b00, 0b1>;
 def MVE_VCADDi16  : MVE_VxCADD<"vcadd", "i16", 0b01, 0b1>;
 def MVE_VCADDi32  : MVE_VxCADD<"vcadd", "i32", 0b10, 0b1, "@earlyclobber $Qd">;
 
 def MVE_VHCADDs8  : MVE_VxCADD<"vhcadd", "s8", 0b00, 0b0>;
 def MVE_VHCADDs16 : MVE_VxCADD<"vhcadd", "s16", 0b01, 0b0>;
 def MVE_VHCADDs32 : MVE_VxCADD<"vhcadd", "s32", 0b10, 0b0, "@earlyclobber $Qd">;
 
 class MVE_VADCSBC<string iname, bit I, bit subtract,
                   dag carryin, list<dag> pattern=[]>
   : MVE_qDest_qSrc<iname, "i32", (outs MQPR:$Qd, cl_FPSCR_NZCV:$carryout),
                    !con((ins MQPR:$Qn, MQPR:$Qm), carryin),
                    "$Qd, $Qn, $Qm", vpred_r, "", pattern> {
   bits<4> Qn;
 
   let Inst{28} = subtract;
   let Inst{21-20} = 0b11;

   : MVE_qDestSrc_rSrc<iname, suffix, pattern> {
 
   let Inst{28} = U;
   let Inst{21-20} = size;
   let Inst{16} = 0b0;
   let Inst{12} = bit_12;
   let Inst{8} = 0b0;
   let Inst{5} = bit_5;
+  let invalidForTailPredication = 1;
 }
 
 multiclass MVE_VQDMLAH_qr_types<string iname, bit bit_5, bit bit_12> {
   def s8  : MVE_VQDMLAH_qr<iname, "s8",  0b0, 0b00, bit_5, bit_12>;
   def s16 : MVE_VQDMLAH_qr<iname, "s16", 0b0, 0b01, bit_5, bit_12>;
   def s32 : MVE_VQDMLAH_qr<iname, "s32", 0b0, 0b10, bit_5, bit_12>;
 }
 
 defm MVE_VQDMLAH_qr   : MVE_VQDMLAH_qr_types<"vqdmlah",   0b1, 0b0>;
 defm MVE_VQRDMLAH_qr  : MVE_VQDMLAH_qr_types<"vqrdmlah",  0b0, 0b0>;
 defm MVE_VQDMLASH_qr  : MVE_VQDMLAH_qr_types<"vqdmlash",  0b1, 0b1>;
 defm MVE_VQRDMLASH_qr : MVE_VQDMLAH_qr_types<"vqrdmlash", 0b0, 0b1>;
 
 class MVE_VxDUP<string iname, string suffix, bits<2> size, bit bit_12,
               list<dag> pattern=[]>
   : MVE_p<(outs MQPR:$Qd, tGPREven:$Rn),
           (ins tGPREven:$Rn_src, MVE_VIDUP_imm:$imm), NoItinerary,
           iname, suffix, "$Qd, $Rn, $imm", vpred_r, "$Rn = $Rn_src",
           pattern> {
   bits<4> Qd;
   bits<4> Rn;
   bits<2> imm;

   let Inst{12-9} = 0b1111;
   let Inst{8-7} = size;
   let Inst{6-5} = stage;
   let Inst{4-1} = 0b0000;
   let Inst{0} = fourregs;
 
   let mayLoad = load;
   let mayStore = !eq(load,0);
+  let invalidForTailPredication = 1;
 }
 
 // A parameter class used to encapsulate all the ways the writeback
 // variants of VLD20 and friends differ from the non-writeback ones.
 class MVE_vldst24_writeback<bit b, dag Oo, dag Io,
                             string sy="", string c="", string n=""> {
   bit writeback = b;
   dag Oops = Oo;

unittests/Target/ARM/MachineInstrTest.cpp

 #include "ARMBaseInstrInfo.h"
 #include "ARMSubtarget.h"
 #include "ARMTargetMachine.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/TargetSelect.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 
 #include "gtest/gtest.h"
 
 using namespace llvm;
 
 // Test for instructions that aren't immediately obviously valid within a
 // tail-predicated loop. This should be marked up in their tablegen
 // descriptions. Currently the horizontal vector operations are tagged.
-// TODO Add instructions that perform:
-// - truncation,
-// - extensions,
-// - byte swapping,
-// - others?
+// TODO: Are there any other instructions that perform narrowing, extending or
+// byte swapping?
+// TODO: Prune this list once we can handle them safely.
 TEST(MachineInstrInvalidTailPredication, IsCorrect) {
   LLVMInitializeARMTargetInfo();
   LLVMInitializeARMTarget();
   LLVMInitializeARMTargetMC();
 
   auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
   std::string Error;
   const Target *T = TargetRegistry::lookupTarget(TT, Error);
auto IsInvalidTPOpcode = [](unsigned Opcode) {
     case MVE_VMINVu16:
     case MVE_VMINVu32:
     case MVE_VMAXAVs8:
     case MVE_VMAXAVs16:
     case MVE_VMAXAVs32:
     case MVE_VMINAVs8:
     case MVE_VMINAVs16:
     case MVE_VMINAVs32:
+    case MVE_VMOVNi16bh:
+    case MVE_VMOVNi16th:
+    case MVE_VMOVNi32bh:
+    case MVE_VMOVNi32th:
+    case MVE_VQMOVNs16bh:
+    case MVE_VQMOVNs16th:
+    case MVE_VQMOVNs32bh:
+    case MVE_VQMOVNs32th:
+    case MVE_VQMOVNu16bh:
+    case MVE_VQMOVNu16th:
+    case MVE_VQMOVNu32bh:
+    case MVE_VQMOVNu32th:
+    case MVE_VQMOVUNs16bh:
+    case MVE_VQMOVUNs16th:
+    case MVE_VQMOVUNs32bh:
+    case MVE_VQMOVUNs32th:
+    case MVE_VMOV_q_rr:
+    case MVE_VMOV_from_lane_32:
+    case MVE_VMOV_from_lane_s16:
+    case MVE_VMOV_from_lane_s8:
+    case MVE_VMOV_from_lane_u16:
+    case MVE_VMOV_from_lane_u8:
+    case MVE_VMOV_rr_q:
+    case MVE_VMOV_to_lane_16:
+    case MVE_VMOV_to_lane_32:
+    case MVE_VMOV_to_lane_8:
+    case MVE_VQDMLADHXs16:
+    case MVE_VQDMLADHXs32:
+    case MVE_VQDMLADHXs8:
+    case MVE_VQDMLADHs16:
+    case MVE_VQDMLADHs32:
+    case MVE_VQDMLADHs8:
+    case MVE_VQDMLAH_qrs16:
+    case MVE_VQDMLAH_qrs32:
+    case MVE_VQDMLAH_qrs8:
+    case MVE_VQDMLASH_qrs16:
+    case MVE_VQDMLASH_qrs32:
+    case MVE_VQDMLASH_qrs8:
+    case MVE_VQDMLSDHXs16:
+    case MVE_VQDMLSDHXs32:
+    case MVE_VQDMLSDHXs8:
+    case MVE_VQDMLSDHs16:
+    case MVE_VQDMLSDHs32:
+    case MVE_VQDMLSDHs8:
+    case MVE_VQRDMLADHXs16:
+    case MVE_VQRDMLADHXs32:
+    case MVE_VQRDMLADHXs8:
+    case MVE_VQRDMLADHs16:
+    case MVE_VQRDMLADHs32:
+    case MVE_VQRDMLADHs8:
+    case MVE_VQRDMLAH_qrs16:
+    case MVE_VQRDMLAH_qrs32:
+    case MVE_VQRDMLAH_qrs8:
+    case MVE_VQRDMLASH_qrs16:
+    case MVE_VQRDMLASH_qrs32:
+    case MVE_VQRDMLASH_qrs8:
+    case MVE_VQRDMLSDHXs16:
+    case MVE_VQRDMLSDHXs32:
+    case MVE_VQRDMLSDHXs8:
+    case MVE_VQRDMLSDHs16:
+    case MVE_VQRDMLSDHs32:
+    case MVE_VQRDMLSDHs8:
+    case MVE_VQRSHRNbhs16:
+    case MVE_VQRSHRNbhs32:
+    case MVE_VQRSHRNbhu16:
+    case MVE_VQRSHRNbhu32:
+    case MVE_VQRSHRNths16:
+    case MVE_VQRSHRNths32:
+    case MVE_VQRSHRNthu16:
+    case MVE_VQRSHRNthu32:
+    case MVE_VQRSHRUNs16bh:
+    case MVE_VQRSHRUNs16th:
+    case MVE_VQRSHRUNs32bh:
+    case MVE_VQRSHRUNs32th:
+    case MVE_VQSHRNbhs16:
+    case MVE_VQSHRNbhs32:
+    case MVE_VQSHRNbhu16:
+    case MVE_VQSHRNbhu32:
+    case MVE_VQSHRNths16:
+    case MVE_VQSHRNths32:
+    case MVE_VQSHRNthu16:
+    case MVE_VQSHRNthu32:
+    case MVE_VQSHRUNs16bh:
+    case MVE_VQSHRUNs16th:
+    case MVE_VQSHRUNs32bh:
+    case MVE_VQSHRUNs32th:
+    case MVE_VREV16_8:
+    case MVE_VREV32_16:
+    case MVE_VREV32_8:
+    case MVE_VREV64_16:
+    case MVE_VREV64_32:
+    case MVE_VREV64_8:
+    case MVE_VRSHRNi16bh:
+    case MVE_VRSHRNi16th:
+    case MVE_VRSHRNi32bh:
+    case MVE_VRSHRNi32th:
+    case MVE_VSHRNi16bh:
+    case MVE_VSHRNi16th:
+    case MVE_VSHRNi32bh:
+    case MVE_VSHRNi32th:
+    case MVE_VLD20_16:
+    case MVE_VLD20_16_wb:
+    case MVE_VLD20_32:
+    case MVE_VLD20_32_wb:
+    case MVE_VLD20_8:
+    case MVE_VLD20_8_wb:
+    case MVE_VLD21_16:
+    case MVE_VLD21_16_wb:
+    case MVE_VLD21_32:
+    case MVE_VLD21_32_wb:
+    case MVE_VLD21_8:
+    case MVE_VLD21_8_wb:
+    case MVE_VLD40_16:
+    case MVE_VLD40_16_wb:
+    case MVE_VLD40_32:
+    case MVE_VLD40_32_wb:
+    case MVE_VLD40_8:
+    case MVE_VLD40_8_wb:
+    case MVE_VLD41_16:
+    case MVE_VLD41_16_wb:
+    case MVE_VLD41_32:
+    case MVE_VLD41_32_wb:
+    case MVE_VLD41_8:
+    case MVE_VLD41_8_wb:
+    case MVE_VLD42_16:
+    case MVE_VLD42_16_wb:
+    case MVE_VLD42_32:
+    case MVE_VLD42_32_wb:
+    case MVE_VLD42_8:
+    case MVE_VLD42_8_wb:
+    case MVE_VLD43_16:
+    case MVE_VLD43_16_wb:
+    case MVE_VLD43_32:
+    case MVE_VLD43_32_wb:
+    case MVE_VLD43_8:
+    case MVE_VLD43_8_wb:
+    case MVE_VST20_16:
+    case MVE_VST20_16_wb:
+    case MVE_VST20_32:
+    case MVE_VST20_32_wb:
+    case MVE_VST20_8:
+    case MVE_VST20_8_wb:
+    case MVE_VST21_16:
+    case MVE_VST21_16_wb:
+    case MVE_VST21_32:
+    case MVE_VST21_32_wb:
+    case MVE_VST21_8:
+    case MVE_VST21_8_wb:
+    case MVE_VST40_16:
+    case MVE_VST40_16_wb:
+    case MVE_VST40_32:
+    case MVE_VST40_32_wb:
+    case MVE_VST40_8:
+    case MVE_VST40_8_wb:
+    case MVE_VST41_16:
+    case MVE_VST41_16_wb:
+    case MVE_VST41_32:
+    case MVE_VST41_32_wb:
+    case MVE_VST41_8:
+    case MVE_VST41_8_wb:
+    case MVE_VST42_16:
+    case MVE_VST42_16_wb:
+    case MVE_VST42_32:
+    case MVE_VST42_32_wb:
+    case MVE_VST42_8:
+    case MVE_VST42_8_wb:
+    case MVE_VST43_16:
+    case MVE_VST43_16_wb:
+    case MVE_VST43_32:
+    case MVE_VST43_32_wb:
+    case MVE_VST43_8:
+    case MVE_VST43_8_wb:
       return true;
     default:
       return false;
     }
   };
 
   for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
     uint64_t Flags = MII->get(i).TSFlags;
     bool Invalid = (Flags & ARMII::InvalidForTailPredication) != 0;
     ASSERT_EQ(IsInvalidTPOpcode(i), Invalid)
         << MII->getName(i)
         << ": mismatched expectation for tail-predicated safety\n";
   }
 }