Add 8548 CPU definition and attributes

[jhibbits]

Summary

8548 CPU is GCC's name for the e500v2, so accept this in clang. The
e500v2 doesn't support lwsync, so define NO_LWSYNC for this as well,
as GCC does.

[jhibbits]

I made 8548 an alias in clang to e500, because e500 is recognized in llvm as a CPU, so gets us the feature list and, more importantly, the instruction scheduler.

[vit9696]

@jhibbits Should not the test in test/Preprocessor/init.c also ensure that __SPE__ and __NO_FPRS__ macros are defined with CPU 8548? The rest looks good to me, thank you.

[jhibbits]

@vit9696 The only thing GCC defines for mcpu=8548 is NO_LWSYNC, the SPE-specific #defines are from -mspe. That said, since I explicitly do enable SPE for e500 CPU, I guess it makes sense to add it to the test.

[vit9696]

Yes, that's the point, since 8548 is an alias.

A side note regarding SPE support. I am currently upgrading to LLVM 9.0 and I discovered that this patch was not committed anyhow at all:
https://reviews.llvm.org/D54583#1444288

[jhibbits]

In D67787#1719251, @vit9696 wrote:

A side note regarding SPE support. I am currently upgrading to LLVM 9.0 and I discovered that this patch was not committed anyhow at all:
https://reviews.llvm.org/D54583#1444288

Yeah, I noticed that after I committed it. Problem is, to submit that for review, I need a valid reduced test case., and my laziness/busy-ness has prevented me from creating a reduced test case in LLVM language.

[jhibbits]

Make 8548 actually denote e500 LLVM target, add SPE checks to 8548 preprocessor test.

[vit9696]

I noticed a typo in the file, but the rest looks good now.

clang/lib/Driver/ToolChains/Arch/PPC.cpp

61

That looks like a typo to me. There is one more 8548 case above.

[jhibbits]

clang/lib/Driver/ToolChains/Arch/PPC.cpp

61

You're right, I missed that I added it above already.

[jhibbits]

Don't double-check 8548 CPU for setting LLVM CPU type.

[vit9696]

Thanks.

[jhibbits]

Add clang-translation tests for e500 and 8548 CPU definitions.

[jhibbits]

@vit9696 mind reviewing again with the added tests?

[vit9696]

Actually thanks for adding C checks too. The new revision also looks good to me.

clang/lib/Basic/Targets/PPC.h

typedef enum {
     ArchDefinePwr5 = 1 << 7,
     ArchDefinePwr5x = 1 << 8,
     ArchDefinePwr6 = 1 << 9,
     ArchDefinePwr6x = 1 << 10,
     ArchDefinePwr7 = 1 << 11,
     ArchDefinePwr8 = 1 << 12,
     ArchDefinePwr9 = 1 << 13,
     ArchDefineA2 = 1 << 14,
-    ArchDefineA2q = 1 << 15
+    ArchDefineA2q = 1 << 15,
+    ArchDefineE500 = 1 << 16
   } ArchDefineTypes;
 
 
   ArchDefineTypes ArchDefs = ArchDefineNone;
   static const Builtin::Info BuiltinInfo[];
   static const char *const GCCRegNames[];
   static const TargetInfo::GCCRegAlias GCCRegAliases[];
   std::string CPU;
if (CPUKnown) {
               .Cases("power8", "pwr8", "ppc64le",
                      ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
                          ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
                          ArchDefinePpcgr | ArchDefinePpcsq)
               .Cases("power9", "pwr9",
                      ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
                          ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
                          ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
+              .Cases("8548", "e500", ArchDefineE500)
               .Default(ArchDefineNone);
     }
     return CPUKnown;
   }
 
   StringRef getABI() const override { return ABI; }
 
   ArrayRef<Builtin::Info> getTargetBuiltins() const override;

clang/lib/Basic/Targets/PPC.cpp

void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
   if (ArchDefs & ArchDefinePwr9)
     Builder.defineMacro("_ARCH_PWR9");
   if (ArchDefs & ArchDefineA2)
     Builder.defineMacro("_ARCH_A2");
   if (ArchDefs & ArchDefineA2q) {
     Builder.defineMacro("_ARCH_A2Q");
     Builder.defineMacro("_ARCH_QP");
   }
+  if (ArchDefs & ArchDefineE500)
+    Builder.defineMacro("__NO_LWSYNC__");
 
   if (getTriple().getVendor() == llvm::Triple::BGQ) {
     Builder.defineMacro("__bg__");
     Builder.defineMacro("__THW_BLUEGENE__");
     Builder.defineMacro("__bgq__");
     Builder.defineMacro("__TOS_BGQ__");
   }
 
Features["vsx"] = llvm::StringSwitch<bool>(CPU)
                         .Case("pwr7", true)
                         .Default(false);
   Features["htm"] = llvm::StringSwitch<bool>(CPU)
                         .Case("ppc64le", true)
                         .Case("pwr9", true)
                         .Case("pwr8", true)
                         .Default(false);
 
+  Features["spe"] = llvm::StringSwitch<bool>(CPU)
+                        .Case("8548", true)
+                        .Case("e500", true)
+                        .Default(false);
+
   if (!ppcUserFeaturesCheck(Diags, FeaturesVec))
     return false;
 
   if (!(ArchDefs & ArchDefinePwr9) && (ArchDefs & ArchDefinePpcgr) &&
       llvm::find(FeaturesVec, "+float128") != FeaturesVec.end()) {
     // We have __float128 on PPC but not power 9 and above.
     Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" << CPU;
     return false;

 ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const {
   if (ABI == "elfv2")
     return llvm::makeArrayRef(GCCAddlRegNames);
   else 
     return TargetInfo::getGCCAddlRegNames(); 
 }
 
 static constexpr llvm::StringLiteral ValidCPUNames[] = {
-    {"generic"}, {"440"},         {"450"},     {"601"},    {"602"},
-    {"603"},     {"603e"},        {"603ev"},   {"604"},    {"604e"},
-    {"620"},     {"630"},         {"g3"},      {"7400"},   {"g4"},
-    {"7450"},    {"g4+"},         {"750"},     {"970"},    {"g5"},
-    {"a2"},      {"a2q"},         {"e500mc"},  {"e5500"},  {"power3"},
-    {"pwr3"},    {"power4"},      {"pwr4"},    {"power5"}, {"pwr5"},
-    {"power5x"}, {"pwr5x"},       {"power6"},  {"pwr6"},   {"power6x"},
-    {"pwr6x"},   {"power7"},      {"pwr7"},    {"power8"}, {"pwr8"},
-    {"power9"},  {"pwr9"},        {"powerpc"}, {"ppc"},    {"powerpc64"},
-    {"ppc64"},   {"powerpc64le"}, {"ppc64le"},
+    {"generic"},   {"440"},       {"450"},         {"601"},         {"602"},
+    {"603"},       {"603e"},      {"603ev"},       {"604"},         {"604e"},
+    {"620"},       {"630"},       {"g3"},          {"7400"},        {"g4"},
+    {"7450"},      {"g4+"},       {"750"},         {"8548"},        {"970"},
+    {"g5"},        {"a2"},        {"a2q"},         {"e500"},        {"e500mc"},
+    {"e5500"},     {"power3"},    {"pwr3"},        {"power4"},      {"pwr4"},
+    {"power5"},    {"pwr5"},      {"power5x"},     {"pwr5x"},       {"power6"},
+    {"pwr6"},      {"power6x"},   {"pwr6x"},       {"power7"},      {"pwr7"},
+    {"power8"},    {"pwr8"},      {"power9"},      {"pwr9"},        {"powerpc"},
+    {"ppc"},       {"powerpc64"}, {"ppc64"},       {"powerpc64le"}, {"ppc64le"},
 };
 
 bool PPCTargetInfo::isValidCPUName(StringRef Name) const {
   return llvm::find(ValidCPUNames, Name) != std::end(ValidCPUNames);
 }
 
 void PPCTargetInfo::fillValidCPUList(SmallVectorImpl<StringRef> &Values) const {
   Values.append(std::begin(ValidCPUNames), std::end(ValidCPUNames));

clang/lib/Driver/ToolChains/Arch/PPC.cpp

return llvm::StringSwitch<const char *>(CPUName)
         .Case("620", "620")
         .Case("630", "pwr3")
         .Case("G3", "g3")
         .Case("7400", "7400")
         .Case("G4", "g4")
         .Case("7450", "7450")
         .Case("G4+", "g4+")
         .Case("750", "750")
+        .Case("8548", "e500")
         .Case("970", "970")
         .Case("G5", "g5")
         .Case("a2", "a2")
         .Case("a2q", "a2q")
+        .Case("e500", "e500")
         .Case("e500mc", "e500mc")
         .Case("e5500", "e5500")
         .Case("power3", "pwr3")
         .Case("power4", "pwr4")
         .Case("power5", "pwr5")
         .Case("power5x", "pwr5x")
         .Case("power6", "pwr6")
         .Case("power6x", "pwr6x")

clang/test/Driver/clang-translation.c

 
 // RUN: %clang -target powerpc64-unknown-linux-gnu \
 // RUN: -### -S %s 2>&1 | FileCheck -check-prefix=PPC64NS %s
 // PPC64NS: clang
 // PPC64NS: "-cc1"
 // PPC64NS: "-target-cpu" "ppc64"
 
 // RUN: %clang -target powerpc-fsl-linux -### -S %s \
+// RUN: -mcpu=e500 2>&1 | FileCheck -check-prefix=PPCE500 %s
+// PPCE500: clang
+// PPCE500: "-cc1"
+// PPCE500: "-target-cpu" "e500"
+
+// RUN: %clang -target powerpc-fsl-linux -### -S %s \
+// RUN: -mcpu=8548 2>&1 | FileCheck -check-prefix=PPC8548 %s
+// PPC8548: clang
+// PPC8548: "-cc1"
+// PPC8548: "-target-cpu" "e500"
+
+// RUN: %clang -target powerpc-fsl-linux -### -S %s \
 // RUN: -mcpu=e500mc 2>&1 | FileCheck -check-prefix=PPCE500MC %s
 // PPCE500MC: clang
 // PPCE500MC: "-cc1"
 // PPCE500MC: "-target-cpu" "e500mc"
 
 // RUN: %clang -target powerpc64-fsl-linux -### -S \
 // RUN: %s -mcpu=e5500 2>&1 | FileCheck -check-prefix=PPCE5500 %s
 // PPCE5500: clang

clang/test/Misc/target-invalid-cpu-note.c

 // RUN: not %clang_cc1 -triple sparcv9--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix SPARCV9
 // SPARCV9: error: unknown target CPU 'not-a-cpu'
 // SPARCV9: note: valid target CPU values are: v9, ultrasparc, ultrasparc3, niagara, niagara2, niagara3, niagara4
 
 // RUN: not %clang_cc1 -triple powerpc--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix PPC
 // PPC: error: unknown target CPU 'not-a-cpu'
 // PPC: note: valid target CPU values are: generic, 440, 450, 601, 602, 603,
 // PPC-SAME: 603e, 603ev, 604, 604e, 620, 630, g3, 7400, g4, 7450, g4+, 750,
-// PPC-SAME: 970, g5, a2, a2q, e500mc, e5500, power3, pwr3, power4, pwr4,
-// PPC-SAME: power5, pwr5, power5x, pwr5x, power6, pwr6, power6x, pwr6x, power7,
-// PPC-SAME: pwr7, power8, pwr8, power9, pwr9, powerpc, ppc, powerpc64, ppc64,
-// PPC-SAME: powerpc64le, ppc64le
+// PPC-SAME: 8548, 970, g5, a2, a2q, e500, e500mc, e5500, power3, pwr3, power4,
+// PPC-SAME: pwr4, power5, pwr5, power5x, pwr5x, power6, pwr6, power6x, pwr6x,
+// PPC-SAME: power7, pwr7, power8, pwr8, power9, pwr9, powerpc, ppc, powerpc64,
+// PPC-SAME: ppc64, powerpc64le, ppc64le
 
 // RUN: not %clang_cc1 -triple mips--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix MIPS
 // MIPS: error: unknown target CPU 'not-a-cpu'
 // MIPS: note: valid target CPU values are: mips1, mips2, mips3, mips4, mips5,
 // MIPS-SAME: mips32, mips32r2, mips32r3, mips32r5, mips32r6, mips64, mips64r2,
 // MIPS-SAME: mips64r3, mips64r5, mips64r6, octeon, octeon+, p5600
 
 // RUN: not %clang_cc1 -triple lanai--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix LANAI

clang/test/Preprocessor/init.c

 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc-unknown-linux-gnu -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPC32-LINUX %s
 //
 // PPC32-LINUX-NOT: _CALL_LINUX
 //
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc-unknown-linux-gnu -target-feature +spe < /dev/null | FileCheck -match-full-lines -check-prefix PPC32-SPE %s
 //
 // PPC32-SPE:#define __NO_FPRS__ 1
 // PPC32-SPE:#define __SPE__ 1
-//
+// 
+// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc-unknown-linux-gnu -target-cpu 8548 < /dev/null | FileCheck -match-full-lines -check-prefix PPC8548 %s
+//
+// PPC8548:#define __NO_FPRS__ 1
+// PPC8548:#define __NO_LWSYNC__ 1
+// PPC8548:#define __SPE__ 1
+//
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc-apple-darwin8 < /dev/null | FileCheck -match-full-lines -check-prefix PPC-DARWIN %s
 //
 // PPC-DARWIN:#define _ARCH_PPC 1
 // PPC-DARWIN:#define _BIG_ENDIAN 1
 // PPC-DARWIN:#define __BIGGEST_ALIGNMENT__ 16
 // PPC-DARWIN:#define __BIG_ENDIAN__ 1
 // PPC-DARWIN:#define __BYTE_ORDER__ __ORDER_BIG_ENDIAN__
 // PPC-DARWIN:#define __CHAR16_TYPE__ unsigned short