[Alignment][NFC] Use Align with TargetLowering::setPrefLoopAlignment

[gchatelet]

Summary

This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

[gchatelet]

Thx !

llvm/include/llvm/CodeGen/TargetLowering.h

protected:
 
   /// Set the target's preferred function alignment.  This should be set if
   /// there is a performance benefit to higher-than-minimum alignment (in
   /// log2(bytes))
   void setPrefFunctionLogAlignment(unsigned LogAlign) {
     PrefFunctionAlignment = llvm::Align(1ULL << LogAlign);
   }
 
-  /// Set the target's preferred loop alignment. Default alignment is zero, it
-  /// means the target does not care about loop alignment.  The alignment is
-  /// specified in log2(bytes). The target may also override
-  /// getPrefLoopAlignment to provide per-loop values.
-  void setPrefLoopLogAlignment(unsigned LogAlign) {
-    PrefLoopAlignment = llvm::Align(1ULL << LogAlign);
-  }
+  /// Set the target's preferred loop alignment. Default alignment is one, it
+  /// means the target does not care about loop alignment. The target may also
+  /// override getPrefLoopAlignment to provide per-loop values.
+  void setPrefLoopAlignment(llvm::Align Align) { PrefLoopAlignment = Align; }
 
   /// Set the minimum stack alignment of an argument.
   void setMinStackArgumentAlignment(unsigned Align) {
     MinStackArgumentAlignment = llvm::Align(Align);
   }
 
   /// Set the maximum atomic operation size supported by the
   /// backend. Atomic operations greater than this size (as well as

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
   setSchedulingPreference(Sched::Hybrid);
 
   EnableExtLdPromotion = true;
 
   // Set required alignment.
   setMinFunctionAlignment(llvm::Align(4));
   // Set preferred alignments.
   setPrefFunctionLogAlignment(STI.getPrefFunctionLogAlignment());
-  setPrefLoopLogAlignment(STI.getPrefLoopLogAlignment());
+  setPrefLoopAlignment(llvm::Align(1ULL << STI.getPrefLoopLogAlignment()));
 
   // Only change the limit for entries in a jump table if specified by
   // the sub target, but not at the command line.
   unsigned MaxJT = STI.getMaximumJumpTableSize();
   if (MaxJT && getMaximumJumpTableSize() == UINT_MAX)
     setMaximumJumpTableSize(MaxJT);
 
   setHasExtractBitsInsn(true);

llvm/lib/Target/ARM/ARMISelLowering.cpp

 
   // On ARM arguments smaller than 4 bytes are extended, so all arguments
   // are at least 4 bytes aligned.
   setMinStackArgumentAlignment(4);
 
   // Prefer likely predicted branches to selects on out-of-order cores.
   PredictableSelectIsExpensive = Subtarget->getSchedModel().isOutOfOrder();
 
-  setPrefLoopLogAlignment(Subtarget->getPrefLoopLogAlignment());
+  setPrefLoopAlignment(
+      llvm::Align(1UL << Subtarget->getPrefLoopLogAlignment()));
 
   setMinFunctionAlignment(Subtarget->isThumb() ? llvm::Align(2)
                                                : llvm::Align(4));
 
   if (Subtarget->isThumb() || Subtarget->isThumb2())
     setTargetDAGCombine(ISD::ABS);
 }
 

llvm/lib/Target/Hexagon/HexagonISelLowering.cpp

 //===----------------------------------------------------------------------===//
 
 HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
                                              const HexagonSubtarget &ST)
     : TargetLowering(TM), HTM(static_cast<const HexagonTargetMachine&>(TM)),
       Subtarget(ST) {
   auto &HRI = *Subtarget.getRegisterInfo();
 
-  setPrefLoopLogAlignment(4);
+  setPrefLoopAlignment(llvm::Align(16));
   setPrefFunctionLogAlignment(4);
   setMinFunctionAlignment(llvm::Align(4));
   setStackPointerRegisterToSaveRestore(HRI.getStackRegister());
   setBooleanContents(TargetLoweringBase::UndefinedBooleanContent);
   setBooleanVectorContents(TargetLoweringBase::UndefinedBooleanContent);
 
   setMaxAtomicSizeInBitsSupported(64);
   setMinCmpXchgSizeInBits(32);

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

   case PPC::DIR_PWR5:
   case PPC::DIR_PWR5X:
   case PPC::DIR_PWR6:
   case PPC::DIR_PWR6X:
   case PPC::DIR_PWR7:
   case PPC::DIR_PWR8:
   case PPC::DIR_PWR9:
     setPrefFunctionLogAlignment(4);
-    setPrefLoopLogAlignment(4);
+    setPrefLoopAlignment(llvm::Align(16));
     break;
   }
 
   if (Subtarget.enableMachineScheduler())
     setSchedulingPreference(Sched::Source);
   else
     setSchedulingPreference(Sched::Hybrid);
 

llvm/lib/Target/X86/X86ISelLowering.cpp

 cl::opt<bool> ExperimentalVectorWideningLegalization(
     "x86-experimental-vector-widening-legalization", cl::init(true),
     cl::desc("Enable an experimental vector type legalization through widening "
              "rather than promotion."),
     cl::Hidden);
 
 static cl::opt<int> ExperimentalPrefLoopAlignment(
     "x86-experimental-pref-loop-alignment", cl::init(4),
-    cl::desc("Sets the preferable loop alignment for experiments "
-             "(the last x86-experimental-pref-loop-alignment bits"
-             " of the loop header PC will be 0)."),
+    cl::desc(
+        "Sets the preferable loop alignment for experiments (as log2 bytes)"
     cl::Hidden);
 
 // Added in 10.0.
 static cl::opt<bool> EnableOldKNLABI(
     "x86-enable-old-knl-abi", cl::init(false),
     cl::desc("Enables passing v32i16 and v64i8 in 2 YMM registers instead of "
              "one ZMM register on AVX512F, but not AVX512BW targets."),
     cl::Hidden);

 
   // TODO: These control memcmp expansion in CGP and could be raised higher, but
   // that needs to benchmarked and balanced with the potential use of vector
   // load/store types (PR33329, PR33914).
   MaxLoadsPerMemcmp = 2;
   MaxLoadsPerMemcmpOptSize = 2;
 
   // Set loop alignment to 2^ExperimentalPrefLoopAlignment bytes (default: 2^4).
-  setPrefLoopLogAlignment(ExperimentalPrefLoopAlignment);
+  setPrefLoopAlignment(llvm::Align(1UL << ExperimentalPrefLoopAlignment));
 
   // An out-of-order CPU can speculatively execute past a predictable branch,
   // but a conditional move could be stalled by an expensive earlier operation.
   PredictableSelectIsExpensive = Subtarget.getSchedModel().isOutOfOrder();
   EnableExtLdPromotion = true;
   setPrefFunctionLogAlignment(4); // 2^4 bytes.
 
   verifyIntrinsicTables();