[X86] Override BuildSDIVPow2 for X86.

[craig.topper]

Summary

As noted in PR43197, we can use test+add+cmov+sra to implement
signed division by a power of 2.

This is based off the similar version in AArch64, but I've
adjusted it to use target independent nodes where AArch64 uses
target specific CMP and CSEL nodes. I've also blocked INT_MIN
as the transform isn't valid for that.

I've limited this to i32 and i64 on 64-bit targets for now and only
when CMOV is supported. i8 and i16 need further investigation to be
sure they get promoted to i32 well.

I adjusted a few tests to enable cmov to demonstrate the new
codegen. I also changed twoaddr-coalesce-3.ll to 32-bit mode
without cmov to avoid perturbing the scenario that is being
set up there.

[xbolva00]

llvm/test/CodeGen/X86/pr32588.ll

19

Maybe not a big deal?

Middle-end can reduce this IR to
define void @fn1() local_unnamed_addr #0 {

%t0 = load i32, i32* @c, align 4
%tobool1 = icmp eq i32 %t0, 0
%xor = zext i1 %tobool1 to i32
store i32 %xor, i32* @d, align 4
ret void

}

and then llc..
fn1: # @fn1

xor     eax, eax
cmp     dword ptr [rip + c], 0
sete    al
mov     dword ptr [rip + d], eax
ret

[spatel]

We should add the minimal/motivating test from PR43197, so we cover that exact case, and we should have at least 1 test with a negative divisor constant rather than relying on srem transforms to get that case.

llvm/lib/Target/X86/X86ISelLowering.cpp

20109–20112

That's a complicated string of logic. It would be easier to read if it was split into 2-3 clauses:

1. Check target capability
2. Check type
3. Check divisor value

20112

The min-signed check is not necessary?
https://rise4fun.com/Alive/Ki68

Name: sdiv X, {+/-} power-of-2-constant
Pre: isPowerOf2(C1) || isPowerOf2(-C1)
%r = sdiv i32 %x, C1
=>
%x_is_negative = icmp slt i32 %x, 0
%x_with_offset = add i32 %x, ((1 << countTrailingZeros(C1)) - 1)
%normx = select i1 %x_is_negative, i32 %x_with_offset, i32 %x
%a = ashr i32 %normx, countTrailingZeros(C1)
%neg = sub i32 0, %a
%divisor_is_negative = icmp slt i32 C1, 0 ; constant fold
%r = select i1 %divisor_is_negative, i32 %neg, %a

20121

This comment doesn't match what we're creating - the 'add' is the true operand of the select:
// (N0 < 0) ? (N0 + Pow2M1) : N0

[craig.topper]

Address review comments

[craig.topper]

With context

[lebedev.ri]

Do we already have test coverage for vector div-by-power-of-2?

[xbolva00]

Can you please add a test for

sdiv X, 2 ?

(gcc somehow avoids cmov in this case)

[craig.topper]

In D67087#1656269, @lebedev.ri wrote:

Do we already have test coverage for vector div-by-power-of-2?

There's some in vec_sdiv_to_shift.ll and vector-idiv-v2i32.ll and combine-sdiv.ll

[craig.topper]

Limit the transform to not apply to division by 2 or -2. Add more test cases

[xbolva00]

i8 and i16

gcc does this for char/long too.. Maybe you can try to lift restrictions and see how it looks like?
(if we miss test cases like sdiv i8 %x, 4 or sdiv i16 %x, 4 + srem variants - please add them - I was unable to find them in X86_combine-sdiv/ srem.ll / rem.ll)

[xbolva00]

Playing with chars, I think there is a way to improve -Oz codesize for this case too.

foo(char): # @foo(char)

mov     eax, edi
mov     cl, 4
cbw
idiv    cl
ret

gcc with -Os
foo(char):

mov     dl, 4
movsx   ax, dil
idiv    dl
ret

with short, -Oz
foo(long): # @foo(long)

mov     rax, rdi
push    4
pop     rcx
cqo
idiv    rcx
ret

[spatel]

Thinking about this sequence in relation to some other folds: if the add was pulled through the select operands, we'd have a select-of-constants where the false op is a zero, and that would get reduced to a 'shift+and' and defeat the goal of this patch. So if cmov is the better option for this case, it's possible that we are doing the wrong transform in some other cases.

Another consideration: if we want to avoid having the 'select' getting squashed by some other transform, then using the x86-specific opcode should ensure that (that might be why AArch chose to go with target-specific opcodes?). Having the tests here (and as usual, we should have the baseline versions committed 1st) should signal if someone changes the behavior, but it might be worth leaving a TODO comment.

llvm/lib/Target/X86/X86ISelLowering.cpp

20119

Does the caller always check this anyway? If so, could just make it an assert.

[craig.topper]

Rebase with tests pre-committed. I've also added i8/i16/i64 tests.

[spatel]

llvm/lib/Target/X86/X86ISelLowering.cpp

20119

This question wasn't answered. The only caller is DAGCombiner::visitSDIVLike()?

[craig.topper]

Change divisor check to an assert.

[spatel]

LGTM

[efriedma]

I've also blocked INT_MIN as the transform isn't valid for that.

The commit message says this, but I don't see any corresponding code?

[craig.topper]

In D67087#1659983, @efriedma wrote:

I've also blocked INT_MIN as the transform isn't valid for that.

The commit message says this, but I don't see any corresponding code?

Oops that was a mistake in my use of Alive. Sanjay pointed out it was fine, but to forgot to update the description.

llvm/lib/Target/X86/X86ISelLowering.h

SDValue getSqrtEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
                             bool Reciprocal) const override;
 
     /// Use rcp* to speed up fdiv calculations.
     SDValue getRecipEstimate(SDValue Operand, SelectionDAG &DAG, int Enabled,
                              int &RefinementSteps) const override;
 
     /// Reassociate floating point divisions into multiply by reciprocal.
     unsigned combineRepeatedFPDivisors() const override;
+
+    SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
+                          SmallVectorImpl<SDNode *> &Created) const override;
   };
 
   namespace X86 {
     FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
                              const TargetLibraryInfo *libInfo);
   } // end namespace X86
 
   // Base class for all X86 non-masked store operations.

llvm/lib/Target/X86/X86ISelLowering.cpp

 /// CPU if a division's cost is not at least twice the cost of a multiplication.
 /// This is because we still need one division to calculate the reciprocal and
 /// then we need two multiplies by that reciprocal as replacements for the
 /// original divisions.
 unsigned X86TargetLowering::combineRepeatedFPDivisors() const {
   return 2;
 }
 
+SDValue
+X86TargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
+                                 SelectionDAG &DAG,
+                                 SmallVectorImpl<SDNode *> &Created) const {
+  AttributeList Attr = DAG.getMachineFunction().getFunction().getAttributes();
+  if (isIntDivCheap(N->getValueType(0), Attr))
+    return SDValue(N,0); // Lower SDIV as SDIV
+
+  // fold (sdiv X, pow2)
+  EVT VT = N->getValueType(0);
+  if (!Subtarget.hasCMov() ||
+      (VT != MVT::i32 && !(Subtarget.is64Bit() && VT == MVT::i64)) ||
+      !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()) ||
+      Divisor.isMinSignedValue())
+    return SDValue();
+
+  SDLoc DL(N);
+  SDValue N0 = N->getOperand(0);
+  unsigned Lg2 = Divisor.countTrailingZeros();
+  SDValue Zero = DAG.getConstant(0, DL, VT);
+  SDValue Pow2MinusOne = DAG.getConstant((1ULL << Lg2) - 1, DL, VT);
+
+  // Add (N0 < 0) ? Pow2 - 1 : 0;
+  SDValue Cmp = DAG.getSetCC(DL, MVT::i8, N0, Zero, ISD::SETLT);
+  SDValue Add = DAG.getNode(ISD::ADD, DL, VT, N0, Pow2MinusOne);
+  SDValue CMov = DAG.getNode(ISD::SELECT, DL, VT, Cmp, Add, N0);
+
+  Created.push_back(Cmp.getNode());
+  Created.push_back(Add.getNode());
+  Created.push_back(CMov.getNode());
+
+  // Divide by pow2.
+  SDValue SRA =
+      DAG.getNode(ISD::SRA, DL, VT, CMov, DAG.getConstant(Lg2, DL, MVT::i64));
+
+  // If we're dividing by a positive value, we're done.  Otherwise, we must
+  // negate the result.
+  if (Divisor.isNonNegative())
+    return SRA;
+
+  Created.push_back(SRA.getNode());
+  return DAG.getNode(ISD::SUB, DL, VT, Zero, SRA);
+}
+
 /// Result of 'and' is compared against zero. Change to a BT node if possible.
 /// Returns the BT node and the condition code needed to use it.
 static SDValue LowerAndToBT(SDValue And, ISD::CondCode CC,
                             const SDLoc &dl, SelectionDAG &DAG,
                             SDValue &X86CC) {
   assert(And.getOpcode() == ISD::AND && "Expected AND node!");
   SDValue Op0 = And.getOperand(0);
   SDValue Op1 = And.getOperand(1);

llvm/test/CodeGen/X86/pr32588.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s
 
 @c = external local_unnamed_addr global i32, align 4
 @b = external local_unnamed_addr global i32, align 4
 @d = external local_unnamed_addr global i32, align 4
 
 define void @fn1() {
 ; CHECK-LABEL: fn1:
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpl $0, {{.*}}(%rip)
+; CHECK-NEXT:    setne %al
+; CHECK-NEXT:    cmpl $0, {{.*}}(%rip)
+; CHECK-NEXT:    setne %cl
+; CHECK-NEXT:    andb %al, %cl
+; CHECK-NEXT:    movzbl %cl, %eax
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    negl %eax
+; CHECK-NEXT:    cmovsl %ecx, %eax
 ; CHECK-NEXT:    cmpl $1, {{.*}}(%rip)
-; CHECK-NEXT:    sbbl %eax, %eax
-; CHECK-NEXT:    andl $1, %eax
+; CHECK-NEXT:    adcl $0, %eax
 ; CHECK-NEXT:    movl %eax, {{.*}}(%rip)
 ; CHECK-NEXT:    retq
   %t0 = load i32, i32* @c, align 4
   %tobool1 = icmp eq i32 %t0, 0
   %xor = zext i1 %tobool1 to i32
   %t1 = load i32, i32* @b, align 4
   %tobool2 = icmp ne i32 %t1, 0
   %t2 = load i32, i32* @d, align 4
   %tobool4 = icmp ne i32 %t2, 0
   %t3 = and i1 %tobool4, %tobool2
   %sub = sext i1 %t3 to i32
   %div = sdiv i32 %sub, 2
   %add = add nsw i32 %div, %xor
   store i32 %add, i32* @d, align 4
   ret void
 }

llvm/test/CodeGen/X86/rem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i386-unknown-unknown | FileCheck %s
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=cmov | FileCheck %s
 
 define i32 @test1(i32 %X) {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; CHECK-NEXT:    movl $-2139062143, %edx # imm = 0x80808081
 ; CHECK-NEXT:    movl %ecx, %eax
 ; CHECK-NEXT:    imull %edx
; CHECK-NEXT:    retl
   %tmp1 = srem i32 %X, 255
   ret i32 %tmp1
 }
 
 define i32 @test2(i32 %X) {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    movl %eax, %ecx
-; CHECK-NEXT:    sarl $31, %ecx
-; CHECK-NEXT:    shrl $24, %ecx
-; CHECK-NEXT:    addl %eax, %ecx
+; CHECK-NEXT:    leal 255(%eax), %ecx
+; CHECK-NEXT:    testl %eax, %eax
+; CHECK-NEXT:    cmovnsl %eax, %ecx
 ; CHECK-NEXT:    andl $-256, %ecx
 ; CHECK-NEXT:    subl %ecx, %eax
 ; CHECK-NEXT:    retl
   %tmp1 = srem i32 %X, 256
   ret i32 %tmp1
 }
 
 define i32 @test3(i32 %X) {

llvm/test/CodeGen/X86/srem-seteq.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=i686-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc -mtriple=i686-unknown-linux-gnu -mattr=cmov < %s | FileCheck %s --check-prefixes=CHECK,X86
 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s --check-prefixes=CHECK,X64
 
 ;------------------------------------------------------------------------------;
 ; Odd divisors
 ;------------------------------------------------------------------------------;
 
 define i32 @test_srem_odd(i32 %X) nounwind {
 ; X86-LABEL: test_srem_odd:
; CHECK-NEXT:    ret{{[l|q]}}
   ret i32 %ret
 }
 
 ; We can lower remainder of division by powers of two much better elsewhere.
 define i32 @test_srem_pow2(i32 %X) nounwind {
 ; X86-LABEL: test_srem_pow2:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT:    movl %ecx, %edx
-; X86-NEXT:    sarl $31, %edx
-; X86-NEXT:    shrl $28, %edx
-; X86-NEXT:    addl %ecx, %edx
+; X86-NEXT:    leal 15(%ecx), %edx
+; X86-NEXT:    testl %ecx, %ecx
+; X86-NEXT:    cmovnsl %ecx, %edx
 ; X86-NEXT:    andl $-16, %edx
 ; X86-NEXT:    xorl %eax, %eax
 ; X86-NEXT:    cmpl %edx, %ecx
 ; X86-NEXT:    sete %al
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: test_srem_pow2:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl %edi, %ecx
-; X64-NEXT:    sarl $31, %ecx
-; X64-NEXT:    shrl $28, %ecx
-; X64-NEXT:    addl %edi, %ecx
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    leal 15(%rdi), %ecx
+; X64-NEXT:    testl %edi, %edi
+; X64-NEXT:    cmovnsl %edi, %ecx
 ; X64-NEXT:    andl $-16, %ecx
 ; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    cmpl %ecx, %edi
 ; X64-NEXT:    sete %al
 ; X64-NEXT:    retq
   %srem = srem i32 %X, 16
   %cmp = icmp eq i32 %srem, 0
   %ret = zext i1 %cmp to i32

llvm/test/CodeGen/X86/twoaddr-coalesce-3.ll

-; RUN: llc < %s -mtriple=x86_64-- -relocation-model=pic | FileCheck %s
+; RUN: llc < %s -mtriple=i386-- -relocation-model=pic | FileCheck %s
 ; This test is to ensure the TwoAddrInstruction pass chooses the proper operands to
 ; merge and generates fewer mov insns.
 
 @M = common global i32 0, align 4
 @total = common global i32 0, align 4
 @g = common global i32 0, align 4
 
 ; Function Attrs: nounwind uwtable