[ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredictable encodings

[MarkMurrayARM]

Summary

Specify the Unpredictable bits, and return softfails when appropriate.

Change-Id: I6831ed815f8e0e386925f1129bc45ffd7ec334b9

[ostannard]

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

6490 ↗

(On Diff #217849)

This case needs a test.

[MarkMurrayARM]

Address review comments from ostannard; add extra test cases.

[ostannard]

LGTM. Do you have commit access, or should I commit this for you?

llvm/lib/Target/ARM/ARMInstrMVE.td

: MVE_ScalarShiftSingleReg<iname, (ins rGPR:$RdaSrc, rGPR:$Rm),
                      "$RdaSrc, $Rm", "$RdaDest = $RdaSrc", pattern> {
   bits<4> Rm;
 
   let Inst{15-12} = Rm{3-0};
   let Inst{11-8} = 0b1111;
   let Inst{7-6} = 0b00;
   let Inst{5-4} = op5_4{1-0};
   let Inst{3-0} = 0b1101;
+
+  let Unpredictable{8-6} = 0b111;
 }
 
 def MVE_SQRSHR : MVE_ScalarShiftSRegReg<"sqrshr", 0b10>;
 def MVE_UQRSHL : MVE_ScalarShiftSRegReg<"uqrshl", 0b00>;
 
 class MVE_ScalarShiftDoubleReg<string iname, dag iops, string asm,
                                string cstr, list<dag> pattern=[]>
   : MVE_ScalarShift<iname, (outs tGPREven:$RdaLo, tGPROdd:$RdaHi),

llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

if (RdaHi == 14) {
     // Rda again as input parameter
     if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
       return MCDisassembler::Fail;
 
     // Rm, the amount to shift by
     if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
       return MCDisassembler::Fail;
 
+    if (fieldFromInstruction (Insn, 6, 3) != 4)
+      return MCDisassembler::SoftFail;
+
+    if (Rda == Rm)
+      return MCDisassembler::SoftFail;
+
     return S;
   }
 
   // Otherwise, we decode as whichever opcode our caller has already
   // put into Inst. Those all look the same:
 
   // RdaLo,RdaHi as output parameters
   if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))

llvm/test/MC/Disassembler/ARM/mve-scalar-shift-unpredictable.txt

+# RUN: llvm-mc -disassemble -triple=thumbv8.1m.main-none-eabi -mattr=+mve -show-encoding %s 2> %t | FileCheck --check-prefix=CHECK %s
+# RUN: FileCheck --check-prefix=STDERR < %t %s
+
+[0x5e 0xea 0x6d 0xcf]
+# CHECK: sqrshr  lr, r12  @ encoding: [0x5e,0xea,0x2d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0xad 0xcf]
+# CHECK: sqrshr  lr, r12  @ encoding: [0x5e,0xea,0x2d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0xed 0xcf]
+# CHECK: sqrshr  lr, r12  @ encoding: [0x5e,0xea,0x2d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0x2d 0xce]
+# CHECK: sqrshr  lr, r12  @ encoding: [0x5e,0xea,0x2d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x51 0xea 0x2d 0x1f]
+# CHECK: sqrshr  r1, r1  @ encoding: [0x51,0xea,0x2d,0x1f]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0x4d 0xcf]
+# CHECK: uqrshl  lr, r12  @ encoding: [0x5e,0xea,0x0d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5b 0xea 0x8d 0xcf]
+# CHECK: uqrshl  r11, r12  @ encoding: [0x5b,0xea,0x0d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5e 0xea 0xcd 0xcf]
+# CHECK: uqrshl  lr, r12  @ encoding: [0x5e,0xea,0x0d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5b 0xea 0x0d 0xce]
+# CHECK: uqrshl  r11, r12  @ encoding: [0x5b,0xea,0x0d,0xcf]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x53 0xea 0x0d 0x3f]
+# CHECK: uqrshl  r3, r3  @ encoding: [0x53,0xea,0x0d,0x3f]
+# STDERR: [[@LINE-2]]:2: warning: potentially undefined instruction encoding