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Differential D66703

[ARM] Ignore Implicit CPSR regs when lowering from Machine to MC operands
ClosedPublic

Authored by dmgreen on Aug 24 2019, 4:16 AM.

Details

Reviewers
efriedma
simon_tatham
rs
t.p.northover
grosbach
samparker
SjoerdMeijer
Commits
rG2f3574c16894: [ARM] Ignore Implicit CPSR regs when lowering from Machine to MC operands
rL370745: [ARM] Ignore Implicit CPSR regs when lowering from Machine to MC operands
Summary

The code here seems to date back to r134705, when tablegen lowering was first being added. I don't believe that we need to include CPSR implicit operands on the MCInst. This now works more like other backends (like AArch64), where all implicit registers are skipped.

This allows the AliasInst for CSEL's to match correctly, as can be seen in the test changes.

Diff Detail

Event Timeline

dmgreen created this revision.Aug 24 2019, 4:16 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 24 2019, 4:16 AM
Herald added subscribers: hiraditya, kristof.beyls, javed.absar. · View Herald Transcript
dmgreen added reviewers: samparker, SjoerdMeijer.Sep 2 2019, 12:00 AM

ping

dmgreen added a parent revision: D66701: [ARM] Invert CSEL predicates if the opposite is a simpler constant to materialise.Sep 2 2019, 12:02 AM
samparker added a comment.Sep 2 2019, 3:26 AM

This makes sense to me, and the verifier is happy! Does this affect how csels are disassembled when using the PC?

dmgreen updated this revision to Diff 218378.Sep 2 2019, 9:41 AM

I don't believe so, if I am understanding the question correctly.

  • The csels will use ZR in the encoding usually meant for PC, so can't use PC directly.
  • The asm/disass don't go through this codepath, which is just for lowering machine->mc (i.e only via codegen)
  • So all the existing disassembly/assembly shouldn't be effected by this as far as I understand (none of the tests are complaining)
  • And none of the codegen tests are failing either, so this doesn't seem to effect the asm output for anything that isn't csel.

We didn't seem to have tests for csel + pc though, so I've added some in the same place we were testing sp.

samparker accepted this revision.Sep 3 2019, 12:11 AM

Ok. LGTM.

This revision is now accepted and ready to land.Sep 3 2019, 12:11 AM
Closed by commit rG2f3574c16894: [ARM] Ignore Implicit CPSR regs when lowering from Machine to MC operands (authored by dmgreen). · Explain WhySep 3 2019, 4:32 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
ARM/
4 lines
test/
CodeGen/
Thumb2/
20 lines
4 lines
16 lines
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336 lines
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44 lines
16 lines
MC/
ARM/
12 lines

Diff 218433

llvm/lib/Target/ARM/ARMMCInstLower.cpp

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
} }
bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO, bool ARMAsmPrinter::lowerOperand(const MachineOperand &MO,
MCOperand &MCOp) { MCOperand &MCOp) {
switch (MO.getType()) { switch (MO.getType()) {
default: llvm_unreachable("unknown operand type"); default: llvm_unreachable("unknown operand type");
case MachineOperand::MO_Register: case MachineOperand::MO_Register:
// Ignore all non-CPSR implicit register operands. // Ignore all implicit register operands.
if (MO.isImplicit() && MO.getReg() != ARM::CPSR) if (MO.isImplicit())
return false; return false;
assert(!MO.getSubReg() && "Subregs should be eliminated!"); assert(!MO.getSubReg() && "Subregs should be eliminated!");
MCOp = MCOperand::createReg(MO.getReg()); MCOp = MCOperand::createReg(MO.getReg());
break; break;
case MachineOperand::MO_Immediate: case MachineOperand::MO_Immediate:
MCOp = MCOperand::createImm(MO.getImm()); MCOp = MCOperand::createImm(MO.getImm());
break; break;
case MachineOperand::MO_MachineBasicBlock: case MachineOperand::MO_MachineBasicBlock:
▲ Show 20 Lines • Show All 146 Lines • Show Last 20 Lines

llvm/test/CodeGen/Thumb2/csel.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi %s -verify-machineinstrs -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi %s -verify-machineinstrs -o - | FileCheck %s
define i32 @csinc_const_65(i32 %a) { define i32 @csinc_const_65(i32 %a) {
; CHECK-LABEL: csinc_const_65: ; CHECK-LABEL: csinc_const_65:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #5 ; CHECK-NEXT: movs r1, #5
; CHECK-NEXT: cmp r0, #45 ; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: csinc r0, r1, r1, le ; CHECK-NEXT: cinc r0, r1, gt
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%cmp = icmp sgt i32 %a, 45 %cmp = icmp sgt i32 %a, 45
%spec.select = select i1 %cmp, i32 6, i32 5 %spec.select = select i1 %cmp, i32 6, i32 5
ret i32 %spec.select ret i32 %spec.select
} }
define i32 @csinc_const_56(i32 %a) { define i32 @csinc_const_56(i32 %a) {
; CHECK-LABEL: csinc_const_56: ; CHECK-LABEL: csinc_const_56:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #5 ; CHECK-NEXT: movs r1, #5
; CHECK-NEXT: cmp r0, #45 ; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: csinc r0, r1, r1, gt ; CHECK-NEXT: cinc r0, r1, le
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%cmp = icmp sgt i32 %a, 45 %cmp = icmp sgt i32 %a, 45
%spec.select = select i1 %cmp, i32 5, i32 6 %spec.select = select i1 %cmp, i32 5, i32 6
ret i32 %spec.select ret i32 %spec.select
} }
define i32 @csinc_const_zext(i32 %a) { define i32 @csinc_const_zext(i32 %a) {
; CHECK-LABEL: csinc_const_zext: ; CHECK-LABEL: csinc_const_zext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45 ; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: csinc r0, zr, zr, le ; CHECK-NEXT: cset r0, gt
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%cmp = icmp sgt i32 %a, 45 %cmp = icmp sgt i32 %a, 45
%spec.select = zext i1 %cmp to i32 %spec.select = zext i1 %cmp to i32
ret i32 %spec.select ret i32 %spec.select
} }
define i32 @csinv_const_56(i32 %a) { define i32 @csinv_const_56(i32 %a) {
; CHECK-LABEL: csinv_const_56: ; CHECK-LABEL: csinv_const_56:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #5 ; CHECK-NEXT: movs r1, #5
; CHECK-NEXT: cmp r0, #45 ; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: csinv r0, r1, r1, le ; CHECK-NEXT: cinv r0, r1, gt
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%cmp = icmp sgt i32 %a, 45 %cmp = icmp sgt i32 %a, 45
%spec.select = select i1 %cmp, i32 -6, i32 5 %spec.select = select i1 %cmp, i32 -6, i32 5
ret i32 %spec.select ret i32 %spec.select
} }
define i32 @csinv_const_65(i32 %a) { define i32 @csinv_const_65(i32 %a) {
; CHECK-LABEL: csinv_const_65: ; CHECK-LABEL: csinv_const_65:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #5 ; CHECK-NEXT: movs r1, #5
; CHECK-NEXT: cmp r0, #45 ; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: csinv r0, r1, r1, gt ; CHECK-NEXT: cinv r0, r1, le
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%cmp = icmp sgt i32 %a, 45 %cmp = icmp sgt i32 %a, 45
%spec.select = select i1 %cmp, i32 5, i32 -6 %spec.select = select i1 %cmp, i32 5, i32 -6
ret i32 %spec.select ret i32 %spec.select
} }
define i32 @csinv_const_sext(i32 %a) { define i32 @csinv_const_sext(i32 %a) {
; CHECK-LABEL: csinv_const_sext: ; CHECK-LABEL: csinv_const_sext:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, #45 ; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: csinv r0, zr, zr, le ; CHECK-NEXT: csetm r0, gt
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%cmp = icmp sgt i32 %a, 45 %cmp = icmp sgt i32 %a, 45
%spec.select = sext i1 %cmp to i32 %spec.select = sext i1 %cmp to i32
ret i32 %spec.select ret i32 %spec.select
} }
define i32 @csneg_const(i32 %a) { define i32 @csneg_const(i32 %a) {
; CHECK-LABEL: csneg_const: ; CHECK-LABEL: csneg_const:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #1 ; CHECK-NEXT: movs r1, #1
; CHECK-NEXT: cmp r0, #45 ; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: csneg r0, r1, r1, gt ; CHECK-NEXT: cneg r0, r1, le
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%cmp = icmp sgt i32 %a, 45 %cmp = icmp sgt i32 %a, 45
%spec.select = select i1 %cmp, i32 1, i32 -1 %spec.select = select i1 %cmp, i32 1, i32 -1
ret i32 %spec.select ret i32 %spec.select
} }
define i32 @csneg_const_r(i32 %a) { define i32 @csneg_const_r(i32 %a) {
; CHECK-LABEL: csneg_const_r: ; CHECK-LABEL: csneg_const_r:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: movs r1, #1 ; CHECK-NEXT: movs r1, #1
; CHECK-NEXT: cmp r0, #45 ; CHECK-NEXT: cmp r0, #45
; CHECK-NEXT: csneg r0, r1, r1, le ; CHECK-NEXT: cneg r0, r1, gt
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%cmp = icmp sgt i32 %a, 45 %cmp = icmp sgt i32 %a, 45
%spec.select = select i1 %cmp, i32 -1, i32 1 %spec.select = select i1 %cmp, i32 -1, i32 1
ret i32 %spec.select ret i32 %spec.select
} }
define i32 @csel_var(i32 %a, i32 %b, i32 %c) { define i32 @csel_var(i32 %a, i32 %b, i32 %c) {
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesentry:
%spec.select = select i1 %cmp, i32 %bneg, i32 %c %spec.select = select i1 %cmp, i32 %bneg, i32 %c
ret i32 %spec.select ret i32 %spec.select
} }
define i32 @csinc_inplace(i32 %a, i32 %b) { define i32 @csinc_inplace(i32 %a, i32 %b) {
; CHECK-LABEL: csinc_inplace: ; CHECK-LABEL: csinc_inplace:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r1, #45 ; CHECK-NEXT: cmp r1, #45
; CHECK-NEXT: csinc r0, r0, r0, le ; CHECK-NEXT: cinc r0, r0, gt
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%cmp = icmp sgt i32 %b, 45 %cmp = icmp sgt i32 %b, 45
%inc = zext i1 %cmp to i32 %inc = zext i1 %cmp to i32
%spec.select = add nsw i32 %inc, %a %spec.select = add nsw i32 %inc, %a
ret i32 %spec.select ret i32 %spec.select
} }
define i32 @csinv_inplace(i32 %a, i32 %b) { define i32 @csinv_inplace(i32 %a, i32 %b) {
; CHECK-LABEL: csinv_inplace: ; CHECK-LABEL: csinv_inplace:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r1, #45 ; CHECK-NEXT: cmp r1, #45
; CHECK-NEXT: csinv r0, r0, r0, le ; CHECK-NEXT: cinv r0, r0, gt
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%cmp = icmp sgt i32 %b, 45 %cmp = icmp sgt i32 %b, 45
%sub = sext i1 %cmp to i32 %sub = sext i1 %cmp to i32
%xor = xor i32 %sub, %a %xor = xor i32 %sub, %a
ret i32 %xor ret i32 %xor
} }

llvm/test/CodeGen/Thumb2/mve-abs.ll

Show First 20 Lines • Show All 43 Lines • ▼ Show 20 Lines
; CHECK-NEXT: push {r7, lr} ; CHECK-NEXT: push {r7, lr}
; CHECK-NEXT: vmov q1, q0 ; CHECK-NEXT: vmov q1, q0
; CHECK-NEXT: mov.w r12, #0 ; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: vmov lr, s4 ; CHECK-NEXT: vmov lr, s4
; CHECK-NEXT: vmov r0, s5 ; CHECK-NEXT: vmov r0, s5
; CHECK-NEXT: rsbs.w r3, lr, #0 ; CHECK-NEXT: rsbs.w r3, lr, #0
; CHECK-NEXT: sbc.w r2, r12, r0 ; CHECK-NEXT: sbc.w r2, r12, r0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinc r1, zr, zr, pl ; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: ands r1, r1, #1 ; CHECK-NEXT: ands r1, r1, #1
; CHECK-NEXT: itt eq ; CHECK-NEXT: itt eq
; CHECK-NEXT: moveq r2, r0 ; CHECK-NEXT: moveq r2, r0
; CHECK-NEXT: moveq r3, lr ; CHECK-NEXT: moveq r3, lr
; CHECK-NEXT: vmov lr, s6 ; CHECK-NEXT: vmov lr, s6
; CHECK-NEXT: vmov.32 q0[0], r3 ; CHECK-NEXT: vmov.32 q0[0], r3
; CHECK-NEXT: vmov r0, s7 ; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: vmov.32 q0[1], r2 ; CHECK-NEXT: vmov.32 q0[1], r2
; CHECK-NEXT: rsbs.w r2, lr, #0 ; CHECK-NEXT: rsbs.w r2, lr, #0
; CHECK-NEXT: sbc.w r3, r12, r0 ; CHECK-NEXT: sbc.w r3, r12, r0
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinc r1, zr, zr, pl ; CHECK-NEXT: cset r1, mi
; CHECK-NEXT: ands r1, r1, #1 ; CHECK-NEXT: ands r1, r1, #1
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: moveq r2, lr ; CHECK-NEXT: moveq r2, lr
; CHECK-NEXT: vmov.32 q0[2], r2 ; CHECK-NEXT: vmov.32 q0[2], r2
; CHECK-NEXT: it eq ; CHECK-NEXT: it eq
; CHECK-NEXT: moveq r3, r0 ; CHECK-NEXT: moveq r3, r0
; CHECK-NEXT: vmov.32 q0[3], r3 ; CHECK-NEXT: vmov.32 q0[3], r3
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
entry: entry:
%0 = icmp slt <2 x i64> %s1, zeroinitializer %0 = icmp slt <2 x i64> %s1, zeroinitializer
%1 = sub nsw <2 x i64> zeroinitializer, %s1 %1 = sub nsw <2 x i64> zeroinitializer, %s1
%2 = select <2 x i1> %0, <2 x i64> %1, <2 x i64> %s1 %2 = select <2 x i1> %0, <2 x i64> %1, <2 x i64> %s1
ret <2 x i64> %2 ret <2 x i64> %2
} }

llvm/test/CodeGen/Thumb2/mve-fmath.ll

Show First 20 Lines • Show All 1,323 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vstr.16 s7, [sp, #4] ; CHECK-NEXT: vstr.16 s7, [sp, #4]
; CHECK-NEXT: vstr.16 s4, [sp] ; CHECK-NEXT: vstr.16 s4, [sp]
; CHECK-NEXT: ldrb.w r0, [sp, #29] ; CHECK-NEXT: ldrb.w r0, [sp, #29]
; CHECK-NEXT: vabs.f16 s4, s0 ; CHECK-NEXT: vabs.f16 s4, s0
; CHECK-NEXT: vneg.f16 s6, s4 ; CHECK-NEXT: vneg.f16 s6, s4
; CHECK-NEXT: ldrb.w r1, [sp, #25] ; CHECK-NEXT: ldrb.w r1, [sp, #25]
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vabs.f16 s8, s1 ; CHECK-NEXT: vabs.f16 s8, s1
; CHECK-NEXT: csinc r0, zr, zr, eq ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: vneg.f16 s10, s8 ; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s4, s4, s6 ; CHECK-NEXT: vseleq.f16 s4, s4, s6
; CHECK-NEXT: tst.w r1, #128 ; CHECK-NEXT: tst.w r1, #128
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: vmovx.f16 s4, s0 ; CHECK-NEXT: vmovx.f16 s4, s0
; CHECK-NEXT: csinc r1, zr, zr, eq ; CHECK-NEXT: cset r1, ne
; CHECK-NEXT: vabs.f16 s4, s4 ; CHECK-NEXT: vabs.f16 s4, s4
; CHECK-NEXT: vneg.f16 s6, s4 ; CHECK-NEXT: vneg.f16 s6, s4
; CHECK-NEXT: lsls r1, r1, #31 ; CHECK-NEXT: lsls r1, r1, #31
; CHECK-NEXT: vseleq.f16 s4, s4, s6 ; CHECK-NEXT: vseleq.f16 s4, s4, s6
; CHECK-NEXT: vmovx.f16 s0, s3 ; CHECK-NEXT: vmovx.f16 s0, s3
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: vmov.16 q1[0], r0 ; CHECK-NEXT: vmov.16 q1[0], r0
; CHECK-NEXT: ldrb.w r0, [sp, #21] ; CHECK-NEXT: ldrb.w r0, [sp, #21]
; CHECK-NEXT: vmov.16 q1[1], r1 ; CHECK-NEXT: vmov.16 q1[1], r1
; CHECK-NEXT: vabs.f16 s0, s0 ; CHECK-NEXT: vabs.f16 s0, s0
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: csinc r0, zr, zr, eq ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10 ; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s1 ; CHECK-NEXT: vmovx.f16 s8, s1
; CHECK-NEXT: vmov.16 q1[2], r0 ; CHECK-NEXT: vmov.16 q1[2], r0
; CHECK-NEXT: ldrb.w r0, [sp, #17] ; CHECK-NEXT: ldrb.w r0, [sp, #17]
; CHECK-NEXT: vabs.f16 s8, s8 ; CHECK-NEXT: vabs.f16 s8, s8
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s10, s8 ; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: csinc r0, zr, zr, eq ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10 ; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vabs.f16 s8, s2 ; CHECK-NEXT: vabs.f16 s8, s2
; CHECK-NEXT: vmov.16 q1[3], r0 ; CHECK-NEXT: vmov.16 q1[3], r0
; CHECK-NEXT: ldrb.w r0, [sp, #13] ; CHECK-NEXT: ldrb.w r0, [sp, #13]
; CHECK-NEXT: vneg.f16 s10, s8 ; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: csinc r0, zr, zr, eq ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10 ; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmovx.f16 s8, s2 ; CHECK-NEXT: vmovx.f16 s8, s2
; CHECK-NEXT: vmov.16 q1[4], r0 ; CHECK-NEXT: vmov.16 q1[4], r0
; CHECK-NEXT: ldrb.w r0, [sp, #9] ; CHECK-NEXT: ldrb.w r0, [sp, #9]
; CHECK-NEXT: vabs.f16 s8, s8 ; CHECK-NEXT: vabs.f16 s8, s8
; CHECK-NEXT: vneg.f16 s2, s0 ; CHECK-NEXT: vneg.f16 s2, s0
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: vneg.f16 s10, s8 ; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: csinc r0, zr, zr, eq ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10 ; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vabs.f16 s8, s3 ; CHECK-NEXT: vabs.f16 s8, s3
; CHECK-NEXT: vmov.16 q1[5], r0 ; CHECK-NEXT: vmov.16 q1[5], r0
; CHECK-NEXT: ldrb.w r0, [sp, #5] ; CHECK-NEXT: ldrb.w r0, [sp, #5]
; CHECK-NEXT: vneg.f16 s10, s8 ; CHECK-NEXT: vneg.f16 s10, s8
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: csinc r0, zr, zr, eq ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s8, s8, s10 ; CHECK-NEXT: vseleq.f16 s8, s8, s10
; CHECK-NEXT: vmov r0, s8 ; CHECK-NEXT: vmov r0, s8
; CHECK-NEXT: vmov.16 q1[6], r0 ; CHECK-NEXT: vmov.16 q1[6], r0
; CHECK-NEXT: ldrb.w r0, [sp, #1] ; CHECK-NEXT: ldrb.w r0, [sp, #1]
; CHECK-NEXT: tst.w r0, #128 ; CHECK-NEXT: tst.w r0, #128
; CHECK-NEXT: csinc r0, zr, zr, eq ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: lsls r0, r0, #31 ; CHECK-NEXT: lsls r0, r0, #31
; CHECK-NEXT: vseleq.f16 s0, s0, s2 ; CHECK-NEXT: vseleq.f16 s0, s0, s2
; CHECK-NEXT: vmov r0, s0 ; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vmov.16 q1[7], r0 ; CHECK-NEXT: vmov.16 q1[7], r0
; CHECK-NEXT: vmov q0, q1 ; CHECK-NEXT: vmov q0, q1
; CHECK-NEXT: add sp, #32 ; CHECK-NEXT: add sp, #32
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
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llvm/test/CodeGen/Thumb2/mve-minmax.ll

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; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: sbcs.w r1, r1, r12 ; CHECK-NEXT: sbcs.w r1, r1, r12
; CHECK-NEXT: vmov r12, s5 ; CHECK-NEXT: vmov r12, s5
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1 ; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csinv r1, zr, zr, eq ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs r2, r3, r2 ; CHECK-NEXT: subs r2, r3, r2
; CHECK-NEXT: sbcs.w r2, lr, r12 ; CHECK-NEXT: sbcs.w r2, lr, r12
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1 ; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q2[2], r1 ; CHECK-NEXT: vmov.32 q2[2], r1
; CHECK-NEXT: vmov.32 q2[3], r1 ; CHECK-NEXT: vmov.32 q2[3], r1
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
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; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: sbcs.w r1, r1, r12 ; CHECK-NEXT: sbcs.w r1, r1, r12
; CHECK-NEXT: vmov r12, s5 ; CHECK-NEXT: vmov r12, s5
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: it lo ; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r1, #1 ; CHECK-NEXT: movlo r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csinv r1, zr, zr, eq ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs r2, r3, r2 ; CHECK-NEXT: subs r2, r3, r2
; CHECK-NEXT: sbcs.w r2, lr, r12 ; CHECK-NEXT: sbcs.w r2, lr, r12
; CHECK-NEXT: it lo ; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1 ; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q2[2], r1 ; CHECK-NEXT: vmov.32 q2[2], r1
; CHECK-NEXT: vmov.32 q2[3], r1 ; CHECK-NEXT: vmov.32 q2[3], r1
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
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; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: sbcs.w r1, r1, r12 ; CHECK-NEXT: sbcs.w r1, r1, r12
; CHECK-NEXT: vmov r12, s1 ; CHECK-NEXT: vmov r12, s1
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1 ; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csinv r1, zr, zr, eq ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs r2, r3, r2 ; CHECK-NEXT: subs r2, r3, r2
; CHECK-NEXT: sbcs.w r2, lr, r12 ; CHECK-NEXT: sbcs.w r2, lr, r12
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1 ; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q2[2], r1 ; CHECK-NEXT: vmov.32 q2[2], r1
; CHECK-NEXT: vmov.32 q2[3], r1 ; CHECK-NEXT: vmov.32 q2[3], r1
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
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; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: sbcs.w r1, r1, r12 ; CHECK-NEXT: sbcs.w r1, r1, r12
; CHECK-NEXT: vmov r12, s1 ; CHECK-NEXT: vmov r12, s1
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: it lo ; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r1, #1 ; CHECK-NEXT: movlo r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csinv r1, zr, zr, eq ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: subs r2, r3, r2 ; CHECK-NEXT: subs r2, r3, r2
; CHECK-NEXT: sbcs.w r2, lr, r12 ; CHECK-NEXT: sbcs.w r2, lr, r12
; CHECK-NEXT: it lo ; CHECK-NEXT: it lo
; CHECK-NEXT: movlo r0, #1 ; CHECK-NEXT: movlo r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov.32 q2[2], r1 ; CHECK-NEXT: vmov.32 q2[2], r1
; CHECK-NEXT: vmov.32 q2[3], r1 ; CHECK-NEXT: vmov.32 q2[3], r1
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: pop {r7, pc} ; CHECK-NEXT: pop {r7, pc}
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; CHECK-NEXT: vmov r2, r3, d11 ; CHECK-NEXT: vmov r2, r3, d11
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: vmov r12, r1, d8 ; CHECK-NEXT: vmov r12, r1, d8
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vmov r2, r3, d10 ; CHECK-NEXT: vmov r2, r3, d10
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1 ; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinv r4, zr, zr, eq ; CHECK-NEXT: csetm r4, ne
; CHECK-NEXT: mov r0, r12 ; CHECK-NEXT: mov r0, r12
; CHECK-NEXT: bl __aeabi_dcmpgt ; CHECK-NEXT: bl __aeabi_dcmpgt
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: movne r0, #1 ; CHECK-NEXT: movne r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q0[0], r0 ; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.32 q0[1], r0 ; CHECK-NEXT: vmov.32 q0[1], r0
; CHECK-NEXT: vmov.32 q0[2], r4 ; CHECK-NEXT: vmov.32 q0[2], r4
; CHECK-NEXT: vmov.32 q0[3], r4 ; CHECK-NEXT: vmov.32 q0[3], r4
; CHECK-NEXT: vbic q1, q5, q0 ; CHECK-NEXT: vbic q1, q5, q0
; CHECK-NEXT: vand q0, q4, q0 ; CHECK-NEXT: vand q0, q4, q0
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
; CHECK-NEXT: pop {r4, pc} ; CHECK-NEXT: pop {r4, pc}
entry: entry:
%cmp = fcmp fast ogt <2 x double> %src2, %src1 %cmp = fcmp fast ogt <2 x double> %src2, %src1
%0 = select <2 x i1> %cmp, <2 x double> %src2, <2 x double> %src1 %0 = select <2 x i1> %cmp, <2 x double> %src2, <2 x double> %src1
ret <2 x double> %0 ret <2 x double> %0
} }

llvm/test/CodeGen/Thumb2/mve-pred-and.ll

Show First 20 Lines • Show All 606 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) { define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: cmpeqz_v2i1: ; CHECK-LABEL: cmpeqz_v2i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vorr q2, q0, q1 ; CHECK-NEXT: vorr q2, q0, q1
; CHECK-NEXT: vmov r0, s9 ; CHECK-NEXT: vmov r0, s9
; CHECK-NEXT: vmov r1, s8 ; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s10 ; CHECK-NEXT: vmov r1, s10
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s11 ; CHECK-NEXT: vmov r0, s11
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q1, q1, q3 ; CHECK-NEXT: vbic q1, q1, q3
; CHECK-NEXT: vand q0, q0, q3 ; CHECK-NEXT: vand q0, q0, q3
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c1 = icmp eq <2 x i64> %a, zeroinitializer %c1 = icmp eq <2 x i64> %a, zeroinitializer
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; CHECK-NEXT: vmov r1, s5 ; CHECK-NEXT: vmov r1, s5
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: eors r0, r1 ; CHECK-NEXT: eors r0, r1
; CHECK-NEXT: vmov r1, s8 ; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s7 ; CHECK-NEXT: vmov r1, s7
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s11 ; CHECK-NEXT: vmov r0, s11
; CHECK-NEXT: eors r0, r1 ; CHECK-NEXT: eors r0, r1
; CHECK-NEXT: vmov r1, s10 ; CHECK-NEXT: vmov r1, s10
; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0 ; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0 ; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vand q2, q2, q3 ; CHECK-NEXT: vand q2, q2, q3
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c1 = icmp eq <2 x i64> %a, zeroinitializer %c1 = icmp eq <2 x i64> %a, zeroinitializer
%c2 = icmp eq <2 x i64> %b, %c %c2 = icmp eq <2 x i64> %b, %c
%o = and <2 x i1> %c1, %c2 %o = and <2 x i1> %c1, %c2
%s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s ret <2 x i64> %s
} }
define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c) { define arm_aapcs_vfpcc <2 x i64> @cmpeqr_v2i1(<2 x i64> %a, <2 x i64> %b, i64 %c) {
; CHECK-LABEL: cmpeqr_v2i1: ; CHECK-LABEL: cmpeqr_v2i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r2, s5 ; CHECK-NEXT: vmov r2, s5
; CHECK-NEXT: vmov r3, s4 ; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: eors r2, r1 ; CHECK-NEXT: eors r2, r1
; CHECK-NEXT: eors r3, r0 ; CHECK-NEXT: eors r3, r0
; CHECK-NEXT: orrs r2, r3 ; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: csinc r2, zr, zr, ne ; CHECK-NEXT: cset r2, eq
; CHECK-NEXT: tst.w r2, #1 ; CHECK-NEXT: tst.w r2, #1
; CHECK-NEXT: csinv r2, zr, zr, eq ; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: vmov.32 q2[0], r2 ; CHECK-NEXT: vmov.32 q2[0], r2
; CHECK-NEXT: vmov.32 q2[1], r2 ; CHECK-NEXT: vmov.32 q2[1], r2
; CHECK-NEXT: vmov r2, s7 ; CHECK-NEXT: vmov r2, s7
; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: eors r0, r2 ; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0 ; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0 ; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vand q2, q3, q2 ; CHECK-NEXT: vand q2, q3, q2
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c1 = icmp eq <2 x i64> %a, zeroinitializer %c1 = icmp eq <2 x i64> %a, zeroinitializer
%i = insertelement <2 x i64> undef, i64 %c, i32 0 %i = insertelement <2 x i64> undef, i64 %c, i32 0
%sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer
%c2 = icmp eq <2 x i64> %b, %sp %c2 = icmp eq <2 x i64> %b, %sp
%o = and <2 x i1> %c1, %c2 %o = and <2 x i1> %c1, %c2
%s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s ret <2 x i64> %s
} }

llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .pad #4 ; CHECK-NEXT: .pad #4
; CHECK-NEXT: sub sp, #4 ; CHECK-NEXT: sub sp, #4
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov r2, s2 ; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s3 ; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: orrs r1, r2 ; CHECK-NEXT: orrs r1, r2
; CHECK-NEXT: csinc r1, zr, zr, ne ; CHECK-NEXT: cset r1, eq
; CHECK-NEXT: ands r1, r1, #1 ; CHECK-NEXT: ands r1, r1, #1
; CHECK-NEXT: it ne ; CHECK-NEXT: it ne
; CHECK-NEXT: mvnne r1, #1 ; CHECK-NEXT: mvnne r1, #1
; CHECK-NEXT: bfi r1, r0, #0, #1 ; CHECK-NEXT: bfi r1, r0, #0, #1
; CHECK-NEXT: and r0, r1, #3 ; CHECK-NEXT: and r0, r1, #3
; CHECK-NEXT: add sp, #4 ; CHECK-NEXT: add sp, #4
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <2 x i64> %a, zeroinitializer %c = icmp eq <2 x i64> %a, zeroinitializer
%b = bitcast <2 x i1> %c to i2 %b = bitcast <2 x i1> %c to i2
ret i2 %b ret i2 %b
} }

llvm/test/CodeGen/Thumb2/mve-pred-build-var.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
define arm_aapcs_vfpcc <4 x i32> @build_var0_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) { define arm_aapcs_vfpcc <4 x i32> @build_var0_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: build_var0_v4i1: ; CHECK-LABEL: build_var0_v4i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #4 ; CHECK-NEXT: bfi r1, r0, #0, #4
; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp ult i32 %s, %t %c = icmp ult i32 %s, %t
%vc = insertelement <4 x i1> zeroinitializer, i1 %c, i64 0 %vc = insertelement <4 x i1> zeroinitializer, i1 %c, i64 0
%r = select <4 x i1> %vc, <4 x i32> %a, <4 x i32> %b %r = select <4 x i1> %vc, <4 x i32> %a, <4 x i32> %b
ret <4 x i32> %r ret <4 x i32> %r
} }
define arm_aapcs_vfpcc <4 x i32> @build_var3_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) { define arm_aapcs_vfpcc <4 x i32> @build_var3_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: build_var3_v4i1: ; CHECK-LABEL: build_var3_v4i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #12, #4 ; CHECK-NEXT: bfi r1, r0, #12, #4
; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp ult i32 %s, %t %c = icmp ult i32 %s, %t
%vc = insertelement <4 x i1> zeroinitializer, i1 %c, i64 3 %vc = insertelement <4 x i1> zeroinitializer, i1 %c, i64 3
%r = select <4 x i1> %vc, <4 x i32> %a, <4 x i32> %b %r = select <4 x i1> %vc, <4 x i32> %a, <4 x i32> %b
ret <4 x i32> %r ret <4 x i32> %r
} }
define arm_aapcs_vfpcc <4 x i32> @build_varN_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) { define arm_aapcs_vfpcc <4 x i32> @build_varN_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: build_varN_v4i1: ; CHECK-LABEL: build_varN_v4i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #4 ; CHECK-NEXT: bfi r1, r0, #0, #4
; CHECK-NEXT: bfi r1, r0, #4, #4 ; CHECK-NEXT: bfi r1, r0, #4, #4
; CHECK-NEXT: bfi r1, r0, #8, #4 ; CHECK-NEXT: bfi r1, r0, #8, #4
; CHECK-NEXT: bfi r1, r0, #12, #4 ; CHECK-NEXT: bfi r1, r0, #12, #4
; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp ult i32 %s, %t %c = icmp ult i32 %s, %t
%vc1 = insertelement <4 x i1> undef, i1 %c, i64 0 %vc1 = insertelement <4 x i1> undef, i1 %c, i64 0
%vc4 = shufflevector <4 x i1> %vc1, <4 x i1> undef, <4 x i32> zeroinitializer %vc4 = shufflevector <4 x i1> %vc1, <4 x i1> undef, <4 x i32> zeroinitializer
%r = select <4 x i1> %vc4, <4 x i32> %a, <4 x i32> %b %r = select <4 x i1> %vc4, <4 x i32> %a, <4 x i32> %b
ret <4 x i32> %r ret <4 x i32> %r
} }
define arm_aapcs_vfpcc <8 x i16> @build_var0_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) { define arm_aapcs_vfpcc <8 x i16> @build_var0_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: build_var0_v8i1: ; CHECK-LABEL: build_var0_v8i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #2 ; CHECK-NEXT: bfi r1, r0, #0, #2
; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp ult i32 %s, %t %c = icmp ult i32 %s, %t
%vc = insertelement <8 x i1> zeroinitializer, i1 %c, i64 0 %vc = insertelement <8 x i1> zeroinitializer, i1 %c, i64 0
%r = select <8 x i1> %vc, <8 x i16> %a, <8 x i16> %b %r = select <8 x i1> %vc, <8 x i16> %a, <8 x i16> %b
ret <8 x i16> %r ret <8 x i16> %r
} }
define arm_aapcs_vfpcc <8 x i16> @build_var3_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) { define arm_aapcs_vfpcc <8 x i16> @build_var3_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: build_var3_v8i1: ; CHECK-LABEL: build_var3_v8i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #6, #2 ; CHECK-NEXT: bfi r1, r0, #6, #2
; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp ult i32 %s, %t %c = icmp ult i32 %s, %t
%vc = insertelement <8 x i1> zeroinitializer, i1 %c, i64 3 %vc = insertelement <8 x i1> zeroinitializer, i1 %c, i64 3
%r = select <8 x i1> %vc, <8 x i16> %a, <8 x i16> %b %r = select <8 x i1> %vc, <8 x i16> %a, <8 x i16> %b
ret <8 x i16> %r ret <8 x i16> %r
} }
define arm_aapcs_vfpcc <8 x i16> @build_varN_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) { define arm_aapcs_vfpcc <8 x i16> @build_varN_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: build_varN_v8i1: ; CHECK-LABEL: build_varN_v8i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #2 ; CHECK-NEXT: bfi r1, r0, #0, #2
; CHECK-NEXT: bfi r1, r0, #2, #2 ; CHECK-NEXT: bfi r1, r0, #2, #2
; CHECK-NEXT: bfi r1, r0, #4, #2 ; CHECK-NEXT: bfi r1, r0, #4, #2
; CHECK-NEXT: bfi r1, r0, #6, #2 ; CHECK-NEXT: bfi r1, r0, #6, #2
; CHECK-NEXT: bfi r1, r0, #8, #2 ; CHECK-NEXT: bfi r1, r0, #8, #2
; CHECK-NEXT: bfi r1, r0, #10, #2 ; CHECK-NEXT: bfi r1, r0, #10, #2
Show All 11 Lines
} }
define arm_aapcs_vfpcc <16 x i8> @build_var0_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) { define arm_aapcs_vfpcc <16 x i8> @build_var0_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: build_var0_v16i1: ; CHECK-LABEL: build_var0_v16i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #1 ; CHECK-NEXT: bfi r1, r0, #0, #1
; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp ult i32 %s, %t %c = icmp ult i32 %s, %t
%vc = insertelement <16 x i1> zeroinitializer, i1 %c, i64 0 %vc = insertelement <16 x i1> zeroinitializer, i1 %c, i64 0
%r = select <16 x i1> %vc, <16 x i8> %a, <16 x i8> %b %r = select <16 x i1> %vc, <16 x i8> %a, <16 x i8> %b
ret <16 x i8> %r ret <16 x i8> %r
} }
define arm_aapcs_vfpcc <16 x i8> @build_var3_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) { define arm_aapcs_vfpcc <16 x i8> @build_var3_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: build_var3_v16i1: ; CHECK-LABEL: build_var3_v16i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #3, #1 ; CHECK-NEXT: bfi r1, r0, #3, #1
; CHECK-NEXT: vmsr p0, r1 ; CHECK-NEXT: vmsr p0, r1
; CHECK-NEXT: vpsel q0, q0, q1 ; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp ult i32 %s, %t %c = icmp ult i32 %s, %t
%vc = insertelement <16 x i1> zeroinitializer, i1 %c, i64 3 %vc = insertelement <16 x i1> zeroinitializer, i1 %c, i64 3
%r = select <16 x i1> %vc, <16 x i8> %a, <16 x i8> %b %r = select <16 x i1> %vc, <16 x i8> %a, <16 x i8> %b
ret <16 x i8> %r ret <16 x i8> %r
} }
define arm_aapcs_vfpcc <16 x i8> @build_varN_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) { define arm_aapcs_vfpcc <16 x i8> @build_varN_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: build_varN_v16i1: ; CHECK-LABEL: build_varN_v16i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: csinc r0, zr, zr, hs ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: bfi r1, r0, #0, #1 ; CHECK-NEXT: bfi r1, r0, #0, #1
; CHECK-NEXT: bfi r1, r0, #1, #1 ; CHECK-NEXT: bfi r1, r0, #1, #1
; CHECK-NEXT: bfi r1, r0, #2, #1 ; CHECK-NEXT: bfi r1, r0, #2, #1
; CHECK-NEXT: bfi r1, r0, #3, #1 ; CHECK-NEXT: bfi r1, r0, #3, #1
; CHECK-NEXT: bfi r1, r0, #4, #1 ; CHECK-NEXT: bfi r1, r0, #4, #1
; CHECK-NEXT: bfi r1, r0, #5, #1 ; CHECK-NEXT: bfi r1, r0, #5, #1
Show All 18 Linesentry:
ret <16 x i8> %r ret <16 x i8> %r
} }
define arm_aapcs_vfpcc <2 x i64> @build_var0_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) { define arm_aapcs_vfpcc <2 x i64> @build_var0_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: build_var0_v2i1: ; CHECK-LABEL: build_var0_v2i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: csinc r0, zr, zr, hs ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmov s8, r0 ; CHECK-NEXT: vmov s8, r0
; CHECK-NEXT: vldr s10, .LCPI9_0 ; CHECK-NEXT: vldr s10, .LCPI9_0
; CHECK-NEXT: vmov.f32 s9, s8 ; CHECK-NEXT: vmov.f32 s9, s8
; CHECK-NEXT: vmov.f32 s11, s10 ; CHECK-NEXT: vmov.f32 s11, s10
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
Show All 9 Linesentry:
%r = select <2 x i1> %vc, <2 x i64> %a, <2 x i64> %b %r = select <2 x i1> %vc, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %r ret <2 x i64> %r
} }
define arm_aapcs_vfpcc <2 x i64> @build_var1_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) { define arm_aapcs_vfpcc <2 x i64> @build_var1_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: build_var1_v2i1: ; CHECK-LABEL: build_var1_v2i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: csinc r0, zr, zr, hs ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vmov s10, r0 ; CHECK-NEXT: vmov s10, r0
; CHECK-NEXT: vldr s8, .LCPI10_0 ; CHECK-NEXT: vldr s8, .LCPI10_0
; CHECK-NEXT: vmov.f32 s9, s8 ; CHECK-NEXT: vmov.f32 s9, s8
; CHECK-NEXT: vmov.f32 s11, s10 ; CHECK-NEXT: vmov.f32 s11, s10
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
Show All 9 Linesentry:
%r = select <2 x i1> %vc, <2 x i64> %a, <2 x i64> %b %r = select <2 x i1> %vc, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %r ret <2 x i64> %r
} }
define arm_aapcs_vfpcc <2 x i64> @build_varN_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) { define arm_aapcs_vfpcc <2 x i64> @build_varN_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: build_varN_v2i1: ; CHECK-LABEL: build_varN_v2i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: cmp r0, r1 ; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: csinc r0, zr, zr, hs ; CHECK-NEXT: cset r0, lo
; CHECK-NEXT: and r0, r0, #1 ; CHECK-NEXT: and r0, r0, #1
; CHECK-NEXT: rsbs r0, r0, #0 ; CHECK-NEXT: rsbs r0, r0, #0
; CHECK-NEXT: vdup.32 q2, r0 ; CHECK-NEXT: vdup.32 q2, r0
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp ult i32 %s, %t %c = icmp ult i32 %s, %t
%vc1 = insertelement <2 x i1> undef, i1 %c, i64 0 %vc1 = insertelement <2 x i1> undef, i1 %c, i64 0
%vc4 = shufflevector <2 x i1> %vc1, <2 x i1> undef, <2 x i32> zeroinitializer %vc4 = shufflevector <2 x i1> %vc1, <2 x i1> undef, <2 x i32> zeroinitializer
%r = select <2 x i1> %vc4, <2 x i64> %a, <2 x i64> %b %r = select <2 x i1> %vc4, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %r ret <2 x i64> %r
} }

llvm/test/CodeGen/Thumb2/mve-pred-ext.ll

Show First 20 Lines • Show All 51 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: rsbs r1, r1, #0 ; CHECK-NEXT: rsbs r1, r1, #0
; CHECK-NEXT: vmov r1, s1 ; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: sbcs.w r0, r2, r0 ; CHECK-NEXT: sbcs.w r0, r2, r0
; CHECK-NEXT: mov.w r0, #0 ; CHECK-NEXT: mov.w r0, #0
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1 ; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: rsbs r3, r3, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: sbcs.w r1, r2, r1 ; CHECK-NEXT: sbcs.w r1, r2, r1
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r2, #1 ; CHECK-NEXT: movlt r2, #1
; CHECK-NEXT: cmp r2, #0 ; CHECK-NEXT: cmp r2, #0
; CHECK-NEXT: csinv r1, zr, zr, eq ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov.32 q0[0], r1 ; CHECK-NEXT: vmov.32 q0[0], r1
; CHECK-NEXT: vmov.32 q0[1], r1 ; CHECK-NEXT: vmov.32 q0[1], r1
; CHECK-NEXT: vmov.32 q0[2], r0 ; CHECK-NEXT: vmov.32 q0[2], r0
; CHECK-NEXT: vmov.32 q0[3], r0 ; CHECK-NEXT: vmov.32 q0[3], r0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp sgt <2 x i64> %src, zeroinitializer %c = icmp sgt <2 x i64> %src, zeroinitializer
%0 = sext <2 x i1> %c to <2 x i64> %0 = sext <2 x i1> %c to <2 x i64>
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; CHECK-NEXT: movs r0, #0 ; CHECK-NEXT: movs r0, #0
; CHECK-NEXT: rsbs r2, r2, #0 ; CHECK-NEXT: rsbs r2, r2, #0
; CHECK-NEXT: vmov r2, s1 ; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: sbcs.w r1, r0, r1 ; CHECK-NEXT: sbcs.w r1, r0, r1
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1 ; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csinv r1, zr, zr, eq ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: rsbs r3, r3, #0 ; CHECK-NEXT: rsbs r3, r3, #0
; CHECK-NEXT: sbcs.w r2, r0, r2 ; CHECK-NEXT: sbcs.w r2, r0, r2
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r0, #1 ; CHECK-NEXT: movlt r0, #1
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q0[0], r0 ; CHECK-NEXT: vmov.32 q0[0], r0
; CHECK-NEXT: vmov.32 q0[2], r1 ; CHECK-NEXT: vmov.32 q0[2], r1
; CHECK-NEXT: vand q0, q0, q1 ; CHECK-NEXT: vand q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 4 ; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1: ; CHECK-NEXT: @ %bb.1:
; CHECK-NEXT: .LCPI7_0: ; CHECK-NEXT: .LCPI7_0:
; CHECK-NEXT: .long 1 @ 0x1 ; CHECK-NEXT: .long 1 @ 0x1
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llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll

Show First 20 Lines • Show All 161 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc void @store_v2i1(<2 x i1> *%dst, <2 x i64> %a) { define arm_aapcs_vfpcc void @store_v2i1(<2 x i1> *%dst, <2 x i64> %a) {
; CHECK-LE-LABEL: store_v2i1: ; CHECK-LE-LABEL: store_v2i1:
; CHECK-LE: @ %bb.0: @ %entry ; CHECK-LE: @ %bb.0: @ %entry
; CHECK-LE-NEXT: vmov r1, s1 ; CHECK-LE-NEXT: vmov r1, s1
; CHECK-LE-NEXT: vmov r2, s0 ; CHECK-LE-NEXT: vmov r2, s0
; CHECK-LE-NEXT: vmov r3, s2 ; CHECK-LE-NEXT: vmov r3, s2
; CHECK-LE-NEXT: orrs r1, r2 ; CHECK-LE-NEXT: orrs r1, r2
; CHECK-LE-NEXT: vmov r2, s3 ; CHECK-LE-NEXT: vmov r2, s3
; CHECK-LE-NEXT: csinc r1, zr, zr, ne ; CHECK-LE-NEXT: cset r1, eq
; CHECK-LE-NEXT: orrs r2, r3 ; CHECK-LE-NEXT: orrs r2, r3
; CHECK-LE-NEXT: csinc r2, zr, zr, ne ; CHECK-LE-NEXT: cset r2, eq
; CHECK-LE-NEXT: ands r2, r2, #1 ; CHECK-LE-NEXT: ands r2, r2, #1
; CHECK-LE-NEXT: it ne ; CHECK-LE-NEXT: it ne
; CHECK-LE-NEXT: mvnne r2, #1 ; CHECK-LE-NEXT: mvnne r2, #1
; CHECK-LE-NEXT: bfi r2, r1, #0, #1 ; CHECK-LE-NEXT: bfi r2, r1, #0, #1
; CHECK-LE-NEXT: and r1, r2, #3 ; CHECK-LE-NEXT: and r1, r2, #3
; CHECK-LE-NEXT: strb r1, [r0] ; CHECK-LE-NEXT: strb r1, [r0]
; CHECK-LE-NEXT: bx lr ; CHECK-LE-NEXT: bx lr
; ;
; CHECK-BE-LABEL: store_v2i1: ; CHECK-BE-LABEL: store_v2i1:
; CHECK-BE: @ %bb.0: @ %entry ; CHECK-BE: @ %bb.0: @ %entry
; CHECK-BE-NEXT: vrev64.32 q1, q0 ; CHECK-BE-NEXT: vrev64.32 q1, q0
; CHECK-BE-NEXT: vmov r1, s6 ; CHECK-BE-NEXT: vmov r1, s6
; CHECK-BE-NEXT: vmov r2, s7 ; CHECK-BE-NEXT: vmov r2, s7
; CHECK-BE-NEXT: vmov r3, s5 ; CHECK-BE-NEXT: vmov r3, s5
; CHECK-BE-NEXT: orrs r1, r2 ; CHECK-BE-NEXT: orrs r1, r2
; CHECK-BE-NEXT: vmov r2, s4 ; CHECK-BE-NEXT: vmov r2, s4
; CHECK-BE-NEXT: csinc r1, zr, zr, ne ; CHECK-BE-NEXT: cset r1, eq
; CHECK-BE-NEXT: orrs r2, r3 ; CHECK-BE-NEXT: orrs r2, r3
; CHECK-BE-NEXT: csinc r2, zr, zr, ne ; CHECK-BE-NEXT: cset r2, eq
; CHECK-BE-NEXT: ands r2, r2, #1 ; CHECK-BE-NEXT: ands r2, r2, #1
; CHECK-BE-NEXT: it ne ; CHECK-BE-NEXT: it ne
; CHECK-BE-NEXT: mvnne r2, #1 ; CHECK-BE-NEXT: mvnne r2, #1
; CHECK-BE-NEXT: bfi r2, r1, #0, #1 ; CHECK-BE-NEXT: bfi r2, r1, #0, #1
; CHECK-BE-NEXT: and r1, r2, #3 ; CHECK-BE-NEXT: and r1, r2, #3
; CHECK-BE-NEXT: strb r1, [r0] ; CHECK-BE-NEXT: strb r1, [r0]
; CHECK-BE-NEXT: bx lr ; CHECK-BE-NEXT: bx lr
entry: entry:
%c = icmp eq <2 x i64> %a, zeroinitializer %c = icmp eq <2 x i64> %a, zeroinitializer
store <2 x i1> %c, <2 x i1>* %dst store <2 x i1> %c, <2 x i1>* %dst
ret void ret void
} }

llvm/test/CodeGen/Thumb2/mve-pred-not.ll

Show First 20 Lines • Show All 321 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) { define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: cmpeqz_v2i1: ; CHECK-LABEL: cmpeqz_v2i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0 ; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0 ; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vbic q0, q0, q2 ; CHECK-NEXT: vbic q0, q0, q2
; CHECK-NEXT: vand q1, q1, q2 ; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c1 = icmp eq <2 x i64> %a, zeroinitializer %c1 = icmp eq <2 x i64> %a, zeroinitializer
%o = xor <2 x i1> %c1, <i1 -1, i1 -1> %o = xor <2 x i1> %c1, <i1 -1, i1 -1>
%s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s ret <2 x i64> %s
} }
define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) { define arm_aapcs_vfpcc <2 x i64> @cmpeq_v2i1(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) {
; CHECK-LABEL: cmpeq_v2i1: ; CHECK-LABEL: cmpeq_v2i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0 ; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0 ; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vbic q0, q0, q2 ; CHECK-NEXT: vbic q0, q0, q2
; CHECK-NEXT: vand q1, q1, q2 ; CHECK-NEXT: vand q1, q1, q2
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c1 = icmp eq <2 x i64> %a, zeroinitializer %c1 = icmp eq <2 x i64> %a, zeroinitializer
Show All 26 Lines

llvm/test/CodeGen/Thumb2/mve-pred-or.ll

Show First 20 Lines • Show All 419 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) { define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: cmpeqz_v2i1: ; CHECK-LABEL: cmpeqz_v2i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, s5 ; CHECK-NEXT: vmov r0, s5
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s6 ; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s7 ; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0 ; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0 ; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vorr q2, q3, q2 ; CHECK-NEXT: vorr q2, q3, q2
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
Show All 11 Lines
; CHECK-NEXT: vmov r1, s5 ; CHECK-NEXT: vmov r1, s5
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: eors r0, r1 ; CHECK-NEXT: eors r0, r1
; CHECK-NEXT: vmov r1, s8 ; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s7 ; CHECK-NEXT: vmov r1, s7
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s11 ; CHECK-NEXT: vmov r0, s11
; CHECK-NEXT: eors r0, r1 ; CHECK-NEXT: eors r0, r1
; CHECK-NEXT: vmov r1, s10 ; CHECK-NEXT: vmov r1, s10
; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0 ; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0 ; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vorr q2, q2, q3 ; CHECK-NEXT: vorr q2, q2, q3
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c1 = icmp eq <2 x i64> %a, zeroinitializer %c1 = icmp eq <2 x i64> %a, zeroinitializer
%c2 = icmp eq <2 x i64> %b, %c %c2 = icmp eq <2 x i64> %b, %c
%o = or <2 x i1> %c1, %c2 %o = or <2 x i1> %c1, %c2
%s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s ret <2 x i64> %s
} }

llvm/test/CodeGen/Thumb2/mve-pred-xor.ll

Show First 20 Lines • Show All 455 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) { define arm_aapcs_vfpcc <2 x i64> @cmpeqz_v2i1(<2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: cmpeqz_v2i1: ; CHECK-LABEL: cmpeqz_v2i1:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, s5 ; CHECK-NEXT: vmov r0, s5
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s6 ; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s7 ; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0 ; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0 ; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: veor q2, q3, q2 ; CHECK-NEXT: veor q2, q3, q2
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
Show All 11 Lines
; CHECK-NEXT: vmov r1, s5 ; CHECK-NEXT: vmov r1, s5
; CHECK-NEXT: vmov r2, s4 ; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: eors r0, r1 ; CHECK-NEXT: eors r0, r1
; CHECK-NEXT: vmov r1, s8 ; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: vmov r2, s6 ; CHECK-NEXT: vmov r2, s6
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s7 ; CHECK-NEXT: vmov r1, s7
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s11 ; CHECK-NEXT: vmov r0, s11
; CHECK-NEXT: eors r0, r1 ; CHECK-NEXT: eors r0, r1
; CHECK-NEXT: vmov r1, s10 ; CHECK-NEXT: vmov r1, s10
; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[0], r0 ; CHECK-NEXT: vmov.32 q2[0], r0
; CHECK-NEXT: vmov.32 q2[1], r0 ; CHECK-NEXT: vmov.32 q2[1], r0
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q2[2], r0 ; CHECK-NEXT: vmov.32 q2[2], r0
; CHECK-NEXT: vmov.32 q2[3], r0 ; CHECK-NEXT: vmov.32 q2[3], r0
; CHECK-NEXT: veor q2, q2, q3 ; CHECK-NEXT: veor q2, q2, q3
; CHECK-NEXT: vbic q1, q1, q2 ; CHECK-NEXT: vbic q1, q1, q2
; CHECK-NEXT: vand q0, q0, q2 ; CHECK-NEXT: vand q0, q0, q2
; CHECK-NEXT: vorr q0, q0, q1 ; CHECK-NEXT: vorr q0, q0, q1
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c1 = icmp eq <2 x i64> %a, zeroinitializer %c1 = icmp eq <2 x i64> %a, zeroinitializer
%c2 = icmp eq <2 x i64> %b, %c %c2 = icmp eq <2 x i64> %b, %c
%o = xor <2 x i1> %c1, %c2 %o = xor <2 x i1> %c1, %c2
%s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b %s = select <2 x i1> %o, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s ret <2 x i64> %s
} }

llvm/test/CodeGen/Thumb2/mve-vcmp.ll

Show First 20 Lines • Show All 372 Lines • ▼ Show 20 Lines
; CHECK-NEXT: vmov r1, s1 ; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: eors r0, r1 ; CHECK-NEXT: eors r0, r1
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: vmov r2, s2 ; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s3 ; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q4[0], r0 ; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.32 q4[1], r0 ; CHECK-NEXT: vmov.32 q4[1], r0
; CHECK-NEXT: vmov r0, s7 ; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: eors r0, r1 ; CHECK-NEXT: eors r0, r1
; CHECK-NEXT: vmov r1, s6 ; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q4[2], r0 ; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.32 q4[3], r0 ; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vbic q0, q3, q4 ; CHECK-NEXT: vbic q0, q3, q4
; CHECK-NEXT: vand q1, q2, q4 ; CHECK-NEXT: vand q1, q2, q4
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
Show All 11 Lines
; CHECK-NEXT: vmov r1, s1 ; CHECK-NEXT: vmov r1, s1
; CHECK-NEXT: vmov r2, s0 ; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: eors r0, r1 ; CHECK-NEXT: eors r0, r1
; CHECK-NEXT: vmov r1, s4 ; CHECK-NEXT: vmov r1, s4
; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: vmov r2, s2 ; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s3 ; CHECK-NEXT: vmov r1, s3
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q4[0], r0 ; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.32 q4[1], r0 ; CHECK-NEXT: vmov.32 q4[1], r0
; CHECK-NEXT: vmov r0, s7 ; CHECK-NEXT: vmov r0, s7
; CHECK-NEXT: eors r0, r1 ; CHECK-NEXT: eors r0, r1
; CHECK-NEXT: vmov r1, s6 ; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q4[2], r0 ; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.32 q4[3], r0 ; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vbic q0, q3, q4 ; CHECK-NEXT: vbic q0, q3, q4
; CHECK-NEXT: vand q1, q2, q4 ; CHECK-NEXT: vand q1, q2, q4
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: vpop {d8, d9} ; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
Show All 10 Lines
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov r2, s8 ; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3 ; CHECK-NEXT: vbic q0, q2, q3
; CHECK-NEXT: vmov lr, s0 ; CHECK-NEXT: vmov lr, s0
; CHECK-NEXT: subs.w r1, lr, r2 ; CHECK-NEXT: subs.w r1, lr, r2
; CHECK-NEXT: asr.w r12, lr, #31 ; CHECK-NEXT: asr.w r12, lr, #31
; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31 ; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: vmov r2, s10 ; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1 ; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csinv r1, zr, zr, eq ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov.32 q3[0], r1 ; CHECK-NEXT: vmov.32 q3[0], r1
; CHECK-NEXT: vmov.32 q3[1], r1 ; CHECK-NEXT: vmov.32 q3[1], r1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: subs r0, r1, r2 ; CHECK-NEXT: subs r0, r1, r2
; CHECK-NEXT: asr.w r12, r1, #31 ; CHECK-NEXT: asr.w r12, r1, #31
; CHECK-NEXT: sbcs.w r0, r12, r2, asr #31 ; CHECK-NEXT: sbcs.w r0, r12, r2, asr #31
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1 ; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp.w lr, #0 ; CHECK-NEXT: cmp.w lr, #0
; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: csinc r0, zr, zr, eq ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: vmov.32 q4[0], r0 ; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.32 q4[1], r0 ; CHECK-NEXT: vmov.32 q4[1], r0
; CHECK-NEXT: csinc r0, zr, zr, eq ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q4[2], r0 ; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.32 q4[3], r0 ; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinc r0, zr, zr, eq ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q5[0], r0 ; CHECK-NEXT: vmov.32 q5[0], r0
; CHECK-NEXT: vmov.32 q5[1], r0 ; CHECK-NEXT: vmov.32 q5[1], r0
; CHECK-NEXT: vmov r0, s6 ; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinc r0, zr, zr, eq ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q5[2], r0 ; CHECK-NEXT: vmov.32 q5[2], r0
; CHECK-NEXT: vmov.32 q5[3], r0 ; CHECK-NEXT: vmov.32 q5[3], r0
; CHECK-NEXT: vand q1, q5, q4 ; CHECK-NEXT: vand q1, q5, q4
; CHECK-NEXT: vand q1, q3, q1 ; CHECK-NEXT: vand q1, q3, q1
; CHECK-NEXT: vbic q0, q0, q1 ; CHECK-NEXT: vbic q0, q0, q1
; CHECK-NEXT: vand q1, q2, q1 ; CHECK-NEXT: vand q1, q2, q1
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
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llvm/test/CodeGen/Thumb2/mve-vcmpf.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v4f32: ; CHECK-MVE-LABEL: vcmp_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1 ; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 20 Lines
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1 ; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 18 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 15 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1 ; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r3, #1 ; CHECK-MVE-NEXT: movge r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 15 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1 ; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 15 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1 ; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r3, #1 ; CHECK-MVE-NEXT: movls r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 20 Lines
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1 ; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 17 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, s5 ; CHECK-MVE-NEXT: vcmp.f32 s1, s5
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s6 ; CHECK-MVE-NEXT: vcmp.f32 s2, s6
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s7 ; CHECK-MVE-NEXT: vcmp.f32 s3, s7
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r3, #1 ; CHECK-MVE-NEXT: movne r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 15 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1 ; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r3, #1 ; CHECK-MVE-NEXT: movhi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 16 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1 ; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r3, #1 ; CHECK-MVE-NEXT: movpl r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 16 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1 ; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r3, #1 ; CHECK-MVE-NEXT: movlt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 16 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1 ; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r3, #1 ; CHECK-MVE-NEXT: movle r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 16 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1 ; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r3, #1 ; CHECK-MVE-NEXT: movvc r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 18 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s5
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s6
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s7
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 23 Lines
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16 ; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2 ; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1 ; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vmovx.f16 s2, s15
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.16 q4[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
Show All 20 Lines
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16 ; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2 ; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1 ; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vmovx.f16 s2, s15
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.16 q4[4], r1
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
Show All 21 Lines
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16 ; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2 ; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1 ; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vmovx.f16 s2, s15
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.16 q4[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
Show All 19 Lines
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1 ; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16 ; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2 ; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1 ; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vmovx.f16 s2, s15
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.16 q4[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
Show All 19 Lines
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16 ; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2 ; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1 ; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vmovx.f16 s2, s15
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.16 q4[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
Show All 19 Lines
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1 ; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16 ; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2 ; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1 ; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vmovx.f16 s2, s15
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.16 q4[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
Show All 20 Lines
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16 ; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2 ; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1 ; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vmovx.f16 s2, s15
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.16 q4[4], r1
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
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; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s5 ; CHECK-MVE-NEXT: vcmp.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16 ; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2 ; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1 ; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s2, s6 ; CHECK-MVE-NEXT: vcmp.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vmovx.f16 s2, s15
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmp.f16 s22, s20 ; CHECK-MVE-NEXT: vcmp.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.16 q4[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmp.f16 s3, s7 ; CHECK-MVE-NEXT: vcmp.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s4 ; CHECK-MVE-NEXT: vcmp.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
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; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1 ; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16 ; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2 ; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1 ; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vmovx.f16 s2, s15
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.16 q4[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
Show All 20 Lines
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1 ; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16 ; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2 ; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1 ; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vmovx.f16 s2, s15
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.16 q4[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
Show All 20 Lines
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1 ; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16 ; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2 ; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1 ; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vmovx.f16 s2, s15
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.16 q4[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
Show All 20 Lines
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1 ; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16 ; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2 ; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1 ; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vmovx.f16 s2, s15
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.16 q4[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
Show All 20 Lines
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1 ; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16 ; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2 ; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1 ; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vmovx.f16 s2, s15
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.16 q4[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
Show All 22 Lines
; CHECK-MVE-NEXT: vmovx.f16 s18, s0 ; CHECK-MVE-NEXT: vmovx.f16 s18, s0
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s8 ; CHECK-MVE-NEXT: vmovx.f16 s16, s8
; CHECK-MVE-NEXT: vmovx.f16 s18, s12 ; CHECK-MVE-NEXT: vmovx.f16 s18, s12
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmpe.f16 s1, s5 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s5
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s22, s1 ; CHECK-MVE-NEXT: vmovx.f16 s22, s1
; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8 ; CHECK-MVE-NEXT: vseleq.f16 s16, s12, s8
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s16 ; CHECK-MVE-NEXT: vmov r2, s16
; CHECK-MVE-NEXT: vmovx.f16 s4, s7 ; CHECK-MVE-NEXT: vmovx.f16 s4, s7
; CHECK-MVE-NEXT: vmov.16 q4[0], r2 ; CHECK-MVE-NEXT: vmov.16 q4[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q4[1], r1 ; CHECK-MVE-NEXT: vmov.16 q4[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9 ; CHECK-MVE-NEXT: vseleq.f16 s20, s13, s9
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s5 ; CHECK-MVE-NEXT: vmovx.f16 s20, s5
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[2], r1 ; CHECK-MVE-NEXT: vmov.16 q4[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vmovx.f16 s22, s13 ; CHECK-MVE-NEXT: vmovx.f16 s22, s13
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s2, s6 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s6
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[3], r1 ; CHECK-MVE-NEXT: vmov.16 q4[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s22, s2 ; CHECK-MVE-NEXT: vmovx.f16 s22, s2
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s15 ; CHECK-MVE-NEXT: vmovx.f16 s2, s15
; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10 ; CHECK-MVE-NEXT: vseleq.f16 s20, s14, s10
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmovx.f16 s20, s6 ; CHECK-MVE-NEXT: vmovx.f16 s20, s6
; CHECK-MVE-NEXT: vcmpe.f16 s22, s20 ; CHECK-MVE-NEXT: vcmpe.f16 s22, s20
; CHECK-MVE-NEXT: vmov.16 q4[4], r1 ; CHECK-MVE-NEXT: vmov.16 q4[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmovx.f16 s22, s14 ; CHECK-MVE-NEXT: vmovx.f16 s22, s14
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20 ; CHECK-MVE-NEXT: vseleq.f16 s20, s22, s20
; CHECK-MVE-NEXT: vcmpe.f16 s3, s7 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s7
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov.16 q4[5], r1 ; CHECK-MVE-NEXT: vmov.16 q4[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmpe.f16 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s4
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s0, s11 ; CHECK-MVE-NEXT: vmovx.f16 s0, s11
; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11 ; CHECK-MVE-NEXT: vseleq.f16 s20, s15, s11
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s20 ; CHECK-MVE-NEXT: vmov r1, s20
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q4[6], r1 ; CHECK-MVE-NEXT: vmov.16 q4[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q4[7], r0 ; CHECK-MVE-NEXT: vmov.16 q4[7], r0
; CHECK-MVE-NEXT: vmov q0, q4 ; CHECK-MVE-NEXT: vmov q0, q4
; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11} ; CHECK-MVE-NEXT: vpop {d8, d9, d10, d11}
Show All 14 Lines

llvm/test/CodeGen/Thumb2/mve-vcmpfr.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, float %src2, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v4f32: ; CHECK-MVE-LABEL: vcmp_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1 ; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 23 Lines
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1 ; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 22 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 18 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1 ; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r3, #1 ; CHECK-MVE-NEXT: movge r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 18 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1 ; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 19 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1 ; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r3, #1 ; CHECK-MVE-NEXT: movls r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 24 Lines
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1 ; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 21 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s0, s4 ; CHECK-MVE-NEXT: vcmp.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, s4 ; CHECK-MVE-NEXT: vcmp.f32 s1, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, s4 ; CHECK-MVE-NEXT: vcmp.f32 s2, s4
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, s4 ; CHECK-MVE-NEXT: vcmp.f32 s3, s4
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r3, #1 ; CHECK-MVE-NEXT: movne r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 18 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1 ; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r3, #1 ; CHECK-MVE-NEXT: movhi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 20 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1 ; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r3, #1 ; CHECK-MVE-NEXT: movpl r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 20 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1 ; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r3, #1 ; CHECK-MVE-NEXT: movlt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 19 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1 ; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r3, #1 ; CHECK-MVE-NEXT: movle r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 19 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1 ; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r3, #1 ; CHECK-MVE-NEXT: movvc r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 22 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s4
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s4
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s4
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s4 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s4
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11 ; CHECK-MVE-NEXT: vseleq.f32 s3, s15, s11
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10 ; CHECK-MVE-NEXT: vseleq.f32 s2, s14, s10
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9 ; CHECK-MVE-NEXT: vseleq.f32 s1, s13, s9
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8 ; CHECK-MVE-NEXT: vseleq.f32 s0, s12, s8
Show All 29 Lines
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s16
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s16 ; CHECK-MVE-NEXT: vcmp.f16 s1, s16
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s1 ; CHECK-MVE-NEXT: vmovx.f16 s18, s1
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s16 ; CHECK-MVE-NEXT: vcmp.f16 s2, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s2 ; CHECK-MVE-NEXT: vmovx.f16 s18, s2
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r0 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s16 ; CHECK-MVE-NEXT: vcmp.f16 s3, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vcmp.f16 s0, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s16
; CHECK-MVE-NEXT: vmov.16 q3[5], r0 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
Show All 25 Lines
; CHECK-MVE-NEXT: vcmp.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s16 ; CHECK-MVE-NEXT: vcmp.f16 s1, s16
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s1 ; CHECK-MVE-NEXT: vmovx.f16 s18, s1
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s16 ; CHECK-MVE-NEXT: vcmp.f16 s2, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s2 ; CHECK-MVE-NEXT: vmovx.f16 s18, s2
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r0 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s16 ; CHECK-MVE-NEXT: vcmp.f16 s3, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vcmp.f16 s0, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s16
; CHECK-MVE-NEXT: vmov.16 q3[5], r0 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
Show All 28 Lines
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s1 ; CHECK-MVE-NEXT: vmovx.f16 s18, s1
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s2 ; CHECK-MVE-NEXT: vmovx.f16 s18, s2
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r0 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: vmov.16 q3[5], r0 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
Show All 24 Lines
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1 ; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s1 ; CHECK-MVE-NEXT: vmovx.f16 s18, s1
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s2 ; CHECK-MVE-NEXT: vmovx.f16 s18, s2
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r0 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: vmov.16 q3[5], r0 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
Show All 24 Lines
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s1 ; CHECK-MVE-NEXT: vmovx.f16 s18, s1
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s2 ; CHECK-MVE-NEXT: vmovx.f16 s18, s2
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r0 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: vmov.16 q3[5], r0 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
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; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1 ; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s1 ; CHECK-MVE-NEXT: vmovx.f16 s18, s1
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s2 ; CHECK-MVE-NEXT: vmovx.f16 s18, s2
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r0 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: vmov.16 q3[5], r0 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
Show All 26 Lines
; CHECK-MVE-NEXT: vcmp.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vcmp.f16 s1, s16 ; CHECK-MVE-NEXT: vcmp.f16 s1, s16
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s1 ; CHECK-MVE-NEXT: vmovx.f16 s18, s1
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, s16 ; CHECK-MVE-NEXT: vcmp.f16 s2, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s2 ; CHECK-MVE-NEXT: vmovx.f16 s18, s2
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r0 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, s16 ; CHECK-MVE-NEXT: vcmp.f16 s3, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vcmp.f16 s0, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s16
; CHECK-MVE-NEXT: vmov.16 q3[5], r0 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
Show All 27 Lines
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmp.f16 s12, s16 ; CHECK-MVE-NEXT: vcmp.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s16
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, s16 ; CHECK-MVE-NEXT: vcmp.f16 s1, s16
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s1 ; CHECK-MVE-NEXT: vmovx.f16 s18, s1
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, s16 ; CHECK-MVE-NEXT: vcmp.f16 s2, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s2 ; CHECK-MVE-NEXT: vmovx.f16 s18, s2
; CHECK-MVE-NEXT: vcmp.f16 s18, s16 ; CHECK-MVE-NEXT: vcmp.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r0 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, s16 ; CHECK-MVE-NEXT: vcmp.f16 s3, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vcmp.f16 s0, s16 ; CHECK-MVE-NEXT: vcmp.f16 s0, s16
; CHECK-MVE-NEXT: vmov.16 q3[5], r0 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
Show All 24 Lines
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1 ; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s1 ; CHECK-MVE-NEXT: vmovx.f16 s18, s1
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s2 ; CHECK-MVE-NEXT: vmovx.f16 s18, s2
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r0 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: vmov.16 q3[5], r0 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
Show All 26 Lines
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1 ; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s1 ; CHECK-MVE-NEXT: vmovx.f16 s18, s1
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s2 ; CHECK-MVE-NEXT: vmovx.f16 s18, s2
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r0 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: vmov.16 q3[5], r0 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
Show All 26 Lines
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1 ; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s1 ; CHECK-MVE-NEXT: vmovx.f16 s18, s1
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s2 ; CHECK-MVE-NEXT: vmovx.f16 s18, s2
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r0 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: vmov.16 q3[5], r0 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
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; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1 ; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s1 ; CHECK-MVE-NEXT: vmovx.f16 s18, s1
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s2 ; CHECK-MVE-NEXT: vmovx.f16 s18, s2
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r0 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: vmov.16 q3[5], r0 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
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; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1 ; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s1 ; CHECK-MVE-NEXT: vmovx.f16 s18, s1
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s2 ; CHECK-MVE-NEXT: vmovx.f16 s18, s2
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r0 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: vmov.16 q3[5], r0 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
Show All 28 Lines
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: vcmpe.f16 s12, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s16
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: movs r2, #0 ; CHECK-MVE-NEXT: movs r2, #0
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s20, s9 ; CHECK-MVE-NEXT: vmovx.f16 s20, s9
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r0, s12 ; CHECK-MVE-NEXT: vmov r0, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s16
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[1], r0 ; CHECK-MVE-NEXT: vmov.16 q3[1], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s18, s9, s5
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s1 ; CHECK-MVE-NEXT: vmovx.f16 s18, s1
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r0 ; CHECK-MVE-NEXT: vmov.16 q3[2], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s5 ; CHECK-MVE-NEXT: vmovx.f16 s18, s5
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s20, s10 ; CHECK-MVE-NEXT: vmovx.f16 s20, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r0 ; CHECK-MVE-NEXT: vmov.16 q3[3], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s18, s10, s6
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vmovx.f16 s18, s2 ; CHECK-MVE-NEXT: vmovx.f16 s18, s2
; CHECK-MVE-NEXT: vcmpe.f16 s18, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s18, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r0 ; CHECK-MVE-NEXT: vmov.16 q3[4], r0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s18, s6 ; CHECK-MVE-NEXT: vmovx.f16 s18, s6
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s16
; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18 ; CHECK-MVE-NEXT: vseleq.f16 s18, s20, s18
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: vcmpe.f16 s0, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s16
; CHECK-MVE-NEXT: vmov.16 q3[5], r0 ; CHECK-MVE-NEXT: vmov.16 q3[5], r0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s18, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: vmov r0, s18 ; CHECK-MVE-NEXT: vmov r0, s18
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vmov.16 q3[6], r0 ; CHECK-MVE-NEXT: vmov.16 q3[6], r0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9, d10} ; CHECK-MVE-NEXT: vpop {d8, d9, d10}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
; ;
Show All 18 Lines

llvm/test/CodeGen/Thumb2/mve-vcmpfz.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve,+fullfp16 -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVE
; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP ; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve.fp -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-MVEFP
define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) { define arm_aapcs_vfpcc <4 x float> @vcmp_oeq_v4f32(<4 x float> %src, <4 x float> %a, <4 x float> %b) {
; CHECK-MVE-LABEL: vcmp_oeq_v4f32: ; CHECK-MVE-LABEL: vcmp_oeq_v4f32:
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1 ; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
Show All 20 Lines
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1 ; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
Show All 19 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s0, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r3, #1 ; CHECK-MVE-NEXT: movgt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
Show All 15 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s0, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1 ; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r3, #1 ; CHECK-MVE-NEXT: movge r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
Show All 15 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s0, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r3, #1 ; CHECK-MVE-NEXT: movmi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
Show All 15 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s0, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1 ; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r3, #1 ; CHECK-MVE-NEXT: movls r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
Show All 20 Lines
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r3, #1 ; CHECK-MVE-NEXT: moveq r3, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
Show All 18 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s0, #0 ; CHECK-MVE-NEXT: vcmp.f32 s0, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f32 s1, #0 ; CHECK-MVE-NEXT: vcmp.f32 s1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmp.f32 s2, #0 ; CHECK-MVE-NEXT: vcmp.f32 s2, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmp.f32 s3, #0 ; CHECK-MVE-NEXT: vcmp.f32 s3, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r3, #1 ; CHECK-MVE-NEXT: movne r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
Show All 15 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s0, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1 ; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r3, #1 ; CHECK-MVE-NEXT: movhi r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
Show All 16 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s0, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1 ; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r3, #1 ; CHECK-MVE-NEXT: movpl r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
Show All 16 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s0, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1 ; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r3, #1 ; CHECK-MVE-NEXT: movlt r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
Show All 16 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s0, #0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s2, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1 ; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, #0 ; CHECK-MVE-NEXT: vcmpe.f32 s3, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r3, #1 ; CHECK-MVE-NEXT: movle r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
Show All 16 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s0 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s1 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s1
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s2 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s2
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1 ; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s3 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s3
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r3, #1 ; CHECK-MVE-NEXT: movvc r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
Show All 19 Lines
; CHECK-MVE: @ %bb.0: @ %entry ; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmpe.f32 s0, s0 ; CHECK-MVE-NEXT: vcmpe.f32 s0, s0
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f32 s1, s1 ; CHECK-MVE-NEXT: vcmpe.f32 s1, s1
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vcmpe.f32 s2, s2 ; CHECK-MVE-NEXT: vcmpe.f32 s2, s2
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r3, #0 ; CHECK-MVE-NEXT: mov.w r3, #0
; CHECK-MVE-NEXT: vcmpe.f32 s3, s3 ; CHECK-MVE-NEXT: vcmpe.f32 s3, s3
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r3, #1 ; CHECK-MVE-NEXT: movvs r3, #1
; CHECK-MVE-NEXT: cmp r3, #0 ; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: csinc r3, zr, zr, eq ; CHECK-MVE-NEXT: cset r3, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7 ; CHECK-MVE-NEXT: vseleq.f32 s3, s11, s7
; CHECK-MVE-NEXT: lsls r0, r3, #31 ; CHECK-MVE-NEXT: lsls r0, r3, #31
; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6 ; CHECK-MVE-NEXT: vseleq.f32 s2, s10, s6
; CHECK-MVE-NEXT: lsls r0, r2, #31 ; CHECK-MVE-NEXT: lsls r0, r2, #31
; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5 ; CHECK-MVE-NEXT: vseleq.f32 s1, s9, s5
; CHECK-MVE-NEXT: lsls r0, r1, #31 ; CHECK-MVE-NEXT: lsls r0, r1, #31
; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4 ; CHECK-MVE-NEXT: vseleq.f32 s0, s8, s4
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; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1 ; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1 ; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
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; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s16, s5 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1 ; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1 ; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
Show All 22 Lines
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s12, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r2, #1 ; CHECK-MVE-NEXT: movgt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1 ; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1 ; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r1, #1 ; CHECK-MVE-NEXT: movgt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it gt ; CHECK-MVE-NEXT: it gt
; CHECK-MVE-NEXT: movgt r0, #1 ; CHECK-MVE-NEXT: movgt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
Show All 19 Lines
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s12, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r2, #1 ; CHECK-MVE-NEXT: movge r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1 ; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1 ; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r1, #1 ; CHECK-MVE-NEXT: movge r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ge ; CHECK-MVE-NEXT: it ge
; CHECK-MVE-NEXT: movge r0, #1 ; CHECK-MVE-NEXT: movge r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
Show All 19 Lines
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s12, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r2, #1 ; CHECK-MVE-NEXT: movmi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1 ; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1 ; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r1, #1 ; CHECK-MVE-NEXT: movmi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it mi ; CHECK-MVE-NEXT: it mi
; CHECK-MVE-NEXT: movmi r0, #1 ; CHECK-MVE-NEXT: movmi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
Show All 19 Lines
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s12, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r2, #1 ; CHECK-MVE-NEXT: movls r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1 ; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1 ; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r1, #1 ; CHECK-MVE-NEXT: movls r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ls ; CHECK-MVE-NEXT: it ls
; CHECK-MVE-NEXT: movls r0, #1 ; CHECK-MVE-NEXT: movls r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
Show All 20 Lines
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r2, #1 ; CHECK-MVE-NEXT: moveq r2, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: mov.w r0, #0 ; CHECK-MVE-NEXT: mov.w r0, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s16, s5 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1 ; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1 ; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r1, #1 ; CHECK-MVE-NEXT: moveq r1, #1
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it eq ; CHECK-MVE-NEXT: it eq
; CHECK-MVE-NEXT: moveq r0, #1 ; CHECK-MVE-NEXT: moveq r0, #1
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
; CHECK-MVE-NEXT: bx lr ; CHECK-MVE-NEXT: bx lr
Show All 21 Lines
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s12, #0 ; CHECK-MVE-NEXT: vcmp.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r2, #1 ; CHECK-MVE-NEXT: movne r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmp.f16 s1, #0 ; CHECK-MVE-NEXT: vcmp.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s2, #0 ; CHECK-MVE-NEXT: vcmp.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1 ; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmp.f16 s16, #0 ; CHECK-MVE-NEXT: vcmp.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmp.f16 s3, #0 ; CHECK-MVE-NEXT: vcmp.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmp.f16 s0, #0 ; CHECK-MVE-NEXT: vcmp.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1 ; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r1, #1 ; CHECK-MVE-NEXT: movne r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it ne ; CHECK-MVE-NEXT: it ne
; CHECK-MVE-NEXT: movne r0, #1 ; CHECK-MVE-NEXT: movne r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
Show All 19 Lines
; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s12, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r2, #1 ; CHECK-MVE-NEXT: movhi r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1 ; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1 ; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r1, #1 ; CHECK-MVE-NEXT: movhi r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it hi ; CHECK-MVE-NEXT: it hi
; CHECK-MVE-NEXT: movhi r0, #1 ; CHECK-MVE-NEXT: movhi r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
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; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s12, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r2, #1 ; CHECK-MVE-NEXT: movpl r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1 ; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1 ; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r1, #1 ; CHECK-MVE-NEXT: movpl r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it pl ; CHECK-MVE-NEXT: it pl
; CHECK-MVE-NEXT: movpl r0, #1 ; CHECK-MVE-NEXT: movpl r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
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; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s12, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r2, #1 ; CHECK-MVE-NEXT: movlt r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1 ; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1 ; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r1, #1 ; CHECK-MVE-NEXT: movlt r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it lt ; CHECK-MVE-NEXT: it lt
; CHECK-MVE-NEXT: movlt r0, #1 ; CHECK-MVE-NEXT: movlt r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
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; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s12, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s12, #0
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r2, #1 ; CHECK-MVE-NEXT: movle r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s1, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s2, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1 ; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmpe.f16 s16, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s16, #0
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s3, #0
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmpe.f16 s0, #0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, #0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1 ; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r1, #1 ; CHECK-MVE-NEXT: movle r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it le ; CHECK-MVE-NEXT: it le
; CHECK-MVE-NEXT: movle r0, #1 ; CHECK-MVE-NEXT: movle r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
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; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s12, s12 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r2, #1 ; CHECK-MVE-NEXT: movvc r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s1 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s1
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmpe.f16 s16, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s16, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s2 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s2
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1 ; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmpe.f16 s16, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s16, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s3 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s3
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmpe.f16 s0, s0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1 ; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r1, #1 ; CHECK-MVE-NEXT: movvc r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vc ; CHECK-MVE-NEXT: it vc
; CHECK-MVE-NEXT: movvc r0, #1 ; CHECK-MVE-NEXT: movvc r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
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; CHECK-MVE-NEXT: movs r1, #0 ; CHECK-MVE-NEXT: movs r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s12, s12 ; CHECK-MVE-NEXT: vcmpe.f16 s12, s12
; CHECK-MVE-NEXT: vmovx.f16 s12, s4 ; CHECK-MVE-NEXT: vmovx.f16 s12, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vcmpe.f16 s0, s0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s14, s8 ; CHECK-MVE-NEXT: vmovx.f16 s14, s8
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: mov.w r2, #0 ; CHECK-MVE-NEXT: mov.w r2, #0
; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12 ; CHECK-MVE-NEXT: vseleq.f16 s12, s14, s12
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r2, #1 ; CHECK-MVE-NEXT: movvs r2, #1
; CHECK-MVE-NEXT: cmp r2, #0 ; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: csinc r2, zr, zr, eq ; CHECK-MVE-NEXT: cset r2, ne
; CHECK-MVE-NEXT: vmov r1, s12 ; CHECK-MVE-NEXT: vmov r1, s12
; CHECK-MVE-NEXT: lsls r2, r2, #31 ; CHECK-MVE-NEXT: lsls r2, r2, #31
; CHECK-MVE-NEXT: vcmpe.f16 s1, s1 ; CHECK-MVE-NEXT: vcmpe.f16 s1, s1
; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4 ; CHECK-MVE-NEXT: vseleq.f16 s12, s8, s4
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r2, s12 ; CHECK-MVE-NEXT: vmov r2, s12
; CHECK-MVE-NEXT: vmovx.f16 s18, s9 ; CHECK-MVE-NEXT: vmovx.f16 s18, s9
; CHECK-MVE-NEXT: vmov.16 q3[0], r2 ; CHECK-MVE-NEXT: vmov.16 q3[0], r2
; CHECK-MVE-NEXT: vmovx.f16 s0, s3 ; CHECK-MVE-NEXT: vmovx.f16 s0, s3
; CHECK-MVE-NEXT: vmov.16 q3[1], r1 ; CHECK-MVE-NEXT: vmov.16 q3[1], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: movs r0, #0 ; CHECK-MVE-NEXT: movs r0, #0
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5 ; CHECK-MVE-NEXT: vseleq.f16 s16, s9, s5
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s1 ; CHECK-MVE-NEXT: vmovx.f16 s16, s1
; CHECK-MVE-NEXT: vcmpe.f16 s16, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s16, s16
; CHECK-MVE-NEXT: vmov.16 q3[2], r1 ; CHECK-MVE-NEXT: vmov.16 q3[2], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s5 ; CHECK-MVE-NEXT: vmovx.f16 s16, s5
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s2, s2 ; CHECK-MVE-NEXT: vcmpe.f16 s2, s2
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s18, s10 ; CHECK-MVE-NEXT: vmovx.f16 s18, s10
; CHECK-MVE-NEXT: vmov.16 q3[3], r1 ; CHECK-MVE-NEXT: vmov.16 q3[3], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6 ; CHECK-MVE-NEXT: vseleq.f16 s16, s10, s6
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vmovx.f16 s16, s2 ; CHECK-MVE-NEXT: vmovx.f16 s16, s2
; CHECK-MVE-NEXT: vcmpe.f16 s16, s16 ; CHECK-MVE-NEXT: vcmpe.f16 s16, s16
; CHECK-MVE-NEXT: vmov.16 q3[4], r1 ; CHECK-MVE-NEXT: vmov.16 q3[4], r1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s16, s6 ; CHECK-MVE-NEXT: vmovx.f16 s16, s6
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vcmpe.f16 s3, s3 ; CHECK-MVE-NEXT: vcmpe.f16 s3, s3
; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16 ; CHECK-MVE-NEXT: vseleq.f16 s16, s18, s16
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: vcmpe.f16 s0, s0 ; CHECK-MVE-NEXT: vcmpe.f16 s0, s0
; CHECK-MVE-NEXT: vmov.16 q3[5], r1 ; CHECK-MVE-NEXT: vmov.16 q3[5], r1
; CHECK-MVE-NEXT: mov.w r1, #0 ; CHECK-MVE-NEXT: mov.w r1, #0
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r1, #1 ; CHECK-MVE-NEXT: movvs r1, #1
; CHECK-MVE-NEXT: cmp r1, #0 ; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: csinc r1, zr, zr, eq ; CHECK-MVE-NEXT: cset r1, ne
; CHECK-MVE-NEXT: vmovx.f16 s0, s7 ; CHECK-MVE-NEXT: vmovx.f16 s0, s7
; CHECK-MVE-NEXT: lsls r1, r1, #31 ; CHECK-MVE-NEXT: lsls r1, r1, #31
; CHECK-MVE-NEXT: vmovx.f16 s2, s11 ; CHECK-MVE-NEXT: vmovx.f16 s2, s11
; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7 ; CHECK-MVE-NEXT: vseleq.f16 s16, s11, s7
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr ; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: it vs ; CHECK-MVE-NEXT: it vs
; CHECK-MVE-NEXT: movvs r0, #1 ; CHECK-MVE-NEXT: movvs r0, #1
; CHECK-MVE-NEXT: cmp r0, #0 ; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: csinc r0, zr, zr, eq ; CHECK-MVE-NEXT: cset r0, ne
; CHECK-MVE-NEXT: vmov r1, s16 ; CHECK-MVE-NEXT: vmov r1, s16
; CHECK-MVE-NEXT: lsls r0, r0, #31 ; CHECK-MVE-NEXT: lsls r0, r0, #31
; CHECK-MVE-NEXT: vmov.16 q3[6], r1 ; CHECK-MVE-NEXT: vmov.16 q3[6], r1
; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0 ; CHECK-MVE-NEXT: vseleq.f16 s0, s2, s0
; CHECK-MVE-NEXT: vmov r0, s0 ; CHECK-MVE-NEXT: vmov r0, s0
; CHECK-MVE-NEXT: vmov.16 q3[7], r0 ; CHECK-MVE-NEXT: vmov.16 q3[7], r0
; CHECK-MVE-NEXT: vmov q0, q3 ; CHECK-MVE-NEXT: vmov q0, q3
; CHECK-MVE-NEXT: vpop {d8, d9} ; CHECK-MVE-NEXT: vpop {d8, d9}
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llvm/test/CodeGen/Thumb2/mve-vcmpr.ll

Show First 20 Lines • Show All 438 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, i64 %src2, <2 x i64> %a, <2 x i64> %b) { define arm_aapcs_vfpcc <2 x i64> @vcmp_eq_v2i64(<2 x i64> %src, i64 %src2, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: vcmp_eq_v2i64: ; CHECK-LABEL: vcmp_eq_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r2, s1 ; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: eors r2, r1 ; CHECK-NEXT: eors r2, r1
; CHECK-NEXT: eors r3, r0 ; CHECK-NEXT: eors r3, r0
; CHECK-NEXT: orrs r2, r3 ; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: csinc r2, zr, zr, ne ; CHECK-NEXT: cset r2, eq
; CHECK-NEXT: tst.w r2, #1 ; CHECK-NEXT: tst.w r2, #1
; CHECK-NEXT: csinv r2, zr, zr, eq ; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: vmov.32 q3[0], r2 ; CHECK-NEXT: vmov.32 q3[0], r2
; CHECK-NEXT: vmov.32 q3[1], r2 ; CHECK-NEXT: vmov.32 q3[1], r2
; CHECK-NEXT: vmov r2, s3 ; CHECK-NEXT: vmov r2, s3
; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: vmov r2, s2 ; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: eors r0, r2 ; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3 ; CHECK-NEXT: vbic q0, q2, q3
; CHECK-NEXT: vand q1, q1, q3 ; CHECK-NEXT: vand q1, q1, q3
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%i = insertelement <2 x i64> undef, i64 %src2, i32 0 %i = insertelement <2 x i64> undef, i64 %src2, i32 0
%sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer %sp = shufflevector <2 x i64> %i, <2 x i64> undef, <2 x i32> zeroinitializer
%c = icmp eq <2 x i64> %src, %sp %c = icmp eq <2 x i64> %src, %sp
%s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s ret <2 x i64> %s
} }
define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, i64 %src2, <2 x i32> %a, <2 x i32> %b) { define arm_aapcs_vfpcc <2 x i32> @vcmp_eq_v2i32(<2 x i64> %src, i64 %src2, <2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: vcmp_eq_v2i32: ; CHECK-LABEL: vcmp_eq_v2i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r2, s1 ; CHECK-NEXT: vmov r2, s1
; CHECK-NEXT: vmov r3, s0 ; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: eors r2, r1 ; CHECK-NEXT: eors r2, r1
; CHECK-NEXT: eors r3, r0 ; CHECK-NEXT: eors r3, r0
; CHECK-NEXT: orrs r2, r3 ; CHECK-NEXT: orrs r2, r3
; CHECK-NEXT: csinc r2, zr, zr, ne ; CHECK-NEXT: cset r2, eq
; CHECK-NEXT: tst.w r2, #1 ; CHECK-NEXT: tst.w r2, #1
; CHECK-NEXT: csinv r2, zr, zr, eq ; CHECK-NEXT: csetm r2, ne
; CHECK-NEXT: vmov.32 q3[0], r2 ; CHECK-NEXT: vmov.32 q3[0], r2
; CHECK-NEXT: vmov.32 q3[1], r2 ; CHECK-NEXT: vmov.32 q3[1], r2
; CHECK-NEXT: vmov r2, s3 ; CHECK-NEXT: vmov r2, s3
; CHECK-NEXT: eors r1, r2 ; CHECK-NEXT: eors r1, r2
; CHECK-NEXT: vmov r2, s2 ; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: eors r0, r2 ; CHECK-NEXT: eors r0, r2
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3 ; CHECK-NEXT: vbic q0, q2, q3
; CHECK-NEXT: vand q1, q1, q3 ; CHECK-NEXT: vand q1, q1, q3
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%i = insertelement <2 x i64> undef, i64 %src2, i32 0 %i = insertelement <2 x i64> undef, i64 %src2, i32 0
Show All 11 Lines
; CHECK-NEXT: .vsave {d8, d9, d10, d11} ; CHECK-NEXT: .vsave {d8, d9, d10, d11}
; CHECK-NEXT: vpush {d8, d9, d10, d11} ; CHECK-NEXT: vpush {d8, d9, d10, d11}
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: movs r3, #0 ; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: vmov r2, s8 ; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3 ; CHECK-NEXT: vbic q0, q2, q3
; CHECK-NEXT: vmov lr, s0 ; CHECK-NEXT: vmov lr, s0
; CHECK-NEXT: subs.w r1, lr, r2 ; CHECK-NEXT: subs.w r1, lr, r2
; CHECK-NEXT: asr.w r12, lr, #31 ; CHECK-NEXT: asr.w r12, lr, #31
; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31 ; CHECK-NEXT: sbcs.w r1, r12, r2, asr #31
; CHECK-NEXT: mov.w r1, #0 ; CHECK-NEXT: mov.w r1, #0
; CHECK-NEXT: vmov r2, s10 ; CHECK-NEXT: vmov r2, s10
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r1, #1 ; CHECK-NEXT: movlt r1, #1
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: csinv r1, zr, zr, eq ; CHECK-NEXT: csetm r1, ne
; CHECK-NEXT: vmov.32 q3[0], r1 ; CHECK-NEXT: vmov.32 q3[0], r1
; CHECK-NEXT: vmov.32 q3[1], r1 ; CHECK-NEXT: vmov.32 q3[1], r1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: subs r0, r1, r2 ; CHECK-NEXT: subs r0, r1, r2
; CHECK-NEXT: asr.w r12, r1, #31 ; CHECK-NEXT: asr.w r12, r1, #31
; CHECK-NEXT: sbcs.w r0, r12, r2, asr #31 ; CHECK-NEXT: sbcs.w r0, r12, r2, asr #31
; CHECK-NEXT: it lt ; CHECK-NEXT: it lt
; CHECK-NEXT: movlt r3, #1 ; CHECK-NEXT: movlt r3, #1
; CHECK-NEXT: cmp r3, #0 ; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp.w lr, #0 ; CHECK-NEXT: cmp.w lr, #0
; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: csinc r0, zr, zr, eq ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: cmp r1, #0 ; CHECK-NEXT: cmp r1, #0
; CHECK-NEXT: vmov.32 q4[0], r0 ; CHECK-NEXT: vmov.32 q4[0], r0
; CHECK-NEXT: vmov.32 q4[1], r0 ; CHECK-NEXT: vmov.32 q4[1], r0
; CHECK-NEXT: csinc r0, zr, zr, eq ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q4[2], r0 ; CHECK-NEXT: vmov.32 q4[2], r0
; CHECK-NEXT: vmov.32 q4[3], r0 ; CHECK-NEXT: vmov.32 q4[3], r0
; CHECK-NEXT: vmov r0, s4 ; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinc r0, zr, zr, eq ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q5[0], r0 ; CHECK-NEXT: vmov.32 q5[0], r0
; CHECK-NEXT: vmov.32 q5[1], r0 ; CHECK-NEXT: vmov.32 q5[1], r0
; CHECK-NEXT: vmov r0, s6 ; CHECK-NEXT: vmov r0, s6
; CHECK-NEXT: cmp r0, #0 ; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: csinc r0, zr, zr, eq ; CHECK-NEXT: cset r0, ne
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q5[2], r0 ; CHECK-NEXT: vmov.32 q5[2], r0
; CHECK-NEXT: vmov.32 q5[3], r0 ; CHECK-NEXT: vmov.32 q5[3], r0
; CHECK-NEXT: vand q1, q5, q4 ; CHECK-NEXT: vand q1, q5, q4
; CHECK-NEXT: vand q1, q3, q1 ; CHECK-NEXT: vand q1, q3, q1
; CHECK-NEXT: vbic q0, q0, q1 ; CHECK-NEXT: vbic q0, q0, q1
; CHECK-NEXT: vand q1, q2, q1 ; CHECK-NEXT: vand q1, q2, q1
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: vpop {d8, d9, d10, d11} ; CHECK-NEXT: vpop {d8, d9, d10, d11}
Show All 11 Lines

llvm/test/CodeGen/Thumb2/mve-vcmpz.ll

Show First 20 Lines • Show All 359 Lines • ▼ Show 20 Lines
define arm_aapcs_vfpcc <2 x i64> @vcmp_eqz_v2i64(<2 x i64> %src, <2 x i64> %a, <2 x i64> %b) { define arm_aapcs_vfpcc <2 x i64> @vcmp_eqz_v2i64(<2 x i64> %src, <2 x i64> %a, <2 x i64> %b) {
; CHECK-LABEL: vcmp_eqz_v2i64: ; CHECK-LABEL: vcmp_eqz_v2i64:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3 ; CHECK-NEXT: vbic q0, q2, q3
; CHECK-NEXT: vand q1, q1, q3 ; CHECK-NEXT: vand q1, q1, q3
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <2 x i64> %src, zeroinitializer %c = icmp eq <2 x i64> %src, zeroinitializer
%s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b %s = select <2 x i1> %c, <2 x i64> %a, <2 x i64> %b
ret <2 x i64> %s ret <2 x i64> %s
} }
define arm_aapcs_vfpcc <2 x i32> @vcmp_eqz_v2i32(<2 x i64> %src, <2 x i32> %a, <2 x i32> %b) { define arm_aapcs_vfpcc <2 x i32> @vcmp_eqz_v2i32(<2 x i64> %src, <2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: vcmp_eqz_v2i32: ; CHECK-LABEL: vcmp_eqz_v2i32:
; CHECK: @ %bb.0: @ %entry ; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmov r0, s1 ; CHECK-NEXT: vmov r0, s1
; CHECK-NEXT: vmov r1, s0 ; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: vmov r1, s2 ; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[0], r0 ; CHECK-NEXT: vmov.32 q3[0], r0
; CHECK-NEXT: vmov.32 q3[1], r0 ; CHECK-NEXT: vmov.32 q3[1], r0
; CHECK-NEXT: vmov r0, s3 ; CHECK-NEXT: vmov r0, s3
; CHECK-NEXT: orrs r0, r1 ; CHECK-NEXT: orrs r0, r1
; CHECK-NEXT: csinc r0, zr, zr, ne ; CHECK-NEXT: cset r0, eq
; CHECK-NEXT: tst.w r0, #1 ; CHECK-NEXT: tst.w r0, #1
; CHECK-NEXT: csinv r0, zr, zr, eq ; CHECK-NEXT: csetm r0, ne
; CHECK-NEXT: vmov.32 q3[2], r0 ; CHECK-NEXT: vmov.32 q3[2], r0
; CHECK-NEXT: vmov.32 q3[3], r0 ; CHECK-NEXT: vmov.32 q3[3], r0
; CHECK-NEXT: vbic q0, q2, q3 ; CHECK-NEXT: vbic q0, q2, q3
; CHECK-NEXT: vand q1, q1, q3 ; CHECK-NEXT: vand q1, q1, q3
; CHECK-NEXT: vorr q0, q1, q0 ; CHECK-NEXT: vorr q0, q1, q0
; CHECK-NEXT: bx lr ; CHECK-NEXT: bx lr
entry: entry:
%c = icmp eq <2 x i64> %src, zeroinitializer %c = icmp eq <2 x i64> %src, zeroinitializer
%s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b %s = select <2 x i1> %c, <2 x i32> %a, <2 x i32> %b
ret <2 x i32> %s ret <2 x i32> %s
} }

llvm/test/MC/ARM/thumbv8.1m.s

Show First 20 Lines • Show All 1,113 Lines • ▼ Show 20 Lines
# CHECK: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80] # CHECK: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80]
# CHECK-FP: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80] # CHECK-FP: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80]
# CHECK-NOLOB: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80] # CHECK-NOLOB: csel r0, r0, r1, eq @ encoding: [0x50,0xea,0x01,0x80]
csel r0, r0, r1, eq csel r0, r0, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 // ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14
csel sp, r0, r1, eq csel sp, r0, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14
csel pc, r0, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr // ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csel r0, sp, r1, eq csel r0, sp, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csel r0, pc, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr // ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csinc r0, sp, r1, eq csinc r0, sp, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csinc r0, pc, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr // ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csinv r0, sp, r1, eq csinv r0, sp, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csinv r0, pc, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr // ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csneg r0, sp, r1, eq csneg r0, sp, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csneg r0, pc, r1, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr // ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csel r0, r0, sp, eq csel r0, r0, sp, eq
// ERROR: :[[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [r0, r12] or r14 or zr
csel r0, r0, pc, eq
// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable // ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable
it eq it eq
csel r0, r0, r1, eq csel r0, r0, r1, eq
// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable // ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable
it eq it eq
csinc r0, r0, r1, ne csinc r0, r0, r1, ne
// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable // ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable
it gt it gt
csinv r0, r0, r1, ge csinv r0, r0, r1, ge
// ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable // ERROR: :[[@LINE+2]]:{{[0-9]+}}: error: instructions in IT block must be predicable
it lt it lt
csneg r0, r0, r1, gt csneg r0, r0, r1, gt