[PowerPC] [Peephole] fold frame offset by using index form to save add.

[shchenz]

Summary

Before pass PEI, all stack variables has a placeholder 0 as its offset to frame base. And in pass PEI, the real offset is filled. Like:

Before PEI:

renamable $x6 = ADDI8 %stack.0, 0
renamable $x6 = ADD8 killed renamable $x6, renamable $x5
STW killed renamable $r3, 4, killed renamable $x6 :: (store 4 into %ir.14, !tbaa !2)

after PEI:

renamable $x6 = ADDI8 $x1, -80      ;;; 0 is replaced with -80
renamable $x6 = ADD8 killed renamable $x6, renamable $x5
STW killed renamable $r3, 4, killed renamable $x6 :: (store 4 into %ir.14, !tbaa !2)

After PEI there is a peephole opt opportunity to combine above -80 in ADDI8 with 4 in the STW to eliminate unnecessary ADD8.

So for above case, optimized instruction should be like:

renamable $x6 = ADDI8 $x1, -76
STWX killed renamable $r3, renamable $x5, killed renamable $x6 :: (store 4 into %ir.6, !tbaa !2)

This patch is to implement such peephole opt.

[stefanp]

I like what this patch is doing. Overall, I only have some refactoring comments.

I do think that there are more opportunities here (however they may be a separate patch):

renamable $x6 = ADDI8 $x1, -80
renamable $x7 = ADD8 (killed?) renamable $x6, renamable $x5   ;; x6 here may or may not be killed...
STW killed renamable $r3, 4, killed renamable $x7 :: (store 4 into %ir.14, !tbaa !2)

Can also be turned into this:

[renamable $x6 = ADDI8 $x1, -80] ? ;; May or may not be there...
renamable $x7 = ADD8 $x1, renamable $x5
STW killed renamable $r3, -76, killed renamable $x7 :: (store 4 into %ir.14, !tbaa !2)

There are some advantages to using this approach too:

1. You don't need an XForm for the Store. You keep the same D form instruction.
2. You don't need to have the result of ADDI killed. If it is killed you can remove the instruction. If it is not killed you leave it but you still win even if you leave it because you have broken the dependency between the two instructions.

One disadvantage that I can see:

1. Some loads/stores require the immediate to be aligned in some way which will limit which immediates you can use for them.

My suggestion is more of an addition to what you already have. I think what you have and what I was describing will catch different opportunities.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

2530

nit:

This opt tries to convert following imm form to index form to save add for stack variables.

to

This opt tries to convert the following imm form to an index form to save an add for stack variables.

2591

You know at this point in the code that this MI is either an ADD4 or and ADD8.
You can create another function to check an operand and then pass in ADDMI->getOperand(1) and ADDMI->getOperand(2). That way you can get rid of the loop. I think the loop makes it look like there could be a number of operands but as far as I know the two adds only ever have 2 input operands.

2593

If you keep the loop this can be an early continue.

if (!ADDMI->getOperand(Idx).isKill())
  continue;

You are only really interested in operands that are killed.

2624

You already use the assumption that you have exactly two operands of interest here. :)

[shchenz]

address @stefanp comments

[shchenz]

In D66329#1651489, @stefanp wrote:

I like what this patch is doing. Overall, I only have some refactoring comments.

I do think that there are more opportunities here (however they may be a separate patch):

renamable $x6 = ADDI8 $x1, -80
renamable $x7 = ADD8 (killed?) renamable $x6, renamable $x5   ;; x6 here may or may not be killed...
STW killed renamable $r3, 4, killed renamable $x7 :: (store 4 into %ir.14, !tbaa !2)

Can also be turned into this:

[renamable $x6 = ADDI8 $x1, -80] ? ;; May or may not be there...
renamable $x7 = ADD8 $x1, renamable $x5
STW killed renamable $r3, -76, killed renamable $x7 :: (store 4 into %ir.14, !tbaa !2)

There are some advantages to using this approach too:

1. You don't need an XForm for the Store. You keep the same D form instruction.
2. You don't need to have the result of ADDI killed. If it is killed you can remove the instruction. If it is not killed you leave it but you still win even if you leave it because you have broken the dependency between the two instructions.

One disadvantage that I can see:

1. Some loads/stores require the immediate to be aligned in some way which will limit which immediates you can use for them.

My suggestion is more of an addition to what you already have. I think what you have and what I was describing will catch different opportunities.

Yes, this is indeed an opportunity for stack variables to save one ADDI. Thanks for pointing it out. This seems not easy to mix together with current patch since this patch will convert dform to xform while above opportunity does not require load/store form changing.

Maybe need to implement it in another patch.

[shchenz]

ping.

[stefanp]

I do have a couple additional comments.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

2694

Since HasImmForm is only used here you can put it directly into the if statement.

However, I'm a little confused as to why you have to call instrHasImmForm and then check the return. It seems like you start with the immediate form and then move on to get the X-Form for it and then you ask to see if there is an immediate. Is it to fill in the III object with the correct flags?

If that is the case we need to have another function to set the flags correctly for an arbitrary immediate opcode. That, however is out of the scope of this patch.

llvm/lib/Target/PowerPC/PPCRegisterInfo.h

68

Instead of returning the map like this I would prefer to have a couple of functions along the lines of hasIndexFormforImm and getIndexFormFormImm. You don't need to use my function names but I think you get the idea. The register info owns that map and should be able to answer questions about it.

[amyk]

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

2540

FraemBaseReg -> FrameBaseReg

2668

nit: Capitalize the W on wrong.

2697

This may be a silly question, but I am curious as to what this line means.

2704

MI.getOperand(III.OpNoForForwarding) is used a few times here, maybe it can be its own variable for more clarity?

[shchenz]

address Stefan and Amy Comments

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

2694

Yes, the flags in III is what this patch needs later. Because the opcode handling in instrHasImmForm and ImmToIdxMap is not the same, so I do a little redundant checking for load/store opcodes to avoid functionality issue.

We already have a plan to redesign the mapping representation between index form and displacement form by using InstrMapping in td files. After that I think we can avoid such code.

2697

I think it means "Is the instruction summing the operand". In load/store instruction, it means we get the EA by summing its operands. For example, for instruction grA = ld Imm, grB, the EA is calculated by Imm + grB

Here we want to put OffsetImm of load/store to ADDI immediate operand, so we must ensure load/store is IsSummingOperands?

[shchenz]

remove one useless comment.

[shchenz]

Hi @stefanp @amyk , any more comments? Thanks.

[stefanp]

I took this patch and applied it to master today and I noticed that one of the LIT tests fails.
The test is:

test-suite/MultiSource/Benchmarks/tramp3d-v4/

It segfaults with this patch and runs fine with out it.
I took a quick look at it and it seems that in this basic block:

; predecessors: %bb.11, %bb.12, %bb.13
  successors: %bb.21(0x80000000); %bb.21(100.00%)
  liveins: $r6, $r7, $r9, $x4, $x5, $x10, $x12, $x30, $r8
  renamable $x3 = ADDI8 $x1, 32
  STW killed renamable $r8, 32, $x1 :: (store 4 into %ir.arrayidx.i.i.i.i.i.i.i.i424, align 8), (store 4 into %ir.129, align 8)
  STW killed renamable $r6, 36, $x1 :: (store 4 into %ir.132)
  STW killed renamable $r7, 44, $x1 :: (store 4 into %ir.134)
  STW killed renamable $r9, 52, $x1 :: (store 4 into %ir.136)
  renamable $x3 = ADD8 killed renamable $x3, killed renamable $x5
  renamable $x5 = nsw ADD8 killed renamable $x10, killed renamable $x12
  renamable $r3 = LWZ 4, killed renamable $x3 :: (load 4 from %ir.137)
  renamable $x5 = nsw SUBF8 renamable $x4, killed renamable $x5
  STW8 killed renamable $x4, 24, renamable $x30 :: (store 4 into %ir.141)
  renamable $r3 = ADD4 killed renamable $r3, killed renamable $r5, implicit $x5
  B %bb.21

We replace

renamable $x3 = ADDI8 $x1, 32
renamable $x3 = ADD8 killed renamable $x3, killed renamable $x5
renamable $r3 = LWZ 4, killed renamable $x3 :: (load 4 from %ir.137)

with:

renamable $x3 = ADDI8 $x1, 36
renamable $r3 = LWZX killed $x5, killed $x3 :: (load 4 from %ir.137)

However, it looks like x5 is redefined before the load so using it in the LWZX is not safe because it is not the same x5 as before.

[shchenz]

I took this patch and applied it to master today and I noticed that one of the LIT tests fails.

Sorry, I didn't do a LIT test recently, I really should do it.

[shchenz]

ScaleReg can not redefined between ADD and Imm instruction.

[shchenz]

ping

[stefanp]

LGTM.
Sorry for taking so long to get to this.

[shchenz]

Thanks for your reviewing. @stefanp

llvm/lib/Target/PowerPC/PPCInstrInfo.h

public:
   /// Return true if the output of the instruction is always zero-extended,
   /// i.e. 0 to 31-th bits are all zeros
   bool isZeroExtended(const MachineInstr &MI, const unsigned depth = 0) const {
    return isSignOrZeroExtended(MI, false, depth);
   }
 
   bool convertToImmediateForm(MachineInstr &MI,
                               MachineInstr **KilledDef = nullptr) const;
+  bool foldFrameOffset(MachineInstr &MI) const;
+  bool isADDIInstrEligibleForFolding(MachineInstr &ADDIMI, int64_t &Imm) const;
+  bool isADDInstrEligibleForFolding(MachineInstr &ADDMI) const;
+  bool isImmInstrEligibleForFolding(MachineInstr &MI, unsigned &BaseReg,
+                                    unsigned &XFormOpcode,
+                                    int64_t &OffsetOfImmInstr,
+                                    ImmInstrInfo &III) const;
+  bool isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
+                             MachineInstr *&ADDIMI, int64_t &OffsetAddi,
+                             int64_t OffsetImm) const;
 
   /// Fixup killed/dead flag for register \p RegNo between instructions [\p
   /// StartMI, \p EndMI]. Some PostRA transformations may violate register
   /// killed/dead flags semantics, this function can be called to fix up. Before
   /// calling this function,
   /// 1. Ensure that \p RegNo liveness is killed after instruction \p EndMI.
   /// 2. Ensure that there is no new definition between (\p StartMI, \p EndMI)
   ///    and possible definition for \p RegNo is \p StartMI or \p EndMI.

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

for (; It != E; ++It) {
     if ((&*It) == &StartMI)
       break;
   }
   // Ensure RegMo liveness is killed after EndMI.
   assert((IsKillSet || (MO && MO->isDead())) &&
          "RegNo should be killed or dead");
 }
 
+// This opt tries to convert the following imm form to an index form to save an
+// add for stack variables.
+// Return false if no such pattern found.
+//
+// ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, OffsetAddi
+// ADD instr:  ToBeDeletedReg = ADD ToBeChangedReg(killed), ScaleReg
+// Imm instr:  Reg            = op OffsetImm, ToBeDeletedReg(killed)
+//
+// can be converted to:
+//
+// new ADDI instr: ToBeChangedReg = ADDI FrameBaseReg, (OffsetAddi + OffsetImm)
+// Index instr:    Reg            = opx ScaleReg, ToBeChangedReg(killed)
+//
+// In order to eliminate ADD instr, make sure that:
+// 1: (OffsetAddi + OffsetImm) must be int16 since this offset will be used in
+//    new ADDI instr and ADDI can only take int16 Imm.
+// 2: ToBeChangedReg must be killed in ADD instr and there is no other use
+//    between ADDI and ADD instr since its original def in ADDI will be changed
+//    in new ADDI instr. And also there should be no new def for it between
+//    ADD and Imm instr as ToBeChangedReg will be used in Index instr.
+// 3: ToBeDeletedReg must be killed in Imm instr and there is no other use
+//    between ADD and Imm instr since ADD instr will be eliminated.
+// 4: ScaleReg must not be redefined between ADD and Imm instr since it will be
+//    moved to Index instr.
+bool PPCInstrInfo::foldFrameOffset(MachineInstr &MI) const {
+  MachineFunction *MF = MI.getParent()->getParent();
+  MachineRegisterInfo *MRI = &MF->getRegInfo();
+  bool PostRA = !MRI->isSSA();
+  // Do this opt after PEI which is after RA. The reason is stack slot expansion
+  // in PEI may expose such opportunities since in PEI, stack slot offsets to
+  // frame base(OffsetAddi) are determined.
+  if (!PostRA)
+    return false;
+  unsigned ToBeDeletedReg = 0;
+  int64_t OffsetImm = 0;
+  unsigned XFormOpcode = 0;
+  ImmInstrInfo III;
+
+  // Check if Imm instr meets requirement.
+  if (!isImmInstrEligibleForFolding(MI, ToBeDeletedReg, XFormOpcode, OffsetImm,
+                                    III))
+    return false;
+
+  bool OtherIntermediateUse = false;
+  MachineInstr *ADDMI = getDefMIPostRA(ToBeDeletedReg, MI, OtherIntermediateUse);
+
+  // Exit if there is other use between ADD and Imm instr or no def found.
+  if (OtherIntermediateUse || !ADDMI)
+    return false;
+
+  // Check if ADD instr meets requirement.
+  if (!isADDInstrEligibleForFolding(*ADDMI))
+    return false;
+
+  unsigned ScaleRegIdx = 0;
+  int64_t OffsetAddi = 0;
+  MachineInstr *ADDIMI = nullptr;
+
+  // Check if there is a valid ToBeChangedReg in ADDMI.
+  // 1: It must be killed.
+  // 2: Its definition must be a valid ADDIMI.
+  // 3: It must satify int16 offset requirement.
+  if (isValidToBeChangedReg(ADDMI, 1, ADDIMI, OffsetAddi, OffsetImm))
+    ScaleRegIdx = 2;
+  else if (isValidToBeChangedReg(ADDMI, 2, ADDIMI, OffsetAddi, OffsetImm))
+    ScaleRegIdx = 1;
+  else
+    return false;
+
+  assert(ADDIMI && "There should be ADDIMI for valid ToBeChangedReg.");
+  unsigned ToBeChangedReg = ADDIMI->getOperand(0).getReg();
+  unsigned ScaleReg = ADDMI->getOperand(ScaleRegIdx).getReg();
+  auto NewDefFor = [&](unsigned Reg, MachineBasicBlock::iterator Start,
+                       MachineBasicBlock::iterator End) {
+    for (auto It = ++Start; It != End; It++)
+      if (It->modifiesRegister(Reg, &getRegisterInfo()))
+        return true;
+    return false;
+  };
+  // Make sure no other def for ToBeChangedReg and ScaleReg between ADD Instr
+  // and Imm Instr.
+  if (NewDefFor(ToBeChangedReg, *ADDMI, MI) || NewDefFor(ScaleReg, *ADDMI, MI))
+    return false;
+
+  // Now start to do the transformation.
+  LLVM_DEBUG(dbgs() << "Replace instruction: "
+                    << "\n");
+  LLVM_DEBUG(ADDIMI->dump());
+  LLVM_DEBUG(ADDMI->dump());
+  LLVM_DEBUG(MI.dump());
+  LLVM_DEBUG(dbgs() << "with: "
+                    << "\n");
+
+  // Update ADDI instr.
+  ADDIMI->getOperand(2).setImm(OffsetAddi + OffsetImm);
+
+  // Update Imm instr.
+  MI.setDesc(get(XFormOpcode));
+  MI.getOperand(III.ImmOpNo)
+      .ChangeToRegister(ScaleReg, false, false,
+                        ADDMI->getOperand(ScaleRegIdx).isKill());
+
+  MI.getOperand(III.OpNoForForwarding)
+      .ChangeToRegister(ToBeChangedReg, false, false, true);
+
+  // Eliminate ADD instr.
+  ADDMI->eraseFromParent();
+
+  LLVM_DEBUG(ADDIMI->dump());
+  LLVM_DEBUG(MI.dump());
+
+  return true;
+}
+
+bool PPCInstrInfo::isADDIInstrEligibleForFolding(MachineInstr &ADDIMI,
+                                                 int64_t &Imm) const {
+  unsigned Opc = ADDIMI.getOpcode();
+
+  // Exit if the instruction is not ADDI.
+  if (Opc != PPC::ADDI && Opc != PPC::ADDI8)
+    return false;
+
+  Imm = ADDIMI.getOperand(2).getImm();
+
+  return true;
+}
+
+bool PPCInstrInfo::isADDInstrEligibleForFolding(MachineInstr &ADDMI) const {
+  unsigned Opc = ADDMI.getOpcode();
+
+  // Exit if the instruction is not ADD.
+  return Opc == PPC::ADD4 || Opc == PPC::ADD8;
+}
+
+bool PPCInstrInfo::isImmInstrEligibleForFolding(MachineInstr &MI,
+                                                unsigned &ToBeDeletedReg,
+                                                unsigned &XFormOpcode,
+                                                int64_t &OffsetImm,
+                                                ImmInstrInfo &III) const {
+  // Only handle load/store.
+  if (!MI.mayLoadOrStore())
+    return false;
+
+  unsigned Opc = MI.getOpcode();
+
+  XFormOpcode = RI.getMappedIdxOpcForImmOpc(Opc);
+
+  // Exit if instruction has no index form.
+  if (XFormOpcode == PPC::INSTRUCTION_LIST_END)
+    return false;
+
+  // TODO: sync the logic between instrHasImmForm() and ImmToIdxMap.
+  if (!instrHasImmForm(XFormOpcode, isVFRegister(MI.getOperand(0).getReg()),
+                       III, true))
+    return false;
+
+  if (!III.IsSummingOperands)
+    return false;
+
+  MachineOperand ImmOperand = MI.getOperand(III.ImmOpNo);
+  MachineOperand RegOperand = MI.getOperand(III.OpNoForForwarding);
+  // Only support imm operands, not relocation slots or others.
+  if (!ImmOperand.isImm())
+    return false;
+
+  assert(RegOperand.isReg() && "Instruction format is not right");
+
+  // There are other use for ToBeDeletedReg after Imm instr, can not delete it.
+  if (!RegOperand.isKill())
+    return false;
+
+  ToBeDeletedReg = RegOperand.getReg();
+  OffsetImm = ImmOperand.getImm();
+
+  return true;
+}
+
+bool PPCInstrInfo::isValidToBeChangedReg(MachineInstr *ADDMI, unsigned Index,
+                                         MachineInstr *&ADDIMI,
+                                         int64_t &OffsetAddi,
+                                         int64_t OffsetImm) const {
+  assert((Index == 1 || Index == 2) && "Invalid operand index for add.");
+  MachineOperand &MO = ADDMI->getOperand(Index);
+
+  if (!MO.isKill())
+    return false;
+
+  bool OtherIntermediateUse = false;
+
+  ADDIMI = getDefMIPostRA(MO.getReg(), *ADDMI, OtherIntermediateUse);
+  // Currently handle only one "add + Imminstr" pair case, exit if other
+  // intermediate use for ToBeChangedReg found.
+  // TODO: handle the cases where there are other "add + Imminstr" pairs
+  // with same offset in Imminstr which is like:
+  //
+  // ADDI instr: ToBeChangedReg  = ADDI FrameBaseReg, OffsetAddi
+  // ADD instr1: ToBeDeletedReg1 = ADD ToBeChangedReg, ScaleReg1
+  // Imm instr1: Reg1            = op1 OffsetImm, ToBeDeletedReg1(killed)
+  // ADD instr2: ToBeDeletedReg2 = ADD ToBeChangedReg(killed), ScaleReg2
+  // Imm instr2: Reg2            = op2 OffsetImm, ToBeDeletedReg2(killed)
+  //
+  // can be converted to:
+  //
+  // new ADDI instr: ToBeChangedReg = ADDI FrameBaseReg,
+  //                                       (OffsetAddi + OffsetImm)
+  // Index instr1:   Reg1           = opx1 ScaleReg1, ToBeChangedReg
+  // Index instr2:   Reg2           = opx2 ScaleReg2, ToBeChangedReg(killed)
+
+  if (OtherIntermediateUse || !ADDIMI)
+    return false;
+  // Check if ADDI instr meets requirement.
+  if (!isADDIInstrEligibleForFolding(*ADDIMI, OffsetAddi))
+    return false;
+
+  if (isInt<16>(OffsetAddi + OffsetImm))
+    return true;
+  return false;
+}
+
 // If this instruction has an immediate form and one of its operands is a
 // result of a load-immediate or an add-immediate, convert it to
 // the immediate form if the constant is in range.
 bool PPCInstrInfo::convertToImmediateForm(MachineInstr &MI,
                                           MachineInstr **KilledDef) const {
   MachineFunction *MF = MI.getParent()->getParent();
   MachineRegisterInfo *MRI = &MF->getRegInfo();
   bool PostRA = !MRI->isSSA();

llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp

 #define DEBUG_TYPE "ppc-pre-emit-peephole"
 
 STATISTIC(NumRRConvertedInPreEmit,
           "Number of r+r instructions converted to r+i in pre-emit peephole");
 STATISTIC(NumRemovedInPreEmit,
           "Number of instructions deleted in pre-emit peephole");
 STATISTIC(NumberOfSelfCopies,
           "Number of self copy instructions eliminated");
+STATISTIC(NumFrameOffFoldInPreEmit,
+          "Number of folding frame offset by using r+r in pre-emit peephole");
 
 static cl::opt<bool>
 RunPreEmitPeephole("ppc-late-peephole", cl::Hidden, cl::init(true),
                    cl::desc("Run pre-emit peephole optimizations."));
 
 namespace {
   class PPCPreEmitPeephole : public MachineFunctionPass {
   public:
bool runOnMachineFunction(MachineFunction &MF) override {
             Changed = true;
             NumRRConvertedInPreEmit++;
             LLVM_DEBUG(dbgs() << "Converted instruction to imm form: ");
             LLVM_DEBUG(MI.dump());
             if (DefMIToErase) {
               InstrsToErase.push_back(DefMIToErase);
             }
           }
+          if (TII->foldFrameOffset(MI)) {
+            Changed = true;
+            NumFrameOffFoldInPreEmit++;
+            LLVM_DEBUG(dbgs() << "Frame offset folding by using index form: ");
+            LLVM_DEBUG(MI.dump());
+          }
         }
 
         // Eliminate conditional branch based on a constant CR bit by
         // CRSET or CRUNSET. We eliminate the conditional branch or
         // convert it into an unconditional branch. Also, if the CR bit
         // is not used by other instructions, we eliminate CRSET as well.
         auto I = MBB.getFirstInstrTerminator();
         if (I == MBB.instr_end())

llvm/lib/Target/PowerPC/PPCRegisterInfo.h

 
 class PPCRegisterInfo : public PPCGenRegisterInfo {
   DenseMap<unsigned, unsigned> ImmToIdxMap;
   const PPCTargetMachine &TM;
 
 public:
   PPCRegisterInfo(const PPCTargetMachine &TM);
 
+  /// getMappedIdxOpcForImmOpc - Return the mapped index form load/store opcode
+  /// for a given imm form load/store opcode \p ImmFormOpcode.
+  /// FIXME: move this to PPCInstrInfo class.
+  unsigned getMappedIdxOpcForImmOpc(unsigned ImmOpcode) const {
+    if (!ImmToIdxMap.count(ImmOpcode))
+      return PPC::INSTRUCTION_LIST_END;
+    return ImmToIdxMap.find(ImmOpcode)->second;
+  }
+
   /// getPointerRegClass - Return the register class to use to hold pointers.
   /// This is used for addressing modes.
   const TargetRegisterClass *
   getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const override;
 
   unsigned getRegPressureLimit(const TargetRegisterClass *RC,
                                MachineFunction &MF) const override;
 

llvm/test/CodeGen/PowerPC/fold-frame-offset-using-rr.mir

 name: testIndexForm1
 #CHECK : name : testIndexForm1
 # ToBeDeletedReg equals to ScaleReg
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3, $x1, $x4, $x6
     $x3 = ADDI8 $x1, -80
-    ; CHECK: $x3 = ADDI8 $x1, -80
+    ; CHECK: $x3 = ADDI8 $x1, -76
     $x4 = ADD8 killed $x3, killed $x4
-    ; CHECK: $x4 = ADD8 killed $x3, killed $x4
+    ; CHECK-NOT: ADD8
     $x6 = LD 4, killed $x4
-    ; CHECK: $x6 = LD 4, killed $x4
+    ; CHECK: $x6 = LDX killed $x4, killed $x3
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: testIndexForm2
 #CHECK : name : testIndexForm2
 # ToBeDeletedReg equals to ToBeChangedReg
 tracksRegLiveness: true
 body: |
   bb.0.entry:
     liveins: $x3, $x1, $x4, $x6
     $x3 = ADDI8 $x1, -80
-    ; CHECK: $x3 = ADDI8 $x1, -80
+    ; CHECK: $x3 = ADDI8 $x1, -76
     $x3 = ADD8 killed $x3, killed $x4
-    ; CHECK: $x3 = ADD8 killed $x3, killed $x4
+    ; CHECK-NOT: ADD8
     $x6 = LD 4, killed $x3
-    ; CHECK: $x6 = LD 4, killed $x3
+    ; CHECK: $x6 = LDX killed $x4, killed $x3
     BLR8 implicit $lr8, implicit $rm
 ...
 ---
 name: testIndexForm3
 #CHECK : name : testIndexForm3
 # There is other use for ToBeDeletedReg between ADD instr and Imm instr
 tracksRegLiveness: true
 body: |
bb.0.entry:
     ; CHECK: $x3 = ADDI8 $x1, -80
     $x4 = ADD8 killed $x3, killed $x4
     ; CHECK: $x4 = ADD8 killed $x3, killed $x4
     $x6 = LD 4, $x4
     ; CHECK: $x6 = LD 4, $x4
     STD killed $x4, killed $x6, 100
     BLR8 implicit $lr8, implicit $rm
 ...
+---
+name: testIndexForm7
+#CHECK : name : testIndexForm7
+# There is other def for ToBeChangedReg between ADD instr and Imm instr
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3, $x1, $x4, $x5, $x6
+    $x3 = ADDI8 $x1, -80
+    ; CHECK: $x3 = ADDI8 $x1, -80
+    $x4 = ADD8 killed $x3, killed $x5
+    ; CHECK: $x4 = ADD8 killed $x3, killed $x5
+    $x3 = LD 100, $x6
+    ; CHECK: $x3 = LD 100, $x6
+    STD killed $x3, killed $x6, 200
+    ; CHECK: STD killed $x3, killed $x6, 200
+    $x6 = LD 4, killed $x4
+    ; CHECK: $x6 = LD 4, killed $x4
+    BLR8 implicit $lr8, implicit $rm
+...
+---
+name: testIndexForm8
+#CHECK : name : testIndexForm8
+# There is other def for ScaleReg between ADD instr and Imm instr
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3, $x1, $x4, $x5, $x6
+    $x3 = ADDI8 $x1, -80
+    ; CHECK: $x3 = ADDI8 $x1, -80
+    $x4 = ADD8 killed $x3, killed $x5
+    ; CHECK: $x4 = ADD8 killed $x3, killed $x5
+    $x5 = LD 100, $x6
+    ; CHECK: $x5 = LD 100, $x6
+    STD killed $x5, killed $x6, 200
+    ; CHECK: STD killed $x5, killed $x6, 200
+    $x6 = LD 4, killed $x4
+    ; CHECK: $x6 = LD 4, killed $x4
+    BLR8 implicit $lr8, implicit $rm
+...