[RISCV] Add Option for Printing Architectural Register Names

[lenary]

Summary

This is an option primarily to use during testing. Instead of always
printing registers using their ABI names, this allows a user to request they
are printed with their architectural name.

This is then used in the register constraint tests to ensure the mapping
between architectural and abi names is correct.

[asb]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

44 ↗

(On Diff #214143)

The description makes it unclear that this affects FPRs as well. Maybe "architectural register names such as x0-x31 rather than the ABI name"?

[lenary]

Address review feeback

• Clarify flag name and description

[apazos]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

43 ↗

(On Diff #214147)

Do we really need another flag? Or can we just reuse riscv-no-aliases?

I think with GNU toolchain, and when calling llvm-mc/llvm-objdump , -M no-aliases will avoid printing any aliases including architecture aliases. There is no separate flag for controlling printing arch reg names.

[lenary]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

43 ↗

(On Diff #214147)

I checked with my version of objdump (seems to be version 2.32) and it separates -M no-aliases and -M numeric (the latter of which prints the architectural register names). I'm happy to rename the flag, but the flags do seem to be separate.

I also thought a separate flag would be a less invasive change.

This flag definition becomes the definition for llvm-mc, and we don't yet support target-specific options using the -M flag for risc-v (but we should).

[luismarques]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

44 ↗

(On Diff #214147)

Giving an example ("such as") and providing a range ("x0-x31", which tends to suggest it describes the range of possibilities) seems a bit of a weird mismatch. Some possible alternatives:

• "such as x0"
• "such as x0, f8, v3..."
• "such as x2, instead of sp"?

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h

51 ↗

(On Diff #214147)

Does this fall under the umbrella of the unsigned -> Register type transition? If so, please update the patch accordingly. (Apply the comment to the other cases in this patch).

[lenary]

Address review feedback

• Update flag description

[lenary]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h

51 ↗

(On Diff #214147)

Not yet, because the two-argument version is generated by tablegen.

[asb]

LGTM, thanks!

[asb]

Actually changing my mind. This would be better tested by adopting something like arch-reg-names.s from D66139 (and extending that to handle FP regs), and leaving the inline-asm tests alone (huge increase in test size, which makes them harder to follow). Make that change, and then it looks good to me.

[lenary]

Address Review Feedback:

• Use numeric-reg-names*.s, based on arch-reg-names.s from D66139
• Revert changes to inline-asm-*abi-names.ll
• Rebase changes

[lenary]

Tests updated, they're now a more reasonable size. I'll need to update D66139.

[asb]

LGTM, thanks!

llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h

public:
   // Autogenerated by tblgen.
   void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
                         raw_ostream &O);
   bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
                        raw_ostream &O);
   void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
                                unsigned PrintMethodIdx,
                                const MCSubtargetInfo &STI, raw_ostream &O);
-  static const char *getRegisterName(unsigned RegNo,
-                                     unsigned AltIdx = RISCV::ABIRegAltName);
+  static const char *getRegisterName(unsigned RegNo);
+  static const char *getRegisterName(unsigned RegNo, unsigned AltIdx);
 };
 } // namespace llvm
 
 #endif

llvm/trunk/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

 #define GEN_UNCOMPRESS_INSTR
 #include "RISCVGenCompressInstEmitter.inc"
 
 static cl::opt<bool>
     NoAliases("riscv-no-aliases",
               cl::desc("Disable the emission of assembler pseudo instructions"),
               cl::init(false), cl::Hidden);
 
+static cl::opt<bool>
+    ArchRegNames("riscv-arch-reg-names",
+                 cl::desc("Print architectural register names rather than the "
+                          "ABI names (such as x2 instead of sp)"),
+                 cl::init(false), cl::Hidden);
+
 void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
                                  StringRef Annot, const MCSubtargetInfo &STI) {
   bool Res = false;
   const MCInst *NewMI = MI;
   MCInst UncompressedMI;
   if (!NoAliases)
     Res = uncompressInst(UncompressedMI, *MI, MRI, STI);
   if (Res)
void RISCVInstPrinter::printAtomicMemOp(const MCInst *MI, unsigned OpNo,
   const MCOperand &MO = MI->getOperand(OpNo);
 
   assert(MO.isReg() && "printAtomicMemOp can only print register operands");
   O << "(";
   printRegName(O, MO.getReg());
   O << ")";
   return;
 }
+
+const char *RISCVInstPrinter::getRegisterName(unsigned RegNo) {
+  return getRegisterName(RegNo, ArchRegNames ? RISCV::NoRegAltName
+                                             : RISCV::ABIRegAltName);
+}

llvm/trunk/test/MC/RISCV/numeric-reg-names-d.s

+# RUN: llvm-mc -triple riscv32 -mattr=+f,+d < %s -riscv-arch-reg-names \
+# RUN:     | FileCheck -check-prefix=CHECK-NUMERIC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f,+d < %s \
+# RUN:     | llvm-objdump -mattr=+f,+d -d -riscv-arch-reg-names - \
+# RUN:     | FileCheck -check-prefix=CHECK-NUMERIC %s
+
+# CHECK-NUMERIC: fsqrt.d f10, f0
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f0
+fsqrt.d fa0, f0
+fsqrt.d fa0, ft0
+
+# CHECK-NUMERIC: fsqrt.d f10, f1
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f1
+fsqrt.d fa0, f1
+fsqrt.d fa0, ft1
+
+# CHECK-NUMERIC: fsqrt.d f10, f2
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f2
+fsqrt.d fa0, f2
+fsqrt.d fa0, ft2
+
+# CHECK-NUMERIC: fsqrt.d f10, f3
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f3
+fsqrt.d fa0, f3
+fsqrt.d fa0, ft3
+
+# CHECK-NUMERIC: fsqrt.d f10, f4
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f4
+fsqrt.d fa0, f4
+fsqrt.d fa0, ft4
+
+# CHECK-NUMERIC: fsqrt.d f10, f5
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f5
+fsqrt.d fa0, f5
+fsqrt.d fa0, ft5
+
+# CHECK-NUMERIC: fsqrt.d f10, f6
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f6
+fsqrt.d fa0, f6
+fsqrt.d fa0, ft6
+
+# CHECK-NUMERIC: fsqrt.d f10, f7
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f7
+fsqrt.d fa0, f7
+fsqrt.d fa0, ft7
+
+# CHECK-NUMERIC: fsqrt.d f10, f8
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f8
+fsqrt.d fa0, f8
+fsqrt.d fa0, fs0
+
+# CHECK-NUMERIC: fsqrt.d f10, f9
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f9
+fsqrt.d fa0, f9
+fsqrt.d fa0, fs1
+
+# CHECK-NUMERIC: fsqrt.d f10, f10
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f10
+fsqrt.d fa0, f10
+fsqrt.d fa0, fa0
+
+# CHECK-NUMERIC: fsqrt.d f10, f11
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f11
+fsqrt.d fa0, f11
+fsqrt.d fa0, fa1
+
+# CHECK-NUMERIC: fsqrt.d f10, f12
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f12
+fsqrt.d fa0, f12
+fsqrt.d fa0, fa2
+
+# CHECK-NUMERIC: fsqrt.d f10, f13
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f13
+fsqrt.d fa0, f13
+fsqrt.d fa0, fa3
+
+# CHECK-NUMERIC: fsqrt.d f10, f14
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f14
+fsqrt.d fa0, f14
+fsqrt.d fa0, fa4
+
+# CHECK-NUMERIC: fsqrt.d f10, f15
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f15
+fsqrt.d fa0, f15
+fsqrt.d fa0, fa5
+
+# CHECK-NUMERIC: fsqrt.d f10, f16
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f16
+fsqrt.d fa0, f16
+fsqrt.d fa0, fa6
+
+# CHECK-NUMERIC: fsqrt.d f10, f17
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f17
+fsqrt.d fa0, f17
+fsqrt.d fa0, fa7
+
+# CHECK-NUMERIC: fsqrt.d f10, f18
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f18
+fsqrt.d fa0, f18
+fsqrt.d fa0, fs2
+
+# CHECK-NUMERIC: fsqrt.d f10, f19
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f19
+fsqrt.d fa0, f19
+fsqrt.d fa0, fs3
+
+# CHECK-NUMERIC: fsqrt.d f10, f20
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f20
+fsqrt.d fa0, f20
+fsqrt.d fa0, fs4
+
+# CHECK-NUMERIC: fsqrt.d f10, f21
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f21
+fsqrt.d fa0, f21
+fsqrt.d fa0, fs5
+
+# CHECK-NUMERIC: fsqrt.d f10, f22
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f22
+fsqrt.d fa0, f22
+fsqrt.d fa0, fs6
+
+# CHECK-NUMERIC: fsqrt.d f10, f23
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f23
+fsqrt.d fa0, f23
+fsqrt.d fa0, fs7
+
+# CHECK-NUMERIC: fsqrt.d f10, f24
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f24
+fsqrt.d fa0, f24
+fsqrt.d fa0, fs8
+
+# CHECK-NUMERIC: fsqrt.d f10, f25
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f25
+fsqrt.d fa0, f25
+fsqrt.d fa0, fs9
+
+# CHECK-NUMERIC: fsqrt.d f10, f26
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f26
+fsqrt.d fa0, f26
+fsqrt.d fa0, fs10
+
+# CHECK-NUMERIC: fsqrt.d f10, f27
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f27
+fsqrt.d fa0, f27
+fsqrt.d fa0, fs11
+
+# CHECK-NUMERIC: fsqrt.d f10, f28
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f28
+fsqrt.d fa0, f28
+fsqrt.d fa0, ft8
+
+# CHECK-NUMERIC: fsqrt.d f10, f29
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f29
+fsqrt.d fa0, f29
+fsqrt.d fa0, ft9
+
+# CHECK-NUMERIC: fsqrt.d f10, f30
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f30
+fsqrt.d fa0, f30
+fsqrt.d fa0, ft10
+
+# CHECK-NUMERIC: fsqrt.d f10, f31
+# CHECK-NUMERIC-NEXT: fsqrt.d f10, f31
+fsqrt.d fa0, f31
+fsqrt.d fa0, ft11

llvm/trunk/test/MC/RISCV/numeric-reg-names-f.s

+# RUN: llvm-mc -triple riscv32 -mattr=+f < %s -riscv-arch-reg-names \
+# RUN:     | FileCheck -check-prefix=CHECK-NUMERIC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
+# RUN:     | llvm-objdump -mattr=+f -d -riscv-arch-reg-names - \
+# RUN:     | FileCheck -check-prefix=CHECK-NUMERIC %s
+
+# CHECK-NUMERIC: fsqrt.s f10, f0
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f0
+fsqrt.s fa0, f0
+fsqrt.s fa0, ft0
+
+# CHECK-NUMERIC: fsqrt.s f10, f1
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f1
+fsqrt.s fa0, f1
+fsqrt.s fa0, ft1
+
+# CHECK-NUMERIC: fsqrt.s f10, f2
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f2
+fsqrt.s fa0, f2
+fsqrt.s fa0, ft2
+
+# CHECK-NUMERIC: fsqrt.s f10, f3
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f3
+fsqrt.s fa0, f3
+fsqrt.s fa0, ft3
+
+# CHECK-NUMERIC: fsqrt.s f10, f4
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f4
+fsqrt.s fa0, f4
+fsqrt.s fa0, ft4
+
+# CHECK-NUMERIC: fsqrt.s f10, f5
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f5
+fsqrt.s fa0, f5
+fsqrt.s fa0, ft5
+
+# CHECK-NUMERIC: fsqrt.s f10, f6
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f6
+fsqrt.s fa0, f6
+fsqrt.s fa0, ft6
+
+# CHECK-NUMERIC: fsqrt.s f10, f7
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f7
+fsqrt.s fa0, f7
+fsqrt.s fa0, ft7
+
+# CHECK-NUMERIC: fsqrt.s f10, f8
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f8
+fsqrt.s fa0, f8
+fsqrt.s fa0, fs0
+
+# CHECK-NUMERIC: fsqrt.s f10, f9
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f9
+fsqrt.s fa0, f9
+fsqrt.s fa0, fs1
+
+# CHECK-NUMERIC: fsqrt.s f10, f10
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f10
+fsqrt.s fa0, f10
+fsqrt.s fa0, fa0
+
+# CHECK-NUMERIC: fsqrt.s f10, f11
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f11
+fsqrt.s fa0, f11
+fsqrt.s fa0, fa1
+
+# CHECK-NUMERIC: fsqrt.s f10, f12
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f12
+fsqrt.s fa0, f12
+fsqrt.s fa0, fa2
+
+# CHECK-NUMERIC: fsqrt.s f10, f13
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f13
+fsqrt.s fa0, f13
+fsqrt.s fa0, fa3
+
+# CHECK-NUMERIC: fsqrt.s f10, f14
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f14
+fsqrt.s fa0, f14
+fsqrt.s fa0, fa4
+
+# CHECK-NUMERIC: fsqrt.s f10, f15
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f15
+fsqrt.s fa0, f15
+fsqrt.s fa0, fa5
+
+# CHECK-NUMERIC: fsqrt.s f10, f16
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f16
+fsqrt.s fa0, f16
+fsqrt.s fa0, fa6
+
+# CHECK-NUMERIC: fsqrt.s f10, f17
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f17
+fsqrt.s fa0, f17
+fsqrt.s fa0, fa7
+
+# CHECK-NUMERIC: fsqrt.s f10, f18
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f18
+fsqrt.s fa0, f18
+fsqrt.s fa0, fs2
+
+# CHECK-NUMERIC: fsqrt.s f10, f19
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f19
+fsqrt.s fa0, f19
+fsqrt.s fa0, fs3
+
+# CHECK-NUMERIC: fsqrt.s f10, f20
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f20
+fsqrt.s fa0, f20
+fsqrt.s fa0, fs4
+
+# CHECK-NUMERIC: fsqrt.s f10, f21
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f21
+fsqrt.s fa0, f21
+fsqrt.s fa0, fs5
+
+# CHECK-NUMERIC: fsqrt.s f10, f22
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f22
+fsqrt.s fa0, f22
+fsqrt.s fa0, fs6
+
+# CHECK-NUMERIC: fsqrt.s f10, f23
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f23
+fsqrt.s fa0, f23
+fsqrt.s fa0, fs7
+
+# CHECK-NUMERIC: fsqrt.s f10, f24
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f24
+fsqrt.s fa0, f24
+fsqrt.s fa0, fs8
+
+# CHECK-NUMERIC: fsqrt.s f10, f25
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f25
+fsqrt.s fa0, f25
+fsqrt.s fa0, fs9
+
+# CHECK-NUMERIC: fsqrt.s f10, f26
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f26
+fsqrt.s fa0, f26
+fsqrt.s fa0, fs10
+
+# CHECK-NUMERIC: fsqrt.s f10, f27
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f27
+fsqrt.s fa0, f27
+fsqrt.s fa0, fs11
+
+# CHECK-NUMERIC: fsqrt.s f10, f28
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f28
+fsqrt.s fa0, f28
+fsqrt.s fa0, ft8
+
+# CHECK-NUMERIC: fsqrt.s f10, f29
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f29
+fsqrt.s fa0, f29
+fsqrt.s fa0, ft9
+
+# CHECK-NUMERIC: fsqrt.s f10, f30
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f30
+fsqrt.s fa0, f30
+fsqrt.s fa0, ft10
+
+# CHECK-NUMERIC: fsqrt.s f10, f31
+# CHECK-NUMERIC-NEXT: fsqrt.s f10, f31
+fsqrt.s fa0, f31
+fsqrt.s fa0, ft11

llvm/trunk/test/MC/RISCV/numeric-reg-names.s

+# RUN: llvm-mc -triple riscv32 < %s -riscv-arch-reg-names \
+# RUN:     | FileCheck -check-prefix=CHECK-NUMERIC %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:     | llvm-objdump -d -riscv-arch-reg-names - \
+# RUN:     | FileCheck -check-prefix=CHECK-NUMERIC %s
+
+# CHECK-NUMERIC: addi x10, x0, 1
+# CHECK-NUMERIC-NEXT: addi x10, x0, 1
+addi a0, x0, 1
+addi a0, zero, 1
+
+# CHECK-NUMERIC: addi x10, x1, 1
+# CHECK-NUMERIC-NEXT: addi x10, x1, 1
+addi a0, x1, 1
+addi a0, ra, 1
+
+# CHECK-NUMERIC: addi x10, x2, 1
+# CHECK-NUMERIC-NEXT: addi x10, x2, 1
+addi a0, x2, 1
+addi a0, sp, 1
+
+# CHECK-NUMERIC: addi x10, x3, 1
+# CHECK-NUMERIC-NEXT: addi x10, x3, 1
+addi a0, x3, 1
+addi a0, gp, 1
+
+# CHECK-NUMERIC: addi x10, x4, 1
+# CHECK-NUMERIC-NEXT: addi x10, x4, 1
+addi a0, x4, 1
+addi a0, tp, 1
+
+# CHECK-NUMERIC: addi x10, x5, 1
+# CHECK-NUMERIC-NEXT: addi x10, x5, 1
+addi a0, x5, 1
+addi a0, t0, 1
+
+# CHECK-NUMERIC: addi x10, x6, 1
+# CHECK-NUMERIC-NEXT: addi x10, x6, 1
+addi a0, x6, 1
+addi a0, t1, 1
+
+# CHECK-NUMERIC: addi x10, x7, 1
+# CHECK-NUMERIC-NEXT: addi x10, x7, 1
+addi a0, x7, 1
+addi a0, t2, 1
+
+# CHECK-NUMERIC: addi x10, x8, 1
+# CHECK-NUMERIC-NEXT: addi x10, x8, 1
+# CHECK-NUMERIC-NEXT: addi x10, x8, 1
+addi a0, x8, 1
+addi a0, s0, 1
+addi a0, fp, 1
+
+# CHECK-NUMERIC: addi x10, x9, 1
+# CHECK-NUMERIC-NEXT: addi x10, x9, 1
+addi a0, x9, 1
+addi a0, s1, 1
+
+# CHECK-NUMERIC: addi x10, x10, 1
+# CHECK-NUMERIC-NEXT: addi x10, x10, 1
+addi a0, x10, 1
+addi a0, a0, 1
+
+# CHECK-NUMERIC: addi x10, x11, 1
+# CHECK-NUMERIC-NEXT: addi x10, x11, 1
+addi a0, x11, 1
+addi a0, a1, 1
+
+# CHECK-NUMERIC: addi x10, x12, 1
+# CHECK-NUMERIC-NEXT: addi x10, x12, 1
+addi a0, x12, 1
+addi a0, a2, 1
+
+# CHECK-NUMERIC: addi x10, x13, 1
+# CHECK-NUMERIC-NEXT: addi x10, x13, 1
+addi a0, x13, 1
+addi a0, a3, 1
+
+# CHECK-NUMERIC: addi x10, x14, 1
+# CHECK-NUMERIC-NEXT: addi x10, x14, 1
+addi a0, x14, 1
+addi a0, a4, 1
+
+# CHECK-NUMERIC: addi x10, x15, 1
+# CHECK-NUMERIC-NEXT: addi x10, x15, 1
+addi a0, x15, 1
+addi a0, a5, 1
+
+# CHECK-NUMERIC: addi x10, x16, 1
+# CHECK-NUMERIC-NEXT: addi x10, x16, 1
+addi a0, x16, 1
+addi a0, a6, 1
+
+# CHECK-NUMERIC: addi x10, x17, 1
+# CHECK-NUMERIC-NEXT: addi x10, x17, 1
+addi a0, x17, 1
+addi a0, a7, 1
+
+# CHECK-NUMERIC: addi x10, x18, 1
+# CHECK-NUMERIC-NEXT: addi x10, x18, 1
+addi a0, x18, 1
+addi a0, s2, 1
+
+# CHECK-NUMERIC: addi x10, x19, 1
+# CHECK-NUMERIC-NEXT: addi x10, x19, 1
+addi a0, x19, 1
+addi a0, s3, 1
+
+# CHECK-NUMERIC: addi x10, x20, 1
+# CHECK-NUMERIC-NEXT: addi x10, x20, 1
+addi a0, x20, 1
+addi a0, s4, 1
+
+# CHECK-NUMERIC: addi x10, x21, 1
+# CHECK-NUMERIC-NEXT: addi x10, x21, 1
+addi a0, x21, 1
+addi a0, s5, 1
+
+# CHECK-NUMERIC: addi x10, x22, 1
+# CHECK-NUMERIC-NEXT: addi x10, x22, 1
+addi a0, x22, 1
+addi a0, s6, 1
+
+# CHECK-NUMERIC: addi x10, x23, 1
+# CHECK-NUMERIC-NEXT: addi x10, x23, 1
+addi a0, x23, 1
+addi a0, s7, 1
+
+# CHECK-NUMERIC: addi x10, x24, 1
+# CHECK-NUMERIC-NEXT: addi x10, x24, 1
+addi a0, x24, 1
+addi a0, s8, 1
+
+# CHECK-NUMERIC: addi x10, x25, 1
+# CHECK-NUMERIC-NEXT: addi x10, x25, 1
+addi a0, x25, 1
+addi a0, s9, 1
+
+# CHECK-NUMERIC: addi x10, x26, 1
+# CHECK-NUMERIC-NEXT: addi x10, x26, 1
+addi a0, x26, 1
+addi a0, s10, 1
+
+# CHECK-NUMERIC: addi x10, x27, 1
+# CHECK-NUMERIC-NEXT: addi x10, x27, 1
+addi a0, x27, 1
+addi a0, s11, 1
+
+# CHECK-NUMERIC: addi x10, x28, 1
+# CHECK-NUMERIC-NEXT: addi x10, x28, 1
+addi a0, x28, 1
+addi a0, t3, 1
+
+# CHECK-NUMERIC: addi x10, x29, 1
+# CHECK-NUMERIC-NEXT: addi x10, x29, 1
+addi a0, x29, 1
+addi a0, t4, 1
+
+# CHECK-NUMERIC: addi x10, x30, 1
+# CHECK-NUMERIC-NEXT: addi x10, x30, 1
+addi a0, x30, 1
+addi a0, t5, 1
+
+# CHECK-NUMERIC: addi x10, x31, 1
+# CHECK-NUMERIC-NEXT: addi x10, x31, 1
+addi a0, x31, 1
+addi a0, t6, 1