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Differential D65950

[RISCV] Add Option for Printing Architectural Register Names
ClosedPublic

Authored by lenary on Aug 8 2019, 6:46 AM.

Details

Reviewers
asb
luismarques
Commits
rG6b877f6aac3d: [RISCV] Add Option for Printing Architectural Register Names
rL371531: [RISCV] Add Option for Printing Architectural Register Names
Summary

This is an option primarily to use during testing. Instead of always
printing registers using their ABI names, this allows a user to request they
are printed with their architectural name.

This is then used in the register constraint tests to ensure the mapping
between architectural and abi names is correct.

Diff Detail

Event Timeline

lenary created this revision.Aug 8 2019, 6:46 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 8 2019, 6:46 AM
Herald added subscribers: llvm-commits, s.egerton, Jim and 22 others. · View Herald Transcript
lenary added a parent revision: D65947: [RISCV] Allow ABI Names in Inline Assembly Constraints.Aug 8 2019, 6:46 AM
Harbormaster completed remote builds in B36426: Diff 214143.Aug 8 2019, 6:48 AM
asb added inline comments.Aug 8 2019, 7:00 AM
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
44

The description makes it unclear that this affects FPRs as well. Maybe "architectural register names such as x0-x31 rather than the ABI name"?

lenary updated this revision to Diff 214147.Aug 8 2019, 7:11 AM

Address review feeback

  • Clarify flag name and description
Harbormaster completed remote builds in B36428: Diff 214147.Aug 8 2019, 7:11 AM
lenary marked an inline comment as done.Aug 8 2019, 7:13 AM
lenary added a reviewer: luismarques.Aug 12 2019, 7:49 AM
apazos added inline comments.Aug 12 2019, 2:51 PM
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
43

Do we really need another flag? Or can we just reuse riscv-no-aliases?

I think with GNU toolchain, and when calling llvm-mc/llvm-objdump , -M no-aliases will avoid printing any aliases including architecture aliases. There is no separate flag for controlling printing arch reg names.

lenary marked an inline comment as done.Aug 13 2019, 3:22 AM
lenary added inline comments.
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
43

I checked with my version of objdump (seems to be version 2.32) and it separates -M no-aliases and -M numeric (the latter of which prints the architectural register names). I'm happy to rename the flag, but the flags do seem to be separate.

I also thought a separate flag would be a less invasive change.

This flag definition becomes the definition for llvm-mc, and we don't yet support target-specific options using the -M flag for risc-v (but we should).

lenary added a child revision: D66139: [RISCV] Support llvm-objdump -M no-aliases and -M numeric.Aug 13 2019, 6:03 AM
luismarques mentioned this in D66139: [RISCV] Support llvm-objdump -M no-aliases and -M numeric.Aug 14 2019, 2:53 PM
luismarques added inline comments.Aug 14 2019, 3:16 PM
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
44

Giving an example ("such as") and providing a range ("x0-x31", which tends to suggest it describes the range of possibilities) seems a bit of a weird mismatch. Some possible alternatives:

  • "such as x0"
  • "such as x0, f8, v3..."
  • "such as x2, instead of sp"?
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
51–52

Does this fall under the umbrella of the unsigned -> Register type transition? If so, please update the patch accordingly. (Apply the comment to the other cases in this patch).

lenary updated this revision to Diff 215378.Aug 15 2019, 5:59 AM
lenary marked 2 inline comments as done.

Address review feedback

  • Update flag description
Harbormaster completed remote builds in B36827: Diff 215378.Aug 15 2019, 5:59 AM
lenary marked an inline comment as done.Aug 15 2019, 5:59 AM
lenary added inline comments.
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
51–52

Not yet, because the two-argument version is generated by tablegen.

asb accepted this revision.Aug 19 2019, 5:28 AM

LGTM, thanks!

This revision is now accepted and ready to land.Aug 19 2019, 5:28 AM
Herald added a subscriber: pzheng. · View Herald TranscriptAug 19 2019, 5:28 AM
asb requested changes to this revision.Aug 19 2019, 5:33 AM

Actually changing my mind. This would be better tested by adopting something like arch-reg-names.s from D66139 (and extending that to handle FP regs), and leaving the inline-asm tests alone (huge increase in test size, which makes them harder to follow). Make that change, and then it looks good to me.

This revision now requires changes to proceed.Aug 19 2019, 5:33 AM
lenary updated this revision to Diff 219383.Sep 9 2019, 10:01 AM

Address Review Feedback:

  • Use numeric-reg-names*.s, based on arch-reg-names.s from D66139
  • Revert changes to inline-asm-*abi-names.ll
  • Rebase changes
lenary added a comment.Sep 9 2019, 10:02 AM

Tests updated, they're now a more reasonable size. I'll need to update D66139.

Harbormaster completed remote builds in B37924: Diff 219383.Sep 9 2019, 10:03 AM
asb accepted this revision.Sep 10 2019, 8:37 AM

LGTM, thanks!

This revision is now accepted and ready to land.Sep 10 2019, 8:37 AM
Closed by commit rL371531: [RISCV] Add Option for Printing Architectural Register Names (authored by lenary). · Explain WhySep 10 2019, 8:54 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
MCTargetDesc/
4 lines
11 lines
test/
CodeGen/
RISCV/
1288 lines
1220 lines
1220 lines

Diff 215378

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h

Show First 20 Lines • Show All 42 Lines • ▼ Show 20 Linespublic:
// Autogenerated by tblgen. // Autogenerated by tblgen.
void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI, void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O); raw_ostream &O);
bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI, bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
raw_ostream &O); raw_ostream &O);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx, void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx, unsigned PrintMethodIdx,
const MCSubtargetInfo &STI, raw_ostream &O); const MCSubtargetInfo &STI, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo, static const char *getRegisterName(unsigned RegNo);
unsigned AltIdx = RISCV::ABIRegAltName); static const char *getRegisterName(unsigned RegNo, unsigned AltIdx);
luismarquesUnsubmitted
Done
ReplyInline Actions

Does this fall under the umbrella of the unsigned -> Register type transition? If so, please update the patch accordingly. (Apply the comment to the other cases in this patch).

luismarques: Does this fall under the umbrella of the `unsigned` -> `Register` type transition? If so…
lenaryAuthorUnsubmitted
Done
ReplyInline Actions

Not yet, because the two-argument version is generated by tablegen.

lenary: Not yet, because the two-argument version is generated by tablegen.
}; };
} // namespace llvm } // namespace llvm
#endif #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp

Show All 33 Lines
#define GEN_UNCOMPRESS_INSTR #define GEN_UNCOMPRESS_INSTR
#include "RISCVGenCompressInstEmitter.inc" #include "RISCVGenCompressInstEmitter.inc"
static cl::opt<bool> static cl::opt<bool>
NoAliases("riscv-no-aliases", NoAliases("riscv-no-aliases",
cl::desc("Disable the emission of assembler pseudo instructions"), cl::desc("Disable the emission of assembler pseudo instructions"),
cl::init(false), cl::Hidden); cl::init(false), cl::Hidden);
static cl::opt<bool>
ArchRegNames("riscv-arch-reg-names",
apazosUnsubmitted
Not Done
ReplyInline Actions

Do we really need another flag? Or can we just reuse riscv-no-aliases?

I think with GNU toolchain, and when calling llvm-mc/llvm-objdump , -M no-aliases will avoid printing any aliases including architecture aliases. There is no separate flag for controlling printing arch reg names.

apazos: Do we really need another flag? Or can we just reuse riscv-no-aliases? I think with GNU…
lenaryAuthorUnsubmitted
Done
ReplyInline Actions

I checked with my version of objdump (seems to be version 2.32) and it separates -M no-aliases and -M numeric (the latter of which prints the architectural register names). I'm happy to rename the flag, but the flags do seem to be separate.

I also thought a separate flag would be a less invasive change.

This flag definition becomes the definition for llvm-mc, and we don't yet support target-specific options using the -M flag for risc-v (but we should).

lenary: I checked with my version of objdump (seems to be version 2.32) and it separates `-M no…
cl::desc("Print architectural register names rather than the "
asbUnsubmitted
Done
ReplyInline Actions

The description makes it unclear that this affects FPRs as well. Maybe "architectural register names such as x0-x31 rather than the ABI name"?

asb: The description makes it unclear that this affects FPRs as well. Maybe "architectural register…
luismarquesUnsubmitted
Done
ReplyInline Actions

Giving an example ("such as") and providing a range ("x0-x31", which tends to suggest it describes the range of possibilities) seems a bit of a weird mismatch. Some possible alternatives:

  • "such as x0"
  • "such as x0, f8, v3..."
  • "such as x2, instead of sp"?
luismarques: Giving an example ("such as") and providing a range ("x0-x31", which tends to suggest it…
"ABI names (such as x2 instead of sp)"),
cl::init(false), cl::Hidden);
void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O, void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) { StringRef Annot, const MCSubtargetInfo &STI) {
bool Res = false; bool Res = false;
const MCInst *NewMI = MI; const MCInst *NewMI = MI;
MCInst UncompressedMI; MCInst UncompressedMI;
if (!NoAliases) if (!NoAliases)
Res = uncompressInst(UncompressedMI, *MI, MRI, STI); Res = uncompressInst(UncompressedMI, *MI, MRI, STI);
if (Res) if (Res)
▲ Show 20 Lines • Show All 69 Lines • ▼ Show 20 Linesvoid RISCVInstPrinter::printAtomicMemOp(const MCInst *MI, unsigned OpNo,
const MCOperand &MO = MI->getOperand(OpNo); const MCOperand &MO = MI->getOperand(OpNo);
assert(MO.isReg() && "printAtomicMemOp can only print register operands"); assert(MO.isReg() && "printAtomicMemOp can only print register operands");
O << "("; O << "(";
printRegName(O, MO.getReg()); printRegName(O, MO.getReg());
O << ")"; O << ")";
return; return;
} }
const char *RISCVInstPrinter::getRegisterName(unsigned RegNo) {
return getRegisterName(RegNo, ArchRegNames ? RISCV::NoRegAltName
: RISCV::ABIRegAltName);
}

llvm/test/CodeGen/RISCV/inline-asm-abi-names.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s ; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s ; RUN: | FileCheck -check-prefix=RV64I %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs -riscv-arch-reg-names < %s \
; RUN: | FileCheck -check-prefix=RV32I-NO-ABI %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs -riscv-arch-reg-names < %s \
; RUN: | FileCheck -check-prefix=RV64I-NO-ABI %s
; These test that we can use both the architectural names (x*) and the ABI names ; These test that we can use both the architectural names (x*) and the ABI names
; (a*, s*, t* etc) to refer to registers in inline asm constraint lists. In each ; (a*, s*, t* etc) to refer to registers in inline asm constraint lists. In each
; case, the named register should be used for the source register of the `addi`. ; case, the named register should be used for the source register of the `addi`.
; It is very likely that `a0` will be chosen as the designation register, but ; It is very likely that `a0` will be chosen as the designation register, but
; this is left to the compiler to choose. ; this is left to the compiler to choose.
; ;
; The inline assembly will, by default, contain the ABI names for the registers. ; The inline assembly will, by default, contain the ABI names for the registers,
; unless `-riscv-arch-reg-names` is passed to llc to print the architectural
; names.
; ;
; Parenthesised registers in comments are the other aliases for this register. ; Parenthesised registers in comments are the other aliases for this register.
; NOTE: This test has to pass in 0 to the inline asm, because that's the only ; NOTE: This test has to pass in 0 to the inline asm, because that's the only
; value `x0` (`zero`) can take. ; value `x0` (`zero`) can take.
define i32 @explicit_register_x0() nounwind { define i32 @explicit_register_x0() nounwind {
; RV32I-LABEL: explicit_register_x0: ; RV32I-LABEL: explicit_register_x0:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, zero, 0 ; RV32I-NEXT: addi a0, zero, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x0: ; RV64I-LABEL: explicit_register_x0:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, zero, 0 ; RV64I-NEXT: addi a0, zero, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x0:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x0, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x0:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x0, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x0}"(i32 0) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x0}"(i32 0)
ret i32 %1 ret i32 %1
} }
; NOTE: This test has to pass in 0 to the inline asm, because that's the only ; NOTE: This test has to pass in 0 to the inline asm, because that's the only
; value that `zero` (`x0`) can take. ; value that `zero` (`x0`) can take.
define i32 @explicit_register_zero() nounwind { define i32 @explicit_register_zero() nounwind {
; RV32I-LABEL: explicit_register_zero: ; RV32I-LABEL: explicit_register_zero:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, zero, 0 ; RV32I-NEXT: addi a0, zero, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_zero: ; RV64I-LABEL: explicit_register_zero:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, zero, 0 ; RV64I-NEXT: addi a0, zero, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_zero:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x0, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_zero:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x0, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{zero}"(i32 0) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{zero}"(i32 0)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x1` (`ra`) as an input, so it should be saved. ; NOTE: This test uses `x1` (`ra`) as an input, so it should be saved.
define i32 @explicit_register_x1(i32 %a) nounwind { define i32 @explicit_register_x1(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x1: ; RV32I-LABEL: explicit_register_x1:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: mv ra, a0 ; RV64I-NEXT: mv ra, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, ra, 0 ; RV64I-NEXT: addi a0, ra, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x1:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x1, 12(x2)
; RV32I-NO-ABI-NEXT: mv x1, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x1, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x1, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x1:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x1, 8(x2)
; RV64I-NO-ABI-NEXT: mv x1, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x1, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x1, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x1}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x1}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `ra` (`x1`) as an input, so it should be saved. ; NOTE: This test uses `ra` (`x1`) as an input, so it should be saved.
define i32 @explicit_register_ra(i32 %a) nounwind { define i32 @explicit_register_ra(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_ra: ; RV32I-LABEL: explicit_register_ra:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd ra, 8(sp) ; RV64I-NEXT: sd ra, 8(sp)
; RV64I-NEXT: mv ra, a0 ; RV64I-NEXT: mv ra, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, ra, 0 ; RV64I-NEXT: addi a0, ra, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld ra, 8(sp) ; RV64I-NEXT: ld ra, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_ra:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x1, 12(x2)
; RV32I-NO-ABI-NEXT: mv x1, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x1, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x1, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_ra:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x1, 8(x2)
; RV64I-NO-ABI-NEXT: mv x1, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x1, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x1, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{ra}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{ra}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x2(i32 %a) nounwind { define i32 @explicit_register_x2(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x2: ; RV32I-LABEL: explicit_register_x2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv sp, a0 ; RV32I-NEXT: mv sp, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, sp, 0 ; RV32I-NEXT: addi a0, sp, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x2: ; RV64I-LABEL: explicit_register_x2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv sp, a0 ; RV64I-NEXT: mv sp, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, sp, 0 ; RV64I-NEXT: addi a0, sp, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x2:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x2, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x2, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x2:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x2, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x2, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x2}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x2}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_sp(i32 %a) nounwind { define i32 @explicit_register_sp(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_sp: ; RV32I-LABEL: explicit_register_sp:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv sp, a0 ; RV32I-NEXT: mv sp, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, sp, 0 ; RV32I-NEXT: addi a0, sp, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_sp: ; RV64I-LABEL: explicit_register_sp:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv sp, a0 ; RV64I-NEXT: mv sp, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, sp, 0 ; RV64I-NEXT: addi a0, sp, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_sp:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x2, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x2, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_sp:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x2, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x2, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{sp}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{sp}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x3` (`gp`) as an input, so it should be saved. ; NOTE: This test uses `x3` (`gp`) as an input, so it should be saved.
define i32 @explicit_register_x3(i32 %a) nounwind { define i32 @explicit_register_x3(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x3: ; RV32I-LABEL: explicit_register_x3:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd gp, 8(sp) ; RV64I-NEXT: sd gp, 8(sp)
; RV64I-NEXT: mv gp, a0 ; RV64I-NEXT: mv gp, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, gp, 0 ; RV64I-NEXT: addi a0, gp, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld gp, 8(sp) ; RV64I-NEXT: ld gp, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x3:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x3, 12(x2)
; RV32I-NO-ABI-NEXT: mv x3, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x3, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x3, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x3:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x3, 8(x2)
; RV64I-NO-ABI-NEXT: mv x3, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x3, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x3, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x3}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x3}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `gp` (`x3`) as an input, so it should be saved. ; NOTE: This test uses `gp` (`x3`) as an input, so it should be saved.
define i32 @explicit_register_gp(i32 %a) nounwind { define i32 @explicit_register_gp(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_gp: ; RV32I-LABEL: explicit_register_gp:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd gp, 8(sp) ; RV64I-NEXT: sd gp, 8(sp)
; RV64I-NEXT: mv gp, a0 ; RV64I-NEXT: mv gp, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, gp, 0 ; RV64I-NEXT: addi a0, gp, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld gp, 8(sp) ; RV64I-NEXT: ld gp, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_gp:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x3, 12(x2)
; RV32I-NO-ABI-NEXT: mv x3, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x3, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x3, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_gp:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x3, 8(x2)
; RV64I-NO-ABI-NEXT: mv x3, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x3, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x3, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{gp}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{gp}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x4` (`tp`) as an input, so it should be saved. ; NOTE: This test uses `x4` (`tp`) as an input, so it should be saved.
define i32 @explicit_register_x4(i32 %a) nounwind { define i32 @explicit_register_x4(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x4: ; RV32I-LABEL: explicit_register_x4:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd tp, 8(sp) ; RV64I-NEXT: sd tp, 8(sp)
; RV64I-NEXT: mv tp, a0 ; RV64I-NEXT: mv tp, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, tp, 0 ; RV64I-NEXT: addi a0, tp, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld tp, 8(sp) ; RV64I-NEXT: ld tp, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x4:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x4, 12(x2)
; RV32I-NO-ABI-NEXT: mv x4, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x4, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x4, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x4:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x4, 8(x2)
; RV64I-NO-ABI-NEXT: mv x4, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x4, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x4, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x4}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x4}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `tp` (`x4`) as an input, so it should be saved. ; NOTE: This test uses `tp` (`x4`) as an input, so it should be saved.
define i32 @explicit_register_tp(i32 %a) nounwind { define i32 @explicit_register_tp(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_tp: ; RV32I-LABEL: explicit_register_tp:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd tp, 8(sp) ; RV64I-NEXT: sd tp, 8(sp)
; RV64I-NEXT: mv tp, a0 ; RV64I-NEXT: mv tp, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, tp, 0 ; RV64I-NEXT: addi a0, tp, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld tp, 8(sp) ; RV64I-NEXT: ld tp, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_tp:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x4, 12(x2)
; RV32I-NO-ABI-NEXT: mv x4, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x4, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x4, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_tp:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x4, 8(x2)
; RV64I-NO-ABI-NEXT: mv x4, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x4, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x4, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{tp}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{tp}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x5(i32 %a) nounwind { define i32 @explicit_register_x5(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x5: ; RV32I-LABEL: explicit_register_x5:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv t0, a0 ; RV32I-NEXT: mv t0, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, t0, 0 ; RV32I-NEXT: addi a0, t0, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x5: ; RV64I-LABEL: explicit_register_x5:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv t0, a0 ; RV64I-NEXT: mv t0, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, t0, 0 ; RV64I-NEXT: addi a0, t0, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x5:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x5, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x5, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x5:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x5, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x5, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x5}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x5}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_t0(i32 %a) nounwind { define i32 @explicit_register_t0(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_t0: ; RV32I-LABEL: explicit_register_t0:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv t0, a0 ; RV32I-NEXT: mv t0, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, t0, 0 ; RV32I-NEXT: addi a0, t0, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_t0: ; RV64I-LABEL: explicit_register_t0:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv t0, a0 ; RV64I-NEXT: mv t0, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, t0, 0 ; RV64I-NEXT: addi a0, t0, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_t0:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x5, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x5, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_t0:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x5, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x5, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{t0}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t0}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x6(i32 %a) nounwind { define i32 @explicit_register_x6(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x6: ; RV32I-LABEL: explicit_register_x6:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv t1, a0 ; RV32I-NEXT: mv t1, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, t1, 0 ; RV32I-NEXT: addi a0, t1, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x6: ; RV64I-LABEL: explicit_register_x6:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv t1, a0 ; RV64I-NEXT: mv t1, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, t1, 0 ; RV64I-NEXT: addi a0, t1, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x6:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x6, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x6, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x6:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x6, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x6, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x6}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x6}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_t1(i32 %a) nounwind { define i32 @explicit_register_t1(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_t1: ; RV32I-LABEL: explicit_register_t1:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv t1, a0 ; RV32I-NEXT: mv t1, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, t1, 0 ; RV32I-NEXT: addi a0, t1, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_t1: ; RV64I-LABEL: explicit_register_t1:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv t1, a0 ; RV64I-NEXT: mv t1, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, t1, 0 ; RV64I-NEXT: addi a0, t1, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_t1:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x6, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x6, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_t1:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x6, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x6, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{t1}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t1}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x7(i32 %a) nounwind { define i32 @explicit_register_x7(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x7: ; RV32I-LABEL: explicit_register_x7:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv t2, a0 ; RV32I-NEXT: mv t2, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, t2, 0 ; RV32I-NEXT: addi a0, t2, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x7: ; RV64I-LABEL: explicit_register_x7:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv t2, a0 ; RV64I-NEXT: mv t2, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, t2, 0 ; RV64I-NEXT: addi a0, t2, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x7:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x7, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x7, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x7:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x7, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x7, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x7}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x7}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_t2(i32 %a) nounwind { define i32 @explicit_register_t2(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_t2: ; RV32I-LABEL: explicit_register_t2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv t2, a0 ; RV32I-NEXT: mv t2, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, t2, 0 ; RV32I-NEXT: addi a0, t2, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_t2: ; RV64I-LABEL: explicit_register_t2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv t2, a0 ; RV64I-NEXT: mv t2, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, t2, 0 ; RV64I-NEXT: addi a0, t2, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_t2:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x7, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x7, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_t2:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x7, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x7, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{t2}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t2}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x8` (`s0`, `fp`) as an input, so it should be saved. ; NOTE: This test uses `x8` (`s0`, `fp`) as an input, so it should be saved.
define i32 @explicit_register_x8(i32 %a) nounwind { define i32 @explicit_register_x8(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x8: ; RV32I-LABEL: explicit_register_x8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s0, 8(sp) ; RV64I-NEXT: sd s0, 8(sp)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s0, 0 ; RV64I-NEXT: addi a0, s0, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s0, 8(sp) ; RV64I-NEXT: ld s0, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x8:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x8, 12(x2)
; RV32I-NO-ABI-NEXT: mv x8, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x8, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x8, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x8:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x8, 8(x2)
; RV64I-NO-ABI-NEXT: mv x8, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x8, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x8, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x8}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x8}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s0` (`x8`, `fp`) as an input, so it should be saved. ; NOTE: This test uses `s0` (`x8`, `fp`) as an input, so it should be saved.
define i32 @explicit_register_s0(i32 %a) nounwind { define i32 @explicit_register_s0(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s0: ; RV32I-LABEL: explicit_register_s0:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s0, 8(sp) ; RV64I-NEXT: sd s0, 8(sp)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s0, 0 ; RV64I-NEXT: addi a0, s0, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s0, 8(sp) ; RV64I-NEXT: ld s0, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_s0:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x8, 12(x2)
; RV32I-NO-ABI-NEXT: mv x8, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x8, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x8, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_s0:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x8, 8(x2)
; RV64I-NO-ABI-NEXT: mv x8, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x8, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x8, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s0}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s0}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fp` (`x8`, `s0`) as an input, so it should be saved. ; NOTE: This test uses `fp` (`x8`, `s0`) as an input, so it should be saved.
define i32 @explicit_register_fp(i32 %a) nounwind { define i32 @explicit_register_fp(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_fp: ; RV32I-LABEL: explicit_register_fp:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s0, 8(sp) ; RV64I-NEXT: sd s0, 8(sp)
; RV64I-NEXT: mv s0, a0 ; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s0, 0 ; RV64I-NEXT: addi a0, s0, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s0, 8(sp) ; RV64I-NEXT: ld s0, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_fp:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x8, 12(x2)
; RV32I-NO-ABI-NEXT: mv x8, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x8, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x8, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_fp:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x8, 8(x2)
; RV64I-NO-ABI-NEXT: mv x8, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x8, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x8, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{fp}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{fp}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x9` (`s1`) as an input, so it should be saved. ; NOTE: This test uses `x9` (`s1`) as an input, so it should be saved.
define i32 @explicit_register_x9(i32 %a) nounwind { define i32 @explicit_register_x9(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x9: ; RV32I-LABEL: explicit_register_x9:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s1, 0 ; RV64I-NEXT: addi a0, s1, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x9:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x9, 12(x2)
; RV32I-NO-ABI-NEXT: mv x9, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x9, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x9, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x9:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x9, 8(x2)
; RV64I-NO-ABI-NEXT: mv x9, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x9, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x9, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x9}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x9}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s1` (`x9`) as an input, so it should be saved. ; NOTE: This test uses `s1` (`x9`) as an input, so it should be saved.
define i32 @explicit_register_s1(i32 %a) nounwind { define i32 @explicit_register_s1(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s1: ; RV32I-LABEL: explicit_register_s1:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s1, 8(sp) ; RV64I-NEXT: sd s1, 8(sp)
; RV64I-NEXT: mv s1, a0 ; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s1, 0 ; RV64I-NEXT: addi a0, s1, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s1, 8(sp) ; RV64I-NEXT: ld s1, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_s1:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x9, 12(x2)
; RV32I-NO-ABI-NEXT: mv x9, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x9, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x9, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_s1:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x9, 8(x2)
; RV64I-NO-ABI-NEXT: mv x9, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x9, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x9, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s1}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s1}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x10(i32 %a) nounwind { define i32 @explicit_register_x10(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x10: ; RV32I-LABEL: explicit_register_x10:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a0, 0 ; RV32I-NEXT: addi a0, a0, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x10: ; RV64I-LABEL: explicit_register_x10:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a0, 0 ; RV64I-NEXT: addi a0, a0, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x10:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x10, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x10:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x10, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x10}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x10}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_a0(i32 %a) nounwind { define i32 @explicit_register_a0(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_a0: ; RV32I-LABEL: explicit_register_a0:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a0, 0 ; RV32I-NEXT: addi a0, a0, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_a0: ; RV64I-LABEL: explicit_register_a0:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a0, 0 ; RV64I-NEXT: addi a0, a0, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_a0:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x10, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_a0:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x10, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{a0}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a0}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x11(i32 %a) nounwind { define i32 @explicit_register_x11(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x11: ; RV32I-LABEL: explicit_register_x11:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a1, 0 ; RV32I-NEXT: addi a0, a1, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x11: ; RV64I-LABEL: explicit_register_x11:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a1, 0 ; RV64I-NEXT: addi a0, a1, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x11:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x11, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x11, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x11:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x11, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x11, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x11}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x11}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_a1(i32 %a) nounwind { define i32 @explicit_register_a1(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_a1: ; RV32I-LABEL: explicit_register_a1:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a1, a0 ; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a1, 0 ; RV32I-NEXT: addi a0, a1, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_a1: ; RV64I-LABEL: explicit_register_a1:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a1, a0 ; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a1, 0 ; RV64I-NEXT: addi a0, a1, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_a1:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x11, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x11, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_a1:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x11, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x11, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{a1}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a1}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x12(i32 %a) nounwind { define i32 @explicit_register_x12(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x12: ; RV32I-LABEL: explicit_register_x12:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a2, 0 ; RV32I-NEXT: addi a0, a2, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x12: ; RV64I-LABEL: explicit_register_x12:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a2, 0 ; RV64I-NEXT: addi a0, a2, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x12:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x12, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x12, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x12:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x12, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x12, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x12}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x12}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_a2(i32 %a) nounwind { define i32 @explicit_register_a2(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_a2: ; RV32I-LABEL: explicit_register_a2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a2, a0 ; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a2, 0 ; RV32I-NEXT: addi a0, a2, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_a2: ; RV64I-LABEL: explicit_register_a2:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a2, a0 ; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a2, 0 ; RV64I-NEXT: addi a0, a2, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_a2:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x12, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x12, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_a2:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x12, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x12, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{a2}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a2}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x13(i32 %a) nounwind { define i32 @explicit_register_x13(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x13: ; RV32I-LABEL: explicit_register_x13:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a3, a0 ; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a3, 0 ; RV32I-NEXT: addi a0, a3, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x13: ; RV64I-LABEL: explicit_register_x13:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a3, a0 ; RV64I-NEXT: mv a3, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a3, 0 ; RV64I-NEXT: addi a0, a3, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x13:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x13, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x13, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x13:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x13, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x13, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x13}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x13}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_a3(i32 %a) nounwind { define i32 @explicit_register_a3(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_a3: ; RV32I-LABEL: explicit_register_a3:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a3, a0 ; RV32I-NEXT: mv a3, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a3, 0 ; RV32I-NEXT: addi a0, a3, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_a3: ; RV64I-LABEL: explicit_register_a3:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a3, a0 ; RV64I-NEXT: mv a3, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a3, 0 ; RV64I-NEXT: addi a0, a3, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_a3:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x13, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x13, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_a3:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x13, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x13, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{a3}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a3}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x14(i32 %a) nounwind { define i32 @explicit_register_x14(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x14: ; RV32I-LABEL: explicit_register_x14:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a4, 0 ; RV32I-NEXT: addi a0, a4, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x14: ; RV64I-LABEL: explicit_register_x14:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a4, a0 ; RV64I-NEXT: mv a4, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a4, 0 ; RV64I-NEXT: addi a0, a4, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x14:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x14, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x14, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x14:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x14, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x14, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x14}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x14}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_a4(i32 %a) nounwind { define i32 @explicit_register_a4(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_a4: ; RV32I-LABEL: explicit_register_a4:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a4, a0 ; RV32I-NEXT: mv a4, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a4, 0 ; RV32I-NEXT: addi a0, a4, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_a4: ; RV64I-LABEL: explicit_register_a4:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a4, a0 ; RV64I-NEXT: mv a4, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a4, 0 ; RV64I-NEXT: addi a0, a4, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_a4:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x14, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x14, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_a4:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x14, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x14, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{a4}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a4}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x15(i32 %a) nounwind { define i32 @explicit_register_x15(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x15: ; RV32I-LABEL: explicit_register_x15:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a5, a0 ; RV32I-NEXT: mv a5, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a5, 0 ; RV32I-NEXT: addi a0, a5, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x15: ; RV64I-LABEL: explicit_register_x15:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a5, a0 ; RV64I-NEXT: mv a5, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a5, 0 ; RV64I-NEXT: addi a0, a5, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x15:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x15, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x15, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x15:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x15, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x15, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x15}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x15}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_a5(i32 %a) nounwind { define i32 @explicit_register_a5(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_a5: ; RV32I-LABEL: explicit_register_a5:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a5, a0 ; RV32I-NEXT: mv a5, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a5, 0 ; RV32I-NEXT: addi a0, a5, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_a5: ; RV64I-LABEL: explicit_register_a5:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a5, a0 ; RV64I-NEXT: mv a5, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a5, 0 ; RV64I-NEXT: addi a0, a5, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_a5:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x15, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x15, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_a5:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x15, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x15, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{a5}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a5}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x16(i32 %a) nounwind { define i32 @explicit_register_x16(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x16: ; RV32I-LABEL: explicit_register_x16:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a6, a0 ; RV32I-NEXT: mv a6, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a6, 0 ; RV32I-NEXT: addi a0, a6, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x16: ; RV64I-LABEL: explicit_register_x16:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a6, a0 ; RV64I-NEXT: mv a6, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a6, 0 ; RV64I-NEXT: addi a0, a6, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x16:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x16, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x16, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x16:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x16, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x16, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x16}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x16}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_a6(i32 %a) nounwind { define i32 @explicit_register_a6(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_a6: ; RV32I-LABEL: explicit_register_a6:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a6, a0 ; RV32I-NEXT: mv a6, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a6, 0 ; RV32I-NEXT: addi a0, a6, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_a6: ; RV64I-LABEL: explicit_register_a6:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a6, a0 ; RV64I-NEXT: mv a6, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a6, 0 ; RV64I-NEXT: addi a0, a6, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_a6:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x16, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x16, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_a6:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x16, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x16, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{a6}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a6}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x17(i32 %a) nounwind { define i32 @explicit_register_x17(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x17: ; RV32I-LABEL: explicit_register_x17:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a7, a0 ; RV32I-NEXT: mv a7, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a7, 0 ; RV32I-NEXT: addi a0, a7, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x17: ; RV64I-LABEL: explicit_register_x17:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a7, a0 ; RV64I-NEXT: mv a7, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a7, 0 ; RV64I-NEXT: addi a0, a7, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x17:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x17, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x17, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x17:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x17, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x17, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x17}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x17}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_a7(i32 %a) nounwind { define i32 @explicit_register_a7(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_a7: ; RV32I-LABEL: explicit_register_a7:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv a7, a0 ; RV32I-NEXT: mv a7, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, a7, 0 ; RV32I-NEXT: addi a0, a7, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_a7: ; RV64I-LABEL: explicit_register_a7:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv a7, a0 ; RV64I-NEXT: mv a7, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, a7, 0 ; RV64I-NEXT: addi a0, a7, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_a7:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x17, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x17, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_a7:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x17, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x17, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{a7}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{a7}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x18` (`s2`) as an input, so it should be saved. ; NOTE: This test uses `x18` (`s2`) as an input, so it should be saved.
define i32 @explicit_register_x18(i32 %a) nounwind { define i32 @explicit_register_x18(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x18: ; RV32I-LABEL: explicit_register_x18:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s2, 8(sp) ; RV64I-NEXT: sd s2, 8(sp)
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s2, 0 ; RV64I-NEXT: addi a0, s2, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s2, 8(sp) ; RV64I-NEXT: ld s2, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x18:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x18, 12(x2)
; RV32I-NO-ABI-NEXT: mv x18, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x18, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x18, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x18:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x18, 8(x2)
; RV64I-NO-ABI-NEXT: mv x18, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x18, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x18, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x18}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x18}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s2` (`x18`) as an input, so it should be saved. ; NOTE: This test uses `s2` (`x18`) as an input, so it should be saved.
define i32 @explicit_register_s2(i32 %a) nounwind { define i32 @explicit_register_s2(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s2: ; RV32I-LABEL: explicit_register_s2:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s2, 8(sp) ; RV64I-NEXT: sd s2, 8(sp)
; RV64I-NEXT: mv s2, a0 ; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s2, 0 ; RV64I-NEXT: addi a0, s2, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s2, 8(sp) ; RV64I-NEXT: ld s2, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_s2:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x18, 12(x2)
; RV32I-NO-ABI-NEXT: mv x18, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x18, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x18, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_s2:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x18, 8(x2)
; RV64I-NO-ABI-NEXT: mv x18, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x18, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x18, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s2}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s2}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x19` (`s3`) as an input, so it should be saved. ; NOTE: This test uses `x19` (`s3`) as an input, so it should be saved.
define i32 @explicit_register_x19(i32 %a) nounwind { define i32 @explicit_register_x19(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x19: ; RV32I-LABEL: explicit_register_x19:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s3, 0 ; RV64I-NEXT: addi a0, s3, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x19:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x19, 12(x2)
; RV32I-NO-ABI-NEXT: mv x19, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x19, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x19, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x19:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x19, 8(x2)
; RV64I-NO-ABI-NEXT: mv x19, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x19, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x19, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x19}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x19}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s3` (`x19`) as an input, so it should be saved. ; NOTE: This test uses `s3` (`x19`) as an input, so it should be saved.
define i32 @explicit_register_s3(i32 %a) nounwind { define i32 @explicit_register_s3(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s3: ; RV32I-LABEL: explicit_register_s3:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s3, 8(sp) ; RV64I-NEXT: sd s3, 8(sp)
; RV64I-NEXT: mv s3, a0 ; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s3, 0 ; RV64I-NEXT: addi a0, s3, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s3, 8(sp) ; RV64I-NEXT: ld s3, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_s3:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x19, 12(x2)
; RV32I-NO-ABI-NEXT: mv x19, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x19, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x19, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_s3:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x19, 8(x2)
; RV64I-NO-ABI-NEXT: mv x19, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x19, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x19, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s3}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s3}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x20` (`s4`) as an input, so it should be saved. ; NOTE: This test uses `x20` (`s4`) as an input, so it should be saved.
define i32 @explicit_register_x20(i32 %a) nounwind { define i32 @explicit_register_x20(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x20: ; RV32I-LABEL: explicit_register_x20:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s4, 8(sp) ; RV64I-NEXT: sd s4, 8(sp)
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s4, 0 ; RV64I-NEXT: addi a0, s4, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s4, 8(sp) ; RV64I-NEXT: ld s4, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x20:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x20, 12(x2)
; RV32I-NO-ABI-NEXT: mv x20, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x20, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x20, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x20:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x20, 8(x2)
; RV64I-NO-ABI-NEXT: mv x20, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x20, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x20, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x20}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x20}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s4` (`x20`) as an input, so it should be saved. ; NOTE: This test uses `s4` (`x20`) as an input, so it should be saved.
define i32 @explicit_register_s4(i32 %a) nounwind { define i32 @explicit_register_s4(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s4: ; RV32I-LABEL: explicit_register_s4:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s4, 8(sp) ; RV64I-NEXT: sd s4, 8(sp)
; RV64I-NEXT: mv s4, a0 ; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s4, 0 ; RV64I-NEXT: addi a0, s4, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s4, 8(sp) ; RV64I-NEXT: ld s4, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_s4:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x20, 12(x2)
; RV32I-NO-ABI-NEXT: mv x20, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x20, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x20, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_s4:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x20, 8(x2)
; RV64I-NO-ABI-NEXT: mv x20, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x20, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x20, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s4}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s4}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x21` (`s5`) as an input, so it should be saved. ; NOTE: This test uses `x21` (`s5`) as an input, so it should be saved.
define i32 @explicit_register_x21(i32 %a) nounwind { define i32 @explicit_register_x21(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x21: ; RV32I-LABEL: explicit_register_x21:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s5, 8(sp) ; RV64I-NEXT: sd s5, 8(sp)
; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: mv s5, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s5, 0 ; RV64I-NEXT: addi a0, s5, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s5, 8(sp) ; RV64I-NEXT: ld s5, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x21:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x21, 12(x2)
; RV32I-NO-ABI-NEXT: mv x21, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x21, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x21, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x21:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x21, 8(x2)
; RV64I-NO-ABI-NEXT: mv x21, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x21, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x21, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x21}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x21}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s5` (`x21`) as an input, so it should be saved. ; NOTE: This test uses `s5` (`x21`) as an input, so it should be saved.
define i32 @explicit_register_s5(i32 %a) nounwind { define i32 @explicit_register_s5(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s5: ; RV32I-LABEL: explicit_register_s5:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s5, 8(sp) ; RV64I-NEXT: sd s5, 8(sp)
; RV64I-NEXT: mv s5, a0 ; RV64I-NEXT: mv s5, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s5, 0 ; RV64I-NEXT: addi a0, s5, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s5, 8(sp) ; RV64I-NEXT: ld s5, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_s5:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x21, 12(x2)
; RV32I-NO-ABI-NEXT: mv x21, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x21, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x21, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_s5:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x21, 8(x2)
; RV64I-NO-ABI-NEXT: mv x21, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x21, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x21, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s5}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s5}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x22` (`s6`) as an input, so it should be saved. ; NOTE: This test uses `x22` (`s6`) as an input, so it should be saved.
define i32 @explicit_register_x22(i32 %a) nounwind { define i32 @explicit_register_x22(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x22: ; RV32I-LABEL: explicit_register_x22:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s6, 8(sp) ; RV64I-NEXT: sd s6, 8(sp)
; RV64I-NEXT: mv s6, a0 ; RV64I-NEXT: mv s6, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s6, 0 ; RV64I-NEXT: addi a0, s6, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s6, 8(sp) ; RV64I-NEXT: ld s6, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x22:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x22, 12(x2)
; RV32I-NO-ABI-NEXT: mv x22, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x22, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x22, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x22:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x22, 8(x2)
; RV64I-NO-ABI-NEXT: mv x22, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x22, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x22, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x22}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x22}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s6` (`x22`) as an input, so it should be saved. ; NOTE: This test uses `s6` (`x22`) as an input, so it should be saved.
define i32 @explicit_register_s6(i32 %a) nounwind { define i32 @explicit_register_s6(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s6: ; RV32I-LABEL: explicit_register_s6:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s6, 8(sp) ; RV64I-NEXT: sd s6, 8(sp)
; RV64I-NEXT: mv s6, a0 ; RV64I-NEXT: mv s6, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s6, 0 ; RV64I-NEXT: addi a0, s6, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s6, 8(sp) ; RV64I-NEXT: ld s6, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_s6:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x22, 12(x2)
; RV32I-NO-ABI-NEXT: mv x22, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x22, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x22, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_s6:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x22, 8(x2)
; RV64I-NO-ABI-NEXT: mv x22, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x22, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x22, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s6}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s6}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x23` (`s7`) as an input, so it should be saved. ; NOTE: This test uses `x23` (`s7`) as an input, so it should be saved.
define i32 @explicit_register_x23(i32 %a) nounwind { define i32 @explicit_register_x23(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x23: ; RV32I-LABEL: explicit_register_x23:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s7, 8(sp) ; RV64I-NEXT: sd s7, 8(sp)
; RV64I-NEXT: mv s7, a0 ; RV64I-NEXT: mv s7, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s7, 0 ; RV64I-NEXT: addi a0, s7, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s7, 8(sp) ; RV64I-NEXT: ld s7, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x23:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x23, 12(x2)
; RV32I-NO-ABI-NEXT: mv x23, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x23, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x23, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x23:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x23, 8(x2)
; RV64I-NO-ABI-NEXT: mv x23, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x23, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x23, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x23}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x23}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s7` (`x23`) as an input, so it should be saved. ; NOTE: This test uses `s7` (`x23`) as an input, so it should be saved.
define i32 @explicit_register_s7(i32 %a) nounwind { define i32 @explicit_register_s7(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s7: ; RV32I-LABEL: explicit_register_s7:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s7, 8(sp) ; RV64I-NEXT: sd s7, 8(sp)
; RV64I-NEXT: mv s7, a0 ; RV64I-NEXT: mv s7, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s7, 0 ; RV64I-NEXT: addi a0, s7, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s7, 8(sp) ; RV64I-NEXT: ld s7, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_s7:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x23, 12(x2)
; RV32I-NO-ABI-NEXT: mv x23, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x23, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x23, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_s7:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x23, 8(x2)
; RV64I-NO-ABI-NEXT: mv x23, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x23, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x23, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s7}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s7}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x24` (`s8`) as an input, so it should be saved. ; NOTE: This test uses `x24` (`s8`) as an input, so it should be saved.
define i32 @explicit_register_x24(i32 %a) nounwind { define i32 @explicit_register_x24(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x24: ; RV32I-LABEL: explicit_register_x24:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s8, 8(sp) ; RV64I-NEXT: sd s8, 8(sp)
; RV64I-NEXT: mv s8, a0 ; RV64I-NEXT: mv s8, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s8, 0 ; RV64I-NEXT: addi a0, s8, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s8, 8(sp) ; RV64I-NEXT: ld s8, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x24:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x24, 12(x2)
; RV32I-NO-ABI-NEXT: mv x24, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x24, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x24, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x24:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x24, 8(x2)
; RV64I-NO-ABI-NEXT: mv x24, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x24, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x24, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x24}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x24}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s8` (`x24`) as an input, so it should be saved. ; NOTE: This test uses `s8` (`x24`) as an input, so it should be saved.
define i32 @explicit_register_s8(i32 %a) nounwind { define i32 @explicit_register_s8(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s8: ; RV32I-LABEL: explicit_register_s8:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s8, 8(sp) ; RV64I-NEXT: sd s8, 8(sp)
; RV64I-NEXT: mv s8, a0 ; RV64I-NEXT: mv s8, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s8, 0 ; RV64I-NEXT: addi a0, s8, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s8, 8(sp) ; RV64I-NEXT: ld s8, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_s8:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x24, 12(x2)
; RV32I-NO-ABI-NEXT: mv x24, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x24, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x24, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_s8:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x24, 8(x2)
; RV64I-NO-ABI-NEXT: mv x24, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x24, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x24, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s8}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s8}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x25` (`s9`) as an input, so it should be saved. ; NOTE: This test uses `x25` (`s9`) as an input, so it should be saved.
define i32 @explicit_register_x25(i32 %a) nounwind { define i32 @explicit_register_x25(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x25: ; RV32I-LABEL: explicit_register_x25:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s9, 8(sp) ; RV64I-NEXT: sd s9, 8(sp)
; RV64I-NEXT: mv s9, a0 ; RV64I-NEXT: mv s9, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s9, 0 ; RV64I-NEXT: addi a0, s9, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s9, 8(sp) ; RV64I-NEXT: ld s9, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x25:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x25, 12(x2)
; RV32I-NO-ABI-NEXT: mv x25, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x25, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x25, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x25:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x25, 8(x2)
; RV64I-NO-ABI-NEXT: mv x25, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x25, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x25, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x25}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x25}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s9` (`x25`) as an input, so it should be saved. ; NOTE: This test uses `s9` (`x25`) as an input, so it should be saved.
define i32 @explicit_register_s9(i32 %a) nounwind { define i32 @explicit_register_s9(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s9: ; RV32I-LABEL: explicit_register_s9:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s9, 8(sp) ; RV64I-NEXT: sd s9, 8(sp)
; RV64I-NEXT: mv s9, a0 ; RV64I-NEXT: mv s9, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s9, 0 ; RV64I-NEXT: addi a0, s9, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s9, 8(sp) ; RV64I-NEXT: ld s9, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_s9:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x25, 12(x2)
; RV32I-NO-ABI-NEXT: mv x25, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x25, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x25, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_s9:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x25, 8(x2)
; RV64I-NO-ABI-NEXT: mv x25, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x25, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x25, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s9}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s9}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x26` (`s10`) as an input, so it should be saved. ; NOTE: This test uses `x26` (`s10`) as an input, so it should be saved.
define i32 @explicit_register_x26(i32 %a) nounwind { define i32 @explicit_register_x26(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x26: ; RV32I-LABEL: explicit_register_x26:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s10, 8(sp) ; RV64I-NEXT: sd s10, 8(sp)
; RV64I-NEXT: mv s10, a0 ; RV64I-NEXT: mv s10, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s10, 0 ; RV64I-NEXT: addi a0, s10, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s10, 8(sp) ; RV64I-NEXT: ld s10, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x26:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x26, 12(x2)
; RV32I-NO-ABI-NEXT: mv x26, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x26, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x26, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x26:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x26, 8(x2)
; RV64I-NO-ABI-NEXT: mv x26, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x26, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x26, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x26}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x26}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s10` (`x28`) as an input, so it should be saved. ; NOTE: This test uses `s10` (`x28`) as an input, so it should be saved.
define i32 @explicit_register_s10(i32 %a) nounwind { define i32 @explicit_register_s10(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s10: ; RV32I-LABEL: explicit_register_s10:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s10, 8(sp) ; RV64I-NEXT: sd s10, 8(sp)
; RV64I-NEXT: mv s10, a0 ; RV64I-NEXT: mv s10, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s10, 0 ; RV64I-NEXT: addi a0, s10, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s10, 8(sp) ; RV64I-NEXT: ld s10, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_s10:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x26, 12(x2)
; RV32I-NO-ABI-NEXT: mv x26, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x26, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x26, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_s10:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x26, 8(x2)
; RV64I-NO-ABI-NEXT: mv x26, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x26, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x26, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s10}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s10}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `x27` (`s11`) as an input, so it should be saved. ; NOTE: This test uses `x27` (`s11`) as an input, so it should be saved.
define i32 @explicit_register_x27(i32 %a) nounwind { define i32 @explicit_register_x27(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x27: ; RV32I-LABEL: explicit_register_x27:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s11, 8(sp) ; RV64I-NEXT: sd s11, 8(sp)
; RV64I-NEXT: mv s11, a0 ; RV64I-NEXT: mv s11, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s11, 0 ; RV64I-NEXT: addi a0, s11, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s11, 8(sp) ; RV64I-NEXT: ld s11, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x27:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x27, 12(x2)
; RV32I-NO-ABI-NEXT: mv x27, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x27, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x27, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x27:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x27, 8(x2)
; RV64I-NO-ABI-NEXT: mv x27, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x27, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x27, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x27}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x27}"(i32 %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `s11` (`x27`) as an input, so it should be saved. ; NOTE: This test uses `s11` (`x27`) as an input, so it should be saved.
define i32 @explicit_register_s11(i32 %a) nounwind { define i32 @explicit_register_s11(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_s11: ; RV32I-LABEL: explicit_register_s11:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
Show All 13 Lines
; RV64I-NEXT: sd s11, 8(sp) ; RV64I-NEXT: sd s11, 8(sp)
; RV64I-NEXT: mv s11, a0 ; RV64I-NEXT: mv s11, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, s11, 0 ; RV64I-NEXT: addi a0, s11, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ld s11, 8(sp) ; RV64I-NEXT: ld s11, 8(sp)
; RV64I-NEXT: addi sp, sp, 16 ; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_s11:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: addi x2, x2, -16
; RV32I-NO-ABI-NEXT: sw x27, 12(x2)
; RV32I-NO-ABI-NEXT: mv x27, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x27, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: lw x27, 12(x2)
; RV32I-NO-ABI-NEXT: addi x2, x2, 16
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_s11:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: addi x2, x2, -16
; RV64I-NO-ABI-NEXT: sd x27, 8(x2)
; RV64I-NO-ABI-NEXT: mv x27, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x27, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ld x27, 8(x2)
; RV64I-NO-ABI-NEXT: addi x2, x2, 16
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{s11}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{s11}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x28(i32 %a) nounwind { define i32 @explicit_register_x28(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x28: ; RV32I-LABEL: explicit_register_x28:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv t3, a0 ; RV32I-NEXT: mv t3, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, t3, 0 ; RV32I-NEXT: addi a0, t3, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x28: ; RV64I-LABEL: explicit_register_x28:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv t3, a0 ; RV64I-NEXT: mv t3, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, t3, 0 ; RV64I-NEXT: addi a0, t3, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x28:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x28, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x28, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x28:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x28, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x28, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x28}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x28}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_t3(i32 %a) nounwind { define i32 @explicit_register_t3(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_t3: ; RV32I-LABEL: explicit_register_t3:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv t3, a0 ; RV32I-NEXT: mv t3, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, t3, 0 ; RV32I-NEXT: addi a0, t3, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_t3: ; RV64I-LABEL: explicit_register_t3:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv t3, a0 ; RV64I-NEXT: mv t3, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, t3, 0 ; RV64I-NEXT: addi a0, t3, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_t3:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x28, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x28, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_t3:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x28, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x28, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{t3}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t3}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x29(i32 %a) nounwind { define i32 @explicit_register_x29(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x29: ; RV32I-LABEL: explicit_register_x29:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv t4, a0 ; RV32I-NEXT: mv t4, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, t4, 0 ; RV32I-NEXT: addi a0, t4, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x29: ; RV64I-LABEL: explicit_register_x29:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv t4, a0 ; RV64I-NEXT: mv t4, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, t4, 0 ; RV64I-NEXT: addi a0, t4, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x29:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x29, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x29, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x29:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x29, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x29, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x29}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x29}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_t4(i32 %a) nounwind { define i32 @explicit_register_t4(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_t4: ; RV32I-LABEL: explicit_register_t4:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv t4, a0 ; RV32I-NEXT: mv t4, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, t4, 0 ; RV32I-NEXT: addi a0, t4, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_t4: ; RV64I-LABEL: explicit_register_t4:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv t4, a0 ; RV64I-NEXT: mv t4, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, t4, 0 ; RV64I-NEXT: addi a0, t4, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_t4:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x29, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x29, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_t4:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x29, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x29, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{t4}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t4}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x30(i32 %a) nounwind { define i32 @explicit_register_x30(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x30: ; RV32I-LABEL: explicit_register_x30:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv t5, a0 ; RV32I-NEXT: mv t5, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, t5, 0 ; RV32I-NEXT: addi a0, t5, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x30: ; RV64I-LABEL: explicit_register_x30:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv t5, a0 ; RV64I-NEXT: mv t5, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, t5, 0 ; RV64I-NEXT: addi a0, t5, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x30:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x30, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x30, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x30:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x30, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x30, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x30}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x30}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_t5(i32 %a) nounwind { define i32 @explicit_register_t5(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_t5: ; RV32I-LABEL: explicit_register_t5:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv t5, a0 ; RV32I-NEXT: mv t5, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, t5, 0 ; RV32I-NEXT: addi a0, t5, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_t5: ; RV64I-LABEL: explicit_register_t5:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv t5, a0 ; RV64I-NEXT: mv t5, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, t5, 0 ; RV64I-NEXT: addi a0, t5, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_t5:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x30, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x30, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_t5:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x30, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x30, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{t5}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t5}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_x31(i32 %a) nounwind { define i32 @explicit_register_x31(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_x31: ; RV32I-LABEL: explicit_register_x31:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv t6, a0 ; RV32I-NEXT: mv t6, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, t6, 0 ; RV32I-NEXT: addi a0, t6, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_x31: ; RV64I-LABEL: explicit_register_x31:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv t6, a0 ; RV64I-NEXT: mv t6, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, t6, 0 ; RV64I-NEXT: addi a0, t6, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_x31:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x31, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x31, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_x31:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x31, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x31, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{x31}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{x31}"(i32 %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_t6(i32 %a) nounwind { define i32 @explicit_register_t6(i32 %a) nounwind {
; RV32I-LABEL: explicit_register_t6: ; RV32I-LABEL: explicit_register_t6:
; RV32I: # %bb.0: ; RV32I: # %bb.0:
; RV32I-NEXT: mv t6, a0 ; RV32I-NEXT: mv t6, a0
; RV32I-NEXT: #APP ; RV32I-NEXT: #APP
; RV32I-NEXT: addi a0, t6, 0 ; RV32I-NEXT: addi a0, t6, 0
; RV32I-NEXT: #NO_APP ; RV32I-NEXT: #NO_APP
; RV32I-NEXT: ret ; RV32I-NEXT: ret
; ;
; RV64I-LABEL: explicit_register_t6: ; RV64I-LABEL: explicit_register_t6:
; RV64I: # %bb.0: ; RV64I: # %bb.0:
; RV64I-NEXT: mv t6, a0 ; RV64I-NEXT: mv t6, a0
; RV64I-NEXT: #APP ; RV64I-NEXT: #APP
; RV64I-NEXT: addi a0, t6, 0 ; RV64I-NEXT: addi a0, t6, 0
; RV64I-NEXT: #NO_APP ; RV64I-NEXT: #NO_APP
; RV64I-NEXT: ret ; RV64I-NEXT: ret
;
; RV32I-NO-ABI-LABEL: explicit_register_t6:
; RV32I-NO-ABI: # %bb.0:
; RV32I-NO-ABI-NEXT: mv x31, x10
; RV32I-NO-ABI-NEXT: #APP
; RV32I-NO-ABI-NEXT: addi x10, x31, 0
; RV32I-NO-ABI-NEXT: #NO_APP
; RV32I-NO-ABI-NEXT: ret
;
; RV64I-NO-ABI-LABEL: explicit_register_t6:
; RV64I-NO-ABI: # %bb.0:
; RV64I-NO-ABI-NEXT: mv x31, x10
; RV64I-NO-ABI-NEXT: #APP
; RV64I-NO-ABI-NEXT: addi x10, x31, 0
; RV64I-NO-ABI-NEXT: #NO_APP
; RV64I-NO-ABI-NEXT: ret
%1 = tail call i32 asm "addi $0, $1, 0", "=r,{t6}"(i32 %a) %1 = tail call i32 asm "addi $0, $1, 0", "=r,{t6}"(i32 %a)
ret i32 %1 ret i32 %1
} }

llvm/test/CodeGen/RISCV/inline-asm-d-abi-names.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f,+d -target-abi ilp32d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f,+d -target-abi ilp32d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IFD %s ; RUN: | FileCheck -check-prefix=RV32IFD %s
; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi lp64d -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi lp64d -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IFD %s ; RUN: | FileCheck -check-prefix=RV64IFD %s
; RUN: llc -mtriple=riscv32 -mattr=+f,+d -target-abi ilp32d -verify-machineinstrs -riscv-arch-reg-names < %s \
; RUN: | FileCheck -check-prefix=RV32IFD-NO-ABI %s
; RUN: llc -mtriple=riscv64 -mattr=+f,+d -target-abi lp64d -verify-machineinstrs -riscv-arch-reg-names < %s \
; RUN: | FileCheck -check-prefix=RV64IFD-NO-ABI %s
; These test that we can use both the architectural names (x*) and the ABI names ; These test that we can use both the architectural names (x*) and the ABI names
; (a*, s*, t* etc) to refer to registers in inline asm constraint lists. In each ; (a*, s*, t* etc) to refer to registers in inline asm constraint lists. In each
; case, the named register should be used for the source register of the `addi`. ; case, the named register should be used for the source register of the `addi`.
; It is very likely that `a0` will be chosen as the designation register, but ; It is very likely that `a0` will be chosen as the designation register, but
; this is left to the compiler to choose. ; this is left to the compiler to choose.
; ;
; The inline assembly will, by default, contain the ABI names for the registers. ; The inline assembly will, by default, contain the ABI names for the registers,
; unless `-riscv-arch-reg-names` is passed to llc to print the architectural
; names.
; ;
; Parenthesised registers in comments are the other aliases for this register. ; Parenthesised registers in comments are the other aliases for this register.
define i32 @explicit_register_f0(double %a) nounwind { define i32 @explicit_register_f0(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f0: ; RV32IFD-LABEL: explicit_register_f0:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft0, fa0 ; RV32IFD-NEXT: fmv.d ft0, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft0 ; RV32IFD-NEXT: fcvt.w.d a0, ft0
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f0: ; RV64IFD-LABEL: explicit_register_f0:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft0, fa0 ; RV64IFD-NEXT: fmv.d ft0, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft0 ; RV64IFD-NEXT: fcvt.w.d a0, ft0
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f0:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f0, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f0
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f0:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f0, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f0
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f0}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f0}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft0(double %a) nounwind { define i32 @explicit_register_ft0(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_ft0: ; RV32IFD-LABEL: explicit_register_ft0:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft0, fa0 ; RV32IFD-NEXT: fmv.d ft0, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft0 ; RV32IFD-NEXT: fcvt.w.d a0, ft0
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_ft0: ; RV64IFD-LABEL: explicit_register_ft0:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft0, fa0 ; RV64IFD-NEXT: fmv.d ft0, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft0 ; RV64IFD-NEXT: fcvt.w.d a0, ft0
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_ft0:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f0, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f0
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_ft0:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f0, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f0
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft0}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft0}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f1(double %a) nounwind { define i32 @explicit_register_f1(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f1: ; RV32IFD-LABEL: explicit_register_f1:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft1, fa0 ; RV32IFD-NEXT: fmv.d ft1, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft1 ; RV32IFD-NEXT: fcvt.w.d a0, ft1
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f1: ; RV64IFD-LABEL: explicit_register_f1:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft1, fa0 ; RV64IFD-NEXT: fmv.d ft1, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft1 ; RV64IFD-NEXT: fcvt.w.d a0, ft1
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f1:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f1, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f1
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f1:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f1, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f1
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f1}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f1}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft1(double %a) nounwind { define i32 @explicit_register_ft1(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_ft1: ; RV32IFD-LABEL: explicit_register_ft1:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft1, fa0 ; RV32IFD-NEXT: fmv.d ft1, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft1 ; RV32IFD-NEXT: fcvt.w.d a0, ft1
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_ft1: ; RV64IFD-LABEL: explicit_register_ft1:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft1, fa0 ; RV64IFD-NEXT: fmv.d ft1, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft1 ; RV64IFD-NEXT: fcvt.w.d a0, ft1
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_ft1:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f1, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f1
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_ft1:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f1, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f1
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft1}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft1}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f2(double %a) nounwind { define i32 @explicit_register_f2(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f2: ; RV32IFD-LABEL: explicit_register_f2:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft2, fa0 ; RV32IFD-NEXT: fmv.d ft2, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft2 ; RV32IFD-NEXT: fcvt.w.d a0, ft2
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f2: ; RV64IFD-LABEL: explicit_register_f2:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft2, fa0 ; RV64IFD-NEXT: fmv.d ft2, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft2 ; RV64IFD-NEXT: fcvt.w.d a0, ft2
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f2:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f2, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f2
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f2:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f2, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f2
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f2}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f2}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft2(double %a) nounwind { define i32 @explicit_register_ft2(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_ft2: ; RV32IFD-LABEL: explicit_register_ft2:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft2, fa0 ; RV32IFD-NEXT: fmv.d ft2, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft2 ; RV32IFD-NEXT: fcvt.w.d a0, ft2
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_ft2: ; RV64IFD-LABEL: explicit_register_ft2:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft2, fa0 ; RV64IFD-NEXT: fmv.d ft2, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft2 ; RV64IFD-NEXT: fcvt.w.d a0, ft2
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_ft2:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f2, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f2
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_ft2:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f2, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f2
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft2}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft2}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f3(double %a) nounwind { define i32 @explicit_register_f3(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f3: ; RV32IFD-LABEL: explicit_register_f3:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft3, fa0 ; RV32IFD-NEXT: fmv.d ft3, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft3 ; RV32IFD-NEXT: fcvt.w.d a0, ft3
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f3: ; RV64IFD-LABEL: explicit_register_f3:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft3, fa0 ; RV64IFD-NEXT: fmv.d ft3, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft3 ; RV64IFD-NEXT: fcvt.w.d a0, ft3
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f3:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f3, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f3
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f3:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f3, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f3
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f3}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f3}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft3(double %a) nounwind { define i32 @explicit_register_ft3(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_ft3: ; RV32IFD-LABEL: explicit_register_ft3:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft3, fa0 ; RV32IFD-NEXT: fmv.d ft3, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft3 ; RV32IFD-NEXT: fcvt.w.d a0, ft3
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_ft3: ; RV64IFD-LABEL: explicit_register_ft3:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft3, fa0 ; RV64IFD-NEXT: fmv.d ft3, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft3 ; RV64IFD-NEXT: fcvt.w.d a0, ft3
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_ft3:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f3, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f3
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_ft3:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f3, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f3
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft3}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft3}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f4(double %a) nounwind { define i32 @explicit_register_f4(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f4: ; RV32IFD-LABEL: explicit_register_f4:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft4, fa0 ; RV32IFD-NEXT: fmv.d ft4, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft4 ; RV32IFD-NEXT: fcvt.w.d a0, ft4
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f4: ; RV64IFD-LABEL: explicit_register_f4:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft4, fa0 ; RV64IFD-NEXT: fmv.d ft4, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft4 ; RV64IFD-NEXT: fcvt.w.d a0, ft4
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f4:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f4, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f4
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f4:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f4, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f4
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f4}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f4}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft4(double %a) nounwind { define i32 @explicit_register_ft4(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_ft4: ; RV32IFD-LABEL: explicit_register_ft4:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft4, fa0 ; RV32IFD-NEXT: fmv.d ft4, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft4 ; RV32IFD-NEXT: fcvt.w.d a0, ft4
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_ft4: ; RV64IFD-LABEL: explicit_register_ft4:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft4, fa0 ; RV64IFD-NEXT: fmv.d ft4, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft4 ; RV64IFD-NEXT: fcvt.w.d a0, ft4
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_ft4:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f4, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f4
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_ft4:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f4, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f4
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft4}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft4}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f5(double %a) nounwind { define i32 @explicit_register_f5(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f5: ; RV32IFD-LABEL: explicit_register_f5:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft5, fa0 ; RV32IFD-NEXT: fmv.d ft5, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft5 ; RV32IFD-NEXT: fcvt.w.d a0, ft5
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f5: ; RV64IFD-LABEL: explicit_register_f5:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft5, fa0 ; RV64IFD-NEXT: fmv.d ft5, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft5 ; RV64IFD-NEXT: fcvt.w.d a0, ft5
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f5:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f5, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f5
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f5:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f5, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f5
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f5}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f5}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft5(double %a) nounwind { define i32 @explicit_register_ft5(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_ft5: ; RV32IFD-LABEL: explicit_register_ft5:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft5, fa0 ; RV32IFD-NEXT: fmv.d ft5, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft5 ; RV32IFD-NEXT: fcvt.w.d a0, ft5
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_ft5: ; RV64IFD-LABEL: explicit_register_ft5:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft5, fa0 ; RV64IFD-NEXT: fmv.d ft5, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft5 ; RV64IFD-NEXT: fcvt.w.d a0, ft5
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_ft5:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f5, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f5
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_ft5:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f5, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f5
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft5}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft5}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f6(double %a) nounwind { define i32 @explicit_register_f6(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f6: ; RV32IFD-LABEL: explicit_register_f6:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft6, fa0 ; RV32IFD-NEXT: fmv.d ft6, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft6 ; RV32IFD-NEXT: fcvt.w.d a0, ft6
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f6: ; RV64IFD-LABEL: explicit_register_f6:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft6, fa0 ; RV64IFD-NEXT: fmv.d ft6, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft6 ; RV64IFD-NEXT: fcvt.w.d a0, ft6
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f6:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f6, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f6
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f6:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f6, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f6
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f6}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f6}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft6(double %a) nounwind { define i32 @explicit_register_ft6(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_ft6: ; RV32IFD-LABEL: explicit_register_ft6:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft6, fa0 ; RV32IFD-NEXT: fmv.d ft6, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft6 ; RV32IFD-NEXT: fcvt.w.d a0, ft6
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_ft6: ; RV64IFD-LABEL: explicit_register_ft6:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft6, fa0 ; RV64IFD-NEXT: fmv.d ft6, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft6 ; RV64IFD-NEXT: fcvt.w.d a0, ft6
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_ft6:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f6, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f6
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_ft6:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f6, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f6
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft6}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft6}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f7(double %a) nounwind { define i32 @explicit_register_f7(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f7: ; RV32IFD-LABEL: explicit_register_f7:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft7, fa0 ; RV32IFD-NEXT: fmv.d ft7, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft7 ; RV32IFD-NEXT: fcvt.w.d a0, ft7
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f7: ; RV64IFD-LABEL: explicit_register_f7:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft7, fa0 ; RV64IFD-NEXT: fmv.d ft7, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft7 ; RV64IFD-NEXT: fcvt.w.d a0, ft7
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f7:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f7, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f7
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f7:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f7, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f7
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f7}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f7}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft7(double %a) nounwind { define i32 @explicit_register_ft7(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_ft7: ; RV32IFD-LABEL: explicit_register_ft7:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft7, fa0 ; RV32IFD-NEXT: fmv.d ft7, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft7 ; RV32IFD-NEXT: fcvt.w.d a0, ft7
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_ft7: ; RV64IFD-LABEL: explicit_register_ft7:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft7, fa0 ; RV64IFD-NEXT: fmv.d ft7, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft7 ; RV64IFD-NEXT: fcvt.w.d a0, ft7
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_ft7:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f7, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f7
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_ft7:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f7, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f7
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft7}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft7}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f8` (`fs0`) as an input, so it should be saved. ; NOTE: This test uses `f8` (`fs0`) as an input, so it should be saved.
define i32 @explicit_register_f8(double %a) nounwind { define i32 @explicit_register_f8(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f8: ; RV32IFD-LABEL: explicit_register_f8:
Show All 14 Lines
; RV64IFD-NEXT: fsd fs0, 8(sp) ; RV64IFD-NEXT: fsd fs0, 8(sp)
; RV64IFD-NEXT: fmv.d fs0, fa0 ; RV64IFD-NEXT: fmv.d fs0, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs0 ; RV64IFD-NEXT: fcvt.w.d a0, fs0
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs0, 8(sp) ; RV64IFD-NEXT: fld fs0, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f8:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f8, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f8, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f8
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f8, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f8:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f8, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f8, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f8
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f8, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f8}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f8}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs0` (`f8`) as an input, so it should be saved. ; NOTE: This test uses `fs0` (`f8`) as an input, so it should be saved.
define i32 @explicit_register_fs0(double %a) nounwind { define i32 @explicit_register_fs0(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs0: ; RV32IFD-LABEL: explicit_register_fs0:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs0, 8(sp) ; RV64IFD-NEXT: fsd fs0, 8(sp)
; RV64IFD-NEXT: fmv.d fs0, fa0 ; RV64IFD-NEXT: fmv.d fs0, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs0 ; RV64IFD-NEXT: fcvt.w.d a0, fs0
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs0, 8(sp) ; RV64IFD-NEXT: fld fs0, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fs0:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f8, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f8, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f8
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f8, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fs0:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f8, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f8, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f8
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f8, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs0}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs0}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f9` (`fs1`) as an input, so it should be saved. ; NOTE: This test uses `f9` (`fs1`) as an input, so it should be saved.
define i32 @explicit_register_f9(double %a) nounwind { define i32 @explicit_register_f9(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f9: ; RV32IFD-LABEL: explicit_register_f9:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs1, 8(sp) ; RV64IFD-NEXT: fsd fs1, 8(sp)
; RV64IFD-NEXT: fmv.d fs1, fa0 ; RV64IFD-NEXT: fmv.d fs1, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs1 ; RV64IFD-NEXT: fcvt.w.d a0, fs1
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs1, 8(sp) ; RV64IFD-NEXT: fld fs1, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f9:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f9, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f9, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f9
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f9, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f9:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f9, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f9, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f9
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f9, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f9}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f9}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs1` (`f9`) as an input, so it should be saved. ; NOTE: This test uses `fs1` (`f9`) as an input, so it should be saved.
define i32 @explicit_register_fs1(double %a) nounwind { define i32 @explicit_register_fs1(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs1: ; RV32IFD-LABEL: explicit_register_fs1:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs1, 8(sp) ; RV64IFD-NEXT: fsd fs1, 8(sp)
; RV64IFD-NEXT: fmv.d fs1, fa0 ; RV64IFD-NEXT: fmv.d fs1, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs1 ; RV64IFD-NEXT: fcvt.w.d a0, fs1
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs1, 8(sp) ; RV64IFD-NEXT: fld fs1, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fs1:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f9, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f9, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f9
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f9, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fs1:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f9, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f9, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f9
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f9, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs1}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs1}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f10(double %a) nounwind { define i32 @explicit_register_f10(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f10: ; RV32IFD-LABEL: explicit_register_f10:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fa0 ; RV32IFD-NEXT: fcvt.w.d a0, fa0
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f10: ; RV64IFD-LABEL: explicit_register_f10:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fa0 ; RV64IFD-NEXT: fcvt.w.d a0, fa0
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f10:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f10
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f10:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f10
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f10}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f10}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_fa0(double %a) nounwind { define i32 @explicit_register_fa0(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fa0: ; RV32IFD-LABEL: explicit_register_fa0:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fa0 ; RV32IFD-NEXT: fcvt.w.d a0, fa0
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fa0: ; RV64IFD-LABEL: explicit_register_fa0:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fa0 ; RV64IFD-NEXT: fcvt.w.d a0, fa0
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fa0:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f10
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fa0:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f10
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa0}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa0}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f11(double %a) nounwind { define i32 @explicit_register_f11(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f11: ; RV32IFD-LABEL: explicit_register_f11:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d fa1, fa0 ; RV32IFD-NEXT: fmv.d fa1, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fa1 ; RV32IFD-NEXT: fcvt.w.d a0, fa1
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f11: ; RV64IFD-LABEL: explicit_register_f11:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d fa1, fa0 ; RV64IFD-NEXT: fmv.d fa1, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fa1 ; RV64IFD-NEXT: fcvt.w.d a0, fa1
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f11:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f11, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f11
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f11:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f11, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f11
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f11}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f11}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_fa1(double %a) nounwind { define i32 @explicit_register_fa1(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fa1: ; RV32IFD-LABEL: explicit_register_fa1:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d fa1, fa0 ; RV32IFD-NEXT: fmv.d fa1, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fa1 ; RV32IFD-NEXT: fcvt.w.d a0, fa1
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fa1: ; RV64IFD-LABEL: explicit_register_fa1:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d fa1, fa0 ; RV64IFD-NEXT: fmv.d fa1, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fa1 ; RV64IFD-NEXT: fcvt.w.d a0, fa1
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fa1:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f11, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f11
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fa1:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f11, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f11
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa1}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa1}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f12(double %a) nounwind { define i32 @explicit_register_f12(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f12: ; RV32IFD-LABEL: explicit_register_f12:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d fa2, fa0 ; RV32IFD-NEXT: fmv.d fa2, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fa2 ; RV32IFD-NEXT: fcvt.w.d a0, fa2
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f12: ; RV64IFD-LABEL: explicit_register_f12:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d fa2, fa0 ; RV64IFD-NEXT: fmv.d fa2, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fa2 ; RV64IFD-NEXT: fcvt.w.d a0, fa2
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f12:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f12, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f12
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f12:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f12, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f12
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f12}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f12}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_fa2(double %a) nounwind { define i32 @explicit_register_fa2(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fa2: ; RV32IFD-LABEL: explicit_register_fa2:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d fa2, fa0 ; RV32IFD-NEXT: fmv.d fa2, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fa2 ; RV32IFD-NEXT: fcvt.w.d a0, fa2
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fa2: ; RV64IFD-LABEL: explicit_register_fa2:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d fa2, fa0 ; RV64IFD-NEXT: fmv.d fa2, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fa2 ; RV64IFD-NEXT: fcvt.w.d a0, fa2
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fa2:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f12, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f12
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fa2:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f12, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f12
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa2}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa2}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f13(double %a) nounwind { define i32 @explicit_register_f13(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f13: ; RV32IFD-LABEL: explicit_register_f13:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d fa3, fa0 ; RV32IFD-NEXT: fmv.d fa3, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fa3 ; RV32IFD-NEXT: fcvt.w.d a0, fa3
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f13: ; RV64IFD-LABEL: explicit_register_f13:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d fa3, fa0 ; RV64IFD-NEXT: fmv.d fa3, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fa3 ; RV64IFD-NEXT: fcvt.w.d a0, fa3
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f13:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f13, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f13
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f13:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f13, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f13
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f13}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f13}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_fa3(double %a) nounwind { define i32 @explicit_register_fa3(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fa3: ; RV32IFD-LABEL: explicit_register_fa3:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d fa3, fa0 ; RV32IFD-NEXT: fmv.d fa3, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fa3 ; RV32IFD-NEXT: fcvt.w.d a0, fa3
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fa3: ; RV64IFD-LABEL: explicit_register_fa3:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d fa3, fa0 ; RV64IFD-NEXT: fmv.d fa3, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fa3 ; RV64IFD-NEXT: fcvt.w.d a0, fa3
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fa3:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f13, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f13
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fa3:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f13, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f13
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa3}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa3}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f14(double %a) nounwind { define i32 @explicit_register_f14(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f14: ; RV32IFD-LABEL: explicit_register_f14:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d fa4, fa0 ; RV32IFD-NEXT: fmv.d fa4, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fa4 ; RV32IFD-NEXT: fcvt.w.d a0, fa4
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f14: ; RV64IFD-LABEL: explicit_register_f14:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d fa4, fa0 ; RV64IFD-NEXT: fmv.d fa4, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fa4 ; RV64IFD-NEXT: fcvt.w.d a0, fa4
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f14:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f14, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f14
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f14:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f14, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f14
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f14}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f14}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_fa4(double %a) nounwind { define i32 @explicit_register_fa4(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fa4: ; RV32IFD-LABEL: explicit_register_fa4:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d fa4, fa0 ; RV32IFD-NEXT: fmv.d fa4, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fa4 ; RV32IFD-NEXT: fcvt.w.d a0, fa4
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fa4: ; RV64IFD-LABEL: explicit_register_fa4:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d fa4, fa0 ; RV64IFD-NEXT: fmv.d fa4, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fa4 ; RV64IFD-NEXT: fcvt.w.d a0, fa4
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fa4:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f14, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f14
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fa4:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f14, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f14
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa4}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa4}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f15(double %a) nounwind { define i32 @explicit_register_f15(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f15: ; RV32IFD-LABEL: explicit_register_f15:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d fa5, fa0 ; RV32IFD-NEXT: fmv.d fa5, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fa5 ; RV32IFD-NEXT: fcvt.w.d a0, fa5
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f15: ; RV64IFD-LABEL: explicit_register_f15:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d fa5, fa0 ; RV64IFD-NEXT: fmv.d fa5, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fa5 ; RV64IFD-NEXT: fcvt.w.d a0, fa5
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f15:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f15, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f15
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f15:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f15, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f15
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f15}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f15}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_fa5(double %a) nounwind { define i32 @explicit_register_fa5(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fa5: ; RV32IFD-LABEL: explicit_register_fa5:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d fa5, fa0 ; RV32IFD-NEXT: fmv.d fa5, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fa5 ; RV32IFD-NEXT: fcvt.w.d a0, fa5
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fa5: ; RV64IFD-LABEL: explicit_register_fa5:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d fa5, fa0 ; RV64IFD-NEXT: fmv.d fa5, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fa5 ; RV64IFD-NEXT: fcvt.w.d a0, fa5
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fa5:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f15, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f15
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fa5:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f15, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f15
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa5}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa5}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f16(double %a) nounwind { define i32 @explicit_register_f16(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f16: ; RV32IFD-LABEL: explicit_register_f16:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d fa6, fa0 ; RV32IFD-NEXT: fmv.d fa6, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fa6 ; RV32IFD-NEXT: fcvt.w.d a0, fa6
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f16: ; RV64IFD-LABEL: explicit_register_f16:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d fa6, fa0 ; RV64IFD-NEXT: fmv.d fa6, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fa6 ; RV64IFD-NEXT: fcvt.w.d a0, fa6
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f16:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f16, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f16
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f16:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f16, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f16
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f16}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f16}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_fa6(double %a) nounwind { define i32 @explicit_register_fa6(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fa6: ; RV32IFD-LABEL: explicit_register_fa6:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d fa6, fa0 ; RV32IFD-NEXT: fmv.d fa6, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fa6 ; RV32IFD-NEXT: fcvt.w.d a0, fa6
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fa6: ; RV64IFD-LABEL: explicit_register_fa6:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d fa6, fa0 ; RV64IFD-NEXT: fmv.d fa6, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fa6 ; RV64IFD-NEXT: fcvt.w.d a0, fa6
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fa6:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f16, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f16
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fa6:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f16, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f16
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa6}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa6}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f17(double %a) nounwind { define i32 @explicit_register_f17(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f17: ; RV32IFD-LABEL: explicit_register_f17:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d fa7, fa0 ; RV32IFD-NEXT: fmv.d fa7, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fa7 ; RV32IFD-NEXT: fcvt.w.d a0, fa7
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f17: ; RV64IFD-LABEL: explicit_register_f17:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d fa7, fa0 ; RV64IFD-NEXT: fmv.d fa7, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fa7 ; RV64IFD-NEXT: fcvt.w.d a0, fa7
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f17:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f17, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f17
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f17:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f17, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f17
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f17}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f17}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_fa7(double %a) nounwind { define i32 @explicit_register_fa7(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fa7: ; RV32IFD-LABEL: explicit_register_fa7:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d fa7, fa0 ; RV32IFD-NEXT: fmv.d fa7, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, fa7 ; RV32IFD-NEXT: fcvt.w.d a0, fa7
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_fa7: ; RV64IFD-LABEL: explicit_register_fa7:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d fa7, fa0 ; RV64IFD-NEXT: fmv.d fa7, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fa7 ; RV64IFD-NEXT: fcvt.w.d a0, fa7
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fa7:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f17, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f17
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fa7:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f17, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f17
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa7}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fa7}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f18` (`fs2`) as an input, so it should be saved. ; NOTE: This test uses `f18` (`fs2`) as an input, so it should be saved.
define i32 @explicit_register_f18(double %a) nounwind { define i32 @explicit_register_f18(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f18: ; RV32IFD-LABEL: explicit_register_f18:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs2, 8(sp) ; RV64IFD-NEXT: fsd fs2, 8(sp)
; RV64IFD-NEXT: fmv.d fs2, fa0 ; RV64IFD-NEXT: fmv.d fs2, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs2 ; RV64IFD-NEXT: fcvt.w.d a0, fs2
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs2, 8(sp) ; RV64IFD-NEXT: fld fs2, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f18:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f18, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f18, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f18
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f18, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f18:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f18, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f18, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f18
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f18, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f18}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f18}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs2` (`f18`) as an input, so it should be saved. ; NOTE: This test uses `fs2` (`f18`) as an input, so it should be saved.
define i32 @explicit_register_fs2(double %a) nounwind { define i32 @explicit_register_fs2(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs2: ; RV32IFD-LABEL: explicit_register_fs2:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs2, 8(sp) ; RV64IFD-NEXT: fsd fs2, 8(sp)
; RV64IFD-NEXT: fmv.d fs2, fa0 ; RV64IFD-NEXT: fmv.d fs2, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs2 ; RV64IFD-NEXT: fcvt.w.d a0, fs2
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs2, 8(sp) ; RV64IFD-NEXT: fld fs2, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fs2:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f18, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f18, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f18
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f18, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fs2:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f18, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f18, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f18
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f18, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs2}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs2}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f19` (`fs3`) as an input, so it should be saved. ; NOTE: This test uses `f19` (`fs3`) as an input, so it should be saved.
define i32 @explicit_register_f19(double %a) nounwind { define i32 @explicit_register_f19(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f19: ; RV32IFD-LABEL: explicit_register_f19:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs3, 8(sp) ; RV64IFD-NEXT: fsd fs3, 8(sp)
; RV64IFD-NEXT: fmv.d fs3, fa0 ; RV64IFD-NEXT: fmv.d fs3, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs3 ; RV64IFD-NEXT: fcvt.w.d a0, fs3
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs3, 8(sp) ; RV64IFD-NEXT: fld fs3, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f19:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f19, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f19, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f19
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f19, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f19:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f19, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f19, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f19
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f19, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f19}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f19}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs3` (`f19`) as an input, so it should be saved. ; NOTE: This test uses `fs3` (`f19`) as an input, so it should be saved.
define i32 @explicit_register_fs3(double %a) nounwind { define i32 @explicit_register_fs3(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs3: ; RV32IFD-LABEL: explicit_register_fs3:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs3, 8(sp) ; RV64IFD-NEXT: fsd fs3, 8(sp)
; RV64IFD-NEXT: fmv.d fs3, fa0 ; RV64IFD-NEXT: fmv.d fs3, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs3 ; RV64IFD-NEXT: fcvt.w.d a0, fs3
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs3, 8(sp) ; RV64IFD-NEXT: fld fs3, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fs3:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f19, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f19, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f19
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f19, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fs3:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f19, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f19, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f19
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f19, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs3}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs3}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f20` (`fs4`) as an input, so it should be saved. ; NOTE: This test uses `f20` (`fs4`) as an input, so it should be saved.
define i32 @explicit_register_f20(double %a) nounwind { define i32 @explicit_register_f20(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f20: ; RV32IFD-LABEL: explicit_register_f20:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs4, 8(sp) ; RV64IFD-NEXT: fsd fs4, 8(sp)
; RV64IFD-NEXT: fmv.d fs4, fa0 ; RV64IFD-NEXT: fmv.d fs4, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs4 ; RV64IFD-NEXT: fcvt.w.d a0, fs4
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs4, 8(sp) ; RV64IFD-NEXT: fld fs4, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f20:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f20, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f20, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f20
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f20, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f20:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f20, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f20, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f20
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f20, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f20}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f20}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs4` (`f20`) as an input, so it should be saved. ; NOTE: This test uses `fs4` (`f20`) as an input, so it should be saved.
define i32 @explicit_register_fs4(double %a) nounwind { define i32 @explicit_register_fs4(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs4: ; RV32IFD-LABEL: explicit_register_fs4:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs4, 8(sp) ; RV64IFD-NEXT: fsd fs4, 8(sp)
; RV64IFD-NEXT: fmv.d fs4, fa0 ; RV64IFD-NEXT: fmv.d fs4, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs4 ; RV64IFD-NEXT: fcvt.w.d a0, fs4
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs4, 8(sp) ; RV64IFD-NEXT: fld fs4, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fs4:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f20, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f20, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f20
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f20, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fs4:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f20, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f20, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f20
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f20, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs4}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs4}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f21` (`fs5`) as an input, so it should be saved. ; NOTE: This test uses `f21` (`fs5`) as an input, so it should be saved.
define i32 @explicit_register_f21(double %a) nounwind { define i32 @explicit_register_f21(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f21: ; RV32IFD-LABEL: explicit_register_f21:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs5, 8(sp) ; RV64IFD-NEXT: fsd fs5, 8(sp)
; RV64IFD-NEXT: fmv.d fs5, fa0 ; RV64IFD-NEXT: fmv.d fs5, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs5 ; RV64IFD-NEXT: fcvt.w.d a0, fs5
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs5, 8(sp) ; RV64IFD-NEXT: fld fs5, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f21:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f21, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f21, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f21
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f21, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f21:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f21, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f21, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f21
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f21, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f21}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f21}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs5` (`f21`) as an input, so it should be saved. ; NOTE: This test uses `fs5` (`f21`) as an input, so it should be saved.
define i32 @explicit_register_fs5(double %a) nounwind { define i32 @explicit_register_fs5(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs5: ; RV32IFD-LABEL: explicit_register_fs5:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs5, 8(sp) ; RV64IFD-NEXT: fsd fs5, 8(sp)
; RV64IFD-NEXT: fmv.d fs5, fa0 ; RV64IFD-NEXT: fmv.d fs5, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs5 ; RV64IFD-NEXT: fcvt.w.d a0, fs5
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs5, 8(sp) ; RV64IFD-NEXT: fld fs5, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fs5:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f21, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f21, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f21
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f21, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fs5:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f21, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f21, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f21
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f21, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs5}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs5}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f22` (`fs6`) as an input, so it should be saved. ; NOTE: This test uses `f22` (`fs6`) as an input, so it should be saved.
define i32 @explicit_register_f22(double %a) nounwind { define i32 @explicit_register_f22(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f22: ; RV32IFD-LABEL: explicit_register_f22:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs6, 8(sp) ; RV64IFD-NEXT: fsd fs6, 8(sp)
; RV64IFD-NEXT: fmv.d fs6, fa0 ; RV64IFD-NEXT: fmv.d fs6, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs6 ; RV64IFD-NEXT: fcvt.w.d a0, fs6
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs6, 8(sp) ; RV64IFD-NEXT: fld fs6, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f22:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f22, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f22, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f22
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f22, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f22:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f22, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f22, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f22
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f22, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f22}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f22}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs6` (`f22`) as an input, so it should be saved. ; NOTE: This test uses `fs6` (`f22`) as an input, so it should be saved.
define i32 @explicit_register_fs6(double %a) nounwind { define i32 @explicit_register_fs6(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs6: ; RV32IFD-LABEL: explicit_register_fs6:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs6, 8(sp) ; RV64IFD-NEXT: fsd fs6, 8(sp)
; RV64IFD-NEXT: fmv.d fs6, fa0 ; RV64IFD-NEXT: fmv.d fs6, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs6 ; RV64IFD-NEXT: fcvt.w.d a0, fs6
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs6, 8(sp) ; RV64IFD-NEXT: fld fs6, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fs6:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f22, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f22, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f22
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f22, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fs6:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f22, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f22, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f22
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f22, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs6}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs6}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f23` (`fs7`) as an input, so it should be saved. ; NOTE: This test uses `f23` (`fs7`) as an input, so it should be saved.
define i32 @explicit_register_f23(double %a) nounwind { define i32 @explicit_register_f23(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f23: ; RV32IFD-LABEL: explicit_register_f23:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs7, 8(sp) ; RV64IFD-NEXT: fsd fs7, 8(sp)
; RV64IFD-NEXT: fmv.d fs7, fa0 ; RV64IFD-NEXT: fmv.d fs7, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs7 ; RV64IFD-NEXT: fcvt.w.d a0, fs7
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs7, 8(sp) ; RV64IFD-NEXT: fld fs7, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f23:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f23, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f23, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f23
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f23, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f23:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f23, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f23, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f23
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f23, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f23}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f23}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs7` (`f23`) as an input, so it should be saved. ; NOTE: This test uses `fs7` (`f23`) as an input, so it should be saved.
define i32 @explicit_register_fs7(double %a) nounwind { define i32 @explicit_register_fs7(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs7: ; RV32IFD-LABEL: explicit_register_fs7:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs7, 8(sp) ; RV64IFD-NEXT: fsd fs7, 8(sp)
; RV64IFD-NEXT: fmv.d fs7, fa0 ; RV64IFD-NEXT: fmv.d fs7, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs7 ; RV64IFD-NEXT: fcvt.w.d a0, fs7
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs7, 8(sp) ; RV64IFD-NEXT: fld fs7, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fs7:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f23, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f23, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f23
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f23, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fs7:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f23, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f23, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f23
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f23, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs7}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs7}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f24` (`fs8`) as an input, so it should be saved. ; NOTE: This test uses `f24` (`fs8`) as an input, so it should be saved.
define i32 @explicit_register_f24(double %a) nounwind { define i32 @explicit_register_f24(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f24: ; RV32IFD-LABEL: explicit_register_f24:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs8, 8(sp) ; RV64IFD-NEXT: fsd fs8, 8(sp)
; RV64IFD-NEXT: fmv.d fs8, fa0 ; RV64IFD-NEXT: fmv.d fs8, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs8 ; RV64IFD-NEXT: fcvt.w.d a0, fs8
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs8, 8(sp) ; RV64IFD-NEXT: fld fs8, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f24:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f24, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f24, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f24
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f24, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f24:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f24, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f24, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f24
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f24, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f24}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f24}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs8` (`f24`) as an input, so it should be saved. ; NOTE: This test uses `fs8` (`f24`) as an input, so it should be saved.
define i32 @explicit_register_fs8(double %a) nounwind { define i32 @explicit_register_fs8(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs8: ; RV32IFD-LABEL: explicit_register_fs8:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs8, 8(sp) ; RV64IFD-NEXT: fsd fs8, 8(sp)
; RV64IFD-NEXT: fmv.d fs8, fa0 ; RV64IFD-NEXT: fmv.d fs8, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs8 ; RV64IFD-NEXT: fcvt.w.d a0, fs8
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs8, 8(sp) ; RV64IFD-NEXT: fld fs8, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fs8:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f24, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f24, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f24
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f24, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fs8:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f24, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f24, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f24
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f24, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs8}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs8}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f25` (`fs9`) as an input, so it should be saved. ; NOTE: This test uses `f25` (`fs9`) as an input, so it should be saved.
define i32 @explicit_register_f25(double %a) nounwind { define i32 @explicit_register_f25(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f25: ; RV32IFD-LABEL: explicit_register_f25:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs9, 8(sp) ; RV64IFD-NEXT: fsd fs9, 8(sp)
; RV64IFD-NEXT: fmv.d fs9, fa0 ; RV64IFD-NEXT: fmv.d fs9, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs9 ; RV64IFD-NEXT: fcvt.w.d a0, fs9
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs9, 8(sp) ; RV64IFD-NEXT: fld fs9, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f25:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f25, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f25, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f25
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f25, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f25:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f25, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f25, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f25
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f25, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f25}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f25}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs9` (`f25`) as an input, so it should be saved. ; NOTE: This test uses `fs9` (`f25`) as an input, so it should be saved.
define i32 @explicit_register_fs9(double %a) nounwind { define i32 @explicit_register_fs9(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs9: ; RV32IFD-LABEL: explicit_register_fs9:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs9, 8(sp) ; RV64IFD-NEXT: fsd fs9, 8(sp)
; RV64IFD-NEXT: fmv.d fs9, fa0 ; RV64IFD-NEXT: fmv.d fs9, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs9 ; RV64IFD-NEXT: fcvt.w.d a0, fs9
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs9, 8(sp) ; RV64IFD-NEXT: fld fs9, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fs9:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f25, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f25, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f25
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f25, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fs9:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f25, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f25, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f25
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f25, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs9}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs9}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f26` (`fs10`) as an input, so it should be saved. ; NOTE: This test uses `f26` (`fs10`) as an input, so it should be saved.
define i32 @explicit_register_f26(double %a) nounwind { define i32 @explicit_register_f26(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f26: ; RV32IFD-LABEL: explicit_register_f26:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs10, 8(sp) ; RV64IFD-NEXT: fsd fs10, 8(sp)
; RV64IFD-NEXT: fmv.d fs10, fa0 ; RV64IFD-NEXT: fmv.d fs10, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs10 ; RV64IFD-NEXT: fcvt.w.d a0, fs10
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs10, 8(sp) ; RV64IFD-NEXT: fld fs10, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f26:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f26, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f26, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f26
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f26, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f26:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f26, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f26, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f26
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f26, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f26}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f26}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs10` (`f26`) as an input, so it should be saved. ; NOTE: This test uses `fs10` (`f26`) as an input, so it should be saved.
define i32 @explicit_register_fs10(double %a) nounwind { define i32 @explicit_register_fs10(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs10: ; RV32IFD-LABEL: explicit_register_fs10:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs10, 8(sp) ; RV64IFD-NEXT: fsd fs10, 8(sp)
; RV64IFD-NEXT: fmv.d fs10, fa0 ; RV64IFD-NEXT: fmv.d fs10, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs10 ; RV64IFD-NEXT: fcvt.w.d a0, fs10
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs10, 8(sp) ; RV64IFD-NEXT: fld fs10, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fs10:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f26, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f26, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f26
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f26, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fs10:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f26, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f26, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f26
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f26, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs10}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs10}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f27` (`fs11`) as an input, so it should be saved. ; NOTE: This test uses `f27` (`fs11`) as an input, so it should be saved.
define i32 @explicit_register_f27(double %a) nounwind { define i32 @explicit_register_f27(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f27: ; RV32IFD-LABEL: explicit_register_f27:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs11, 8(sp) ; RV64IFD-NEXT: fsd fs11, 8(sp)
; RV64IFD-NEXT: fmv.d fs11, fa0 ; RV64IFD-NEXT: fmv.d fs11, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs11 ; RV64IFD-NEXT: fcvt.w.d a0, fs11
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs11, 8(sp) ; RV64IFD-NEXT: fld fs11, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f27:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f27, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f27, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f27
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f27, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f27:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f27, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f27, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f27
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f27, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f27}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f27}"(double %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs11` (`f27`) as an input, so it should be saved. ; NOTE: This test uses `fs11` (`f27`) as an input, so it should be saved.
define i32 @explicit_register_fs11(double %a) nounwind { define i32 @explicit_register_fs11(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_fs11: ; RV32IFD-LABEL: explicit_register_fs11:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
Show All 13 Lines
; RV64IFD-NEXT: fsd fs11, 8(sp) ; RV64IFD-NEXT: fsd fs11, 8(sp)
; RV64IFD-NEXT: fmv.d fs11, fa0 ; RV64IFD-NEXT: fmv.d fs11, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, fs11 ; RV64IFD-NEXT: fcvt.w.d a0, fs11
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: fld fs11, 8(sp) ; RV64IFD-NEXT: fld fs11, 8(sp)
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_fs11:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV32IFD-NO-ABI-NEXT: fsd f27, 8(x2)
; RV32IFD-NO-ABI-NEXT: fmv.d f27, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f27
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: fld f27, 8(x2)
; RV32IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_fs11:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: addi x2, x2, -16
; RV64IFD-NO-ABI-NEXT: fsd f27, 8(x2)
; RV64IFD-NO-ABI-NEXT: fmv.d f27, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f27
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: fld f27, 8(x2)
; RV64IFD-NO-ABI-NEXT: addi x2, x2, 16
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs11}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{fs11}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f28(double %a) nounwind { define i32 @explicit_register_f28(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f28: ; RV32IFD-LABEL: explicit_register_f28:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft8, fa0 ; RV32IFD-NEXT: fmv.d ft8, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft8 ; RV32IFD-NEXT: fcvt.w.d a0, ft8
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f28: ; RV64IFD-LABEL: explicit_register_f28:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft8, fa0 ; RV64IFD-NEXT: fmv.d ft8, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft8 ; RV64IFD-NEXT: fcvt.w.d a0, ft8
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f28:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f28, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f28
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f28:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f28, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f28
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f28}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f28}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft8(double %a) nounwind { define i32 @explicit_register_ft8(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_ft8: ; RV32IFD-LABEL: explicit_register_ft8:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft8, fa0 ; RV32IFD-NEXT: fmv.d ft8, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft8 ; RV32IFD-NEXT: fcvt.w.d a0, ft8
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_ft8: ; RV64IFD-LABEL: explicit_register_ft8:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft8, fa0 ; RV64IFD-NEXT: fmv.d ft8, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft8 ; RV64IFD-NEXT: fcvt.w.d a0, ft8
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_ft8:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f28, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f28
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_ft8:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f28, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f28
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft8}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft8}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f29(double %a) nounwind { define i32 @explicit_register_f29(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f29: ; RV32IFD-LABEL: explicit_register_f29:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft9, fa0 ; RV32IFD-NEXT: fmv.d ft9, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft9 ; RV32IFD-NEXT: fcvt.w.d a0, ft9
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f29: ; RV64IFD-LABEL: explicit_register_f29:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft9, fa0 ; RV64IFD-NEXT: fmv.d ft9, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft9 ; RV64IFD-NEXT: fcvt.w.d a0, ft9
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f29:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f29, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f29
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f29:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f29, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f29
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f29}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f29}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft9(double %a) nounwind { define i32 @explicit_register_ft9(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_ft9: ; RV32IFD-LABEL: explicit_register_ft9:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft9, fa0 ; RV32IFD-NEXT: fmv.d ft9, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft9 ; RV32IFD-NEXT: fcvt.w.d a0, ft9
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_ft9: ; RV64IFD-LABEL: explicit_register_ft9:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft9, fa0 ; RV64IFD-NEXT: fmv.d ft9, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft9 ; RV64IFD-NEXT: fcvt.w.d a0, ft9
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_ft9:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f29, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f29
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_ft9:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f29, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f29
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft9}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft9}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f30(double %a) nounwind { define i32 @explicit_register_f30(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f30: ; RV32IFD-LABEL: explicit_register_f30:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft10, fa0 ; RV32IFD-NEXT: fmv.d ft10, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft10 ; RV32IFD-NEXT: fcvt.w.d a0, ft10
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f30: ; RV64IFD-LABEL: explicit_register_f30:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft10, fa0 ; RV64IFD-NEXT: fmv.d ft10, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft10 ; RV64IFD-NEXT: fcvt.w.d a0, ft10
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f30:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f30, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f30
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f30:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f30, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f30
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f30}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f30}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft10(double %a) nounwind { define i32 @explicit_register_ft10(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_ft10: ; RV32IFD-LABEL: explicit_register_ft10:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft10, fa0 ; RV32IFD-NEXT: fmv.d ft10, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft10 ; RV32IFD-NEXT: fcvt.w.d a0, ft10
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_ft10: ; RV64IFD-LABEL: explicit_register_ft10:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft10, fa0 ; RV64IFD-NEXT: fmv.d ft10, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft10 ; RV64IFD-NEXT: fcvt.w.d a0, ft10
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_ft10:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f30, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f30
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_ft10:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f30, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f30
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft10}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft10}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f31(double %a) nounwind { define i32 @explicit_register_f31(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_f31: ; RV32IFD-LABEL: explicit_register_f31:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft11, fa0 ; RV32IFD-NEXT: fmv.d ft11, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft11 ; RV32IFD-NEXT: fcvt.w.d a0, ft11
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_f31: ; RV64IFD-LABEL: explicit_register_f31:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft11, fa0 ; RV64IFD-NEXT: fmv.d ft11, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft11 ; RV64IFD-NEXT: fcvt.w.d a0, ft11
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_f31:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f31, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f31
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_f31:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f31, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f31
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f31}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{f31}"(double %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft11(double %a) nounwind { define i32 @explicit_register_ft11(double %a) nounwind {
; RV32IFD-LABEL: explicit_register_ft11: ; RV32IFD-LABEL: explicit_register_ft11:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmv.d ft11, fa0 ; RV32IFD-NEXT: fmv.d ft11, fa0
; RV32IFD-NEXT: #APP ; RV32IFD-NEXT: #APP
; RV32IFD-NEXT: fcvt.w.d a0, ft11 ; RV32IFD-NEXT: fcvt.w.d a0, ft11
; RV32IFD-NEXT: #NO_APP ; RV32IFD-NEXT: #NO_APP
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
; RV64IFD-LABEL: explicit_register_ft11: ; RV64IFD-LABEL: explicit_register_ft11:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d ft11, fa0 ; RV64IFD-NEXT: fmv.d ft11, fa0
; RV64IFD-NEXT: #APP ; RV64IFD-NEXT: #APP
; RV64IFD-NEXT: fcvt.w.d a0, ft11 ; RV64IFD-NEXT: fcvt.w.d a0, ft11
; RV64IFD-NEXT: #NO_APP ; RV64IFD-NEXT: #NO_APP
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
;
; RV32IFD-NO-ABI-LABEL: explicit_register_ft11:
; RV32IFD-NO-ABI: # %bb.0:
; RV32IFD-NO-ABI-NEXT: fmv.d f31, f10
; RV32IFD-NO-ABI-NEXT: #APP
; RV32IFD-NO-ABI-NEXT: fcvt.w.d x10, f31
; RV32IFD-NO-ABI-NEXT: #NO_APP
; RV32IFD-NO-ABI-NEXT: ret
;
; RV64IFD-NO-ABI-LABEL: explicit_register_ft11:
; RV64IFD-NO-ABI: # %bb.0:
; RV64IFD-NO-ABI-NEXT: fmv.d f31, f10
; RV64IFD-NO-ABI-NEXT: #APP
; RV64IFD-NO-ABI-NEXT: fcvt.w.d x10, f31
; RV64IFD-NO-ABI-NEXT: #NO_APP
; RV64IFD-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft11}"(double %a) %1 = tail call i32 asm "fcvt.w.d $0, $1", "=r,{ft11}"(double %a)
ret i32 %1 ret i32 %1
} }

llvm/test/CodeGen/RISCV/inline-asm-f-abi-names.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32IF %s ; RUN: | FileCheck -check-prefix=RV32IF %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \ ; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64IF %s ; RUN: | FileCheck -check-prefix=RV64IF %s
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f -verify-machineinstrs -riscv-arch-reg-names < %s \
; RUN: | FileCheck -check-prefix=RV32IF-NO-ABI %s
; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f -verify-machineinstrs -riscv-arch-reg-names < %s \
; RUN: | FileCheck -check-prefix=RV64IF-NO-ABI %s
; These test that we can use both the architectural names (x*) and the ABI names ; These test that we can use both the architectural names (x*) and the ABI names
; (a*, s*, t* etc) to refer to registers in inline asm constraint lists. In each ; (a*, s*, t* etc) to refer to registers in inline asm constraint lists. In each
; case, the named register should be used for the source register of the `addi`. ; case, the named register should be used for the source register of the `addi`.
; It is very likely that `a0` will be chosen as the designation register, but ; It is very likely that `a0` will be chosen as the designation register, but
; this is left to the compiler to choose. ; this is left to the compiler to choose.
; ;
; The inline assembly will, by default, contain the ABI names for the registers. ; The inline assembly will, by default, contain the ABI names for the registers,
; unless `-riscv-arch-reg-names` is passed to llc to print the architectural
; names.
; ;
; Parenthesised registers in comments are the other aliases for this register. ; Parenthesised registers in comments are the other aliases for this register.
define i32 @explicit_register_f0(float %a) nounwind { define i32 @explicit_register_f0(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f0: ; RV32IF-LABEL: explicit_register_f0:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft0, fa0 ; RV32IF-NEXT: fmv.s ft0, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft0 ; RV32IF-NEXT: fcvt.w.s a0, ft0
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f0: ; RV64IF-LABEL: explicit_register_f0:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft0, fa0 ; RV64IF-NEXT: fmv.s ft0, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft0 ; RV64IF-NEXT: fcvt.w.s a0, ft0
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f0:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f0, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f0
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f0:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f0, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f0
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f0}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f0}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft0(float %a) nounwind { define i32 @explicit_register_ft0(float %a) nounwind {
; RV32IF-LABEL: explicit_register_ft0: ; RV32IF-LABEL: explicit_register_ft0:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft0, fa0 ; RV32IF-NEXT: fmv.s ft0, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft0 ; RV32IF-NEXT: fcvt.w.s a0, ft0
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_ft0: ; RV64IF-LABEL: explicit_register_ft0:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft0, fa0 ; RV64IF-NEXT: fmv.s ft0, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft0 ; RV64IF-NEXT: fcvt.w.s a0, ft0
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_ft0:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f0, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f0
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_ft0:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f0, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f0
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft0}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft0}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f1(float %a) nounwind { define i32 @explicit_register_f1(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f1: ; RV32IF-LABEL: explicit_register_f1:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft1, fa0 ; RV32IF-NEXT: fmv.s ft1, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft1 ; RV32IF-NEXT: fcvt.w.s a0, ft1
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f1: ; RV64IF-LABEL: explicit_register_f1:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft1, fa0 ; RV64IF-NEXT: fmv.s ft1, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft1 ; RV64IF-NEXT: fcvt.w.s a0, ft1
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f1:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f1, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f1
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f1:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f1, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f1
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f1}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f1}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft1(float %a) nounwind { define i32 @explicit_register_ft1(float %a) nounwind {
; RV32IF-LABEL: explicit_register_ft1: ; RV32IF-LABEL: explicit_register_ft1:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft1, fa0 ; RV32IF-NEXT: fmv.s ft1, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft1 ; RV32IF-NEXT: fcvt.w.s a0, ft1
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_ft1: ; RV64IF-LABEL: explicit_register_ft1:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft1, fa0 ; RV64IF-NEXT: fmv.s ft1, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft1 ; RV64IF-NEXT: fcvt.w.s a0, ft1
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_ft1:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f1, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f1
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_ft1:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f1, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f1
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft1}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft1}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f2(float %a) nounwind { define i32 @explicit_register_f2(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f2: ; RV32IF-LABEL: explicit_register_f2:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft2, fa0 ; RV32IF-NEXT: fmv.s ft2, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft2 ; RV32IF-NEXT: fcvt.w.s a0, ft2
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f2: ; RV64IF-LABEL: explicit_register_f2:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft2, fa0 ; RV64IF-NEXT: fmv.s ft2, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft2 ; RV64IF-NEXT: fcvt.w.s a0, ft2
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f2:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f2, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f2
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f2:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f2, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f2
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f2}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f2}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft2(float %a) nounwind { define i32 @explicit_register_ft2(float %a) nounwind {
; RV32IF-LABEL: explicit_register_ft2: ; RV32IF-LABEL: explicit_register_ft2:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft2, fa0 ; RV32IF-NEXT: fmv.s ft2, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft2 ; RV32IF-NEXT: fcvt.w.s a0, ft2
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_ft2: ; RV64IF-LABEL: explicit_register_ft2:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft2, fa0 ; RV64IF-NEXT: fmv.s ft2, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft2 ; RV64IF-NEXT: fcvt.w.s a0, ft2
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_ft2:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f2, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f2
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_ft2:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f2, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f2
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft2}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft2}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f3(float %a) nounwind { define i32 @explicit_register_f3(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f3: ; RV32IF-LABEL: explicit_register_f3:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft3, fa0 ; RV32IF-NEXT: fmv.s ft3, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft3 ; RV32IF-NEXT: fcvt.w.s a0, ft3
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f3: ; RV64IF-LABEL: explicit_register_f3:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft3, fa0 ; RV64IF-NEXT: fmv.s ft3, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft3 ; RV64IF-NEXT: fcvt.w.s a0, ft3
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f3:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f3, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f3
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f3:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f3, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f3
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f3}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f3}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft3(float %a) nounwind { define i32 @explicit_register_ft3(float %a) nounwind {
; RV32IF-LABEL: explicit_register_ft3: ; RV32IF-LABEL: explicit_register_ft3:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft3, fa0 ; RV32IF-NEXT: fmv.s ft3, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft3 ; RV32IF-NEXT: fcvt.w.s a0, ft3
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_ft3: ; RV64IF-LABEL: explicit_register_ft3:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft3, fa0 ; RV64IF-NEXT: fmv.s ft3, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft3 ; RV64IF-NEXT: fcvt.w.s a0, ft3
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_ft3:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f3, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f3
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_ft3:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f3, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f3
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft3}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft3}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f4(float %a) nounwind { define i32 @explicit_register_f4(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f4: ; RV32IF-LABEL: explicit_register_f4:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft4, fa0 ; RV32IF-NEXT: fmv.s ft4, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft4 ; RV32IF-NEXT: fcvt.w.s a0, ft4
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f4: ; RV64IF-LABEL: explicit_register_f4:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft4, fa0 ; RV64IF-NEXT: fmv.s ft4, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft4 ; RV64IF-NEXT: fcvt.w.s a0, ft4
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f4:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f4, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f4
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f4:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f4, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f4
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f4}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f4}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft4(float %a) nounwind { define i32 @explicit_register_ft4(float %a) nounwind {
; RV32IF-LABEL: explicit_register_ft4: ; RV32IF-LABEL: explicit_register_ft4:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft4, fa0 ; RV32IF-NEXT: fmv.s ft4, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft4 ; RV32IF-NEXT: fcvt.w.s a0, ft4
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_ft4: ; RV64IF-LABEL: explicit_register_ft4:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft4, fa0 ; RV64IF-NEXT: fmv.s ft4, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft4 ; RV64IF-NEXT: fcvt.w.s a0, ft4
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_ft4:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f4, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f4
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_ft4:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f4, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f4
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft4}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft4}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f5(float %a) nounwind { define i32 @explicit_register_f5(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f5: ; RV32IF-LABEL: explicit_register_f5:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft5, fa0 ; RV32IF-NEXT: fmv.s ft5, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft5 ; RV32IF-NEXT: fcvt.w.s a0, ft5
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f5: ; RV64IF-LABEL: explicit_register_f5:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft5, fa0 ; RV64IF-NEXT: fmv.s ft5, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft5 ; RV64IF-NEXT: fcvt.w.s a0, ft5
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f5:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f5, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f5
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f5:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f5, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f5
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f5}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f5}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft5(float %a) nounwind { define i32 @explicit_register_ft5(float %a) nounwind {
; RV32IF-LABEL: explicit_register_ft5: ; RV32IF-LABEL: explicit_register_ft5:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft5, fa0 ; RV32IF-NEXT: fmv.s ft5, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft5 ; RV32IF-NEXT: fcvt.w.s a0, ft5
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_ft5: ; RV64IF-LABEL: explicit_register_ft5:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft5, fa0 ; RV64IF-NEXT: fmv.s ft5, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft5 ; RV64IF-NEXT: fcvt.w.s a0, ft5
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_ft5:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f5, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f5
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_ft5:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f5, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f5
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft5}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft5}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f6(float %a) nounwind { define i32 @explicit_register_f6(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f6: ; RV32IF-LABEL: explicit_register_f6:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft6, fa0 ; RV32IF-NEXT: fmv.s ft6, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft6 ; RV32IF-NEXT: fcvt.w.s a0, ft6
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f6: ; RV64IF-LABEL: explicit_register_f6:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft6, fa0 ; RV64IF-NEXT: fmv.s ft6, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft6 ; RV64IF-NEXT: fcvt.w.s a0, ft6
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f6:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f6, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f6
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f6:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f6, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f6
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f6}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f6}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft6(float %a) nounwind { define i32 @explicit_register_ft6(float %a) nounwind {
; RV32IF-LABEL: explicit_register_ft6: ; RV32IF-LABEL: explicit_register_ft6:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft6, fa0 ; RV32IF-NEXT: fmv.s ft6, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft6 ; RV32IF-NEXT: fcvt.w.s a0, ft6
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_ft6: ; RV64IF-LABEL: explicit_register_ft6:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft6, fa0 ; RV64IF-NEXT: fmv.s ft6, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft6 ; RV64IF-NEXT: fcvt.w.s a0, ft6
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_ft6:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f6, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f6
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_ft6:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f6, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f6
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft6}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft6}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f7(float %a) nounwind { define i32 @explicit_register_f7(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f7: ; RV32IF-LABEL: explicit_register_f7:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft7, fa0 ; RV32IF-NEXT: fmv.s ft7, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft7 ; RV32IF-NEXT: fcvt.w.s a0, ft7
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f7: ; RV64IF-LABEL: explicit_register_f7:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft7, fa0 ; RV64IF-NEXT: fmv.s ft7, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft7 ; RV64IF-NEXT: fcvt.w.s a0, ft7
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f7:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f7, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f7
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f7:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f7, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f7
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f7}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f7}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft7(float %a) nounwind { define i32 @explicit_register_ft7(float %a) nounwind {
; RV32IF-LABEL: explicit_register_ft7: ; RV32IF-LABEL: explicit_register_ft7:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft7, fa0 ; RV32IF-NEXT: fmv.s ft7, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft7 ; RV32IF-NEXT: fcvt.w.s a0, ft7
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_ft7: ; RV64IF-LABEL: explicit_register_ft7:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft7, fa0 ; RV64IF-NEXT: fmv.s ft7, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft7 ; RV64IF-NEXT: fcvt.w.s a0, ft7
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_ft7:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f7, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f7
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_ft7:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f7, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f7
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft7}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft7}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f8` (`fs0`) as an input, so it should be saved. ; NOTE: This test uses `f8` (`fs0`) as an input, so it should be saved.
define i32 @explicit_register_f8(float %a) nounwind { define i32 @explicit_register_f8(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f8: ; RV32IF-LABEL: explicit_register_f8:
Show All 14 Lines
; RV64IF-NEXT: fsw fs0, 12(sp) ; RV64IF-NEXT: fsw fs0, 12(sp)
; RV64IF-NEXT: fmv.s fs0, fa0 ; RV64IF-NEXT: fmv.s fs0, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs0 ; RV64IF-NEXT: fcvt.w.s a0, fs0
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs0, 12(sp) ; RV64IF-NEXT: flw fs0, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f8:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f8, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f8, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f8
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f8, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f8:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f8, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f8, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f8
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f8, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f8}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f8}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs0` (`f8`) as an input, so it should be saved. ; NOTE: This test uses `fs0` (`f8`) as an input, so it should be saved.
define i32 @explicit_register_fs0(float %a) nounwind { define i32 @explicit_register_fs0(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs0: ; RV32IF-LABEL: explicit_register_fs0:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs0, 12(sp) ; RV64IF-NEXT: fsw fs0, 12(sp)
; RV64IF-NEXT: fmv.s fs0, fa0 ; RV64IF-NEXT: fmv.s fs0, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs0 ; RV64IF-NEXT: fcvt.w.s a0, fs0
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs0, 12(sp) ; RV64IF-NEXT: flw fs0, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fs0:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f8, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f8, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f8
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f8, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fs0:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f8, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f8, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f8
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f8, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs0}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs0}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f9` (`fs1`) as an input, so it should be saved. ; NOTE: This test uses `f9` (`fs1`) as an input, so it should be saved.
define i32 @explicit_register_f9(float %a) nounwind { define i32 @explicit_register_f9(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f9: ; RV32IF-LABEL: explicit_register_f9:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs1, 12(sp) ; RV64IF-NEXT: fsw fs1, 12(sp)
; RV64IF-NEXT: fmv.s fs1, fa0 ; RV64IF-NEXT: fmv.s fs1, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs1 ; RV64IF-NEXT: fcvt.w.s a0, fs1
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs1, 12(sp) ; RV64IF-NEXT: flw fs1, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f9:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f9, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f9, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f9
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f9, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f9:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f9, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f9, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f9
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f9, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f9}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f9}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs1` (`f9`) as an input, so it should be saved. ; NOTE: This test uses `fs1` (`f9`) as an input, so it should be saved.
define i32 @explicit_register_fs1(float %a) nounwind { define i32 @explicit_register_fs1(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs1: ; RV32IF-LABEL: explicit_register_fs1:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs1, 12(sp) ; RV64IF-NEXT: fsw fs1, 12(sp)
; RV64IF-NEXT: fmv.s fs1, fa0 ; RV64IF-NEXT: fmv.s fs1, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs1 ; RV64IF-NEXT: fcvt.w.s a0, fs1
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs1, 12(sp) ; RV64IF-NEXT: flw fs1, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fs1:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f9, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f9, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f9
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f9, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fs1:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f9, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f9, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f9
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f9, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs1}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs1}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f10(float %a) nounwind { define i32 @explicit_register_f10(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f10: ; RV32IF-LABEL: explicit_register_f10:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fa0 ; RV32IF-NEXT: fcvt.w.s a0, fa0
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f10: ; RV64IF-LABEL: explicit_register_f10:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fa0 ; RV64IF-NEXT: fcvt.w.s a0, fa0
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f10:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f10
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f10:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f10
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f10}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f10}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_fa0(float %a) nounwind { define i32 @explicit_register_fa0(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fa0: ; RV32IF-LABEL: explicit_register_fa0:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fa0 ; RV32IF-NEXT: fcvt.w.s a0, fa0
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fa0: ; RV64IF-LABEL: explicit_register_fa0:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fa0 ; RV64IF-NEXT: fcvt.w.s a0, fa0
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fa0:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f10
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fa0:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f10
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa0}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa0}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f11(float %a) nounwind { define i32 @explicit_register_f11(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f11: ; RV32IF-LABEL: explicit_register_f11:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s fa1, fa0 ; RV32IF-NEXT: fmv.s fa1, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fa1 ; RV32IF-NEXT: fcvt.w.s a0, fa1
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f11: ; RV64IF-LABEL: explicit_register_f11:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s fa1, fa0 ; RV64IF-NEXT: fmv.s fa1, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fa1 ; RV64IF-NEXT: fcvt.w.s a0, fa1
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f11:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f11, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f11
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f11:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f11, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f11
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f11}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f11}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_fa1(float %a) nounwind { define i32 @explicit_register_fa1(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fa1: ; RV32IF-LABEL: explicit_register_fa1:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s fa1, fa0 ; RV32IF-NEXT: fmv.s fa1, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fa1 ; RV32IF-NEXT: fcvt.w.s a0, fa1
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fa1: ; RV64IF-LABEL: explicit_register_fa1:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s fa1, fa0 ; RV64IF-NEXT: fmv.s fa1, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fa1 ; RV64IF-NEXT: fcvt.w.s a0, fa1
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fa1:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f11, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f11
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fa1:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f11, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f11
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa1}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa1}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f12(float %a) nounwind { define i32 @explicit_register_f12(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f12: ; RV32IF-LABEL: explicit_register_f12:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s fa2, fa0 ; RV32IF-NEXT: fmv.s fa2, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fa2 ; RV32IF-NEXT: fcvt.w.s a0, fa2
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f12: ; RV64IF-LABEL: explicit_register_f12:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s fa2, fa0 ; RV64IF-NEXT: fmv.s fa2, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fa2 ; RV64IF-NEXT: fcvt.w.s a0, fa2
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f12:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f12, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f12
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f12:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f12, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f12
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f12}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f12}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_fa2(float %a) nounwind { define i32 @explicit_register_fa2(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fa2: ; RV32IF-LABEL: explicit_register_fa2:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s fa2, fa0 ; RV32IF-NEXT: fmv.s fa2, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fa2 ; RV32IF-NEXT: fcvt.w.s a0, fa2
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fa2: ; RV64IF-LABEL: explicit_register_fa2:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s fa2, fa0 ; RV64IF-NEXT: fmv.s fa2, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fa2 ; RV64IF-NEXT: fcvt.w.s a0, fa2
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fa2:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f12, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f12
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fa2:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f12, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f12
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa2}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa2}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f13(float %a) nounwind { define i32 @explicit_register_f13(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f13: ; RV32IF-LABEL: explicit_register_f13:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s fa3, fa0 ; RV32IF-NEXT: fmv.s fa3, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fa3 ; RV32IF-NEXT: fcvt.w.s a0, fa3
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f13: ; RV64IF-LABEL: explicit_register_f13:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s fa3, fa0 ; RV64IF-NEXT: fmv.s fa3, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fa3 ; RV64IF-NEXT: fcvt.w.s a0, fa3
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f13:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f13, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f13
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f13:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f13, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f13
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f13}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f13}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_fa3(float %a) nounwind { define i32 @explicit_register_fa3(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fa3: ; RV32IF-LABEL: explicit_register_fa3:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s fa3, fa0 ; RV32IF-NEXT: fmv.s fa3, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fa3 ; RV32IF-NEXT: fcvt.w.s a0, fa3
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fa3: ; RV64IF-LABEL: explicit_register_fa3:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s fa3, fa0 ; RV64IF-NEXT: fmv.s fa3, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fa3 ; RV64IF-NEXT: fcvt.w.s a0, fa3
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fa3:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f13, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f13
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fa3:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f13, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f13
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa3}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa3}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f14(float %a) nounwind { define i32 @explicit_register_f14(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f14: ; RV32IF-LABEL: explicit_register_f14:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s fa4, fa0 ; RV32IF-NEXT: fmv.s fa4, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fa4 ; RV32IF-NEXT: fcvt.w.s a0, fa4
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f14: ; RV64IF-LABEL: explicit_register_f14:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s fa4, fa0 ; RV64IF-NEXT: fmv.s fa4, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fa4 ; RV64IF-NEXT: fcvt.w.s a0, fa4
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f14:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f14, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f14
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f14:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f14, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f14
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f14}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f14}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_fa4(float %a) nounwind { define i32 @explicit_register_fa4(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fa4: ; RV32IF-LABEL: explicit_register_fa4:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s fa4, fa0 ; RV32IF-NEXT: fmv.s fa4, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fa4 ; RV32IF-NEXT: fcvt.w.s a0, fa4
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fa4: ; RV64IF-LABEL: explicit_register_fa4:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s fa4, fa0 ; RV64IF-NEXT: fmv.s fa4, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fa4 ; RV64IF-NEXT: fcvt.w.s a0, fa4
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fa4:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f14, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f14
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fa4:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f14, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f14
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa4}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa4}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f15(float %a) nounwind { define i32 @explicit_register_f15(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f15: ; RV32IF-LABEL: explicit_register_f15:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s fa5, fa0 ; RV32IF-NEXT: fmv.s fa5, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fa5 ; RV32IF-NEXT: fcvt.w.s a0, fa5
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f15: ; RV64IF-LABEL: explicit_register_f15:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s fa5, fa0 ; RV64IF-NEXT: fmv.s fa5, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fa5 ; RV64IF-NEXT: fcvt.w.s a0, fa5
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f15:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f15, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f15
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f15:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f15, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f15
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f15}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f15}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_fa5(float %a) nounwind { define i32 @explicit_register_fa5(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fa5: ; RV32IF-LABEL: explicit_register_fa5:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s fa5, fa0 ; RV32IF-NEXT: fmv.s fa5, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fa5 ; RV32IF-NEXT: fcvt.w.s a0, fa5
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fa5: ; RV64IF-LABEL: explicit_register_fa5:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s fa5, fa0 ; RV64IF-NEXT: fmv.s fa5, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fa5 ; RV64IF-NEXT: fcvt.w.s a0, fa5
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fa5:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f15, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f15
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fa5:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f15, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f15
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa5}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa5}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f16(float %a) nounwind { define i32 @explicit_register_f16(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f16: ; RV32IF-LABEL: explicit_register_f16:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s fa6, fa0 ; RV32IF-NEXT: fmv.s fa6, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fa6 ; RV32IF-NEXT: fcvt.w.s a0, fa6
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f16: ; RV64IF-LABEL: explicit_register_f16:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s fa6, fa0 ; RV64IF-NEXT: fmv.s fa6, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fa6 ; RV64IF-NEXT: fcvt.w.s a0, fa6
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f16:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f16, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f16
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f16:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f16, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f16
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f16}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f16}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_fa6(float %a) nounwind { define i32 @explicit_register_fa6(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fa6: ; RV32IF-LABEL: explicit_register_fa6:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s fa6, fa0 ; RV32IF-NEXT: fmv.s fa6, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fa6 ; RV32IF-NEXT: fcvt.w.s a0, fa6
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fa6: ; RV64IF-LABEL: explicit_register_fa6:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s fa6, fa0 ; RV64IF-NEXT: fmv.s fa6, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fa6 ; RV64IF-NEXT: fcvt.w.s a0, fa6
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fa6:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f16, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f16
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fa6:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f16, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f16
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa6}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa6}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f17(float %a) nounwind { define i32 @explicit_register_f17(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f17: ; RV32IF-LABEL: explicit_register_f17:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s fa7, fa0 ; RV32IF-NEXT: fmv.s fa7, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fa7 ; RV32IF-NEXT: fcvt.w.s a0, fa7
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f17: ; RV64IF-LABEL: explicit_register_f17:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s fa7, fa0 ; RV64IF-NEXT: fmv.s fa7, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fa7 ; RV64IF-NEXT: fcvt.w.s a0, fa7
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f17:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f17, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f17
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f17:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f17, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f17
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f17}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f17}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_fa7(float %a) nounwind { define i32 @explicit_register_fa7(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fa7: ; RV32IF-LABEL: explicit_register_fa7:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s fa7, fa0 ; RV32IF-NEXT: fmv.s fa7, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, fa7 ; RV32IF-NEXT: fcvt.w.s a0, fa7
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_fa7: ; RV64IF-LABEL: explicit_register_fa7:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s fa7, fa0 ; RV64IF-NEXT: fmv.s fa7, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fa7 ; RV64IF-NEXT: fcvt.w.s a0, fa7
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fa7:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f17, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f17
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fa7:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f17, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f17
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa7}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fa7}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f18` (`fs2`) as an input, so it should be saved. ; NOTE: This test uses `f18` (`fs2`) as an input, so it should be saved.
define i32 @explicit_register_f18(float %a) nounwind { define i32 @explicit_register_f18(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f18: ; RV32IF-LABEL: explicit_register_f18:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs2, 12(sp) ; RV64IF-NEXT: fsw fs2, 12(sp)
; RV64IF-NEXT: fmv.s fs2, fa0 ; RV64IF-NEXT: fmv.s fs2, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs2 ; RV64IF-NEXT: fcvt.w.s a0, fs2
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs2, 12(sp) ; RV64IF-NEXT: flw fs2, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f18:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f18, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f18, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f18
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f18, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f18:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f18, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f18, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f18
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f18, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f18}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f18}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs2` (`f18`) as an input, so it should be saved. ; NOTE: This test uses `fs2` (`f18`) as an input, so it should be saved.
define i32 @explicit_register_fs2(float %a) nounwind { define i32 @explicit_register_fs2(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs2: ; RV32IF-LABEL: explicit_register_fs2:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs2, 12(sp) ; RV64IF-NEXT: fsw fs2, 12(sp)
; RV64IF-NEXT: fmv.s fs2, fa0 ; RV64IF-NEXT: fmv.s fs2, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs2 ; RV64IF-NEXT: fcvt.w.s a0, fs2
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs2, 12(sp) ; RV64IF-NEXT: flw fs2, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fs2:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f18, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f18, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f18
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f18, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fs2:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f18, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f18, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f18
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f18, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs2}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs2}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f19` (`fs3`) as an input, so it should be saved. ; NOTE: This test uses `f19` (`fs3`) as an input, so it should be saved.
define i32 @explicit_register_f19(float %a) nounwind { define i32 @explicit_register_f19(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f19: ; RV32IF-LABEL: explicit_register_f19:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs3, 12(sp) ; RV64IF-NEXT: fsw fs3, 12(sp)
; RV64IF-NEXT: fmv.s fs3, fa0 ; RV64IF-NEXT: fmv.s fs3, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs3 ; RV64IF-NEXT: fcvt.w.s a0, fs3
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs3, 12(sp) ; RV64IF-NEXT: flw fs3, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f19:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f19, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f19, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f19
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f19, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f19:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f19, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f19, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f19
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f19, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f19}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f19}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs3` (`f19`) as an input, so it should be saved. ; NOTE: This test uses `fs3` (`f19`) as an input, so it should be saved.
define i32 @explicit_register_fs3(float %a) nounwind { define i32 @explicit_register_fs3(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs3: ; RV32IF-LABEL: explicit_register_fs3:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs3, 12(sp) ; RV64IF-NEXT: fsw fs3, 12(sp)
; RV64IF-NEXT: fmv.s fs3, fa0 ; RV64IF-NEXT: fmv.s fs3, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs3 ; RV64IF-NEXT: fcvt.w.s a0, fs3
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs3, 12(sp) ; RV64IF-NEXT: flw fs3, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fs3:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f19, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f19, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f19
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f19, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fs3:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f19, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f19, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f19
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f19, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs3}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs3}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f20` (`fs4`) as an input, so it should be saved. ; NOTE: This test uses `f20` (`fs4`) as an input, so it should be saved.
define i32 @explicit_register_f20(float %a) nounwind { define i32 @explicit_register_f20(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f20: ; RV32IF-LABEL: explicit_register_f20:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs4, 12(sp) ; RV64IF-NEXT: fsw fs4, 12(sp)
; RV64IF-NEXT: fmv.s fs4, fa0 ; RV64IF-NEXT: fmv.s fs4, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs4 ; RV64IF-NEXT: fcvt.w.s a0, fs4
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs4, 12(sp) ; RV64IF-NEXT: flw fs4, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f20:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f20, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f20, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f20
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f20, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f20:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f20, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f20, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f20
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f20, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f20}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f20}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs4` (`f20`) as an input, so it should be saved. ; NOTE: This test uses `fs4` (`f20`) as an input, so it should be saved.
define i32 @explicit_register_fs4(float %a) nounwind { define i32 @explicit_register_fs4(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs4: ; RV32IF-LABEL: explicit_register_fs4:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs4, 12(sp) ; RV64IF-NEXT: fsw fs4, 12(sp)
; RV64IF-NEXT: fmv.s fs4, fa0 ; RV64IF-NEXT: fmv.s fs4, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs4 ; RV64IF-NEXT: fcvt.w.s a0, fs4
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs4, 12(sp) ; RV64IF-NEXT: flw fs4, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fs4:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f20, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f20, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f20
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f20, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fs4:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f20, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f20, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f20
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f20, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs4}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs4}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f21` (`fs5`) as an input, so it should be saved. ; NOTE: This test uses `f21` (`fs5`) as an input, so it should be saved.
define i32 @explicit_register_f21(float %a) nounwind { define i32 @explicit_register_f21(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f21: ; RV32IF-LABEL: explicit_register_f21:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs5, 12(sp) ; RV64IF-NEXT: fsw fs5, 12(sp)
; RV64IF-NEXT: fmv.s fs5, fa0 ; RV64IF-NEXT: fmv.s fs5, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs5 ; RV64IF-NEXT: fcvt.w.s a0, fs5
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs5, 12(sp) ; RV64IF-NEXT: flw fs5, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f21:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f21, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f21, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f21
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f21, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f21:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f21, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f21, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f21
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f21, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f21}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f21}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs5` (`f21`) as an input, so it should be saved. ; NOTE: This test uses `fs5` (`f21`) as an input, so it should be saved.
define i32 @explicit_register_fs5(float %a) nounwind { define i32 @explicit_register_fs5(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs5: ; RV32IF-LABEL: explicit_register_fs5:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs5, 12(sp) ; RV64IF-NEXT: fsw fs5, 12(sp)
; RV64IF-NEXT: fmv.s fs5, fa0 ; RV64IF-NEXT: fmv.s fs5, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs5 ; RV64IF-NEXT: fcvt.w.s a0, fs5
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs5, 12(sp) ; RV64IF-NEXT: flw fs5, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fs5:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f21, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f21, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f21
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f21, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fs5:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f21, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f21, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f21
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f21, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs5}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs5}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f22` (`fs6`) as an input, so it should be saved. ; NOTE: This test uses `f22` (`fs6`) as an input, so it should be saved.
define i32 @explicit_register_f22(float %a) nounwind { define i32 @explicit_register_f22(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f22: ; RV32IF-LABEL: explicit_register_f22:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs6, 12(sp) ; RV64IF-NEXT: fsw fs6, 12(sp)
; RV64IF-NEXT: fmv.s fs6, fa0 ; RV64IF-NEXT: fmv.s fs6, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs6 ; RV64IF-NEXT: fcvt.w.s a0, fs6
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs6, 12(sp) ; RV64IF-NEXT: flw fs6, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f22:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f22, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f22, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f22
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f22, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f22:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f22, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f22, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f22
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f22, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f22}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f22}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs6` (`f22`) as an input, so it should be saved. ; NOTE: This test uses `fs6` (`f22`) as an input, so it should be saved.
define i32 @explicit_register_fs6(float %a) nounwind { define i32 @explicit_register_fs6(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs6: ; RV32IF-LABEL: explicit_register_fs6:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs6, 12(sp) ; RV64IF-NEXT: fsw fs6, 12(sp)
; RV64IF-NEXT: fmv.s fs6, fa0 ; RV64IF-NEXT: fmv.s fs6, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs6 ; RV64IF-NEXT: fcvt.w.s a0, fs6
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs6, 12(sp) ; RV64IF-NEXT: flw fs6, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fs6:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f22, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f22, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f22
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f22, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fs6:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f22, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f22, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f22
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f22, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs6}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs6}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f23` (`fs7`) as an input, so it should be saved. ; NOTE: This test uses `f23` (`fs7`) as an input, so it should be saved.
define i32 @explicit_register_f23(float %a) nounwind { define i32 @explicit_register_f23(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f23: ; RV32IF-LABEL: explicit_register_f23:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs7, 12(sp) ; RV64IF-NEXT: fsw fs7, 12(sp)
; RV64IF-NEXT: fmv.s fs7, fa0 ; RV64IF-NEXT: fmv.s fs7, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs7 ; RV64IF-NEXT: fcvt.w.s a0, fs7
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs7, 12(sp) ; RV64IF-NEXT: flw fs7, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f23:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f23, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f23, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f23
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f23, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f23:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f23, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f23, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f23
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f23, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f23}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f23}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs7` (`f23`) as an input, so it should be saved. ; NOTE: This test uses `fs7` (`f23`) as an input, so it should be saved.
define i32 @explicit_register_fs7(float %a) nounwind { define i32 @explicit_register_fs7(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs7: ; RV32IF-LABEL: explicit_register_fs7:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs7, 12(sp) ; RV64IF-NEXT: fsw fs7, 12(sp)
; RV64IF-NEXT: fmv.s fs7, fa0 ; RV64IF-NEXT: fmv.s fs7, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs7 ; RV64IF-NEXT: fcvt.w.s a0, fs7
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs7, 12(sp) ; RV64IF-NEXT: flw fs7, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fs7:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f23, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f23, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f23
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f23, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fs7:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f23, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f23, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f23
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f23, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs7}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs7}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f24` (`fs8`) as an input, so it should be saved. ; NOTE: This test uses `f24` (`fs8`) as an input, so it should be saved.
define i32 @explicit_register_f24(float %a) nounwind { define i32 @explicit_register_f24(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f24: ; RV32IF-LABEL: explicit_register_f24:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs8, 12(sp) ; RV64IF-NEXT: fsw fs8, 12(sp)
; RV64IF-NEXT: fmv.s fs8, fa0 ; RV64IF-NEXT: fmv.s fs8, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs8 ; RV64IF-NEXT: fcvt.w.s a0, fs8
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs8, 12(sp) ; RV64IF-NEXT: flw fs8, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f24:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f24, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f24, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f24
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f24, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f24:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f24, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f24, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f24
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f24, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f24}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f24}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs8` (`f24`) as an input, so it should be saved. ; NOTE: This test uses `fs8` (`f24`) as an input, so it should be saved.
define i32 @explicit_register_fs8(float %a) nounwind { define i32 @explicit_register_fs8(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs8: ; RV32IF-LABEL: explicit_register_fs8:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs8, 12(sp) ; RV64IF-NEXT: fsw fs8, 12(sp)
; RV64IF-NEXT: fmv.s fs8, fa0 ; RV64IF-NEXT: fmv.s fs8, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs8 ; RV64IF-NEXT: fcvt.w.s a0, fs8
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs8, 12(sp) ; RV64IF-NEXT: flw fs8, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fs8:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f24, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f24, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f24
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f24, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fs8:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f24, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f24, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f24
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f24, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs8}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs8}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f25` (`fs9`) as an input, so it should be saved. ; NOTE: This test uses `f25` (`fs9`) as an input, so it should be saved.
define i32 @explicit_register_f25(float %a) nounwind { define i32 @explicit_register_f25(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f25: ; RV32IF-LABEL: explicit_register_f25:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs9, 12(sp) ; RV64IF-NEXT: fsw fs9, 12(sp)
; RV64IF-NEXT: fmv.s fs9, fa0 ; RV64IF-NEXT: fmv.s fs9, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs9 ; RV64IF-NEXT: fcvt.w.s a0, fs9
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs9, 12(sp) ; RV64IF-NEXT: flw fs9, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f25:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f25, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f25, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f25
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f25, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f25:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f25, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f25, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f25
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f25, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f25}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f25}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs9` (`f25`) as an input, so it should be saved. ; NOTE: This test uses `fs9` (`f25`) as an input, so it should be saved.
define i32 @explicit_register_fs9(float %a) nounwind { define i32 @explicit_register_fs9(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs9: ; RV32IF-LABEL: explicit_register_fs9:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs9, 12(sp) ; RV64IF-NEXT: fsw fs9, 12(sp)
; RV64IF-NEXT: fmv.s fs9, fa0 ; RV64IF-NEXT: fmv.s fs9, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs9 ; RV64IF-NEXT: fcvt.w.s a0, fs9
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs9, 12(sp) ; RV64IF-NEXT: flw fs9, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fs9:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f25, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f25, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f25
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f25, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fs9:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f25, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f25, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f25
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f25, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs9}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs9}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f26` (`fs10`) as an input, so it should be saved. ; NOTE: This test uses `f26` (`fs10`) as an input, so it should be saved.
define i32 @explicit_register_f26(float %a) nounwind { define i32 @explicit_register_f26(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f26: ; RV32IF-LABEL: explicit_register_f26:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs10, 12(sp) ; RV64IF-NEXT: fsw fs10, 12(sp)
; RV64IF-NEXT: fmv.s fs10, fa0 ; RV64IF-NEXT: fmv.s fs10, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs10 ; RV64IF-NEXT: fcvt.w.s a0, fs10
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs10, 12(sp) ; RV64IF-NEXT: flw fs10, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f26:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f26, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f26, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f26
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f26, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f26:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f26, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f26, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f26
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f26, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f26}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f26}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs10` (`f26`) as an input, so it should be saved. ; NOTE: This test uses `fs10` (`f26`) as an input, so it should be saved.
define i32 @explicit_register_fs10(float %a) nounwind { define i32 @explicit_register_fs10(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs10: ; RV32IF-LABEL: explicit_register_fs10:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs10, 12(sp) ; RV64IF-NEXT: fsw fs10, 12(sp)
; RV64IF-NEXT: fmv.s fs10, fa0 ; RV64IF-NEXT: fmv.s fs10, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs10 ; RV64IF-NEXT: fcvt.w.s a0, fs10
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs10, 12(sp) ; RV64IF-NEXT: flw fs10, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fs10:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f26, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f26, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f26
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f26, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fs10:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f26, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f26, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f26
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f26, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs10}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs10}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `f27` (`fs11`) as an input, so it should be saved. ; NOTE: This test uses `f27` (`fs11`) as an input, so it should be saved.
define i32 @explicit_register_f27(float %a) nounwind { define i32 @explicit_register_f27(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f27: ; RV32IF-LABEL: explicit_register_f27:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs11, 12(sp) ; RV64IF-NEXT: fsw fs11, 12(sp)
; RV64IF-NEXT: fmv.s fs11, fa0 ; RV64IF-NEXT: fmv.s fs11, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs11 ; RV64IF-NEXT: fcvt.w.s a0, fs11
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs11, 12(sp) ; RV64IF-NEXT: flw fs11, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f27:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f27, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f27, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f27
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f27, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f27:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f27, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f27, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f27
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f27, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f27}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f27}"(float %a)
ret i32 %1 ret i32 %1
} }
; NOTE: This test uses `fs11` (`f27`) as an input, so it should be saved. ; NOTE: This test uses `fs11` (`f27`) as an input, so it should be saved.
define i32 @explicit_register_fs11(float %a) nounwind { define i32 @explicit_register_fs11(float %a) nounwind {
; RV32IF-LABEL: explicit_register_fs11: ; RV32IF-LABEL: explicit_register_fs11:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
Show All 13 Lines
; RV64IF-NEXT: fsw fs11, 12(sp) ; RV64IF-NEXT: fsw fs11, 12(sp)
; RV64IF-NEXT: fmv.s fs11, fa0 ; RV64IF-NEXT: fmv.s fs11, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, fs11 ; RV64IF-NEXT: fcvt.w.s a0, fs11
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: flw fs11, 12(sp) ; RV64IF-NEXT: flw fs11, 12(sp)
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_fs11:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: addi x2, x2, -16
; RV32IF-NO-ABI-NEXT: fsw f27, 12(x2)
; RV32IF-NO-ABI-NEXT: fmv.s f27, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f27
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: flw f27, 12(x2)
; RV32IF-NO-ABI-NEXT: addi x2, x2, 16
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_fs11:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: addi x2, x2, -16
; RV64IF-NO-ABI-NEXT: fsw f27, 12(x2)
; RV64IF-NO-ABI-NEXT: fmv.s f27, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f27
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: flw f27, 12(x2)
; RV64IF-NO-ABI-NEXT: addi x2, x2, 16
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs11}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{fs11}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f28(float %a) nounwind { define i32 @explicit_register_f28(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f28: ; RV32IF-LABEL: explicit_register_f28:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft8, fa0 ; RV32IF-NEXT: fmv.s ft8, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft8 ; RV32IF-NEXT: fcvt.w.s a0, ft8
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f28: ; RV64IF-LABEL: explicit_register_f28:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft8, fa0 ; RV64IF-NEXT: fmv.s ft8, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft8 ; RV64IF-NEXT: fcvt.w.s a0, ft8
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f28:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f28, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f28
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f28:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f28, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f28
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f28}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f28}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft8(float %a) nounwind { define i32 @explicit_register_ft8(float %a) nounwind {
; RV32IF-LABEL: explicit_register_ft8: ; RV32IF-LABEL: explicit_register_ft8:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft8, fa0 ; RV32IF-NEXT: fmv.s ft8, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft8 ; RV32IF-NEXT: fcvt.w.s a0, ft8
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_ft8: ; RV64IF-LABEL: explicit_register_ft8:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft8, fa0 ; RV64IF-NEXT: fmv.s ft8, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft8 ; RV64IF-NEXT: fcvt.w.s a0, ft8
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_ft8:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f28, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f28
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_ft8:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f28, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f28
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft8}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft8}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f29(float %a) nounwind { define i32 @explicit_register_f29(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f29: ; RV32IF-LABEL: explicit_register_f29:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft9, fa0 ; RV32IF-NEXT: fmv.s ft9, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft9 ; RV32IF-NEXT: fcvt.w.s a0, ft9
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f29: ; RV64IF-LABEL: explicit_register_f29:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft9, fa0 ; RV64IF-NEXT: fmv.s ft9, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft9 ; RV64IF-NEXT: fcvt.w.s a0, ft9
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f29:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f29, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f29
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f29:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f29, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f29
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f29}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f29}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft9(float %a) nounwind { define i32 @explicit_register_ft9(float %a) nounwind {
; RV32IF-LABEL: explicit_register_ft9: ; RV32IF-LABEL: explicit_register_ft9:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft9, fa0 ; RV32IF-NEXT: fmv.s ft9, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft9 ; RV32IF-NEXT: fcvt.w.s a0, ft9
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_ft9: ; RV64IF-LABEL: explicit_register_ft9:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft9, fa0 ; RV64IF-NEXT: fmv.s ft9, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft9 ; RV64IF-NEXT: fcvt.w.s a0, ft9
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_ft9:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f29, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f29
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_ft9:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f29, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f29
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft9}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft9}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f30(float %a) nounwind { define i32 @explicit_register_f30(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f30: ; RV32IF-LABEL: explicit_register_f30:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft10, fa0 ; RV32IF-NEXT: fmv.s ft10, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft10 ; RV32IF-NEXT: fcvt.w.s a0, ft10
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f30: ; RV64IF-LABEL: explicit_register_f30:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft10, fa0 ; RV64IF-NEXT: fmv.s ft10, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft10 ; RV64IF-NEXT: fcvt.w.s a0, ft10
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f30:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f30, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f30
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f30:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f30, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f30
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f30}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f30}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft10(float %a) nounwind { define i32 @explicit_register_ft10(float %a) nounwind {
; RV32IF-LABEL: explicit_register_ft10: ; RV32IF-LABEL: explicit_register_ft10:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft10, fa0 ; RV32IF-NEXT: fmv.s ft10, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft10 ; RV32IF-NEXT: fcvt.w.s a0, ft10
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_ft10: ; RV64IF-LABEL: explicit_register_ft10:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft10, fa0 ; RV64IF-NEXT: fmv.s ft10, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft10 ; RV64IF-NEXT: fcvt.w.s a0, ft10
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_ft10:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f30, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f30
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_ft10:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f30, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f30
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft10}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft10}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_f31(float %a) nounwind { define i32 @explicit_register_f31(float %a) nounwind {
; RV32IF-LABEL: explicit_register_f31: ; RV32IF-LABEL: explicit_register_f31:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft11, fa0 ; RV32IF-NEXT: fmv.s ft11, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft11 ; RV32IF-NEXT: fcvt.w.s a0, ft11
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_f31: ; RV64IF-LABEL: explicit_register_f31:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft11, fa0 ; RV64IF-NEXT: fmv.s ft11, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft11 ; RV64IF-NEXT: fcvt.w.s a0, ft11
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_f31:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f31, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f31
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_f31:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f31, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f31
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f31}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{f31}"(float %a)
ret i32 %1 ret i32 %1
} }
define i32 @explicit_register_ft11(float %a) nounwind { define i32 @explicit_register_ft11(float %a) nounwind {
; RV32IF-LABEL: explicit_register_ft11: ; RV32IF-LABEL: explicit_register_ft11:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.s ft11, fa0 ; RV32IF-NEXT: fmv.s ft11, fa0
; RV32IF-NEXT: #APP ; RV32IF-NEXT: #APP
; RV32IF-NEXT: fcvt.w.s a0, ft11 ; RV32IF-NEXT: fcvt.w.s a0, ft11
; RV32IF-NEXT: #NO_APP ; RV32IF-NEXT: #NO_APP
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
; RV64IF-LABEL: explicit_register_ft11: ; RV64IF-LABEL: explicit_register_ft11:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.s ft11, fa0 ; RV64IF-NEXT: fmv.s ft11, fa0
; RV64IF-NEXT: #APP ; RV64IF-NEXT: #APP
; RV64IF-NEXT: fcvt.w.s a0, ft11 ; RV64IF-NEXT: fcvt.w.s a0, ft11
; RV64IF-NEXT: #NO_APP ; RV64IF-NEXT: #NO_APP
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
;
; RV32IF-NO-ABI-LABEL: explicit_register_ft11:
; RV32IF-NO-ABI: # %bb.0:
; RV32IF-NO-ABI-NEXT: fmv.s f31, f10
; RV32IF-NO-ABI-NEXT: #APP
; RV32IF-NO-ABI-NEXT: fcvt.w.s x10, f31
; RV32IF-NO-ABI-NEXT: #NO_APP
; RV32IF-NO-ABI-NEXT: ret
;
; RV64IF-NO-ABI-LABEL: explicit_register_ft11:
; RV64IF-NO-ABI: # %bb.0:
; RV64IF-NO-ABI-NEXT: fmv.s f31, f10
; RV64IF-NO-ABI-NEXT: #APP
; RV64IF-NO-ABI-NEXT: fcvt.w.s x10, f31
; RV64IF-NO-ABI-NEXT: #NO_APP
; RV64IF-NO-ABI-NEXT: ret
%1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft11}"(float %a) %1 = tail call i32 asm "fcvt.w.s $0, $1", "=r,{ft11}"(float %a)
ret i32 %1 ret i32 %1
} }