[X86] Making X86OptimizeLEAs pass public. NFC

[RKSimon]

I'm happy with making this pass properly public, but I'm not sure what you're gaining from splitting off X86MemOpKey.h - are you intending to reuse that code someplace else?

[gpei]

In D65933#1620742, @RKSimon wrote:

I'm happy with making this pass properly public, but I'm not sure what you're gaining from splitting off X86MemOpKey.h - are you intending to reuse that code someplace else?

It’s useful to us and it seemed like a generally good code reorganization.

[RKSimon]

In D65933#1622789, @gpei wrote:

In D65933#1620742, @RKSimon wrote:

I'm happy with making this pass properly public, but I'm not sure what you're gaining from splitting off X86MemOpKey.h - are you intending to reuse that code someplace else?

It’s useful to us and it seemed like a generally good code reorganization.

In which case I'd recommend splitting the X86MemOpKey.h change into a separate followup patch and making this patch just about making the pass public.

[RKSimon]

Not sure we should consider this NFC any more

@craig.topper Any comments?

llvm/lib/Target/X86/X86.h

146

Naming convention: initializeX86OptimizeLEAPassPass

[craig.topper]

Address those two comments and I'm happy.

llvm/lib/Target/X86/X86.h

146

Alphabetize also.

[RKSimon]

llvm/lib/Target/X86/X86TargetMachine.cpp

84

There's no need to reorder this - @craig.topper 's comment was about sorting the definitions in X86.h

[RKSimon]

please rebase on rL369126

llvm/lib/Target/X86/X86.h

146

void initializeX86FlagsCopyLoweringPassPass(PassRegistry &);
void initializeX86OptimizeLEAPassPass(PassRegistry &);
void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &);

[RKSimon]

llvm/lib/Target/X86/X86.h

146

Still not alphabetized

[RKSimon]

LGTM - you just need to clang-format X86OptimizeLEAs.cpp as the addition of "X86" has screwed up indentations.

llvm/lib/Target/X86/X86OptimizeLEAs.cpp

160

clang-format

242

clang-format

266

clang-format

419

clang-format

[RKSimon]

LGTM

llvm/lib/Target/X86/X86.h

 void initializeX86CallFrameOptimizationPass(PassRegistry &);
 void initializeX86CmovConverterPassPass(PassRegistry &);
 void initializeX86ExpandPseudoPass(PassRegistry&);
 void initializeX86CondBrFoldingPassPass(PassRegistry &);
 void initializeX86DomainReassignmentPass(PassRegistry &);
 void initializeX86ExecutionDomainFixPass(PassRegistry &);
 void initializeX86FlagsCopyLoweringPassPass(PassRegistry &);
 void initializeX86SpeculativeLoadHardeningPassPass(PassRegistry &);
-
+void initializeOptimizeLEAPassPass(PassRegistry &);
 } // End llvm namespace
 
 #endif

llvm/lib/Target/X86/X86MemOpKey.h

+//=- X86MemOpKey.h - A key based on instruction's memory operands. --*- C++ -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// A key based on instruction's memory operands.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_X86_X86MEMOPKEY_H
+#define LLVM_LIB_TARGET_X86_X86MEMOPKEY_H
+
+#include "llvm/ADT/DenseMapInfo.h"
+#include "llvm/ADT/Hashing.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+
+/// Returns true if two machine operands are identical and they are not
+/// physical registers.
+static inline bool isIdenticalOp(const llvm::MachineOperand &MO1,
+                                 const llvm::MachineOperand &MO2);
+
+/// Returns true if two address displacement operands are of the same
+/// type and use the same symbol/index/address regardless of the offset.
+static bool isSimilarDispOp(const llvm::MachineOperand &MO1,
+                            const llvm::MachineOperand &MO2);
+
+namespace {
+
+/// A key based on instruction's memory operands.
+class MemOpKey {
+public:
+  MemOpKey(const llvm::MachineOperand *Base, const llvm::MachineOperand *Scale,
+           const llvm::MachineOperand *Index, const llvm::MachineOperand *Segment,
+           const llvm::MachineOperand *Disp)
+      : Disp(Disp) {
+    Operands[0] = Base;
+    Operands[1] = Scale;
+    Operands[2] = Index;
+    Operands[3] = Segment;
+  }
+
+  bool operator==(const MemOpKey &Other) const {
+    // Addresses' bases, scales, indices and segments must be identical.
+    for (int i = 0; i < 4; ++i)
+      if (!isIdenticalOp(*Operands[i], *Other.Operands[i]))
+        return false;
+
+    // Addresses' displacements don't have to be exactly the same. It only
+    // matters that they use the same symbol/index/address. Immediates' or
+    // offsets' differences will be taken care of during instruction
+    // substitution.
+    return isSimilarDispOp(*Disp, *Other.Disp);
+  }
+
+  // Address' base, scale, index and segment operands.
+  const llvm::MachineOperand *Operands[4];
+
+  // Address' displacement operand.
+  const llvm::MachineOperand *Disp;
+};
+
+} // end anonymous namespace
+
+/// Provide DenseMapInfo for MemOpKey.
+namespace llvm {
+
+template <> struct DenseMapInfo<MemOpKey> {
+  using PtrInfo = DenseMapInfo<const MachineOperand *>;
+
+  static inline MemOpKey getEmptyKey() {
+    return MemOpKey(PtrInfo::getEmptyKey(), PtrInfo::getEmptyKey(),
+                    PtrInfo::getEmptyKey(), PtrInfo::getEmptyKey(),
+                    PtrInfo::getEmptyKey());
+  }
+
+  static inline MemOpKey getTombstoneKey() {
+    return MemOpKey(PtrInfo::getTombstoneKey(), PtrInfo::getTombstoneKey(),
+                    PtrInfo::getTombstoneKey(), PtrInfo::getTombstoneKey(),
+                    PtrInfo::getTombstoneKey());
+  }
+
+  static unsigned getHashValue(const MemOpKey &Val) {
+    // Checking any field of MemOpKey is enough to determine if the key is
+    // empty or tombstone.
+    assert(Val.Disp != PtrInfo::getEmptyKey() && "Cannot hash the empty key");
+    assert(Val.Disp != PtrInfo::getTombstoneKey() &&
+           "Cannot hash the tombstone key");
+
+    hash_code Hash = hash_combine(*Val.Operands[0], *Val.Operands[1],
+                                  *Val.Operands[2], *Val.Operands[3]);
+
+    // If the address displacement is an immediate, it should not affect the
+    // hash so that memory operands which differ only be immediate displacement
+    // would have the same hash. If the address displacement is something else,
+    // we should reflect symbol/index/address in the hash.
+    switch (Val.Disp->getType()) {
+    case MachineOperand::MO_Immediate:
+      break;
+    case MachineOperand::MO_ConstantPoolIndex:
+    case MachineOperand::MO_JumpTableIndex:
+      Hash = hash_combine(Hash, Val.Disp->getIndex());
+      break;
+    case MachineOperand::MO_ExternalSymbol:
+      Hash = hash_combine(Hash, Val.Disp->getSymbolName());
+      break;
+    case MachineOperand::MO_GlobalAddress:
+      Hash = hash_combine(Hash, Val.Disp->getGlobal());
+      break;
+    case MachineOperand::MO_BlockAddress:
+      Hash = hash_combine(Hash, Val.Disp->getBlockAddress());
+      break;
+    case MachineOperand::MO_MCSymbol:
+      Hash = hash_combine(Hash, Val.Disp->getMCSymbol());
+      break;
+    case MachineOperand::MO_MachineBasicBlock:
+      Hash = hash_combine(Hash, Val.Disp->getMBB());
+      break;
+    default:
+      llvm_unreachable("Invalid address displacement operand");
+    }
+
+    return (unsigned)Hash;
+  }
+
+  static bool isEqual(const MemOpKey &LHS, const MemOpKey &RHS) {
+    // Checking any field of MemOpKey is enough to determine if the key is
+    // empty or tombstone.
+    if (RHS.Disp == PtrInfo::getEmptyKey())
+      return LHS.Disp == PtrInfo::getEmptyKey();
+    if (RHS.Disp == PtrInfo::getTombstoneKey())
+      return LHS.Disp == PtrInfo::getTombstoneKey();
+    return LHS == RHS;
+  }
+};
+
+} // end namespace llvm
+
+static inline bool isIdenticalOp(const llvm::MachineOperand &MO1,
+                                 const llvm::MachineOperand &MO2) {
+  return MO1.isIdenticalTo(MO2) &&
+         (!MO1.isReg() || !llvm::Register::isPhysicalRegister(MO1.getReg()));
+}
+
+#ifndef NDEBUG
+static bool isValidDispOp(const llvm::MachineOperand &MO) {
+  return MO.isImm() || MO.isCPI() || MO.isJTI() || MO.isSymbol() ||
+         MO.isGlobal() || MO.isBlockAddress() || MO.isMCSymbol() || MO.isMBB();
+}
+#endif
+
+static bool isSimilarDispOp(const llvm::MachineOperand &MO1,
+                            const llvm::MachineOperand &MO2) {
+  assert(isValidDispOp(MO1) && isValidDispOp(MO2) &&
+         "Address displacement operand is not valid");
+  return (MO1.isImm() && MO2.isImm()) ||
+         (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) ||
+         (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) ||
+         (MO1.isSymbol() && MO2.isSymbol() &&
+          MO1.getSymbolName() == MO2.getSymbolName()) ||
+         (MO1.isGlobal() && MO2.isGlobal() &&
+          MO1.getGlobal() == MO2.getGlobal()) ||
+         (MO1.isBlockAddress() && MO2.isBlockAddress() &&
+          MO1.getBlockAddress() == MO2.getBlockAddress()) ||
+         (MO1.isMCSymbol() && MO2.isMCSymbol() &&
+          MO1.getMCSymbol() == MO2.getMCSymbol()) ||
+         (MO1.isMBB() && MO2.isMBB() && MO1.getMBB() == MO2.getMBB());
+}
+#endif // LLVM_LIB_TARGET_X86_X86MEMOPKEY_H

llvm/lib/Target/X86/X86OptimizeLEAs.cpp

 #include "llvm/IR/DebugLoc.h"
 #include "llvm/IR/Function.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
+#include "X86MemOpKey.h"
 #include <cassert>
 #include <cstdint>
 #include <iterator>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "x86-optimize-LEAs"
 
 static cl::opt<bool>
     DisableX86LEAOpt("disable-x86-lea-opt", cl::Hidden,
                      cl::desc("X86: Disable LEA optimizations."),
                      cl::init(false));
 
 STATISTIC(NumSubstLEAs, "Number of LEA instruction substitutions");
 STATISTIC(NumRedundantLEAs, "Number of redundant LEA instructions removed");
 
-/// Returns true if two machine operands are identical and they are not
-/// physical registers.
-static inline bool isIdenticalOp(const MachineOperand &MO1,
-                                 const MachineOperand &MO2);
-
-/// Returns true if two address displacement operands are of the same
-/// type and use the same symbol/index/address regardless of the offset.
-static bool isSimilarDispOp(const MachineOperand &MO1,
-                            const MachineOperand &MO2);
-
 /// Returns true if the instruction is LEA.
 static inline bool isLEA(const MachineInstr &MI);
 
-namespace {
-
-/// A key based on instruction's memory operands.
-class MemOpKey {
-public:
-  MemOpKey(const MachineOperand *Base, const MachineOperand *Scale,
-           const MachineOperand *Index, const MachineOperand *Segment,
-           const MachineOperand *Disp)
-      : Disp(Disp) {
-    Operands[0] = Base;
-    Operands[1] = Scale;
-    Operands[2] = Index;
-    Operands[3] = Segment;
-  }
-
-  bool operator==(const MemOpKey &Other) const {
-    // Addresses' bases, scales, indices and segments must be identical.
-    for (int i = 0; i < 4; ++i)
-      if (!isIdenticalOp(*Operands[i], *Other.Operands[i]))
-        return false;
-
-    // Addresses' displacements don't have to be exactly the same. It only
-    // matters that they use the same symbol/index/address. Immediates' or
-    // offsets' differences will be taken care of during instruction
-    // substitution.
-    return isSimilarDispOp(*Disp, *Other.Disp);
-  }
-
-  // Address' base, scale, index and segment operands.
-  const MachineOperand *Operands[4];
-
-  // Address' displacement operand.
-  const MachineOperand *Disp;
-};
-
-} // end anonymous namespace
-
-/// Provide DenseMapInfo for MemOpKey.
-namespace llvm {
-
-template <> struct DenseMapInfo<MemOpKey> {
-  using PtrInfo = DenseMapInfo<const MachineOperand *>;
-
-  static inline MemOpKey getEmptyKey() {
-    return MemOpKey(PtrInfo::getEmptyKey(), PtrInfo::getEmptyKey(),
-                    PtrInfo::getEmptyKey(), PtrInfo::getEmptyKey(),
-                    PtrInfo::getEmptyKey());
-  }
-
-  static inline MemOpKey getTombstoneKey() {
-    return MemOpKey(PtrInfo::getTombstoneKey(), PtrInfo::getTombstoneKey(),
-                    PtrInfo::getTombstoneKey(), PtrInfo::getTombstoneKey(),
-                    PtrInfo::getTombstoneKey());
-  }
-
-  static unsigned getHashValue(const MemOpKey &Val) {
-    // Checking any field of MemOpKey is enough to determine if the key is
-    // empty or tombstone.
-    assert(Val.Disp != PtrInfo::getEmptyKey() && "Cannot hash the empty key");
-    assert(Val.Disp != PtrInfo::getTombstoneKey() &&
-           "Cannot hash the tombstone key");
-
-    hash_code Hash = hash_combine(*Val.Operands[0], *Val.Operands[1],
-                                  *Val.Operands[2], *Val.Operands[3]);
-
-    // If the address displacement is an immediate, it should not affect the
-    // hash so that memory operands which differ only be immediate displacement
-    // would have the same hash. If the address displacement is something else,
-    // we should reflect symbol/index/address in the hash.
-    switch (Val.Disp->getType()) {
-    case MachineOperand::MO_Immediate:
-      break;
-    case MachineOperand::MO_ConstantPoolIndex:
-    case MachineOperand::MO_JumpTableIndex:
-      Hash = hash_combine(Hash, Val.Disp->getIndex());
-      break;
-    case MachineOperand::MO_ExternalSymbol:
-      Hash = hash_combine(Hash, Val.Disp->getSymbolName());
-      break;
-    case MachineOperand::MO_GlobalAddress:
-      Hash = hash_combine(Hash, Val.Disp->getGlobal());
-      break;
-    case MachineOperand::MO_BlockAddress:
-      Hash = hash_combine(Hash, Val.Disp->getBlockAddress());
-      break;
-    case MachineOperand::MO_MCSymbol:
-      Hash = hash_combine(Hash, Val.Disp->getMCSymbol());
-      break;
-    case MachineOperand::MO_MachineBasicBlock:
-      Hash = hash_combine(Hash, Val.Disp->getMBB());
-      break;
-    default:
-      llvm_unreachable("Invalid address displacement operand");
-    }
-
-    return (unsigned)Hash;
-  }
-
-  static bool isEqual(const MemOpKey &LHS, const MemOpKey &RHS) {
-    // Checking any field of MemOpKey is enough to determine if the key is
-    // empty or tombstone.
-    if (RHS.Disp == PtrInfo::getEmptyKey())
-      return LHS.Disp == PtrInfo::getEmptyKey();
-    if (RHS.Disp == PtrInfo::getTombstoneKey())
-      return LHS.Disp == PtrInfo::getTombstoneKey();
-    return LHS == RHS;
-  }
-};
-
-} // end namespace llvm
-
 /// Returns a hash table key based on memory operands of \p MI. The
 /// number of the first memory operand of \p MI is specified through \p N.
 static inline MemOpKey getMemOpKey(const MachineInstr &MI, unsigned N) {
   assert((isLEA(MI) || MI.mayLoadOrStore()) &&
          "The instruction must be a LEA, a load or a store");
   return MemOpKey(&MI.getOperand(N + X86::AddrBaseReg),
                   &MI.getOperand(N + X86::AddrScaleAmt),
                   &MI.getOperand(N + X86::AddrIndexReg),
                   &MI.getOperand(N + X86::AddrSegmentReg),
                   &MI.getOperand(N + X86::AddrDisp));
 }
 
-static inline bool isIdenticalOp(const MachineOperand &MO1,
-                                 const MachineOperand &MO2) {
-  return MO1.isIdenticalTo(MO2) &&
-         (!MO1.isReg() || !Register::isPhysicalRegister(MO1.getReg()));
-}
-
-#ifndef NDEBUG
-static bool isValidDispOp(const MachineOperand &MO) {
-  return MO.isImm() || MO.isCPI() || MO.isJTI() || MO.isSymbol() ||
-         MO.isGlobal() || MO.isBlockAddress() || MO.isMCSymbol() || MO.isMBB();
-}
-#endif
-
-static bool isSimilarDispOp(const MachineOperand &MO1,
-                            const MachineOperand &MO2) {
-  assert(isValidDispOp(MO1) && isValidDispOp(MO2) &&
-         "Address displacement operand is not valid");
-  return (MO1.isImm() && MO2.isImm()) ||
-         (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) ||
-         (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) ||
-         (MO1.isSymbol() && MO2.isSymbol() &&
-          MO1.getSymbolName() == MO2.getSymbolName()) ||
-         (MO1.isGlobal() && MO2.isGlobal() &&
-          MO1.getGlobal() == MO2.getGlobal()) ||
-         (MO1.isBlockAddress() && MO2.isBlockAddress() &&
-          MO1.getBlockAddress() == MO2.getBlockAddress()) ||
-         (MO1.isMCSymbol() && MO2.isMCSymbol() &&
-          MO1.getMCSymbol() == MO2.getMCSymbol()) ||
-         (MO1.isMBB() && MO2.isMBB() && MO1.getMBB() == MO2.getMBB());
-}
-
 static inline bool isLEA(const MachineInstr &MI) {
   unsigned Opcode = MI.getOpcode();
   return Opcode == X86::LEA16r || Opcode == X86::LEA32r ||
          Opcode == X86::LEA64r || Opcode == X86::LEA64_32r;
 }
 
 namespace {
 
 class OptimizeLEAPass : public MachineFunctionPass {
 public:
   OptimizeLEAPass() : MachineFunctionPass(ID) {}
 
   StringRef getPassName() const override { return "X86 LEA Optimize"; }
 
   /// Loop over all of the basic blocks, replacing address
   /// calculations in load and store instructions, if it's already
   /// been calculated by LEA. Also, remove redundant LEAs.
   bool runOnMachineFunction(MachineFunction &MF) override;
 
+  static char ID;
 private:
   using MemOpMap = DenseMap<MemOpKey, SmallVector<MachineInstr *, 16>>;
 
   /// Returns a distance between two instructions inside one basic block.
   /// Negative result means, that instructions occur in reverse order.
   int calcInstrDist(const MachineInstr &First, const MachineInstr &Last);
 
   /// Choose the best \p LEA instruction from the \p List to replace
private:
   bool removeRedundantLEAs(MemOpMap &LEAs);
 
   DenseMap<const MachineInstr *, unsigned> InstrPos;
 
   MachineRegisterInfo *MRI;
   const X86InstrInfo *TII;
   const X86RegisterInfo *TRI;
 
-  static char ID;
 };
 
 } // end anonymous namespace
 
 char OptimizeLEAPass::ID = 0;
 
 FunctionPass *llvm::createX86OptimizeLEAs() { return new OptimizeLEAPass(); }
+INITIALIZE_PASS(OptimizeLEAPass, DEBUG_TYPE,
+                "X86 optimize LEA pass", false, false)
 
 int OptimizeLEAPass::calcInstrDist(const MachineInstr &First,
                                    const MachineInstr &Last) {
   // Both instructions must be in the same basic block and they must be
   // presented in InstrPos.
   assert(Last.getParent() == First.getParent() &&
          "Instructions are in different basic blocks");
   assert(InstrPos.find(&First) != InstrPos.end() &&
          InstrPos.find(&Last) != InstrPos.end() &&
          "Instructions' positions are undefined");
 
bool OptimizeLEAPass::chooseBestLEA(const SmallVectorImpl<MachineInstr *> &List,
   return BestLEA != nullptr;
 }
 
 // Get the difference between the addresses' displacements of the two
 // instructions \p MI1 and \p MI2. The numbers of the first memory operands are
 // passed through \p N1 and \p N2.
 int64_t OptimizeLEAPass::getAddrDispShift(const MachineInstr &MI1, unsigned N1,
                                           const MachineInstr &MI2,
                                           unsigned N2) const {
   const MachineOperand &Op1 = MI1.getOperand(N1 + X86::AddrDisp);
   const MachineOperand &Op2 = MI2.getOperand(N2 + X86::AddrDisp);
 
   assert(isSimilarDispOp(Op1, Op2) &&
          "Address displacement operands are not compatible");
 
   // After the assert above we can be sure that both operands are of the same
   // valid type and use the same symbol/index/address, thus displacement shift
   // calculation is rather simple.
   if (Op1.isJTI())
     return 0;
   return Op1.isImm() ? Op1.getImm() - Op2.getImm()
                      : Op1.getOffset() - Op2.getOffset();
 }
 
 // Check that the Last LEA can be replaced by the First LEA. To be so,
 // these requirements must be met:
 // 1) Addresses calculated by LEAs differ only by displacement.
 // 2) Def registers of LEAs belong to the same class.
 // 3) All uses of the Last LEA def register are replaceable, thus the
 //    register is used only as address base.
 bool OptimizeLEAPass::isReplaceable(const MachineInstr &First,
                                     const MachineInstr &Last,
                                     int64_t &AddrDispShift) const {
   assert(isLEA(First) && isLEA(Last) &&
          "The function works only with LEA instructions");
 
   // Make sure that LEA def registers belong to the same class. There may be
   // instructions (like MOV8mr_NOREX) which allow a limited set of registers to
   // be used as their operands, so we must be sure that replacing one LEA
   // with another won't lead to putting a wrong register in the instruction.
   if (MRI->getRegClass(First.getOperand(0).getReg()) !=
for (auto I = MBB->begin(), E = MBB->end(); I != E;) {
     Changed = true;
   }
 
   return Changed;
 }
 
 MachineInstr *OptimizeLEAPass::replaceDebugValue(MachineInstr &MI,
                                                  unsigned VReg,
                                                  int64_t AddrDispShift) {
   DIExpression *Expr = const_cast<DIExpression *>(MI.getDebugExpression());
   if (AddrDispShift != 0)
     Expr = DIExpression::prepend(Expr, DIExpression::StackValue, AddrDispShift);
 
   // Replace DBG_VALUE instruction with modified version.
   MachineBasicBlock *MBB = MI.getParent();
   DebugLoc DL = MI.getDebugLoc();
   bool IsIndirect = MI.isIndirectDebugValue();

llvm/lib/Target/X86/X86TargetMachine.cpp

extern "C" void LLVMInitializeX86Target() {
   initializeX86CmovConverterPassPass(PR);
   initializeX86ExpandPseudoPass(PR);
   initializeX86ExecutionDomainFixPass(PR);
   initializeX86DomainReassignmentPass(PR);
   initializeX86AvoidSFBPassPass(PR);
   initializeX86SpeculativeLoadHardeningPassPass(PR);
   initializeX86FlagsCopyLoweringPassPass(PR);
   initializeX86CondBrFoldingPassPass(PR);
+  initializeOptimizeLEAPassPass(PR);
 }
 
 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
   if (TT.isOSBinFormatMachO()) {
     if (TT.getArch() == Triple::x86_64)
       return llvm::make_unique<X86_64MachoTargetObjectFile>();
     return llvm::make_unique<TargetLoweringObjectFileMachO>();
   }