[X86] Add DSB subtarget feature. NFC

[gpei]

Summary

Add DSB(Decoded Stream Buffer) subtarget feature.

[lebedev.ri]

DSB part seems really out-of-place - it's not used in this patch.
I think these should be 2 NFC patches.

[RKSimon]

Is there anything we can add as tests here?

[gpei]

In D65921#1620693, @RKSimon wrote:

Is there anything we can add as tests here?

It's hard to add tests for this sub-target feature. Could you please give me an example?

[RKSimon]

In D65921#1625064, @gpei wrote:

In D65921#1620693, @RKSimon wrote:

Is there anything we can add as tests here?

It's hard to add tests for this sub-target feature. Could you please give me an example?

How are you intending to use this feature? DSB is an uop-cache so are you intending to connect this to the instruction schedulers some how? Or is it going to affect instruction selection decisions?

[gpei]

In D65921#1639186, @RKSimon wrote:

In D65921#1625064, @gpei wrote:

In D65921#1620693, @RKSimon wrote:

Is there anything we can add as tests here?

It's hard to add tests for this sub-target feature. Could you please give me an example?

How are you intending to use this feature? DSB is an uop-cache so are you intending to connect this to the instruction schedulers some how? Or is it going to affect instruction selection decisions?

Sorry for replying your message so late. Yes, this feature is for some proprietary passes.

[RKSimon]

In D65921#1648674, @gpei wrote:

In D65921#1639186, @RKSimon wrote:

In D65921#1625064, @gpei wrote:

In D65921#1620693, @RKSimon wrote:

Is there anything we can add as tests here?

It's hard to add tests for this sub-target feature. Could you please give me an example?

How are you intending to use this feature? DSB is an uop-cache so are you intending to connect this to the instruction schedulers some how? Or is it going to affect instruction selection decisions?

Sorry for replying your message so late. Yes, this feature is for some proprietary passes.

Are these passes likely to pushed for review any time soon? I'd really prefer not to have yet more X86 feature flags added to trunk unless we have a clear purpose for them.

[gpei]

In D65921#1648722, @RKSimon wrote:

In D65921#1648674, @gpei wrote:

In D65921#1639186, @RKSimon wrote:

In D65921#1625064, @gpei wrote:

In D65921#1620693, @RKSimon wrote:

Is there anything we can add as tests here?

It's hard to add tests for this sub-target feature. Could you please give me an example?

How are you intending to use this feature? DSB is an uop-cache so are you intending to connect this to the instruction schedulers some how? Or is it going to affect instruction selection decisions?

Sorry for replying your message so late. Yes, this feature is for some proprietary passes.

Are these passes likely to pushed for review any time soon? I'd really prefer not to have yet more X86 feature flags added to trunk unless we have a clear purpose for them.

Not sure how long, it's depending on the policy.

[andrew.w.kaylor]

Can this patch be abandoned?

[gpei]

I will abandon this.

llvm/lib/Target/X86/X86.td

: SubtargetFeature<
         "Prefer a left/right vector logical shift pair over a shift+and pair">;
 
 // Merge branches using three-way conditional code.
 def FeatureMergeToThreeWayBranch : SubtargetFeature<"merge-to-threeway-branch",
                                         "ThreewayBranchProfitable", "true",
                                         "Merge branches to a three-way "
                                         "conditional branch">;
 
+def FeatureHasDSB : SubtargetFeature<"dsb", "HasDSB", "true",
+                                    "Target has decoded stream buffer">;
+
 // Bonnell
 def ProcIntelAtom : SubtargetFeature<"", "X86ProcFamily", "IntelAtom", "">;
 // Silvermont
 def ProcIntelSLM  : SubtargetFeature<"", "X86ProcFamily", "IntelSLM", "">;
 // Goldmont
 def ProcIntelGLM  : SubtargetFeature<"", "X86ProcFamily", "IntelGLM", "">;
 // Goldmont Plus
 def ProcIntelGLP  : SubtargetFeature<"", "X86ProcFamily", "IntelGLP", "">;
list<SubtargetFeature> WSMFeatures =
     !listconcat(WSMInheritableFeatures, WSMSpecificFeatures);
 
   // Sandybridge
   list<SubtargetFeature> SNBAdditionalFeatures = [FeatureAVX,
                                                   FeatureSlowDivide64,
                                                   FeatureXSAVE,
                                                   FeatureXSAVEOPT,
                                                   FeatureSlow3OpsLEA,
+                                                  FeatureHasDSB,
                                                   FeatureFastScalarFSQRT,
                                                   FeatureFastSHLDRotate,
                                                   FeatureMergeToThreeWayBranch];
   list<SubtargetFeature> SNBSpecificFeatures = [FeatureSlowUAMem32,
                                                 FeaturePOPCNTFalseDeps];
   list<SubtargetFeature> SNBInheritableFeatures =
     !listconcat(WSMInheritableFeatures, SNBAdditionalFeatures);
   list<SubtargetFeature> SNBFeatures =

llvm/lib/Target/X86/X86Subtarget.h

protected:
   unsigned MaxInlineSizeThreshold = 128;
 
   /// Indicates target prefers 256 bit instructions.
   bool Prefer256Bit = false;
 
   /// Threeway branch is profitable in this subtarget.
   bool ThreewayBranchProfitable = false;
 
+  /// Processor supports Decoded Stream Buffer.
+  bool HasDSB = false;
+
   /// What processor and OS we're targeting.
   Triple TargetTriple;
 
   /// GlobalISel related APIs.
   std::unique_ptr<CallLowering> CallLoweringInfo;
   std::unique_ptr<LegalizerInfo> Legalizer;
   std::unique_ptr<RegisterBankInfo> RegBankInfo;
   std::unique_ptr<InstructionSelector> InstSelector;
public:
   bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
   bool hasCLWB() const { return HasCLWB; }
   bool hasWBNOINVD() const { return HasWBNOINVD; }
   bool hasRDPID() const { return HasRDPID; }
   bool hasWAITPKG() const { return HasWAITPKG; }
   bool hasPCONFIG() const { return HasPCONFIG; }
   bool hasSGX() const { return HasSGX; }
   bool threewayBranchProfitable() const { return ThreewayBranchProfitable; }
+  bool hasDSB() const { return HasDSB; }
   bool hasINVPCID() const { return HasINVPCID; }
   bool hasENQCMD() const { return HasENQCMD; }
   bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
   bool useRetpolineIndirectBranches() const {
     return UseRetpolineIndirectBranches;
   }
   bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
 

llvm/lib/Target/X86/X86TargetTransformInfo.h

const FeatureBitset InlineFeatureIgnoreList = {
       X86::FeatureFastVariableShuffle,
       X86::FeatureFastVectorFSQRT,
       X86::FeatureLEAForSP,
       X86::FeatureLEAUsesAG,
       X86::FeatureLZCNTFalseDeps,
       X86::FeatureBranchFusion,
       X86::FeatureMacroFusion,
       X86::FeatureMergeToThreeWayBranch,
+      X86::FeatureHasDSB,
       X86::FeaturePadShortFunctions,
       X86::FeaturePOPCNTFalseDeps,
       X86::FeatureSSEUnalignedMem,
       X86::FeatureSlow3OpsLEA,
       X86::FeatureSlowDivide32,
       X86::FeatureSlowDivide64,
       X86::FeatureSlowIncDec,
       X86::FeatureSlowLEA,