[LLD][ELF][AArch64] Support for movz, movk tprel relocations

[peter.smith]

Summary

This patch Implements the R_AARCH64_TLSLE_MOVW_TPREL_G*[_NC]. These are logically the same calculation as the existing TLSLE relocations with the result written back to mov[nz] and movk instructions. A typical code sequence is:

movz x0, #:tprel_g2:foo       // bits [47:32] of R_TLS with overflow check
movk x0, #:tprel_g1_nc:foo // bits [31:16] of R_TLS with no overflow check
movk x0, #:tprel_g0_nc:foo // bits [15:0] of R_TLS with no overflow check

This type of code sequence is usually used with a large code model.

fixes PR42853

We also do not yet support the :dtprel_g*: and :gottprel_g*: associated with local dynamic and initial exec. These can be added in separate patches as they may need some thought over how to deal with relaxation. The tprel relocations are already local exec so can't be relaxed further.

[MaskRay]

Looks good to me. Some nits of the test:

test/ELF/aarch64-movw-tprel.s

27

The address can be omitted. The encoding bytes may be omitted, too (--no-show-raw-insn).

Probably make all instruction CHECK: lines CHECK-NEXT:. I think they are contiguous.

40

(Or use llvm-nm %t | FileCheck ... to make it concise :)

[ruiu]

LGTM

[peter.smith]

Thanks for the review, I've applied the changes to the test prior to commit.

ELF/Arch/AArch64.cpp

case R_AARCH64_TLSDESC_CALL:
     return R_TLSDESC_CALL;
   case R_AARCH64_TLSLE_ADD_TPREL_HI12:
   case R_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
   case R_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
   case R_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
   case R_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
   case R_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
   case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC:
+  case R_AARCH64_TLSLE_MOVW_TPREL_G0:
+  case R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
+  case R_AARCH64_TLSLE_MOVW_TPREL_G1:
+  case R_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
+  case R_AARCH64_TLSLE_MOVW_TPREL_G2:
     return R_TLS;
   case R_AARCH64_CALL26:
   case R_AARCH64_CONDBR19:
   case R_AARCH64_JUMP26:
   case R_AARCH64_TSTBR14:
     return R_PLT_PC;
   case R_AARCH64_PREL16:
   case R_AARCH64_PREL32:
void AArch64::relocateOne(uint8_t *loc, RelType type, uint64_t val) const {
   case R_AARCH64_MOVW_UABS_G2_NC:
     or32le(loc, (val & 0xFFFF00000000) >> 27);
     break;
   case R_AARCH64_MOVW_UABS_G3:
     or32le(loc, (val & 0xFFFF000000000000) >> 43);
     break;
   case R_AARCH64_MOVW_PREL_G0:
   case R_AARCH64_MOVW_SABS_G0:
+  case R_AARCH64_TLSLE_MOVW_TPREL_G0:
     checkInt(loc, val, 17, type);
     LLVM_FALLTHROUGH;
   case R_AARCH64_MOVW_PREL_G0_NC:
+  case R_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
     writeSMovWImm(loc, val);
     break;
   case R_AARCH64_MOVW_PREL_G1:
   case R_AARCH64_MOVW_SABS_G1:
+  case R_AARCH64_TLSLE_MOVW_TPREL_G1:
     checkInt(loc, val, 33, type);
     LLVM_FALLTHROUGH;
   case R_AARCH64_MOVW_PREL_G1_NC:
+  case R_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
     writeSMovWImm(loc, val >> 16);
     break;
   case R_AARCH64_MOVW_PREL_G2:
   case R_AARCH64_MOVW_SABS_G2:
+  case R_AARCH64_TLSLE_MOVW_TPREL_G2:
     checkInt(loc, val, 49, type);
     LLVM_FALLTHROUGH;
   case R_AARCH64_MOVW_PREL_G2_NC:
     writeSMovWImm(loc, val >> 32);
     break;
   case R_AARCH64_MOVW_PREL_G3:
     writeSMovWImm(loc, val >> 48);
     break;

test/ELF/aarch64-movw-error.s

 # CHECK: relocation R_AARCH64_MOVW_PREL_G2 out of range: 281474976710656 is not in [-281474976710656, 281474976710655]
 movn x0, #:prel_g2:.+0x1000000000000
 # CHECK: relocation R_AARCH64_MOVW_PREL_G0 out of range: -65537 is not in [-65536, 65535]
 movn x0, #:prel_g0:.-0x10001
 # CHECK: relocation R_AARCH64_MOVW_PREL_G1 out of range: -4295032832 is not in [-4294967296, 4294967295]
 movn x0, #:prel_g1:.-0x100010000
 # CHECK: relocation R_AARCH64_MOVW_PREL_G2 out of range: -281479271677952 is not in [-281474976710656, 281474976710655]
 movn x0, #:prel_g2:.-0x1000100000000
+
+movz x0, #:tprel_g0: v1
+# CHECK: relocation R_AARCH64_TLSLE_MOVW_TPREL_G0 out of range: 65552 is not in [-65536, 65535]
+movz x0, #:tprel_g1: v2
+# CHECK: relocation R_AARCH64_TLSLE_MOVW_TPREL_G1 out of range: 4295032848 is not in [-4294967296, 4294967295]
+movz x0, #:tprel_g2: v3
+# CHECK: relocation R_AARCH64_TLSLE_MOVW_TPREL_G2 out of range: 281479271743496 is not in [-281474976710656, 281474976710655]
+
+.section .tbss,"awT",@nobits
+.balign 16
+.space 0x10000
+v1:
+.quad 0
+.space 0x100000000 - 8
+v2:
+.quad 0
+.space 0x1000000000000 - 16
+v3:
+.quad 0

test/ELF/aarch64-movw-tprel.s

+# REQUIRES: aarch64
+# RUN: llvm-mc -filetype=obj -triple=aarch64-linux-gnu %s -o %t.o
+# RUN: ld.lld %t.o -o %t
+# RUN: llvm-objdump -d %t
+# RUN: llvm-readobj --symbols %t
+# RUN: llvm-objdump -d %t | FileCheck %s
+# RUN: llvm-readobj --symbols %t | FileCheck --check-prefix=CHECK-SYM %s
+
+## Test the the local exec relocations that map to:
+## R_AARCH64_TLSLE_MOVW_TPREL_G2
+## R_AARCH64_TLSLE_MOVW_TPREL_G1
+## R_AARCH64_TLSLE_MOVW_TPREL_G1_NC
+## R_AARCH64_TLSLE_MOVW_TPREL_G0
+## R_AARCH64_TLSLE_MOVW_TPREL_G0_NC
+## They calculate the same value as the other TPREL relocations, namely the
+## offset from the thread pointer TP. The G0, G1 and G2 refer to partitions
+## of the result with G2 bits [47:32], G1 bits [31:16] and G0 bits [15:0]
+## the NC variant does not check for overflow.
+## In AArch64 the structure of the TLS at runtime is:
+## | TCB | Alignment Padding | TLS Block |
+## With TP pointing to the start of the TCB. All offsets will be positive.
+
+.text
+## Access variable in first partition
+movz x0, #:tprel_g0:v0
+## TCB + 0 == 16
+# CHECK:  210000: 00 02 80 d2                   mov     x0, #16
+
+# CHECK-SYM:      Name: v0
+# CHECK-SYM-NEXT: Value: 0x0
+
+## Access variable in second partition
+movz x0, #:tprel_g1:v1
+movk x0, #:tprel_g0_nc:v1
+
+## TCB + 65536 across movz and movk
+# CHECK:      210004: 20 00 a0 d2                       mov     x0, #65536
+# CHECK-NEXT: 210008: 00 02 80 f2                       movk    x0, #16
+
+# CHECK-SYM:      Name: v1
+# CHECK-SYM-NEXT: Value: 0x10000
+
+## Access variable in third partition
+movz x0, #:tprel_g2:v2
+movk x0, #:tprel_g1_nc:v2
+movk x0, #:tprel_g0_nc:v2
+
+## TCB + 65536 + 4294967296 across movz and 2 movk instructions
+# CHECK:        21000c: 20 00 c0 d2                     mov     x0, #4294967296
+# CHECK-NEXT:   210010: 20 00 a0 f2                     movk    x0, #1, lsl #16
+# CHECK-NEXT:   210014: 00 02 80 f2                     movk    x0, #16
+
+# CHECK-SYM:     Name: v2
+# CHECK-SYM-NEXT:     Value: 0x100010000
+
+.section .tbss,"awT",@nobits
+.balign 16
+v0:
+.quad 0
+.space 0x10000 - 8
+v1:
+.quad 0
+.space 0x100000000 - 8
+v2:
+.quad 0