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Differential D65442

[AArch64] Update MTE system register encodings
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Authored by LukeCheeseman on Jul 30 2019, 6:06 AM.

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pbarrio
momchil.velikov
miyuki
MarkMurrayARM
labrinea
simon_tatham
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rG71d38b3c6217: [AArch64] Update MTE system register encodings
rL369505: [AArch64] Update MTE system register encodings
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LukeCheeseman created this revision.Jul 30 2019, 6:06 AM
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ostannard accepted this revision.Jul 30 2019, 10:04 AM
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LGTM

This revision is now accepted and ready to land.Jul 30 2019, 10:04 AM
Closed by commit rL369505: [AArch64] Update MTE system register encodings (authored by LukeCheeseman). · Explain WhyAug 21 2019, 2:13 AM
This revision was automatically updated to reflect the committed changes.

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llvm/
lib/
Target/
AArch64/
10 lines
test/
MC/
AArch64/
20 lines
Disassembler/
AArch64/
40 lines

Diff 212323

llvm/lib/Target/AArch64/AArch64SystemOperands.td

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def : RWSysReg<"SSBS", 0b11, 0b011, 0b0100, 0b0010, 0b110>; def : RWSysReg<"SSBS", 0b11, 0b011, 0b0100, 0b0010, 0b110>;
// v8.5a Memory Tagging Extension // v8.5a Memory Tagging Extension
// Op0 Op1 CRn CRm Op2 // Op0 Op1 CRn CRm Op2
let Requires = [{ {AArch64::FeatureMTE} }] in { let Requires = [{ {AArch64::FeatureMTE} }] in {
def : RWSysReg<"TCO", 0b11, 0b011, 0b0100, 0b0010, 0b111>; def : RWSysReg<"TCO", 0b11, 0b011, 0b0100, 0b0010, 0b111>;
def : RWSysReg<"GCR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b110>; def : RWSysReg<"GCR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b110>;
def : RWSysReg<"RGSR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b101>; def : RWSysReg<"RGSR_EL1", 0b11, 0b000, 0b0001, 0b0000, 0b101>;
def : RWSysReg<"TFSR_EL1", 0b11, 0b000, 0b0110, 0b0101, 0b000>; def : RWSysReg<"TFSR_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b000>;
def : RWSysReg<"TFSR_EL2", 0b11, 0b100, 0b0110, 0b0101, 0b000>; def : RWSysReg<"TFSR_EL2", 0b11, 0b100, 0b0101, 0b0110, 0b000>;
def : RWSysReg<"TFSR_EL3", 0b11, 0b110, 0b0110, 0b0110, 0b000>; def : RWSysReg<"TFSR_EL3", 0b11, 0b110, 0b0101, 0b0110, 0b000>;
def : RWSysReg<"TFSR_EL12", 0b11, 0b101, 0b0110, 0b0110, 0b000>; def : RWSysReg<"TFSR_EL12", 0b11, 0b101, 0b0101, 0b0110, 0b000>;
def : RWSysReg<"TFSRE0_EL1", 0b11, 0b000, 0b0110, 0b0110, 0b001>; def : RWSysReg<"TFSRE0_EL1", 0b11, 0b000, 0b0101, 0b0110, 0b001>;
def : ROSysReg<"GMID_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b100>; def : ROSysReg<"GMID_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b100>;
} // HasMTE } // HasMTE
// Embedded Trace Extension R/W System registers // Embedded Trace Extension R/W System registers
let Requires = [{ {AArch64::FeatureETE} }] in { let Requires = [{ {AArch64::FeatureETE} }] in {
// Name Op0 Op1 CRn CRm Op2 // Name Op0 Op1 CRn CRm Op2
def : RWSysReg<"TRCRSR", 0b10, 0b001, 0b0000, 0b1010, 0b000>; def : RWSysReg<"TRCRSR", 0b10, 0b001, 0b0000, 0b1010, 0b000>;
// TRCEXTINSELR0 has the same encoding as ETM TRCEXTINSELR // TRCEXTINSELR0 has the same encoding as ETM TRCEXTINSELR
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llvm/test/MC/AArch64/armv8.5a-mte.s

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mrs x5, tfsr_el3 mrs x5, tfsr_el3
mrs x6, tfsr_el12 mrs x6, tfsr_el12
mrs x7, tfsre0_el1 mrs x7, tfsre0_el1
mrs x7, gmid_el1 mrs x7, gmid_el1
// CHECK: mrs x0, TCO // encoding: [0xe0,0x42,0x3b,0xd5] // CHECK: mrs x0, TCO // encoding: [0xe0,0x42,0x3b,0xd5]
// CHECK: mrs x1, GCR_EL1 // encoding: [0xc1,0x10,0x38,0xd5] // CHECK: mrs x1, GCR_EL1 // encoding: [0xc1,0x10,0x38,0xd5]
// CHECK: mrs x2, RGSR_EL1 // encoding: [0xa2,0x10,0x38,0xd5] // CHECK: mrs x2, RGSR_EL1 // encoding: [0xa2,0x10,0x38,0xd5]
// CHECK: mrs x3, TFSR_EL1 // encoding: [0x03,0x65,0x38,0xd5] // CHECK: mrs x3, TFSR_EL1 // encoding: [0x03,0x56,0x38,0xd5]
// CHECK: mrs x4, TFSR_EL2 // encoding: [0x04,0x65,0x3c,0xd5] // CHECK: mrs x4, TFSR_EL2 // encoding: [0x04,0x56,0x3c,0xd5]
// CHECK: mrs x5, TFSR_EL3 // encoding: [0x05,0x66,0x3e,0xd5] // CHECK: mrs x5, TFSR_EL3 // encoding: [0x05,0x56,0x3e,0xd5]
// CHECK: mrs x6, TFSR_EL12 // encoding: [0x06,0x66,0x3d,0xd5] // CHECK: mrs x6, TFSR_EL12 // encoding: [0x06,0x56,0x3d,0xd5]
// CHECK: mrs x7, TFSRE0_EL1 // encoding: [0x27,0x66,0x38,0xd5] // CHECK: mrs x7, TFSRE0_EL1 // encoding: [0x27,0x56,0x38,0xd5]
// CHECK: mrs x7, GMID_EL1 // encoding: [0x87,0x00,0x39,0xd5] // CHECK: mrs x7, GMID_EL1 // encoding: [0x87,0x00,0x39,0xd5]
// NOMTE: expected readable system register // NOMTE: expected readable system register
// NOMTE-NEXT: tco // NOMTE-NEXT: tco
// NOMTE: expected readable system register // NOMTE: expected readable system register
// NOMTE-NEXT: gcr_el1 // NOMTE-NEXT: gcr_el1
// NOMTE: expected readable system register // NOMTE: expected readable system register
// NOMTE-NEXT: rgsr_el1 // NOMTE-NEXT: rgsr_el1
Show All 24 Lines
msr tfsr_el2, x4 msr tfsr_el2, x4
msr tfsr_el3, x5 msr tfsr_el3, x5
msr tfsr_el12, x6 msr tfsr_el12, x6
msr tfsre0_el1, x7 msr tfsre0_el1, x7
// CHECK: msr TCO, x0 // encoding: [0xe0,0x42,0x1b,0xd5] // CHECK: msr TCO, x0 // encoding: [0xe0,0x42,0x1b,0xd5]
// CHECK: msr GCR_EL1, x1 // encoding: [0xc1,0x10,0x18,0xd5] // CHECK: msr GCR_EL1, x1 // encoding: [0xc1,0x10,0x18,0xd5]
// CHECK: msr RGSR_EL1, x2 // encoding: [0xa2,0x10,0x18,0xd5] // CHECK: msr RGSR_EL1, x2 // encoding: [0xa2,0x10,0x18,0xd5]
// CHECK: msr TFSR_EL1, x3 // encoding: [0x03,0x65,0x18,0xd5] // CHECK: msr TFSR_EL1, x3 // encoding: [0x03,0x56,0x18,0xd5]
// CHECK: msr TFSR_EL2, x4 // encoding: [0x04,0x65,0x1c,0xd5] // CHECK: msr TFSR_EL2, x4 // encoding: [0x04,0x56,0x1c,0xd5]
// CHECK: msr TFSR_EL3, x5 // encoding: [0x05,0x66,0x1e,0xd5] // CHECK: msr TFSR_EL3, x5 // encoding: [0x05,0x56,0x1e,0xd5]
// CHECK: msr TFSR_EL12, x6 // encoding: [0x06,0x66,0x1d,0xd5] // CHECK: msr TFSR_EL12, x6 // encoding: [0x06,0x56,0x1d,0xd5]
// CHECK: msr TFSRE0_EL1, x7 // encoding: [0x27,0x66,0x18,0xd5] // CHECK: msr TFSRE0_EL1, x7 // encoding: [0x27,0x56,0x18,0xd5]
// NOMTE: expected writable system register or pstate // NOMTE: expected writable system register or pstate
// NOMTE-NEXT: tco // NOMTE-NEXT: tco
// NOMTE: expected writable system register or pstate // NOMTE: expected writable system register or pstate
// NOMTE-NEXT: gcr_el1 // NOMTE-NEXT: gcr_el1
// NOMTE: expected writable system register or pstate // NOMTE: expected writable system register or pstate
// NOMTE-NEXT: rgsr_el1 // NOMTE-NEXT: rgsr_el1
// NOMTE: expected writable system register or pstate // NOMTE: expected writable system register or pstate
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llvm/test/MC/Disassembler/AArch64/armv8.5a-mte.txt

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# NOMTE: sys #3, c7, c12, #5, x14 # NOMTE: sys #3, c7, c12, #5, x14
# NOMTE: sys #3, c7, c13, #5, x15 # NOMTE: sys #3, c7, c13, #5, x15
# NOMTE: sys #3, c7, c14, #5, x16 # NOMTE: sys #3, c7, c14, #5, x16
# NOMTE: sys #3, c7, c4, #4, x17 # NOMTE: sys #3, c7, c4, #4, x17
[0xe0,0x42,0x3b,0xd5] [0xe0,0x42,0x3b,0xd5]
[0xc1,0x10,0x38,0xd5] [0xc1,0x10,0x38,0xd5]
[0xa2,0x10,0x38,0xd5] [0xa2,0x10,0x38,0xd5]
[0x03,0x65,0x38,0xd5] [0x03,0x56,0x38,0xd5]
[0x04,0x65,0x3c,0xd5] [0x04,0x56,0x3c,0xd5]
[0x05,0x66,0x3e,0xd5] [0x05,0x56,0x3e,0xd5]
[0x06,0x66,0x3d,0xd5] [0x06,0x56,0x3d,0xd5]
[0x27,0x66,0x38,0xd5] [0x27,0x56,0x38,0xd5]
[0x88,0x00,0x39,0xd5] [0x88,0x00,0x39,0xd5]
# CHECK: mrs x0, TCO # CHECK: mrs x0, TCO
# CHECK: mrs x1, GCR_EL1 # CHECK: mrs x1, GCR_EL1
# CHECK: mrs x2, RGSR_EL1 # CHECK: mrs x2, RGSR_EL1
# CHECK: mrs x3, TFSR_EL1 # CHECK: mrs x3, TFSR_EL1
# CHECK: mrs x4, TFSR_EL2 # CHECK: mrs x4, TFSR_EL2
# CHECK: mrs x5, TFSR_EL3 # CHECK: mrs x5, TFSR_EL3
# CHECK: mrs x6, TFSR_EL12 # CHECK: mrs x6, TFSR_EL12
# CHECK: mrs x7, TFSRE0_EL1 # CHECK: mrs x7, TFSRE0_EL1
# CHECK: mrs x8, GMID_EL1 # CHECK: mrs x8, GMID_EL1
# NOMTE: mrs x0, S3_3_C4_C2_7 # NOMTE: mrs x0, S3_3_C4_C2_7
# NOMTE: mrs x1, S3_0_C1_C0_6 # NOMTE: mrs x1, S3_0_C1_C0_6
# NOMTE: mrs x2, S3_0_C1_C0_5 # NOMTE: mrs x2, S3_0_C1_C0_5
# NOMTE: mrs x3, S3_0_C6_C5_0 # NOMTE: mrs x3, S3_0_C5_C6_0
# NOMTE: mrs x4, S3_4_C6_C5_0 # NOMTE: mrs x4, S3_4_C5_C6_0
# NOMTE: mrs x5, S3_6_C6_C6_0 # NOMTE: mrs x5, S3_6_C5_C6_0
# NOMTE: mrs x6, S3_5_C6_C6_0 # NOMTE: mrs x6, S3_5_C5_C6_0
# NOMTE: mrs x7, S3_0_C6_C6_1 # NOMTE: mrs x7, S3_0_C5_C6_1
# NOMTE: mrs x8, S3_1_C0_C0_4 # NOMTE: mrs x8, S3_1_C0_C0_4
[0x9f,0x40,0x03,0xd5] [0x9f,0x40,0x03,0xd5]
# CHECK: msr TCO, #0 # CHECK: msr TCO, #0
# NOMTE: msr S0_3_C4_C0_4, xzr # NOMTE: msr S0_3_C4_C0_4, xzr
[0xe0,0x42,0x1b,0xd5] [0xe0,0x42,0x1b,0xd5]
[0xc1,0x10,0x18,0xd5] [0xc1,0x10,0x18,0xd5]
[0xa2,0x10,0x18,0xd5] [0xa2,0x10,0x18,0xd5]
[0x03,0x65,0x18,0xd5] [0x03,0x56,0x18,0xd5]
[0x04,0x65,0x1c,0xd5] [0x04,0x56,0x1c,0xd5]
[0x05,0x66,0x1e,0xd5] [0x05,0x56,0x1e,0xd5]
[0x06,0x66,0x1d,0xd5] [0x06,0x56,0x1d,0xd5]
[0x27,0x66,0x18,0xd5] [0x27,0x56,0x18,0xd5]
[0x88,0x00,0x19,0xd5] [0x88,0x00,0x19,0xd5]
# CHECK: msr TCO, x0 # CHECK: msr TCO, x0
# CHECK: msr GCR_EL1, x1 # CHECK: msr GCR_EL1, x1
# CHECK: msr RGSR_EL1, x2 # CHECK: msr RGSR_EL1, x2
# CHECK: msr TFSR_EL1, x3 # CHECK: msr TFSR_EL1, x3
# CHECK: msr TFSR_EL2, x4 # CHECK: msr TFSR_EL2, x4
# CHECK: msr TFSR_EL3, x5 # CHECK: msr TFSR_EL3, x5
# CHECK: msr TFSR_EL12, x6 # CHECK: msr TFSR_EL12, x6
# CHECK: msr TFSRE0_EL1, x7 # CHECK: msr TFSRE0_EL1, x7
# GMID_EL1 is read only # GMID_EL1 is read only
# CHECK: msr S3_1_C0_C0_4, x8 # CHECK: msr S3_1_C0_C0_4, x8
# NOMTE: msr S3_3_C4_C2_7, x0 # NOMTE: msr S3_3_C4_C2_7, x0
# NOMTE: msr S3_0_C1_C0_6, x1 # NOMTE: msr S3_0_C1_C0_6, x1
# NOMTE: msr S3_0_C1_C0_5, x2 # NOMTE: msr S3_0_C1_C0_5, x2
# NOMTE: msr S3_0_C6_C5_0, x3 # NOMTE: msr S3_0_C5_C6_0, x3
# NOMTE: msr S3_4_C6_C5_0, x4 # NOMTE: msr S3_4_C5_C6_0, x4
# NOMTE: msr S3_6_C6_C6_0, x5 # NOMTE: msr S3_6_C5_C6_0, x5
# NOMTE: msr S3_5_C6_C6_0, x6 # NOMTE: msr S3_5_C5_C6_0, x6
# NOMTE: msr S3_0_C6_C6_1, x7 # NOMTE: msr S3_0_C5_C6_1, x7
# NOMTE: msr S3_1_C0_C0_4, x8 # NOMTE: msr S3_1_C0_C0_4, x8