[PowerPC][Peephole] Check if `extsw`'s second operand is a virtual register

[lkail]

Summary

When combining extsw and sldi in PPCMIPeephole, we have to check if extsw's second operand is a virtual register, otherwise we might get miscompile. For now, I haven't find a real world case, so I posted a MIR test case.

[jsji]

LGTM.

[lkail]

Updated patch to use Register::isVirtualRegister, a replacement of TargetRegisterInfo::isVirtualRegister.

commit 2bea69bf6503ffc9f3cde9a52b5dac1a25e94e1c
Author: Daniel Sanders <[e-mail]>
Date:   Thu Aug 1 23:27:28 2019 +0000

Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC

  llvm-svn: 367633

[steven.zhang]

LGTM with the update.

llvm/lib/Target/PowerPC/PPCMIPeephole.cpp

if (SrcMI->getOpcode() != PPC::EXTSW &&
       SrcMI->getOpcode() != PPC::EXTSW_32_64)
     return false;
 
   // If the register defined by extsw has more than one use, combination is not
   // needed.
   if (!MRI->hasOneNonDBGUse(SrcReg))
     return false;
 
+  assert(SrcMI->getNumOperands() == 2 && "EXTSW should have 2 operands");
+  assert(SrcMI->getOperand(1).isReg() &&
+         "EXTSW's second operand should be a register");
+  if (!TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg()))
+    return false;
+
   LLVM_DEBUG(dbgs() << "Combining pair: ");
   LLVM_DEBUG(SrcMI->dump());
   LLVM_DEBUG(MI.dump());
 
   MachineInstr *NewInstr =
       BuildMI(*MI.getParent(), &MI, MI.getDebugLoc(),
               SrcMI->getOpcode() == PPC::EXTSW ? TII->get(PPC::EXTSWSLI)
                                                : TII->get(PPC::EXTSWSLI_32_64),

llvm/test/CodeGen/MIR/PowerPC/peephole-miscompile-extswsli.mir

body:             |
   ; CHECK:   [[COPY2:%[0-9]+]]:g8rc = COPY $x4
   ; CHECK:   [[COPY3:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
   ; CHECK:   [[ANDIo8_:%[0-9]+]]:g8rc = ANDIo8 [[COPY1]], 1, implicit-def $cr0
   ; CHECK:   [[COPY4:%[0-9]+]]:crbitrc = COPY $cr0gt
   ; CHECK:   BCn killed [[COPY4]], %bb.2
   ; CHECK:   B %bb.1
   ; CHECK: bb.1:
   ; CHECK:   liveins: $x3
+  ; CHECK:   [[EXTSW:%[0-9]+]]:g8rc = EXTSW $x3
   ; CHECK:   [[RLDICR:%[0-9]+]]:g8rc = RLDICR [[ANDIo8_]], 2, 61
   ; CHECK:   $x3 = COPY [[RLDICR]]
-  ; CHECK:   [[EXTSWSLI:%[0-9]+]]:g8rc = EXTSWSLI $x3, 2, implicit-def $carry
-  ; CHECK:   [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[EXTSWSLI]]
+  ; CHECK:   [[RLDICR1:%[0-9]+]]:g8rc = RLDICR [[EXTSW]], 2, 61
+  ; CHECK:   [[ADD8_:%[0-9]+]]:g8rc = ADD8 [[COPY3]], [[RLDICR1]]
   ; CHECK:   $x3 = COPY [[ADD8_]]
   ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3
   ; CHECK: bb.2:
   ; CHECK:   [[COPY5:%[0-9]+]]:gprc = COPY [[COPY]].sub_32
   ; CHECK:   [[DEF:%[0-9]+]]:g8rc = IMPLICIT_DEF
   ; CHECK:   [[INSERT_SUBREG:%[0-9]+]]:g8rc = INSERT_SUBREG [[DEF]], [[COPY5]], %subreg.sub_32
   ; CHECK:   $x3 = COPY [[INSERT_SUBREG]]
   ; CHECK:   BLR8 implicit $lr8, implicit $rm, implicit $x3