[ARM] Add <saturate> operand to SQRSHRL and UQRSHLL

[miyuki]

Summary

According to the new Armv8-M specification
https://static.docs.arm.com/ddi0553/bh/DDI0553B_h_armv8m_arm.pdf the
instructions SQRSHRL and UQRSHLL now have an additional immediate
operand <saturate>. The new assembly syntax is:

SQRSHRL<c> RdaLo, RdaHi, #<saturate>, Rm
UQRSHLL<c> RdaLo, RdaHi, #<saturate>, Rm

where <saturate> can be either 64 (the existing behavior) or 48, in
that case the result is saturated to 48 bits.

The new operand is encoded as follows:

#64 Encoded as sat = 0
#48 Encoded as sat = 1

sat is bit 7 of the instruction bit pattern.

This patch adds a new assembler operand class MveSaturateOperand which
implements parsing and encoding. Decoding is implemented in
DecodeMVEOverlappingLongShift.

[simon_tatham]

llvm/lib/Target/ARM/ARMInstrMVE.td

431 ↗

(On Diff #210132)

This class seems almost identical to MVE_ScalarShiftDRegReg, differing only in the extra input operand, the different AsmString, and the introduction of bit sat; assigned to Inst{7}. They could be merged into a common superclass to avoid all that copy and paste?

[miyuki]

Removed some redundancy.

llvm/trunk/lib/Target/ARM/ARMInstrFormats.td

def complexrotateop : Operand<i32> {
   let ParserMatchClass = ComplexRotationOperand<90, 0, "Even", "0, 90, 180 or 270">;
   let PrintMethod = "printComplexRotationOp<90, 0>";
 }
 def complexrotateopodd : Operand<i32> {
   let ParserMatchClass = ComplexRotationOperand<180, 90, "Odd", "90 or 270">;
   let PrintMethod = "printComplexRotationOp<180, 90>";
 }
 
+def MveSaturateOperand : AsmOperandClass {
+  let PredicateMethod = "isMveSaturateOp";
+  let DiagnosticString = "saturate operand must be 48 or 64";
+  let Name = "MveSaturate";
+}
+def saturateop : Operand<i32> {
+  let ParserMatchClass = MveSaturateOperand;
+  let PrintMethod = "printMveSaturateOp";
+}
+
 // Data type suffix token aliases. Implements Table A7-3 in the ARM ARM.
 def : TokenAlias<".s8", ".i8">;
 def : TokenAlias<".u8", ".i8">;
 def : TokenAlias<".s16", ".i16">;
 def : TokenAlias<".u16", ".i16">;
 def : TokenAlias<".s32", ".i32">;
 def : TokenAlias<".u32", ".i32">;
 def : TokenAlias<".s64", ".i64">;

llvm/trunk/lib/Target/ARM/ARMInstrMVE.td

class MVE_ScalarShiftDRegImm<string iname, bits<2> op5_4, bit op16,
   let Inst{16} = op16;
   let Inst{15} = 0b0;
   let Inst{14-12} = imm{4-2};
   let Inst{7-6} = imm{1-0};
   let Inst{5-4} = op5_4{1-0};
   let Inst{3-0} = 0b1111;
 }
 
-class MVE_ScalarShiftDRegReg<string iname, bit op5, bit op16,
-                             list<dag> pattern=[]>
+class MVE_ScalarShiftDRegRegBase<string iname, dag iops, string asm,
+                                 bit op5, bit op16, list<dag> pattern=[]>
   : MVE_ScalarShiftDoubleReg<
-     iname, (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, rGPR:$Rm),
-     "$RdaLo, $RdaHi, $Rm", "@earlyclobber $RdaHi,@earlyclobber $RdaLo,"
-                            "$RdaLo = $RdaLo_src,$RdaHi = $RdaHi_src",
+     iname, iops, asm, "@earlyclobber $RdaHi,@earlyclobber $RdaLo,"
      pattern> {
   bits<4> Rm;
 
   let Inst{16} = op16;
   let Inst{15-12} = Rm{3-0};
-  let Inst{7-6} = 0b00;
+  let Inst{6} = 0b0;
   let Inst{5} = op5;
   let Inst{4} = 0b0;
   let Inst{3-0} = 0b1101;
 
   // Custom decoder method because of the following overlapping encodings:
   // ASRL and SQRSHR
   // LSLL and UQRSHL
   // SQRSHRL and SQRSHR
   // UQRSHLL and UQRSHL
   let DecoderMethod = "DecodeMVEOverlappingLongShift";
 }
 
-def MVE_ASRLr   : MVE_ScalarShiftDRegReg<"asrl",    0b1,  0b0, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
+class MVE_ScalarShiftDRegReg<string iname, bit op5, list<dag> pattern=[]>
+  : MVE_ScalarShiftDRegRegBase<
+     iname, (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, rGPR:$Rm),
+     "$RdaLo, $RdaHi, $Rm", op5, 0b0, pattern> {
+
+  let Inst{7} = 0b0;
+}
+
+class MVE_ScalarShiftDRegRegWithSat<string iname, bit op5, list<dag> pattern=[]>
+  : MVE_ScalarShiftDRegRegBase<
+     iname, (ins tGPREven:$RdaLo_src, tGPROdd:$RdaHi_src, rGPR:$Rm, saturateop:$sat),
+     "$RdaLo, $RdaHi, $sat, $Rm", op5, 0b1, pattern> {
+  bit sat;
+
+  let Inst{7} = sat;
+}
+
+def MVE_ASRLr   : MVE_ScalarShiftDRegReg<"asrl",    0b1,  [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
                                         (ARMasrl tGPREven:$RdaLo_src,
                                         tGPROdd:$RdaHi_src, rGPR:$Rm))]>;
 def MVE_ASRLi   : MVE_ScalarShiftDRegImm<"asrl",    0b10, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
                                         (ARMasrl tGPREven:$RdaLo_src,
                                         tGPROdd:$RdaHi_src, (i32 imm:$imm)))]>;
-def MVE_LSLLr   : MVE_ScalarShiftDRegReg<"lsll",    0b0,  0b0, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
+def MVE_LSLLr   : MVE_ScalarShiftDRegReg<"lsll",    0b0,  [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
                                         (ARMlsll tGPREven:$RdaLo_src,
                                         tGPROdd:$RdaHi_src, rGPR:$Rm))]>;
 def MVE_LSLLi   : MVE_ScalarShiftDRegImm<"lsll",    0b00, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
                                         (ARMlsll tGPREven:$RdaLo_src,
                                         tGPROdd:$RdaHi_src, (i32 imm:$imm)))]>;
 def MVE_LSRL    : MVE_ScalarShiftDRegImm<"lsrl",    0b01, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
                                         (ARMlsrl tGPREven:$RdaLo_src,
                                         tGPROdd:$RdaHi_src, (i32 imm:$imm)))]>;
 
-def MVE_SQRSHRL : MVE_ScalarShiftDRegReg<"sqrshrl", 0b1,  0b1>;
+def MVE_SQRSHRL : MVE_ScalarShiftDRegRegWithSat<"sqrshrl", 0b1>;
 def MVE_SQSHLL  : MVE_ScalarShiftDRegImm<"sqshll",  0b11, 0b1>;
 def MVE_SRSHRL  : MVE_ScalarShiftDRegImm<"srshrl",  0b10, 0b1>;
 
-def MVE_UQRSHLL : MVE_ScalarShiftDRegReg<"uqrshll", 0b0,  0b1>;
+def MVE_UQRSHLL : MVE_ScalarShiftDRegRegWithSat<"uqrshll", 0b0>;
 def MVE_UQSHLL  : MVE_ScalarShiftDRegImm<"uqshll",  0b00, 0b1>;
 def MVE_URSHRL  : MVE_ScalarShiftDRegImm<"urshrl",  0b01, 0b1>;
 
 // start of mve_rDest instructions
 
 class MVE_rDest<dag oops, dag iops, InstrItinClass itin,
                 string iname, string suffix,
                 string ops, string cstr, list<dag> pattern=[]>

llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

bool isMVELongShift() const {
     if (!isImm()) return false;
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     // Must be a constant.
     if (!CE) return false;
     uint64_t Value = CE->getValue();
     return Value >= 1 && Value <= 32;
   }
 
+  bool isMveSaturateOp() const {
+    if (!isImm()) return false;
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    if (!CE) return false;
+    uint64_t Value = CE->getValue();
+    return Value == 48 || Value == 64;
+  }
+
   bool isITCondCodeNoAL() const {
     if (!isITCondCode()) return false;
     ARMCC::CondCodes CC = getCondCode();
     return CC != ARMCC::AL;
   }
 
   bool isITCondCodeRestrictedI() const {
     if (!isITCondCode())

   }
 
   void addComplexRotationOddOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
     Inst.addOperand(MCOperand::createImm((CE->getValue() - 90) / 180));
   }
 
+  void addMveSaturateOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
+    unsigned Imm = CE->getValue();
+    assert((Imm == 48 || Imm == 64) && "Invalid saturate operand");
+    Inst.addOperand(MCOperand::createImm(Imm == 48 ? 1 : 0));
+  }
+
   void print(raw_ostream &OS) const override;
 
   static std::unique_ptr<ARMOperand> CreateITMask(unsigned Mask, SMLoc S) {
     auto Op = make_unique<ARMOperand>(k_ITCondMask);
     Op->ITMask.Mask = Mask;
     Op->StartLoc = S;
     Op->EndLoc = S;
     return Op;

llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
     return MCDisassembler::Fail;
   if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
     return MCDisassembler::Fail;
 
   // Rm, the amount to shift by
   if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
     return MCDisassembler::Fail;
 
+  if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||
+      Inst.getOpcode() == ARM::MVE_UQRSHLL) {
+    unsigned Saturate = fieldFromInstruction(Insn, 7, 1);
+    // Saturate, the bit position for saturation
+    Inst.addOperand(MCOperand::createImm(Saturate));
+  }
+
   return S;
 }
 
 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn, uint64_t Address,
                                       const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
   unsigned Qd = ((fieldFromInstruction(Insn, 22, 1) << 3) |
                  fieldFromInstruction(Insn, 13, 3));

llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.h

void printVPTMask(const MCInst *MI, unsigned OpNum,
                     const MCSubtargetInfo &STI, raw_ostream &O);
   template<int shift>
   void printMveAddrModeRQOperand(const MCInst *MI, unsigned OpNum,
                                  const MCSubtargetInfo &STI, raw_ostream &O);
   void printMveAddrModeQOperand(const MCInst *MI, unsigned OpNum,
                                 const MCSubtargetInfo &STI, raw_ostream &O);
   void printExpandedImmOperand(const MCInst *MI, unsigned OpNum,
                                const MCSubtargetInfo &STI, raw_ostream &O);
-
+  void printMveSaturateOp(const MCInst *MI, unsigned OpNum,
+                         const MCSubtargetInfo &STI, raw_ostream &O);
 private:
   unsigned DefaultAltIdx = ARM::NoRegAltName;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_ARM_MCTARGETDESC_ARMINSTPRINTER_H

llvm/trunk/lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp

 void ARMInstPrinter::printExpandedImmOperand(const MCInst *MI, unsigned OpNum,
                                              const MCSubtargetInfo &STI,
                                              raw_ostream &O) {
   uint32_t Val = MI->getOperand(OpNum).getImm();
   O << markup("<imm:") << "#0x";
   O.write_hex(Val);
   O << markup(">");
 }
+
+void ARMInstPrinter::printMveSaturateOp(const MCInst *MI, unsigned OpNum,
+                                        const MCSubtargetInfo &STI,
+                                        raw_ostream &O) {
+  uint32_t Val = MI->getOperand(OpNum).getImm();
+  assert(Val <= 1 && "Invalid MVE saturate operand");
+  O << "#" << (Val == 1 ? 48 : 64);
+}

llvm/trunk/test/MC/ARM/mve-scalar-shift.s

 # CHECK: sqrshr  lr, r12  @ encoding: [0x5e,0xea,0x2d,0xcf]
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
 sqrshr  lr, r12
 
 # CHECK: sqrshr  r11, r12  @ encoding: [0x5b,0xea,0x2d,0xcf]
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
 sqrshr  r11, r12
 
-# CHECK: sqrshrl lr, r3, r8  @ encoding: [0x5f,0xea,0x2d,0x83]
+# CHECK: sqrshrl lr, r3, #64, r8  @ encoding: [0x5f,0xea,0x2d,0x83]
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
-sqrshrl lr, r3, r8
+sqrshrl lr, r3, #64, r8
+
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: saturate operand must be 48 or 64
+# ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
+sqrshrl lr, r3, #32, r8
 
 # CHECK: sqshl   lr, #17  @ encoding: [0x5e,0xea,0x7f,0x4f]
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
 sqshl   lr, #17
 
 # CHECK: sqshll  lr, r11, #28  @ encoding: [0x5f,0xea,0x3f,0x7b]
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
 sqshll  lr, r11, #28
 
 # CHECK: srshr   lr, #11  @ encoding: [0x5e,0xea,0xef,0x2f]
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
 srshr   lr, #11
 
 # CHECK: srshrl  lr, r11, #23  @ encoding: [0x5f,0xea,0xef,0x5b]
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
 srshrl  lr, r11, #23
 
 # CHECK: uqrshl  lr, r1  @ encoding: [0x5e,0xea,0x0d,0x1f]
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
 uqrshl  lr, r1
 
-# CHECK: uqrshll lr, r1, r4  @ encoding: [0x5f,0xea,0x0d,0x41]
+# CHECK: uqrshll lr, r1, #48, r4  @ encoding: [0x5f,0xea,0x8d,0x41]
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
-uqrshll lr, r1, r4
+uqrshll lr, r1, #48, r4
+
+# ERROR: [[@LINE+2]]:{{[0-9]+}}: {{error|note}}: saturate operand must be 48 or 64
+# ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
+uqrshll lr, r1, #0, r4
 
 # CHECK: uqshl   r0, #1  @ encoding: [0x50,0xea,0x4f,0x0f]
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
 uqshl   r0, #1
 
 # CHECK: uqshll  lr, r7, #7  @ encoding: [0x5f,0xea,0xcf,0x17]
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
 uqshll  lr, r7, #7
 
 # CHECK: urshr   r0, #10  @ encoding: [0x50,0xea,0x9f,0x2f]
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
 urshr   r0, #10
 
 # CHECK: urshrl  r0, r9, #29  @ encoding: [0x51,0xea,0x5f,0x79]
 # ERROR-NOMVE: [[@LINE+1]]:{{[0-9]+}}: error: instruction requires: mve
 urshrl  r0, r9, #29

llvm/trunk/test/MC/Disassembler/ARM/mve-scalar-shift.txt

 # CHECK: lsll    lr, r1, r4  @ encoding: [0x5e,0xea,0x0d,0x41]
 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
 
 [0x5e 0xea 0x1f 0x31]
 # CHECK: lsrl    lr, r1, #12  @ encoding: [0x5e,0xea,0x1f,0x31]
 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
 
 [0x5f 0xea 0x2d 0x83]
-# CHECK: sqrshrl lr, r3, r8  @ encoding: [0x5f,0xea,0x2d,0x83]
+# CHECK: sqrshrl lr, r3, #64, r8  @ encoding: [0x5f,0xea,0x2d,0x83]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
+
+[0x5f 0xea 0xad 0x83]
+# CHECK: sqrshrl lr, r3, #48, r8  @ encoding: [0x5f,0xea,0xad,0x83]
 # CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
 
 [0x5e 0xea 0x7f 0x4f]
 # CHECK: sqshl   lr, #17  @ encoding: [0x5e,0xea,0x7f,0x4f]
 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
 
 [0x5f 0xea 0x3f 0x7b]
 # CHECK: sqshll  lr, r11, #28  @ encoding: [0x5f,0xea,0x3f,0x7b]

 # CHECK: uqrshl  lr, r12  @ encoding: [0x5e,0xea,0x0d,0xcf]
 # CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
 
 [0x5b 0xea 0x0d 0xcf]
 # CHECK: uqrshl  r11, r12  @ encoding: [0x5b,0xea,0x0d,0xcf]
 # CHECK-NOMVE: [[@LINE-2]]:2: warning: invalid instruction encoding
 
 [0x5f 0xea 0x0d 0x41]
-# CHECK: uqrshll lr, r1, r4  @ encoding: [0x5f,0xea,0x0d,0x41]
+# CHECK: uqrshll lr, r1, #64, r4  @ encoding: [0x5f,0xea,0x0d,0x41]
+# CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
+
+[0x5f 0xea 0x8d 0x41]
+# CHECK: uqrshll lr, r1, #48, r4  @ encoding: [0x5f,0xea,0x8d,0x41]
 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
 
 [0x50 0xea 0x4f 0x0f]
 # CHECK: uqshl   r0, #1  @ encoding: [0x50,0xea,0x4f,0x0f]
 # CHECK-NOMVE: [[@LINE-2]]:2: warning: potentially undefined instruction encoding
 
 [0x5f 0xea 0xcf 0x17]
 # CHECK: uqshll  lr, r7, #7  @ encoding: [0x5f,0xea,0xcf,0x17]