[SVE][Inline-Asm] Add support to specify SVE registers in the clobber list

[kmclaughlin]

Summary

Adds the SVE vector and predicate registers to the list of known registers.

[sdesmalen]

Functionally the patch looks good, but the title suggests this adds full inline-asm support for SVE (which would require the ACLE types proposed in D62960, as well as other changes), where this patch only adds support to specify SVE registers in the clobber list.

clang/test/CodeGen/aarch64-sve-inline-asm.c

5

nit: there is no reason to have a different code-style for code and tests (curly brace is on next line here).
Maybe run this through clang-format?

8

nit: The asm/instructions here don't really need to make sense (as in: they are not executed), so you can combine all three tests into one, as long as the instructions are valid and z0, p0, z31 and z15 are used.

[rovka]

clang/lib/Basic/Targets/AArch64.cpp

344

You should commit the typo fixes separately.

clang/test/CodeGen/aarch64-sve-inline-asm.c

2

Can you also add a test without +sve, to make sure we get a diagnostic?

[kmclaughlin]

• Removed typo fixes from this patch
• Consolidated the tests in aarch64-sve-inline-asm.c into one test & fixed formatting
• Added a test without +sve to ensure we get the correct diagnostic

[sdesmalen]

clang/test/CodeGen/aarch64-sve-inline-asm.c

2

Without the -emit-llvm part this test invokes (and tests the diagnostic of) the compiler. I don't think this is what we want. At the same time, this code should probably still continue match the z and p registers even if the target feature is not given, and thus leave it to LLVM to determine whether the use of these registers makes sense or not. So removing -target-feature +sve from the RUN line should be sufficient here. @rovka do you agree?

13

There is no variable linked to t in this inline asm, so you can remove this clause.

[rovka]

clang/test/CodeGen/aarch64-sve-inline-asm.c

2

Good point, we probably don't want this to be an integration test of the whole compiler. Removing the target feature altogether sounds good to me.

[kmclaughlin]

• Updated test to remove unused variable 't'

[kmclaughlin]

• Removed second test in aarch64-sve-inline-asm.c which didn't use -emit-llvm

[sdesmalen]

LGTM

clang/lib/Basic/Targets/AArch64.cpp

const char *const AArch64TargetInfo::GCCRegNames[] = {
     "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", "w22",
     "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
 
     // 64-bit Integer registers
     "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", "x11",
     "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", "x22",
     "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp",
 
     // 32-bit floating point regsisters
     "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", "s11",
     "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", "s22",
     "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
 
     // 64-bit floating point regsisters
     "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", "d11",
     "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", "d22",
     "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
 
-    // Vector registers
+    // Neon vector registers
     "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", "v11",
     "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", "v22",
-    "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
+    "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
+
+    // SVE vector registers
+    "z0",  "z1",  "z2",  "z3",  "z4",  "z5",  "z6",  "z7",  "z8",  "z9",  "z10",
+    "z11", "z12", "z13", "z14", "z15", "z16", "z17", "z18", "z19", "z20", "z21",
+    "z22", "z23", "z24", "z25", "z26", "z27", "z28", "z29", "z30", "z31",
+
+    // SVE predicate registers
+    "p0",  "p1",  "p2",  "p3",  "p4",  "p5",  "p6",  "p7",  "p8",  "p9",  "p10",
+    "p11", "p12", "p13", "p14", "p15"
 };
 
 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const {
   return llvm::makeArrayRef(GCCRegNames);
 }
 
 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
     {{"w31"}, "wsp"},

clang/test/CodeGen/aarch64-sve-inline-asm.c

+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -target-feature +sve -o - %s | FileCheck %s -check-prefix=CHECK-SVE
+// RUN: not %clang_cc1 -triple aarch64-none-linux-gnu -S %s -o - 2>&1 | FileCheck %s -check-prefix=CHECK-ERROR
+
+void test_sve_asm() {
+  asm volatile(
+      "ptrue p0.d\n"
+      "ptrue p15.d\n"
+      "add z0.d, p0/m, z0.d, z0.d\n"
+      "add z31.d, p0/m, z31.d, z31.d\n"
+      :
+      :
+      : "z0", "z31", "p0", "p15");
+  // CHECK-SVE: "~{z0},~{z31},~{p0},~{p15}"
+  // CHECK-ERROR: error: instruction requires: sve
+}