ELF: Add support for remaining R_AARCH64_MOVW* relocations.

[pcc]

Summary

Depends on D64683

Depends on D64684

[MaskRay]

lld/test/ELF/aarch64-relocs.s

242 ↗

(On Diff #209662)

You can consider moving this chunk to a separate test and using llvm-objdump -d --print-imm-hex, then you don't have to explain -65537 = 0xfffffffffffeffff.

x86-64-reloc-*.s and ppc32-reloc-*.s are organized this way.

[peter.smith]

Functionally looks good. To my eyes it matches what is in the Arm ARM and ELF for the 64-bit architecture:

https://developer.arm.com/docs/ihi0056/latest/elf-for-the-arm-64-bit-architecture-aarch64-abi-2019q2-documentation
https://developer.arm.com/docs/ddi0487/latest/arm-architecture-reference-manual-armv8-for-armv8-a-architecture-profile

lld/ELF/Arch/AArch64.cpp

257 ↗

(On Diff #209662)

Really trivial nit, we use lower case in the comment before the function but upper case in the body. Is it worth choosing one? The rest of the file seems to mostly use lower case although there are some uses of MOVZ and MOVK in relaxTlsIeToLE.

262 ↗

(On Diff #209662)

To save a lookup in the Arm ARM, is it worth a quick comment along the lines:
// opcode field is bits 30, 29, with 10 = movz, 00 = movn and 11 = movk.

[ruiu]

LGTM

lld/ELF/Arch/AArch64.cpp

260 ↗

(On Diff #209662)

As a single-letter variable, l is perhaps not a good name because it looks like 1. Maybe loc?

[pcc]

lld/test/ELF/aarch64-relocs.s

242 ↗

(On Diff #209662)

I think I'll leave this as is. The switch to --print-imm-hex would probably be better done as a cleanup over this entire file since there are already a number of instances of the same pattern here.

lld/trunk/ELF/Arch/AArch64.cpp

RelExpr AArch64::getRelExpr(RelType type, const Symbol &s,
   case R_AARCH64_JUMP26:
   case R_AARCH64_TSTBR14:
     return R_PLT_PC;
   case R_AARCH64_PREL16:
   case R_AARCH64_PREL32:
   case R_AARCH64_PREL64:
   case R_AARCH64_ADR_PREL_LO21:
   case R_AARCH64_LD_PREL_LO19:
+  case R_AARCH64_MOVW_PREL_G0:
+  case R_AARCH64_MOVW_PREL_G0_NC:
+  case R_AARCH64_MOVW_PREL_G1:
+  case R_AARCH64_MOVW_PREL_G1_NC:
+  case R_AARCH64_MOVW_PREL_G2:
+  case R_AARCH64_MOVW_PREL_G2_NC:
+  case R_AARCH64_MOVW_PREL_G3:
     return R_PC;
   case R_AARCH64_ADR_PREL_PG_HI21:
   case R_AARCH64_ADR_PREL_PG_HI21_NC:
     return R_AARCH64_PAGE_PC;
   case R_AARCH64_LD64_GOT_LO12_NC:
   case R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC:
     return R_GOT;
   case R_AARCH64_ADR_GOT_PAGE:

 
 static void or32le(uint8_t *p, int32_t v) { write32le(p, read32le(p) | v); }
 
 // Update the immediate field in a AARCH64 ldr, str, and add instruction.
 static void or32AArch64Imm(uint8_t *l, uint64_t imm) {
   or32le(l, (imm & 0xFFF) << 10);
 }
 
+// Update the immediate field in an AArch64 movk, movn or movz instruction
+// for a signed relocation, and update the opcode of a movn or movz instruction
+// to match the sign of the operand.
+static void writeSMovWImm(uint8_t *loc, uint32_t imm) {
+  uint32_t inst = read32le(loc);
+  // Opcode field is bits 30, 29, with 10 = movz, 00 = movn and 11 = movk.
+  if (!(inst & (1 << 29))) {
+    // movn or movz.
+    if (imm & 0x10000) {
+      // Change opcode to movn, which takes an inverted operand.
+      imm ^= 0xFFFF;
+      inst &= ~(1 << 30);
+    } else {
+      // Change opcode to movz.
+      inst |= 1 << 30;
+    }
+  }
+  write32le(loc, inst | ((imm & 0xFFFF) << 5));
+}
+
 void AArch64::relocateOne(uint8_t *loc, RelType type, uint64_t val) const {
   switch (type) {
   case R_AARCH64_ABS16:
   case R_AARCH64_PREL16:
     checkIntUInt(loc, val, 16, type);
     write16le(loc, val);
     break;
   case R_AARCH64_ABS32:
case R_AARCH64_TLSDESC_LD64_LO12:
     checkAlignment(loc, val, 8, type);
     or32AArch64Imm(loc, getBits(val, 3, 11));
     break;
   case R_AARCH64_LDST128_ABS_LO12_NC:
   case R_AARCH64_TLSLE_LDST128_TPREL_LO12_NC:
     checkAlignment(loc, val, 16, type);
     or32AArch64Imm(loc, getBits(val, 4, 11));
     break;
+  case R_AARCH64_MOVW_UABS_G0:
+    checkUInt(loc, val, 16, type);
+    LLVM_FALLTHROUGH;
   case R_AARCH64_MOVW_UABS_G0_NC:
     or32le(loc, (val & 0xFFFF) << 5);
     break;
+  case R_AARCH64_MOVW_UABS_G1:
+    checkUInt(loc, val, 32, type);
+    LLVM_FALLTHROUGH;
   case R_AARCH64_MOVW_UABS_G1_NC:
     or32le(loc, (val & 0xFFFF0000) >> 11);
     break;
+  case R_AARCH64_MOVW_UABS_G2:
+    checkUInt(loc, val, 48, type);
+    LLVM_FALLTHROUGH;
   case R_AARCH64_MOVW_UABS_G2_NC:
     or32le(loc, (val & 0xFFFF00000000) >> 27);
     break;
   case R_AARCH64_MOVW_UABS_G3:
     or32le(loc, (val & 0xFFFF000000000000) >> 43);
     break;
+  case R_AARCH64_MOVW_PREL_G0:
+  case R_AARCH64_MOVW_SABS_G0:
+    checkInt(loc, val, 17, type);
+    LLVM_FALLTHROUGH;
+  case R_AARCH64_MOVW_PREL_G0_NC:
+    writeSMovWImm(loc, val);
+    break;
+  case R_AARCH64_MOVW_PREL_G1:
+  case R_AARCH64_MOVW_SABS_G1:
+    checkInt(loc, val, 33, type);
+    LLVM_FALLTHROUGH;
+  case R_AARCH64_MOVW_PREL_G1_NC:
+    writeSMovWImm(loc, val >> 16);
+    break;
+  case R_AARCH64_MOVW_PREL_G2:
+  case R_AARCH64_MOVW_SABS_G2:
+    checkInt(loc, val, 49, type);
+    LLVM_FALLTHROUGH;
+  case R_AARCH64_MOVW_PREL_G2_NC:
+    writeSMovWImm(loc, val >> 32);
+    break;
+  case R_AARCH64_MOVW_PREL_G3:
+    writeSMovWImm(loc, val >> 48);
+    break;
   case R_AARCH64_TSTBR14:
     checkInt(loc, val, 16, type);
     or32le(loc, (val & 0xFFFC) << 3);
     break;
   case R_AARCH64_TLSLE_ADD_TPREL_HI12:
     checkUInt(loc, val, 24, type);
     or32AArch64Imm(loc, val >> 12);
     break;

lld/trunk/test/ELF/aarch64-movw-error.s

+# REQUIRES: aarch64
+# RUN: llvm-mc -filetype=obj -triple=aarch64-unknown-freebsd %s -o %t
+# RUN: echo '.globl zero; zero = 0' | llvm-mc -filetype=obj -triple=aarch64-unknown-freebsd -o %t2.o
+# RUN: not ld.lld %t %t2.o -o /dev/null 2>&1 | FileCheck %s
+
+# CHECK: relocation R_AARCH64_MOVW_UABS_G0 out of range: 65536 is not in [0, 65535]
+movn x0, #:abs_g0:zero+0x10000
+# CHECK: relocation R_AARCH64_MOVW_UABS_G1 out of range: 4294967296 is not in [0, 4294967295]
+movn x0, #:abs_g1:zero+0x100000000
+# CHECK: relocation R_AARCH64_MOVW_UABS_G2 out of range: 281474976710656 is not in [0, 281474976710655]
+movn x0, #:abs_g2:zero+0x1000000000000
+# CHECK: relocation R_AARCH64_MOVW_SABS_G0 out of range: 65536 is not in [-65536, 65535]
+movn x0, #:abs_g0_s:zero+0x10000
+# CHECK: relocation R_AARCH64_MOVW_SABS_G1 out of range: 4294967296 is not in [-4294967296, 4294967295]
+movn x0, #:abs_g1_s:zero+0x100000000
+# CHECK: relocation R_AARCH64_MOVW_SABS_G2 out of range: 281474976710656 is not in [-281474976710656, 281474976710655]
+movn x0, #:abs_g2_s:zero+0x1000000000000
+# CHECK: relocation R_AARCH64_MOVW_SABS_G0 out of range: -65537 is not in [-65536, 65535]
+movn x0, #:abs_g0_s:zero-0x10001
+# CHECK: relocation R_AARCH64_MOVW_SABS_G1 out of range: -4295032832 is not in [-4294967296, 4294967295]
+movn x0, #:abs_g1_s:zero-0x100010000
+# CHECK: relocation R_AARCH64_MOVW_SABS_G2 out of range: -281479271677952 is not in [-281474976710656, 281474976710655]
+movn x0, #:abs_g2_s:zero-0x1000100000000
+
+# CHECK: relocation R_AARCH64_MOVW_PREL_G0 out of range: 65536 is not in [-65536, 65535]
+movn x0, #:prel_g0:.+0x10000
+# CHECK: relocation R_AARCH64_MOVW_PREL_G1 out of range: 4294967296 is not in [-4294967296, 4294967295]
+movn x0, #:prel_g1:.+0x100000000
+# CHECK: relocation R_AARCH64_MOVW_PREL_G2 out of range: 281474976710656 is not in [-281474976710656, 281474976710655]
+movn x0, #:prel_g2:.+0x1000000000000
+# CHECK: relocation R_AARCH64_MOVW_PREL_G0 out of range: -65537 is not in [-65536, 65535]
+movn x0, #:prel_g0:.-0x10001
+# CHECK: relocation R_AARCH64_MOVW_PREL_G1 out of range: -4295032832 is not in [-4294967296, 4294967295]
+movn x0, #:prel_g1:.-0x100010000
+# CHECK: relocation R_AARCH64_MOVW_PREL_G2 out of range: -281479271677952 is not in [-281474976710656, 281474976710655]
+movn x0, #:prel_g2:.-0x1000100000000

lld/trunk/test/ELF/aarch64-relocs.s

 # CHECK-EMPTY:
 # CHECK-NEXT: ldst16:
 # CHECK-NEXT:   210054:       71 c2 40 7d     ldr     h17, [x19, #96]
 # CHECK-NEXT:   210058:       61 c2 40 79     ldrh    w1, [x19, #96]
 # CHECK-NEXT:   21005c:       62 c6 40 79     ldrh    w2, [x19, #98]
 
 .section .R_AARCH64_MOVW_UABS,"ax",@progbits
 movz1:
+   movk x12, #:abs_g0:zero+0xC
    movk x12, #:abs_g0_nc:zero+0xF000E000D000C
+   movk x13, #:abs_g1:zero+0xD000C
    movk x13, #:abs_g1_nc:zero+0xF000E000D000C
+   movk x14, #:abs_g2:zero+0xE000D000C
    movk x14, #:abs_g2_nc:zero+0xF000E000D000C
    movz x15, #:abs_g3:zero+0xF000E000D000C
    movk x16, #:abs_g3:zero+0xF000E000D000C
 
 ## 4222124650659840 == (0xF << 48)
 # CHECK: Disassembly of section .R_AARCH64_MOVW_UABS:
 # CHECK-EMPTY:
 # CHECK-NEXT: movz1:
 # CHECK-NEXT: 8c 01 80 f2   movk  x12, #12
+# CHECK-NEXT: 8c 01 80 f2   movk  x12, #12
+# CHECK-NEXT: ad 01 a0 f2   movk  x13, #13, lsl #16
 # CHECK-NEXT: ad 01 a0 f2   movk  x13, #13, lsl #16
 # CHECK-NEXT: ce 01 c0 f2   movk  x14, #14, lsl #32
+# CHECK-NEXT: ce 01 c0 f2   movk  x14, #14, lsl #32
 # CHECK-NEXT: ef 01 e0 d2   mov x15, #4222124650659840
 # CHECK-NEXT: f0 01 e0 f2   movk  x16, #15, lsl #48
+
+.section .R_AARCH64_MOVW_SABS,"ax",@progbits
+   movz x1, #:abs_g0_s:zero+1
+   movz x1, #:abs_g0_s:zero-1
+   movz x2, #:abs_g1_s:zero+0x20000
+   movz x2, #:abs_g1_s:zero-0x20000
+   movz x3, #:abs_g2_s:zero+0x300000000
+   movz x3, #:abs_g2_s:zero-0x300000000
+
+# CHECK: Disassembly of section .R_AARCH64_MOVW_SABS:
+# CHECK-EMPTY:
+# CHECK-NEXT: :
+# CHECK-NEXT: 21 00 80 d2   mov x1, #1
+# CHECK-NEXT: 01 00 80 92   mov x1, #-1
+# CHECK-NEXT: 42 00 a0 d2   mov x2, #131072
+## -65537 = 0xfffffffffffeffff
+# CHECK-NEXT: 22 00 a0 92   mov x2, #-65537
+## 12884901888 = 0x300000000
+# CHECK-NEXT: 63 00 c0 d2   mov x3, #12884901888
+## -8589934593 = #0xfffffffdffffffff
+# CHECK-NEXT: 43 00 c0 92   mov x3, #-8589934593
+
+.section .R_AARCH64_MOVW_PREL,"ax",@progbits
+   movz x1, #:prel_g0:.+1
+   movz x1, #:prel_g0_nc:.-1
+   movk x1, #:prel_g0:.+1
+   movk x1, #:prel_g0_nc:.-1
+   movz x2, #:prel_g1:.+0x20000
+   movz x2, #:prel_g1_nc:.-0x20000
+   movk x2, #:prel_g1:.+0x20000
+   movk x2, #:prel_g1_nc:.-0x20000
+   movz x3, #:prel_g2:.+0x300000000
+   movz x3, #:prel_g2_nc:.-0x300000000
+   movk x3, #:prel_g2:.+0x300000000
+   movk x3, #:prel_g2_nc:.-0x300000000
+   movz x3, #:prel_g2:.+0x300000000
+   movz x4, #:prel_g3:.+0x4000000000000
+   movz x4, #:prel_g3:.-0x4000000000000
+   movk x4, #:prel_g3:.+0x4000000000000
+   movk x4, #:prel_g3:.-0x4000000000000
+
+# CHECK: Disassembly of section .R_AARCH64_MOVW_PREL:
+# CHECK-EMPTY:
+# CHECK-NEXT: :
+# CHECK-NEXT: 21009c: 21 00 80 d2  mov  x1, #1
+# CHECK-NEXT: 2100a0: 01 00 80 92  mov  x1, #-1
+# CHECK-NEXT: 2100a4: 21 00 80 f2  movk x1, #1
+# CHECK-NEXT: 2100a8: e1 ff 9f f2  movk x1, #65535
+# CHECK-NEXT: 2100ac: 42 00 a0 d2  mov  x2, #131072
+## -65537 = 0xfffffffffffeffff
+# CHECK-NEXT: 2100b0: 22 00 a0 92  mov  x2, #-65537
+# CHECK-NEXT: 2100b4: 42 00 a0 f2  movk x2, #2, lsl #16
+# CHECK-NEXT: 2100b8: c2 ff bf f2  movk x2, #65534, lsl #16
+## 12884901888 = 0x300000000
+# CHECK-NEXT: 2100bc: 63 00 c0 d2  mov  x3, #12884901888
+## -8589934593 = #0xfffffffdffffffff
+# CHECK-NEXT: 2100c0: 43 00 c0 92  mov  x3, #-8589934593
+# CHECK-NEXT: 2100c4: 63 00 c0 f2  movk x3, #3, lsl #32
+# CHECK-NEXT: 2100c8: a3 ff df f2  movk x3, #65533, lsl #32
+# CHECK-NEXT: 2100cc: 63 00 c0 d2  mov  x3, #12884901888
+## 1125899906842624 = 0x4000000000000
+# CHECK-NEXT: 2100d0: 84 00 e0 d2  mov  x4, #1125899906842624
+# CHECK-NEXT: 2100d4: 84 ff ff d2  mov  x4, #-1125899906842624
+# CHECK-NEXT: 2100d8: 84 00 e0 f2  movk x4, #4, lsl #48
+# CHECK-NEXT: 2100dc: 84 ff ff f2  movk x4, #65532, lsl #48