Page MenuHomePhabricator

[ARM] Add support for the MVE long shift instructions

Authored by samtebbs on Jun 17 2019, 7:35 AM.



MVE adds the lsll, lsrl and asrl instructions, which perform a shift on a 64 bit value separated into two 32 bit registers.

The Expand64BitShift function is modified to accept ISD::SHL, ISD::SRL and ISD::SRA and convert it into the appropriate opcode in ARMISD. An SHL is converted into an lsll, an SRL is converted into an lsrl for the immediate form and a negation and lsll for the register form, and SRA is converted into an asrl.

test/CodeGen/ARM/shift_parts.ll is added to test the logic of emitting these instructions.

Diff Detail


Event Timeline

samtebbs created this revision.Jun 17 2019, 7:35 AM
samparker added inline comments.Jun 18 2019, 12:21 AM
5537 ↗(On Diff #205068)

Unnecessary opcode checks, the above assert is good enough.

5553 ↗(On Diff #205068)

This isn't immediately obvious to me why this is correct, so could you please expand in the comment?

181 ↗(On Diff #205068)

Why do we have Glue flags here?

samtebbs updated this revision to Diff 205294.Jun 18 2019, 3:35 AM
samtebbs marked 4 inline comments as done.
samtebbs added inline comments.Jun 20 2019, 2:06 AM
181 ↗(On Diff #205068)

They were copied from existing patterns but I've verified that they are unnecessary so will remove.

dmgreen added inline comments.Jun 20 2019, 3:32 AM
5553 ↗(On Diff #205068)

Maybe be explicit that there isn't a t2LSRLr instruction, which is why the negative t2LSLLr is needed.

168 ↗(On Diff #205294)

You can remove this comment.

samtebbs updated this revision to Diff 205803.Jun 20 2019, 6:58 AM
samtebbs marked an inline comment as done.
samtebbs updated this revision to Diff 205807.Jun 20 2019, 7:07 AM
samtebbs marked an inline comment as done.
This revision is now accepted and ready to land.Jun 24 2019, 2:34 AM
This revision was automatically updated to reflect the committed changes.