[GlobalISel] IRTranslator: Translate the intrinsics ignored by CodeGen

[volkan]

Summary

Translate llvm.assume, llvm.var.annotation and llvm.sideeffect to nothing
as they have no effect on CodeGen.

[arsenm]

LGTM

[arsenm]

lib/CodeGen/GlobalISel/IRTranslator.cpp

1109–1114

Might as well just merge these cases

[volkan]

Merged the switch cases.

lib/CodeGen/GlobalISel/IRTranslator.cpp

case Intrinsic::ctlz: {
     return true;
   }
   case Intrinsic::invariant_start: {
     LLT PtrTy = getLLTForType(*CI.getArgOperand(0)->getType(), *DL);
     unsigned Undef = MRI->createGenericVirtualRegister(PtrTy);
     MIRBuilder.buildUndef(Undef);
     return true;
   }
   case Intrinsic::invariant_end:
+  case Intrinsic::assume:
+  case Intrinsic::var_annotation:
+  case Intrinsic::sideeffect:
+    // Discard annotate attributes, assumptions, and artificial side-effects.
     return true;
   }
   return false;
 }
 
 bool IRTranslator::translateInlineAsm(const CallInst &CI,
                                       MachineIRBuilder &MIRBuilder) {
   const InlineAsm &IA = cast<InlineAsm>(*CI.getCalledValue());
   if (!IA.getConstraintString().empty())

test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

 
 declare float @llvm.rint.f32(float)
 define float @test_rint_f32(float %x) {
   ; CHECK-LABEL: name:            test_rint_f32
   ; CHECK: %{{[0-9]+}}:_(s32) = G_FRINT %{{[0-9]+}}
   %y = call float @llvm.rint.f32(float %x)
   ret float %y
 }
+
+declare void @llvm.assume(i1)
+define void @test_assume(i1 %x) {
+  ; CHECK-LABEL: name:            test_assume
+  ; CHECK-NOT: llvm.assume
+  ; CHECK: RET_ReallyLR
+  call void @llvm.assume(i1 %x)
+  ret void
+}
+
+declare void @llvm.sideeffect()
+define void @test_sideeffect() {
+  ; CHECK-LABEL: name:            test_sideeffect
+  ; CHECK-NOT: llvm.sideeffect
+  ; CHECK: RET_ReallyLR
+  call void @llvm.sideeffect()
+  ret void
+}
+
+declare void @llvm.var.annotation(i8*, i8*, i8*, i32)
+define void @test_var_annotation(i8*, i8*, i8*, i32) {
+  ; CHECK-LABEL: name:            test_var_annotation
+  ; CHECK-NOT: llvm.var.annotation
+  ; CHECK: RET_ReallyLR
+  call void @llvm.var.annotation(i8* %0, i8* %1, i8* %2, i32 %3)
+  ret void
+}