[AsmPrinter] refactor to support %c w/ GlobalAddress'

[nickdesaulniers]

Summary

Targets like ARM, MSP430, PPC, and SystemZ have complex behavior when
printing the address of a MachineOperand::MO_GlobalAddress. Move that
handling into a new overriden method in each base class. A virtual
method was added to the base class for handling the generic case.

Refactors a few subclasses to support the target independent %a, %c, and
%n.

The patch also contains small cleanups for AVRAsmPrinter and
SystemZAsmPrinter.

It seems that NVPTXTargetLowering is possibly missing some logic to
transform GlobalAddressSDNodes for
TargetLowering::LowerAsmOperandForConstraint to handle with "i" extended
inline assembly asm constraints.

Fixes:

• https://bugs.llvm.org/show_bug.cgi?id=41402
• https://github.com/ClangBuiltLinux/linux/issues/449

[nickdesaulniers]

When I added test cases for RISCV and AVR, I got the following error message from llvm-lit that I don't understand:

UNSUPPORTED: LLVM :: CodeGen/RISCV/inlineasm-output-template.ll (1 of 1)
UNSUPPORTED: LLVM :: CodeGen/AVR/inlineasm-output-template.ll (1 of 1)

I'm not setting -DLLVM_TARGETS_TO_BUILD cmake variable, so I guess these backends are defaulted off or something?

llvm/test/CodeGen/NVPTX/inlineasm-output-template.ll

12 ↗

(On Diff #195809)

I'm not particularly happy about this, but didn't have enough background with SelectionDAG to quickly understand the issue. Please let me know if I should drop this added but commented out test case from this patch.

[nickdesaulniers]

so I guess these backends are defaulted off or something?

@srhines identified that AVR and RISCV are not in LLVM_ALL_TARGETS in llvm/CMakeLists.txt. Should I send a patch to turn them on? (assuming the tests aren't red).

[peter.smith]

In D60887#1472308, @nickdesaulniers wrote:

so I guess these backends are defaulted off or something?

@srhines identified that AVR and RISCV are not in LLVM_ALL_TARGETS in llvm/CMakeLists.txt. Should I send a patch to turn them on? (assuming the tests aren't red).

I think the AVR and RISCV backends are, or at least were, in "experimental" state so weren't included in LLVM_ALL_TARGETS. I thought that RISCV at least had been promoted out of experimental but I guess the backend owner (ASB I think) hasn't done that yet.

I've checked the patch and it looks good from the Arm/AArch64 perspective. Only thing I spotted was a change to the MSP340 that I didn't understand, but that could be intentional.

llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp

101 ↗

(On Diff #195809)

This looks to have taken out the case when isMemOp is true (the removed code could output &). I don't know enough about MSP430 to know whether this is the right thing to do though.

[nickdesaulniers]

llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp

101 ↗

(On Diff #195809)

The conditional in the initialization of isMemOp and the condition I removed here are quite tricky and require careful attention.

The unconditional printing of '#' comes from the observation in the previous version of the code that:

1. there is no such modifier "mem" ever
2. thus strcmp will always be non-zero
3. thus !strcmp will always be 0
4. thus Modifier && !strcmp will always be false
5. thus isMemOp will always be false
6. thus (isMemOp ? '&' : '#') will always evaluate to '#'

The next transform is based on the above AND the observations:

1. the only modifier is "nohash"
2. thus if there is no Modifier, print '#'
3. or if the only possible modifier is the only possible value, print '#'
4. thus what we have is an unconditional print of '#'

But I will admit this was tricky when first looking at it and would appreciate you triple checking as I may have made a mistake in the above logic. It's definitely the most curious part of this patch for sure. Also, sorry if I misunderstood your point. Thanks for your review!

[nickdesaulniers]

llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp

101 ↗

(On Diff #195809)

Also, I had previously tackled this in https://reviews.llvm.org/D60738, but abandoned it when I started the overall fix, as I needed it one way or another. Happy to revive that there, land it first, then rebase this if you prefer?

[peter.smith]

llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp

96 ↗

(On Diff #195809)

This comment looks to be out of date as & will never be printed.

101 ↗

(On Diff #195809)

I agree with the first part about "mem". I'm not sure about the second as it is strcmp and not !strcmp. With printOperand(MI, OpNum+1, O, "nohash"); we would have
Modifier = "nohash".
In this case

if (!Modifier || strcmp(Modifier, "nohash"))
  O << (isMemOp ? '&' : '#');

Would end up with the condition failing as strcmp("nohash", "nohash") == 0 and !Modifier also being false so we would not output a '#' in this case. So I think it should be:

if (!Modifier || strcmp(Modifier, "nohash"))
      O << '#';

As in line 86.

Hope I have that right, it has been a long time since I've read strcmp/!strcmp.

Also, I had previously tackled this in https://reviews.llvm.org/D60738, but abandoned it when I started the overall fix, as I needed it one way or another. Happy to revive that there, land it first, then rebase this if you prefer?

I don't have a strong preference. This was the only part of the patch that I saw that made significant changes that I didn't know where they came from so it looked like it could have been an oversight.

[nickdesaulniers]

• - fix MSP430AsmPrinter '#', adjust comment

[nickdesaulniers]

llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp

101 ↗

(On Diff #195809)

Great catch!

[void]

This looks like a nice cleanup. Accepting unless Peter has any objections.

[peter.smith]

In D60887#1479269, @void wrote:

This looks like a nice cleanup. Accepting unless Peter has any objections.

I don't have any objections.

llvm/trunk/include/llvm/CodeGen/AsmPrinter.h

public:
   /// independent of the operand, and may be independent of the instr itself.
   /// This can be useful for portably encoding the comment character or other
   /// bits of target-specific knowledge into the asmstrings.  The syntax used is
   /// ${:comment}.  Targets can override this to add support for their own
   /// strange codes.
   virtual void PrintSpecial(const MachineInstr *MI, raw_ostream &OS,
                             const char *Code) const;
 
+  /// Print the MachineOperand as a symbol. Targets with complex handling of
+  /// symbol references should override the base implementation.
+  virtual void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &OS);
+
   /// Print the specified operand of MI, an INLINEASM instruction, using the
   /// specified assembler variant.  Targets should override this to format as
   /// appropriate.  This method can return true if the operand is erroneous.
   virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                const char *ExtraCode, raw_ostream &OS);
 
   /// Print the specified operand of MI, an INLINEASM instruction, using the
   /// specified assembler variant as an address. Targets should override this to

llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp

if (!strcmp(Code, "private")) {
     std::string msg;
     raw_string_ostream Msg(msg);
     Msg << "Unknown special formatter '" << Code
          << "' for machine instr: " << *MI;
     report_fatal_error(Msg.str());
   }
 }
 
+void AsmPrinter::PrintSymbolOperand(const MachineOperand &MO, raw_ostream &OS) {
+  assert(MO.isGlobal() && "caller should check MO.isGlobal");
+  getSymbol(MO.getGlobal())->print(OS, MAI);
+  printOffset(MO.getOffset(), OS);
+}
+
 /// PrintAsmOperand - Print the specified operand of MI, an INLINEASM
 /// instruction, using the specified assembler variant.  Targets should
 /// override this to format as appropriate for machine specific ExtraCodes
 /// or when the arch-independent handling would be too complex otherwise.
 bool AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                  const char *ExtraCode, raw_ostream &O) {
   // Does this asm operand have a single letter operand modifier?
   if (ExtraCode && ExtraCode[0]) {
     if (ExtraCode[1] != 0) return true; // Unknown modifier.
 
     // https://gcc.gnu.org/onlinedocs/gccint/Output-Template.html
     const MachineOperand &MO = MI->getOperand(OpNo);
     switch (ExtraCode[0]) {
     default:
       return true;  // Unknown modifier.
     case 'a': // Print as memory address.
       if (MO.isReg()) {
         PrintAsmMemoryOperand(MI, OpNo, nullptr, O);
         return false;
       }
       LLVM_FALLTHROUGH; // GCC allows '%a' to behave like '%c' with immediates.
     case 'c': // Substitute immediate value without immediate syntax
-      if (!MO.isImm())
-        return true;
+      if (MO.isImm()) {
         O << MO.getImm();
         return false;
+      }
+      if (MO.isGlobal()) {
+        PrintSymbolOperand(MO, O);
+        return false;
+      }
+      return true;
     case 'n':  // Negate the immediate constant.
       if (!MO.isImm())
         return true;
       O << -MO.getImm();
       return false;
     case 's':  // The GCC deprecated s modifier
       if (!MO.isImm())
         return true;

llvm/trunk/lib/Target/AArch64/AArch64AsmPrinter.cpp

case MachineOperand::MO_Register: {
     break;
   }
   case MachineOperand::MO_Immediate: {
     int64_t Imm = MO.getImm();
     O << '#' << Imm;
     break;
   }
   case MachineOperand::MO_GlobalAddress: {
-    const GlobalValue *GV = MO.getGlobal();
-    MCSymbol *Sym = getSymbol(GV);
-
-    // FIXME: Can we get anything other than a plain symbol here?
-    assert(!MO.getTargetFlags() && "Unknown operand target flag!");
-
-    Sym->print(O, MAI);
-    printOffset(MO.getOffset(), O);
+    PrintSymbolOperand(MO, O);
     break;
   }
   case MachineOperand::MO_BlockAddress: {
     MCSymbol *Sym = GetBlockAddressSymbol(MO.getBlockAddress());
     Sym->print(O, MAI);
     break;
   }
   }

llvm/trunk/lib/Target/ARM/ARMAsmPrinter.h

explicit ARMAsmPrinter(TargetMachine &TM,
                          std::unique_ptr<MCStreamer> Streamer);
 
   StringRef getPassName() const override {
     return "ARM Assembly Printer";
   }
 
   void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O);
 
+  void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override;
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
                        const char *ExtraCode, raw_ostream &O) override;
   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
                              const char *ExtraCode, raw_ostream &O) override;
 
   void emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
                         const MCSubtargetInfo *EndInfo) const override;
 

llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp

if (! ThumbIndirectPads.empty()) {
     }
     ThumbIndirectPads.clear();
   }
 
   // We didn't modify anything.
   return false;
 }
 
+void ARMAsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
+                                       raw_ostream &O) {
+  assert(MO.isGlobal() && "caller should check MO.isGlobal");
+  unsigned TF = MO.getTargetFlags();
+  if (TF & ARMII::MO_LO16)
+    O << ":lower16:";
+  else if (TF & ARMII::MO_HI16)
+    O << ":upper16:";
+  GetARMGVSymbol(MO.getGlobal(), TF)->print(O, MAI);
+  printOffset(MO.getOffset(), O);
+}
+
 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
                                  raw_ostream &O) {
   const MachineOperand &MO = MI->getOperand(OpNum);
-  unsigned TF = MO.getTargetFlags();
 
   switch (MO.getType()) {
   default: llvm_unreachable("<unknown operand type>");
   case MachineOperand::MO_Register: {
     unsigned Reg = MO.getReg();
     assert(TargetRegisterInfo::isPhysicalRegister(Reg));
     assert(!MO.getSubReg() && "Subregs should be eliminated!");
     if(ARM::GPRPairRegClass.contains(Reg)) {
       const MachineFunction &MF = *MI->getParent()->getParent();
       const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
       Reg = TRI->getSubReg(Reg, ARM::gsub_0);
     }
     O << ARMInstPrinter::getRegisterName(Reg);
     break;
   }
   case MachineOperand::MO_Immediate: {
-    int64_t Imm = MO.getImm();
     O << '#';
+    unsigned TF = MO.getTargetFlags();
     if (TF == ARMII::MO_LO16)
       O << ":lower16:";
     else if (TF == ARMII::MO_HI16)
       O << ":upper16:";
-    O << Imm;
+    O << MO.getImm();
     break;
   }
   case MachineOperand::MO_MachineBasicBlock:
     MO.getMBB()->getSymbol()->print(O, MAI);
     return;
   case MachineOperand::MO_GlobalAddress: {
-    const GlobalValue *GV = MO.getGlobal();
-    if (TF & ARMII::MO_LO16)
-      O << ":lower16:";
-    else if (TF & ARMII::MO_HI16)
-      O << ":upper16:";
-    GetARMGVSymbol(GV, TF)->print(O, MAI);
-
-    printOffset(MO.getOffset(), O);
+    PrintSymbolOperand(MO, O);
     break;
   }
   case MachineOperand::MO_ConstantPoolIndex:
     if (Subtarget->genExecuteOnly())
       llvm_unreachable("execute-only should not generate constant pools");
     GetCPISymbol(MO.getIndex())->print(O, MAI);
     break;
   }

llvm/trunk/lib/Target/AVR/AVRAsmPrinter.cpp

 class AVRAsmPrinter : public AsmPrinter {
 public:
   AVRAsmPrinter(TargetMachine &TM,
                 std::unique_ptr<MCStreamer> Streamer)
       : AsmPrinter(TM, std::move(Streamer)), MRI(*TM.getMCRegisterInfo()) { }
 
   StringRef getPassName() const override { return "AVR Assembly Printer"; }
 
-  void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O,
-                    const char *Modifier = 0);
+  void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
 
   bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
                        const char *ExtraCode, raw_ostream &O) override;
 
   bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
                              const char *ExtraCode, raw_ostream &O) override;
 
   void EmitInstruction(const MachineInstr *MI) override;
 
 private:
   const MCRegisterInfo &MRI;
 };
 
 void AVRAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
-                                 raw_ostream &O, const char *Modifier) {
+                                 raw_ostream &O) {
   const MachineOperand &MO = MI->getOperand(OpNo);
 
   switch (MO.getType()) {
   case MachineOperand::MO_Register:
     O << AVRInstPrinter::getPrettyRegisterName(MO.getReg(), MRI);
     break;
   case MachineOperand::MO_Immediate:
     O << MO.getImm();

llvm/trunk/lib/Target/BPF/BPFAsmPrinter.cpp

void BPFAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
   default:
     llvm_unreachable("<unknown operand type>");
   }
 }
 
 bool BPFAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                     const char *ExtraCode, raw_ostream &O) {
   if (ExtraCode && ExtraCode[0])
-    return true; // BPF does not have special modifiers
+    return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O);
 
   printOperand(MI, OpNo, O);
   return false;
 }
 
 bool BPFAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
                                           unsigned OpNum, const char *ExtraCode,
                                           raw_ostream &O) {

llvm/trunk/lib/Target/Hexagon/HexagonAsmPrinter.cpp

case MachineOperand::MO_Immediate:
     return;
   case MachineOperand::MO_MachineBasicBlock:
     MO.getMBB()->getSymbol()->print(O, MAI);
     return;
   case MachineOperand::MO_ConstantPoolIndex:
     GetCPISymbol(MO.getIndex())->print(O, MAI);
     return;
   case MachineOperand::MO_GlobalAddress:
-    // Computing the address of a global symbol, not calling it.
-    getSymbol(MO.getGlobal())->print(O, MAI);
-    printOffset(MO.getOffset(), O);
+    PrintSymbolOperand(MO, O);
     return;
   }
 }
 
 // isBlockOnlyReachableByFallthrough - We need to override this since the
 // default AsmPrinter does not print labels for any basic block that
 // is only reachable by a fall through. That works for all cases except
 // for the case in which the basic block is reachable by a fall through but

llvm/trunk/lib/Target/Lanai/LanaiAsmPrinter.cpp

case 'H': {
       const MachineOperand &MO = MI->getOperand(RegOp);
       if (!MO.isReg())
         return true;
       unsigned Reg = MO.getReg();
       O << LanaiInstPrinter::getRegisterName(Reg);
       return false;
     }
     default:
-      return true; // Unknown modifier.
+      return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O);
     }
   }
   printOperand(MI, OpNo, O);
   return false;
 }
 
 //===----------------------------------------------------------------------===//
 void LanaiAsmPrinter::emitCallInstruction(const MachineInstr *MI) {

llvm/trunk/lib/Target/MSP430/MSP430AsmPrinter.cpp

namespace {
   public:
     MSP430AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
         : AsmPrinter(TM, std::move(Streamer)) {}
 
     StringRef getPassName() const override { return "MSP430 Assembly Printer"; }
 
     bool runOnMachineFunction(MachineFunction &MF) override;
 
+    void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override;
     void printOperand(const MachineInstr *MI, int OpNum,
                       raw_ostream &O, const char* Modifier = nullptr);
     void printSrcMemOperand(const MachineInstr *MI, int OpNum,
                             raw_ostream &O);
     bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                          const char *ExtraCode, raw_ostream &O) override;
     bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
                                const char *ExtraCode, raw_ostream &O) override;
     void EmitInstruction(const MachineInstr *MI) override;
 
     void EmitInterruptVectorSection(MachineFunction &ISR);
   };
 } // end of anonymous namespace
 
+void MSP430AsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
+                                          raw_ostream &O) {
+  uint64_t Offset = MO.getOffset();
+  if (Offset)
+    O << '(' << Offset << '+';
+
+  getSymbol(MO.getGlobal())->print(O, MAI);
+
+  if (Offset)
+    O << ')';
+}
 
 void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
                                     raw_ostream &O, const char *Modifier) {
   const MachineOperand &MO = MI->getOperand(OpNum);
   switch (MO.getType()) {
   default: llvm_unreachable("Not implemented yet!");
   case MachineOperand::MO_Register:
     O << MSP430InstPrinter::getRegisterName(MO.getReg());
     return;
   case MachineOperand::MO_Immediate:
     if (!Modifier || strcmp(Modifier, "nohash"))
       O << '#';
     O << MO.getImm();
     return;
   case MachineOperand::MO_MachineBasicBlock:
     MO.getMBB()->getSymbol()->print(O, MAI);
     return;
   case MachineOperand::MO_GlobalAddress: {
-    bool isMemOp  = Modifier && !strcmp(Modifier, "mem");
-    uint64_t Offset = MO.getOffset();
-
     // If the global address expression is a part of displacement field with a
     // register base, we should not emit any prefix symbol here, e.g.
-    //   mov.w &foo, r1
-    // vs
     //   mov.w glb(r1), r2
     // Otherwise (!) msp430-as will silently miscompile the output :(
     if (!Modifier || strcmp(Modifier, "nohash"))
-      O << (isMemOp ? '&' : '#');
-    if (Offset)
-      O << '(' << Offset << '+';
-
-    getSymbol(MO.getGlobal())->print(O, MAI);
-
-    if (Offset)
-      O << ')';
-
+      O << '#';
+    PrintSymbolOperand(MO, O);
     return;
   }
   }
 }
 
 void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum,
                                           raw_ostream &O) {
   const MachineOperand &Base = MI->getOperand(OpNum);

 }
 
 /// PrintAsmOperand - Print out an operand for an inline asm expression.
 ///
 bool MSP430AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                        const char *ExtraCode, raw_ostream &O) {
   // Does this asm operand have a single letter operand modifier?
   if (ExtraCode && ExtraCode[0])
-    return true; // Unknown modifier.
+    return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, O);
 
   printOperand(MI, OpNo, O);
   return false;
 }
 
 bool MSP430AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
                                              unsigned OpNo,
                                              const char *ExtraCode,

llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp

case MachineOperand::MO_Immediate:
       O << MO.getImm();
       break;
 
     case MachineOperand::MO_MachineBasicBlock:
       MO.getMBB()->getSymbol()->print(O, MAI);
       return;
 
     case MachineOperand::MO_GlobalAddress:
-      getSymbol(MO.getGlobal())->print(O, MAI);
+      PrintSymbolOperand(MO, O);
       break;
 
     case MachineOperand::MO_BlockAddress: {
       MCSymbol *BA = GetBlockAddressSymbol(MO.getBlockAddress());
       O << BA->getName();
       break;
     }
 

llvm/trunk/lib/Target/NVPTX/NVPTXAsmPrinter.cpp

case MachineOperand::MO_Immediate:
     O << MO.getImm();
     break;
 
   case MachineOperand::MO_FPImmediate:
     printFPConstant(MO.getFPImm(), O);
     break;
 
   case MachineOperand::MO_GlobalAddress:
-    getSymbol(MO.getGlobal())->print(O, MAI);
+    PrintSymbolOperand(MO, O);
     break;
 
   case MachineOperand::MO_MachineBasicBlock:
     MO.getMBB()->getSymbol()->print(O, MAI);
     break;
 
   default:
     llvm_unreachable("Operand type not supported.");

llvm/trunk/lib/Target/PowerPC/PPCAsmPrinter.cpp

bool doInitialization(Module &M) override {
 
     void EmitInstruction(const MachineInstr *MI) override;
 
     /// This function is for PrintAsmOperand and PrintAsmMemoryOperand,
     /// invoked by EmitMSInlineAsmStr and EmitGCCInlineAsmStr only.
     /// The \p MI would be INLINEASM ONLY.
     void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
 
+    void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override;
     bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                          const char *ExtraCode, raw_ostream &O) override;
     bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
                                const char *ExtraCode, raw_ostream &O) override;
 
     void EmitEndOfAsmFile(Module &M) override;
 
     void LowerSTACKMAP(StackMaps &SM, const MachineInstr &MI);
public:
     }
 
     bool doFinalization(Module &M) override;
     void EmitStartOfAsmFile(Module &M) override;
   };
 
 } // end anonymous namespace
 
+void PPCAsmPrinter::PrintSymbolOperand(const MachineOperand &MO,
+                                       raw_ostream &O) {
+  // Computing the address of a global symbol, not calling it.
+  const GlobalValue *GV = MO.getGlobal();
+  MCSymbol *SymToPrint;
+
+  // External or weakly linked global variables need non-lazily-resolved stubs
+  if (Subtarget->hasLazyResolverStub(GV)) {
+    SymToPrint = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
+    MachineModuleInfoImpl::StubValueTy &StubSym =
+        MMI->getObjFileInfo<MachineModuleInfoMachO>().getGVStubEntry(
+            SymToPrint);
+    if (!StubSym.getPointer())
+      StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
+                                                   !GV->hasInternalLinkage());
+  } else {
+    SymToPrint = getSymbol(GV);
+  }
+
+  SymToPrint->print(O, MAI);
+
+  printOffset(MO.getOffset(), O);
+}
+
 void PPCAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
                                  raw_ostream &O) {
   const DataLayout &DL = getDataLayout();
   const MachineOperand &MO = MI->getOperand(OpNo);
 
   switch (MO.getType()) {
   case MachineOperand::MO_Register: {
     // The MI is INLINEASM ONLY and UseVSXReg is always false.
void PPCAsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNo,
   case MachineOperand::MO_ConstantPoolIndex:
     O << DL.getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << '_'
       << MO.getIndex();
     return;
   case MachineOperand::MO_BlockAddress:
     GetBlockAddressSymbol(MO.getBlockAddress())->print(O, MAI);
     return;
   case MachineOperand::MO_GlobalAddress: {
-    // Computing the address of a global symbol, not calling it.
-    const GlobalValue *GV = MO.getGlobal();
-    MCSymbol *SymToPrint;
-
-    // External or weakly linked global variables need non-lazily-resolved stubs
-    if (Subtarget->hasLazyResolverStub(GV)) {
-      SymToPrint = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
-      MachineModuleInfoImpl::StubValueTy &StubSym =
-          MMI->getObjFileInfo<MachineModuleInfoMachO>().getGVStubEntry(
-              SymToPrint);
-      if (!StubSym.getPointer())
-        StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
-                                                     !GV->hasInternalLinkage());
-    } else {
-      SymToPrint = getSymbol(GV);
-    }
-
-    SymToPrint->print(O, MAI);
-
-    printOffset(MO.getOffset(), O);
+    PrintSymbolOperand(MO, O);
     return;
   }
 
   default:
     O << "<unknown operand type: " << (unsigned)MO.getType() << ">";
     return;
   }
 }

llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp

#endif
 
   case MachineOperand::MO_Immediate:
     O << (int)MO.getImm();
     break;
   case MachineOperand::MO_MachineBasicBlock:
     MO.getMBB()->getSymbol()->print(O, MAI);
     return;
   case MachineOperand::MO_GlobalAddress:
-    getSymbol(MO.getGlobal())->print(O, MAI);
+    PrintSymbolOperand(MO, O);
     break;
   case MachineOperand::MO_BlockAddress:
     O <<  GetBlockAddressSymbol(MO.getBlockAddress())->getName();
     break;
   case MachineOperand::MO_ExternalSymbol:
     O << MO.getSymbolName();
     break;
   case MachineOperand::MO_ConstantPoolIndex:

llvm/trunk/lib/Target/SystemZ/SystemZAsmPrinter.cpp

EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
   uint64_t Size = getDataLayout().getTypeAllocSize(ZCPV->getType());
 
   OutStreamer->EmitValue(Expr, Size);
 }
 
 bool SystemZAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                                         const char *ExtraCode,
                                         raw_ostream &OS) {
-  if (ExtraCode && *ExtraCode == 'n') {
-    if (!MI->getOperand(OpNo).isImm())
-      return true;
-    OS << -int64_t(MI->getOperand(OpNo).getImm());
-  } else {
-    SystemZMCInstLower Lower(MF->getContext(), *this);
-    MCOperand MO(Lower.lowerOperand(MI->getOperand(OpNo)));
-    SystemZInstPrinter::printOperand(MO, MAI, OS);
-  }
+  if (ExtraCode)
+    return AsmPrinter::PrintAsmOperand(MI, OpNo, ExtraCode, OS);
   return false;
 }
 
 bool SystemZAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
                                               unsigned OpNo,
                                               const char *ExtraCode,
                                               raw_ostream &OS) {
   SystemZInstPrinter::printAddress(MI->getOperand(OpNo).getReg(),

llvm/trunk/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp

case MachineOperand::MO_Immediate:
       return false;
     case MachineOperand::MO_Register:
       // FIXME: only opcode that still contains registers, as required by
       // MachineInstr::getDebugVariable().
       assert(MI->getOpcode() == WebAssembly::INLINEASM);
       OS << regToString(MO);
       return false;
     case MachineOperand::MO_GlobalAddress:
-      getSymbol(MO.getGlobal())->print(OS, MAI);
-      printOffset(MO.getOffset(), OS);
+      PrintSymbolOperand(MO, OS);
       return false;
     case MachineOperand::MO_ExternalSymbol:
       GetExternalSymbolSymbol(MO.getSymbolName())->print(OS, MAI);
       printOffset(MO.getOffset(), OS);
       return false;
     case MachineOperand::MO_MachineBasicBlock:
       MO.getMBB()->getSymbol()->print(OS, MAI);
       return false;

llvm/trunk/lib/Target/X86/X86AsmPrinter.h

class LLVM_LIBRARY_VISIBILITY X86AsmPrinter : public AsmPrinter {
   void LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI,
                                        X86MCInstLower &MCIL);
 
   void LowerFENTRY_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
 
   // Choose between emitting .seh_ directives and .cv_fpo_ directives.
   void EmitSEHInstruction(const MachineInstr *MI);
 
-  void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O);
+  void PrintSymbolOperand(const MachineOperand &MO, raw_ostream &O) override;
   void PrintOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
   void PrintModifiedOperand(const MachineInstr *MI, unsigned OpNo,
                             raw_ostream &O, const char *Modifier);
   void PrintPCRelImm(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
   void PrintLeaMemReference(const MachineInstr *MI, unsigned OpNo,
                             raw_ostream &O, const char *Modifier);
   void PrintMemReference(const MachineInstr *MI, unsigned OpNo, raw_ostream &O,
                          const char *Modifier);

llvm/trunk/lib/Target/X86/X86AsmPrinter.cpp

case MachineOperand::MO_Immediate: {
     int DispVal = DispSpec.getImm();
     if (DispVal || !HasParenPart)
       O << DispVal;
     break;
   }
   case MachineOperand::MO_GlobalAddress:
   case MachineOperand::MO_ConstantPoolIndex:
     PrintSymbolOperand(DispSpec, O);
+    break;
   }
 
   if (Modifier && strcmp(Modifier, "H") == 0)
     O << "+8";
 
   if (HasParenPart) {
     assert(IndexReg.getReg() != X86::ESP &&
            "X86 doesn't allow scaling by ESP");

llvm/trunk/lib/Target/XCore/XCoreAsmPrinter.cpp

case MachineOperand::MO_Register:
     break;
   case MachineOperand::MO_Immediate:
     O << MO.getImm();
     break;
   case MachineOperand::MO_MachineBasicBlock:
     MO.getMBB()->getSymbol()->print(O, MAI);
     break;
   case MachineOperand::MO_GlobalAddress:
-    getSymbol(MO.getGlobal())->print(O, MAI);
+    PrintSymbolOperand(MO, O);
     break;
   case MachineOperand::MO_ConstantPoolIndex:
     O << DL.getPrivateGlobalPrefix() << "CPI" << getFunctionNumber() << '_'
       << MO.getIndex();
     break;
   case MachineOperand::MO_BlockAddress:
     GetBlockAddressSymbol(MO.getBlockAddress())->print(O, MAI);
     break;

llvm/trunk/test/CodeGen/AArch64/inlineasm-output-template.ll

+; RUN: llc -mtriple=aarch64-linux-gnu < %s | FileCheck %s
+
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+  tail call void asm sideeffect "//TEST ${0:c}", "i"(i32 42)
+  ret i32 42
+}
+
+; Test that %c works with global address
+; CHECK-LABEL: test_inlineasm_c_output_template1:
+; CHECK: TEST {{_?}}baz
+@baz = internal global i32 0, align 4
+define dso_local i32 @test_inlineasm_c_output_template1() {
+  tail call void asm sideeffect "//TEST ${0:c}", "i"(i32* nonnull @baz)
+  ret i32 43
+}
+
+; Test that %n works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template2
+; CHECK: TEST -42
+define dso_local i32 @test_inlineasm_c_output_template2() {
+  tail call void asm sideeffect "//TEST ${0:n}", "i"(i32 42)
+  ret i32 42
+}

llvm/trunk/test/CodeGen/ARM/inlineasm-output-template.ll

 ; RUN: llc -mtriple=armv7-linux-gnueabi < %s | FileCheck %s
 
 ; Test that %c works with immediates
 ; CHECK-LABEL: test_inlineasm_c_output_template0
 ; CHECK: @TEST 42
 define dso_local i32 @test_inlineasm_c_output_template0() {
   tail call void asm sideeffect "@TEST ${0:c}", "i"(i32 42)
   ret i32 42
 }
 
+; Test that %c works with global address
+; CHECK-LABEL: test_inlineasm_c_output_template2
+; CHECK: @TEST baz
+@baz = internal global i32 0, align 4
+define dso_local i32 @test_inlineasm_c_output_template2() {
+  tail call void asm sideeffect "@TEST ${0:c}", "i"(i32* nonnull @baz)
+  ret i32 42
+}
+
 ; Test that %n works with immediates
 ; CHECK-LABEL: test_inlineasm_c_output_template1
 ; CHECK: @TEST -42
 define dso_local i32 @test_inlineasm_c_output_template1() {
   tail call void asm sideeffect "@TEST ${0:n}", "i"(i32 42)
   ret i32 42
 }

llvm/trunk/test/CodeGen/BPF/inlineasm-output-template.ll

+; RUN: llc -mtriple=bpfel-linux-gnu < %s | FileCheck %s
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: #TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+  tail call void asm sideeffect "#TEST ${0:c}", "i"(i32 42)
+  ret i32 42
+}
+
+; Test that %c works with global address
+; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK: #TEST baz
+@baz = internal global i32 0, align 4
+define dso_local i32 @test_inlineasm_c_output_template1() {
+  tail call void asm sideeffect "#TEST ${0:c}", "i"(i32* nonnull @baz)
+  ret i32 42
+}
+
+; Test that %n works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template2
+; CHECK: #TEST -42
+define dso_local i32 @test_inlineasm_c_output_template2() {
+  tail call void asm sideeffect "#TEST ${0:n}", "i"(i32 42)
+  ret i32 42
+}

llvm/trunk/test/CodeGen/Hexagon/inlineasm-output-template.ll

 ; RUN: llc -mtriple=hexagon < %s | FileCheck %s
 
 ; Test that %c works with immediates
 ; CHECK-LABEL: test_inlineasm_c_output_template0
 ; CHECK: //TEST 42
 define dso_local i32 @test_inlineasm_c_output_template0() {
   tail call void asm sideeffect "//TEST ${0:c}", "i"(i32 42)
   ret i32 42
 }
 
+; Test that %c works with global address
+; CHECK-LABEL: test_inlineasm_c_output_template1:
+; CHECK: TEST {{_?}}baz
+@baz = internal global i32 0, align 4
+define dso_local i32 @test_inlineasm_c_output_template1() {
+  tail call void asm sideeffect "//TEST ${0:c}", "i"(i32* nonnull @baz)
+  ret i32 43
+}
+
 ; Test that %n works with immediates
-; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK-LABEL: test_inlineasm_c_output_template2
 ; CHECK: //TEST -42
-define dso_local i32 @test_inlineasm_c_output_template1() {
+define dso_local i32 @test_inlineasm_c_output_template2() {
   tail call void asm sideeffect "//TEST ${0:n}", "i"(i32 42)
   ret i32 42
 }

llvm/trunk/test/CodeGen/Lanai/inlineasm-output-template.ll

+; RUN: llc -mtriple=lanai-linux-gnueabi < %s | FileCheck %s
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: !TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+  tail call void asm sideeffect "!TEST ${0:c}", "i"(i32 42)
+  ret i32 42
+}
+
+; Test that %c works with global address
+; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK: !TEST baz
+@baz = internal global i32 0, align 4
+define dso_local i32 @test_inlineasm_c_output_template1() {
+  tail call void asm sideeffect "!TEST ${0:c}", "i"(i32* nonnull @baz)
+  ret i32 42
+}
+
+; Test that %n works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template2
+; CHECK: !TEST -42
+define dso_local i32 @test_inlineasm_c_output_template2() {
+  tail call void asm sideeffect "!TEST ${0:n}", "i"(i32 42)
+  ret i32 42
+}

llvm/trunk/test/CodeGen/MSP430/inlineasm-output-template.ll

+; RUN: llc -mtriple=msp430-linux-gnu < %s | FileCheck %s
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: ;TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+  tail call void asm sideeffect ";TEST ${0:c}", "i"(i32 42)
+  ret i32 42
+}
+
+; Test that %c works with global address
+; CHECK-LABEL: test_inlineasm_c_output_template2
+; CHECK: ;TEST baz
+@baz = internal global i32 0, align 4
+define dso_local i32 @test_inlineasm_c_output_template2() {
+  tail call void asm sideeffect ";TEST ${0:c}", "i"(i32* nonnull @baz)
+  ret i32 42
+}
+
+; Test that %n works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK: ;TEST -42
+define dso_local i32 @test_inlineasm_c_output_template1() {
+  tail call void asm sideeffect ";TEST ${0:n}", "i"(i32 42)
+  ret i32 42
+}

llvm/trunk/test/CodeGen/Mips/inlineasm-output-template.ll

+; RUN: llc -mtriple=mips64el-linux-gnu < %s | FileCheck %s
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: #TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+  tail call void asm sideeffect "#TEST ${0:c}", "i"(i32 42)
+  ret i32 42
+}
+
+; Test that %c works with global address
+; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK: #TEST baz
+@baz = internal global i32 0, align 4
+define dso_local i32 @test_inlineasm_c_output_template1() {
+  tail call void asm sideeffect "#TEST ${0:c}", "i"(i32* nonnull @baz)
+  ret i32 42
+}
+
+; Test that %n works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template2
+; CHECK: #TEST -42
+define dso_local i32 @test_inlineasm_c_output_template2() {
+  tail call void asm sideeffect "#TEST ${0:n}", "i"(i32 42)
+  ret i32 42
+}

llvm/trunk/test/CodeGen/NVPTX/inlineasm-output-template.ll

+; RUN: llc -march=nvptx < %s | FileCheck %s
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: //TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+  tail call void asm sideeffect "//TEST ${0:c}", "i"(i32 42)
+  ret i32 42
+}
+
+; Test that %c works with global address
+; FIXME: seems this case isn't handled properly by
+; SelectionDAG TargetLowering::LowerAsmOperandForConstraint?
+; check: test_inlineasm_c_output_template1
+; check: //TEST baz
+;@baz = internal global i32 0, align 4
+;define dso_local i32 @test_inlineasm_c_output_template1() {
+;  tail call void asm sideeffect "//TEST ${0:c}", "i"(i32* nonnull @baz)
+;  ret i32 42
+;}
+
+; Test that %n works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template2
+; CHECK: //TEST -42
+define dso_local i32 @test_inlineasm_c_output_template2() {
+  tail call void asm sideeffect "//TEST ${0:n}", "i"(i32 42)
+  ret i32 42
+}

llvm/trunk/test/CodeGen/PowerPC/inlineasm-output-template.ll

 ; RUN: llc -mtriple=ppc32-- < %s | FileCheck %s
 
 ; Test that %c works with immediates
 ; CHECK-LABEL: test_inlineasm_c_output_template0
 ; CHECK: #TEST 42
 define dso_local i32 @test_inlineasm_c_output_template0() {
   tail call void asm sideeffect "#TEST ${0:c}", "i"(i32 42)
   ret i32 42
 }
 
+; Test that %c works with global address
+; CHECK-LABEL: test_inlineasm_c_output_template1:
+; CHECK: #TEST baz
+@baz = internal global i32 0, align 4
+define dso_local i32 @test_inlineasm_c_output_template1() {
+  tail call void asm sideeffect "#TEST ${0:c}", "i"(i32* nonnull @baz)
+  ret i32 43
+}
+
 ; Test that %n works with immediates
-; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK-LABEL: test_inlineasm_c_output_template2
 ; CHECK: #TEST -42
-define dso_local i32 @test_inlineasm_c_output_template1() {
+define dso_local i32 @test_inlineasm_c_output_template2() {
   tail call void asm sideeffect "#TEST ${0:n}", "i"(i32 42)
   ret i32 42
 }

llvm/trunk/test/CodeGen/SPARC/inlineasm-output-template.ll

+; RUN: llc -mtriple=sparc-linux-gnu < %s | FileCheck %s
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: !TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+  tail call void asm sideeffect "!TEST ${0:c}", "i"(i32 42)
+  ret i32 42
+}
+
+; Test that %c works with global address
+; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK: !TEST baz
+@baz = internal global i32 0, align 4
+define dso_local i32 @test_inlineasm_c_output_template1() {
+  tail call void asm sideeffect "!TEST ${0:c}", "i"(i32* nonnull @baz)
+  ret i32 42
+}
+
+; Test that %n works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template2
+; CHECK: !TEST -42
+define dso_local i32 @test_inlineasm_c_output_template2() {
+  tail call void asm sideeffect "!TEST ${0:n}", "i"(i32 42)
+  ret i32 42
+}

llvm/trunk/test/CodeGen/SystemZ/inlineasm-output-template.ll

+; RUN: llc -mtriple=s390x-linux-gnu < %s | FileCheck %s
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: #TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+  tail call void asm sideeffect "#TEST ${0:c}", "i"(i32 42)
+  ret i32 42
+}
+
+; Test that %c works with global address
+; CHECK-LABEL: test_inlineasm_c_output_template2
+; CHECK: #TEST baz
+@baz = internal global i32 0, align 4
+define dso_local i32 @test_inlineasm_c_output_template2() {
+  tail call void asm sideeffect "#TEST ${0:c}", "i"(i32* nonnull @baz)
+  ret i32 42
+}
+
+; Test that %n works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK: #TEST -42
+define dso_local i32 @test_inlineasm_c_output_template1() {
+  tail call void asm sideeffect "#TEST ${0:n}", "i"(i32 42)
+  ret i32 42
+}

llvm/trunk/test/CodeGen/WebAssembly/inlineasm-output-template.ll

+; RUN: llc -mtriple=wasm32 < %s | FileCheck %s
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: #TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+  tail call void asm sideeffect "#TEST ${0:c}", "i"(i32 42)
+  ret i32 42
+}
+
+; Test that %c works with global address
+; CHECK-LABEL: test_inlineasm_c_output_template2
+; CHECK: #TEST baz
+@baz = internal global i32 0, align 4
+define dso_local i32 @test_inlineasm_c_output_template2() {
+  tail call void asm sideeffect "#TEST ${0:c}", "i"(i32* nonnull @baz)
+  ret i32 42
+}
+
+; Test that %n works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK: #TEST -42
+define dso_local i32 @test_inlineasm_c_output_template1() {
+  tail call void asm sideeffect "#TEST ${0:n}", "i"(i32 42)
+  ret i32 42
+}

llvm/trunk/test/CodeGen/X86/inline-asm-modifier-c.ll

+; RUN: llc -mtriple=x86_64-linux-gnu < %s | FileCheck %s
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: #TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+  tail call void asm sideeffect "#TEST ${0:c}", "i"(i32 42)
+  ret i32 42
+}
+
+; Test that %c works with global address
+; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK: #TEST baz
+@baz = internal global i32 0, align 4
+define dso_local i32 @test_inlineasm_c_output_template1() {
+  tail call void asm sideeffect "#TEST ${0:c}", "i"(i32* nonnull @baz)
+  ret i32 42
+}

llvm/trunk/test/CodeGen/XCore/inlineasm-output-template.ll

+; RUN: llc -march=xcore < %s | FileCheck %s
+
+; Test that %c works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template0
+; CHECK: #TEST 42
+define dso_local i32 @test_inlineasm_c_output_template0() {
+  tail call void asm sideeffect "#TEST ${0:c}", "i"(i32 42)
+  ret i32 42
+}
+
+; Test that %c works with global address
+; CHECK-LABEL: test_inlineasm_c_output_template2
+; CHECK: #TEST baz
+@baz = internal global i32 0, align 4
+define dso_local i32 @test_inlineasm_c_output_template2() {
+  tail call void asm sideeffect "#TEST ${0:c}", "i"(i32* nonnull @baz)
+  ret i32 42
+}
+
+; Test that %n works with immediates
+; CHECK-LABEL: test_inlineasm_c_output_template1
+; CHECK: #TEST -42
+define dso_local i32 @test_inlineasm_c_output_template1() {
+  tail call void asm sideeffect "#TEST ${0:n}", "i"(i32 42)
+  ret i32 42
+}