[TargetLowering][X86] Teach SimplifyDemandedBits to use ShrinkDemandedOp on ISD::SHL nodes.

[craig.topper]

Summary

If the upper bits of the SHL result aren't used, we might be able to use a narrower shift. For example, on X86 this can turn a 64-bit into 32-bit enabling a smaller encoding.

[craig.topper]

Rebase

[RKSimon]

llvm/test/CodeGen/X86/zext-logicop-shift-load.ll

25

Are you looking at this as a followup?

[spatel]

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

11041–11045

It would be better to split this change off on its own while adding a test specifically for this pattern.

IIUC, we can modify the existing test slightly and show the missing fold:

declare void @t()
define void @tbz_zext(i32 %in) {
  %shl = shl i32 %in, 3
  %t = zext i32 %shl to i64
  %and = and i64 %t, 32
  %cond = icmp eq i64 %and, 0
  br i1 %cond, label %then, label %end

then:
  call void @t()
  br label %end

end:
  ret void
}

[craig.topper]

Remove the AArch64 code change. Show the regression instead. I'll work on the separate patch and rebase accordingly depending on what order they get committed

[spatel]

I think D60482 should go in 1st, so we avoid that known regression. There's still an open question about the x86 LEA matching. I've seen that or similar matching failures in other tests, so it would be nice to catch it first too.

I wonder if losing the wrapping flags is hurting. Although we should be able to use knownbits to restore the knowledge. Something like this?

define i64 @lea(i64 %t0, i32 %t1) {
  %t4 = add nuw nsw i32 %t1, 8
  %sh = shl nsw i32 %t4, 2
  %t5 = zext i32 %sh to i64
  %t6 = add i64 %t5, %t0
  ret i64 %t6
}

Produces:
leal 32(,%rsi,4), %eax
addq %rdi, %rax

Instead of:
leaq 32(%rdi,%rsi,4), %rax

[craig.topper]

For the LEA regression here, we need to teach foldMaskedShiftToScaledMask to look through the any_extend to find the shift and reinsert the any_extend in the new ordering.

[craig.topper]

Rebase

[spatel]

LGTM

[efriedma]

I just pushed rGd8b9ed72ee83, a testcase affected by this patch.

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

if (ConstantSDNode *SA = isConstOrConstSplat(Op1)) {
           }
         }
       }
 
       if (SimplifyDemandedBits(Op0, DemandedBits.lshr(ShAmt), DemandedElts,
                                Known, TLO, Depth + 1))
         return true;
 
+      // Try shrinking the operation as long as the shift amount will still be
+      // in range.
+      if ((ShAmt < DemandedBits.getActiveBits()) &&
+          ShrinkDemandedOp(Op, BitWidth, DemandedBits, TLO))
+        return true;
+
       // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits
       // are not demanded. This will likely allow the anyext to be folded away.
       if (Op0.getOpcode() == ISD::ANY_EXTEND) {
         SDValue InnerOp = Op0.getOperand(0);
         EVT InnerVT = InnerOp.getValueType();
         unsigned InnerBits = InnerVT.getScalarSizeInBits();
         if (ShAmt < InnerBits && DemandedBits.getActiveBits() <= InnerBits &&
             isTypeDesirableForOp(ISD::SHL, InnerVT)) {

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

static SDValue getTestBitOperand(SDValue Op, unsigned &Bit, bool &Invert,
 
   // (tbz (trunc x), b) -> (tbz x, b)
   // This case is just here to enable more of the below cases to be caught.
   if (Op->getOpcode() == ISD::TRUNCATE &&
       Bit < Op->getValueType(0).getSizeInBits()) {
     return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
   }
 
+  // (tbz (any_ext x), b) -> (tbz x, b) if we don't use the extended bits.
+  if (Op->getOpcode() == ISD::ANY_EXTEND &&
+      Bit < Op->getOperand(0).getValueSizeInBits()) {
+    return getTestBitOperand(Op->getOperand(0), Bit, Invert, DAG);
+  }
+
   if (Op->getNumOperands() != 2)
     return Op;
 
   auto *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
   if (!C)
     return Op;
 
   switch (Op->getOpcode()) {

llvm/test/CodeGen/X86/narrow-shl-cst.ll

; CHECK-NEXT:    retq
   %shl = and i32 %and, 255
   store i32 %shl, i32* %y
   ret i32 %shl
 }
 
 define i64 @test13(i64 %x, i64* %y) nounwind {
 ; CHECK-LABEL: test13:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    movq %rdi, %rax
-; CHECK-NEXT:    andl $127, %eax
-; CHECK-NEXT:    addq %rax, %rax
+; CHECK-NEXT:    addl %edi, %edi
+; CHECK-NEXT:    movzbl %dil, %eax
 ; CHECK-NEXT:    movq %rax, (%rsi)
 ; CHECK-NEXT:    retq
   %and = shl i64 %x, 1
   %shl = and i64 %and, 255
   store i64 %shl, i64* %y
   ret i64 %shl
 }
 

llvm/test/CodeGen/X86/zext-logicop-shift-load.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
 
 
 define i64 @test1(i8* %data) {
 ; CHECK-LABEL: test1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movzbl (%rdi), %eax
-; CHECK-NEXT:    shlq $2, %rax
+; CHECK-NEXT:    movl (%rdi), %eax
+; CHECK-NEXT:    shll $2, %eax
 ; CHECK-NEXT:    andl $60, %eax
 ; CHECK-NEXT:    retq
 entry:
   %bf.load = load i8, i8* %data, align 4
   %bf.clear = shl i8 %bf.load, 2
   %0 = and i8 %bf.clear, 60
   %mul = zext i8 %0 to i64
   ret i64 %mul
 }
 
 define i8* @test2(i8* %data) {
 ; CHECK-LABEL: test2:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movzbl (%rdi), %eax
-; CHECK-NEXT:    andl $15, %eax
-; CHECK-NEXT:    leaq (%rdi,%rax,4), %rax
+; CHECK-NEXT:    movl (%rdi), %eax
+; CHECK-NEXT:    shll $2, %eax
+; CHECK-NEXT:    andl $60, %eax
+; CHECK-NEXT:    addq %rdi, %rax
 ; CHECK-NEXT:    retq
 entry:
   %bf.load = load i8, i8* %data, align 4
   %bf.clear = shl i8 %bf.load, 2
   %0 = and i8 %bf.clear, 60
   %mul = zext i8 %0 to i64
   %add.ptr = getelementptr inbounds i8, i8* %data, i64 %mul
   ret i8* %add.ptr